(R) DEVICE SPECIFICATION 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP S2091 S2091 functional and data bypasses to the next available disk drive. Normal mode is enabled with a High on the SEL pin and Bypass mode is enable by a Low on the SEL pin. Direct Attach Fibre Channel Disk Drives have an "LRC Interlock" signal defined to control the SEL function. A system diagram showing the S2091 in a single loop of a disk array is illustrated in Figure 2. FEATURES * Supports 2.5 Gbps Data Rates * Fully differential for minimum jitter accumulation * TTL Bypass Select * High speed 50 source terminated outputs * 0.4W Typical power dissipation * 3.3V power supply * 20 Pin TSSOP The S2091 can be cascaded with the S3040 (Data retimer) for arrays of disk drives greater than 4. Table 1 is a truth table detailing the data flow through the S2091. Figure 3 shows a timing diagram of the data relationship in the S2091. The primary AC parameter of importance is the deterministic jitter or data eye degradation inserted by the port bypass circuit. The design for the S2091 minimized jitter accumulation by using high bandwidth, low skew fully differential circuits. This provides for symmetric rise and fall delays as well as noise rejection. GENERAL DESCRIPTION The S2091 is a Port Bypass Circuit (PBC). A single channel Fibre Channel PBC offers designers maximum flexibility in FC-AL disk architectures. The S2091 is designed to minimize jitter accumulation by providing a high bandwidth fully differential signal path. Port Bypass circuits are used to provide resiliency in Fibre Channel Arbitrated Loop (FC-AL) architectures. PBC's are used within FC-AL disk arrays to allow for resiliency and hot swapping of FC-AL drives. Table 1. Truth Table A Port-by-Pass Circuit is a 2:1 Multiplexer with two modes of operations: Normal and Bypass. In Normal mode, the disk drive is connected to the loop. In Bypass mode, the disk drive is either absent or non- SEL1 OUT DDO 0 IN IN 1 DDI IN Figure 1. S2091 Block Diagram DDO P/N DDI P/N SEL 1 IN P/N 0 OUT P/N PBC 1 S2091 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Figure 2. Functional Block Diagram Dual SC or DB-9 Optics or Copper normal 0 FC-AL Disk Drive 1 LRC Interlock TX E_STORE RX Disk Storage S2091 bypass 0 1 Pulldown for Bypass in Absence of Disk Drive TX S2091 FC-AL Disk Drive normal 0 1 LRC Interlock TX E_STORE RX S2091 2 Disk Storage 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP S2091 Figure 3. Timing Waveforms IN P/N DI P/N OUT P/N DO P/N T1, 2, 3 Figure 4. Differential Voltage Single-ended swing VP-P = 2 x single-ended swing 3 S2091 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Table 2. Pin Assignment and Descriptions Pin Name Level I/O Pin# INP INN Diff. LVPECL I 7, 6 Differential inputs from the downstream PBC port. DDIP DDIN Diff. LVPECL I 4, 3 Serial input from the local disk drive. SEL LVTTL I 11 A Low selects the "BYPASS" mode causing the output of the previous port to propagate to the next port or OUT. When High, this signal selects "NORMAL" mode which routes the previous port to the local output, DDO and routes the local input, DDI to the next port or OUT. D DOP DDO N Diff. CML O 19, 18 Serial output driving the local disk drive. OUTP OUTN Diff. CML O 15, 14 Serial output driving the upstream PBC port. VCC Description 1, 2, 10, Power Supply. 3.3V nominal. 12, 17, 20 GND 5, 8, 9, 13, 16 Ground. Ground pins are phyisically attached to the die mounting surface, and are an important part of the thermal path. For best thermal performance, all ground pins should be connected to a ground plane, using multiple vias if possible. Figure 5. S2091 Pinout Package 4 VCC 1 20 VCC VCC 2 19 DDOP DDIN 3 18 DDON DDIP 4 17 VCC GND 5 16 GND INN 6 15 OUTP INP 7 14 OUTN GND 8 13 GND GND 9 12 VCC VCC 10 11 SEL 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP S2091 Figure 6. 20 TSSOP Package Thermal Management Device ja (Still Air) jc S2091A 77 C/W 25 C/W 5 S2091 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Table 3. AC Characteristics (Over recommended operating conditions.) Parameter Description Typ Max Units T R1 TF1 Serial Data rise and fall time (IN to OUT) 105 135 ps 20% to 80% tested on a sample basis. (100 line-to-line.) TR2 TF2 Serial Data rise and fall time (IN to DDO) 105 135 ps 20% to 80% tested on a sample basis. (100 line-to-line.) TR3 TF3 Serial Data rise and fall time (DDI to OUT) 105 150 ps 20% to 80% tested on a sample basis. (100 line-to-line.) T1 Flow through propagation delay IN to OUT 1.15 1.4 ns Delay with all circuits bypassed. 50 Ohm load. T2 Flow through propagation delay IN to DDO 1.15 1.4 ns Delay with PBC in Normal or Bypass mode. 50 Ohm load. T3 Flow through propagation delay DDI to OUT 1.15 1.4 ns Delay with PBC in Normal mode. 50 Ohm load. ps RMS output jitter accumulated with valid 8B/10B code from IN to OUT PBC in bypass mode. Tested on a sample basis. ps Deterministic output jitter accumulated with valid 8B/10B code from IN to OUT, both PBC stages bypassed. Determined by simulation. Actual value not verified due to bandwidth limitation of test equipment. TjitterRMS TjitterDJ 6 Random jitter accumulation (RMS) Deterministic jitter accumulation (p-p) 2.2 6 4 7 Conditions 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP S2091 Table 4. DC Characteristics (Over recommended operating conditions.) Parameter Description Min VIH(ITL) Input HIGH voltage (SEL-TTL) VIL(ITL) Input LOW voltage (SEL-TTL) IIH(ITL) Input HIGH current (SEL-TTL) IIL(ITL) Input LOW current (SEL-TTL) VCC Supply Voltage ICC Supply Current PD Power Dissipation VIN(DF) Receiver differential peak-to-peak input sensitivity, INP/N & DDIP/N VOUTN(L_SO) VOUTN(OUT) Typ Max Units Conditions 2.0 VCC V 0 0.8 V 50 A VIN = 2.4V -500 -50 A VIN = 0.5V 3.14 3.47 V VCC = 3.30V 5% 180 230 mA Outputs open, VCC = VCC max 0.4 .8 W Outputs open, VCC = VCC max 300 2000 mVp-p1 AC Coupled. Internally DC biased VCC - 0.65V DDOP/N output differential peak-topeak voltage swing 1000 1460 mVp-p1 100 line-to-line OUTP/N output differential peak-topeak voltage swing 1000 1460 mVp-p1 100 line-to-line 1. See Figure 4. Table 5. Absolute Maximum Ratings1 Parameter Min Power Supply Voltage (VCC) Typ Max Units 0.5 +4 V PECL DC Input Voltage (VINP) -0.5 VCC+0.5 V TTL DC Input Voltage (VINP) -0.5 VCC+0.5 V 90 mA CML Output Current (IOUT), (DC output High) Case Temperature Under Bias (TC) -55 125 C Storage Temperature (TSTG) -65 150 C 1000 V Static Discharge Voltage 1. CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied one at a time to devices without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Table 6. Recommended Operating Conditions1 Parameter Power Supply Voltage (VCC) Ambient Operating Temperature Range (T) Min Typ Max Units +3.14 +3.47 V -40 +85 C 1. AMCC guarantees the functional and parametric operation of the part under "Recommended Operating Conditions" (except where specifically noted in the AC and DC parametric tables). 7 S2091 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP Input Structures Two input structures exist in this part; TTL and high speed, differential inputs. The LVTTL inputs will interface with any LVTTL outputs. The high speed, differential inputs can be AC coupled per the FC-PH specification. Therefore, the high speed, differential input buffers are biased at Vcc -0.65V. Refer to Figure 7 for high speed differential input termination. Figure 7. Input Termination Biased at Vcc -0.65V S2091 100 Figure 8. Output VCC 50 50 Backplane S2091 8 GND 2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP S2091 Ordering Information GRADE PART NO. PACKAGE S- Commercial 2091 A - 20 TSSOP XXXX X Part No. Package O 900 D E CE RT 1 IS X Grade IFI Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (619) 450-9333 * (800) 755-2622 * Fax: (619) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1998 Applied Micro Circuits Corporation September 24, 1998 9