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DS90LV027A
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SNLS026D –MARCH 2000–REVISED JUNE 2016
Product Folder Links: DS90LV027A
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(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD.
(2) The DS90LV027A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers
outputs.
(3) All typicals are given for: VCC = 3.3 V and TA= 25°C.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS MIN TYP(3) MAX UNIT
VOD Output differential voltage RL= 100 Ω(see Figure 15), DO+, DO−pins 250 360 450 mV
ΔVOD VOD magnitude change RL= 100 Ω(see Figure 15), DO+, DO−pins 1 35 mV
VOH Output high voltage RL= 100 Ω(see Figure 15), DO+, DO−pins 1.4 1.6 V
VOL Output low voltage RL= 100 Ω(see Figure 15), DO+, DO−pins 0.9 1.1 V
VOS Offset voltage RL= 100 Ω(see Figure 15), DO+, DO−pins 1.125 1.2 1.375 V
ΔVOS Offset magnitude change RL= 100 Ω(see Figure 15), DO+, DO−pins 0 3 25 mV
IOXD Power-off leakage VOUT = VCC or GND, VCC = 0 V, DO+, DO−pins ±1 ±10 μA
IOSD Output short-circuit current DO+, DO−pins –5.7 –8 mA
VIH Input high voltage DI pin 2 VCC V
VIL Input low voltage DI pin GND 0.8 V
IIH Input high current VIN = 3.3 V or 2.4 V, DI pin ±2 ±10 μA
IIL Input low current VIN = GND or 0.5 V, DI pin ±1 ±10 μA
VCL Input clamp voltage ICL =−18 mA, DI pin –1.5 –0.6 V
ICC Power supply current VIN = VCC or GND, VCC pin No load 8 14 mA
RL= 100 Ω14 20
(1) These parameters are ensured by design. The limits are based on statistical analysis of the device over PVT (process, voltage,
temperature) ranges.
(2) CLincludes probe and fixture capacitance.
(3) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50 Ω, tr≤1 ns, tf≤1 ns (10%-90%).
(4) All typicals are given for: VCC = 3.3 V and TA= 25°C.
(5) tSKD1, |tPHLD −tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(6) tSKD2 is the Differential Channel to Channel Skew of any event on the same device.
(7) tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(8) tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max −Min|
differential propagation delay.
(9) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%,
VOD > 250 mV, all channels switching.
6.6 Switching Characteristics
RL= 100 Ωand CL= 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP(4) MAX UNIT
tPHLD Differential propagation delay high to low 0.3 0.8 1.5 ns
tPLHD Differential propagation delay low to high 0.3 1.1 1.5 ns
tSKD1 Differential pulse skew |tPHLD −tPLHD|(5) 0 0.3 0.7 ns
tSKD2 Channel to channel skew(6) 0 0.4 0.8 ns
tSKD3 Differential part to part skew(7) 0 1 ns
tSKD4 Differential part to part skew(8) 0 1.2 ns
tTLH Transition low to high time 0.2 0.5 1 ns
tTHL Transition high to low time 0.2 0.5 1 ns
fMAX Maximum operating frequency(9) 350 MHz