R XC4000XLA/XV Field Programmable Gate Arrays XV Specification Information Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. All specifications subject to change without notice. XC4000XV D.C. Characteristics Absolute Maximum Ratings Symbol Description Value Units VCCINT Supply voltage relative to GND -0.5 to 3.0 V VCCIO Supply voltage relative to GND -0.5 to 4.0 V VIN Input voltage relative to GND (Note 1) -0.5 to 5.5 V VTS Voltage applied to 3-state output (Note 1) -0.5 to 5.5 V VCC Longest Supply Voltage Rise Time from 1 V to 3V 50 ms TSTG Storage temperature (ambient) -65 to +150 C TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 C Ceramic packages +150 C Plastic packages +125 C TJ Note 1: Note: Junction temperature Maximum DC excursion above Vcc or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot toVCC + 2.0 V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. May 14, 1999 (Version 1.2) 6-187 6 R XC4000XLA/XV Field Programmable Gate Arrays Recommended Operating Conditions Symbol VCCINT VCCIO Description Min Max Units Supply voltage relative to GND, TJ = 0 C to +85C Commercial 2.3 2.7 V Supply voltage relative to GND, TJ = -40C to +100C Industrial 2.3 2.7 V Supply voltage relative to GND, TJ = 0 C to +85C Commercial 3.0 3.6 V Supply voltage relative to GND, TJ = -40C to +100C Industrial 3.0 3.6 V VIH High-level input voltage 50% of VCC 5.5 V VIL Low-level input voltage 0 30% of VCC V TIN Input signal transition time 250 ns Notes: At junction temperatures above those listed above, all delay parameters increase by 0.35% per C. Input and output measurement threshold is ~50% of VCC. DC Characteristics Over Recommended Operating Conditions Symbol VOH VOL Description High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) High-level output voltage @ IOH = -500 A, (LVCMOS) Min Max Units 2.4 V 90% VCC V Low-level output voltage @ IOL = 24.0 mA, VCC min (LVTTL) (Note 1) Low-level output voltage @ IOL = 1500 A, (LVCMOS) 0.4 V 10% VCC V VDRINT VCCINT Data Retention Supply Voltage (below which configuration data may be lost) 2.1 V VDRIO VCCIO Data Retention Supply Voltage (below which configuration data may be lost) 2.5 V ICCO IL Quiescent FPGA supply current (Note 2) 10 mA +10 A BGA, SBGA, PQ, HQ, & MQ packages 10 pF PGA packages 16 pF Input or output leakage current -10 CIN Input capacitance (sample tested) IRPU Pad pull-up (when selected) @ Vin = 0 V (sample tested) 0.02 0.25 mA IRPD Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) 0.02 0.15 mA IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA Note 1: 6-188 With up to 64 pins simultaneously sinking 24 mA. Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating. May 14, 1999 (Version 1.2) R XC4000XLA/XV Field Programmable Gate Arrays XC4000XV Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Global Buffer Switching Characteristics Guidelines Speed Grade All -09 -08 -07 Min Max Max Max Units Description Symbol Device Delay from pad through Global Low Skew (GLS) clock buffer to any clock input, K. TGLS XC40110XV 7.2 6.3 5.4 ns XC40150XV 7.3 6.4 5.5 ns XC40200XV 8.8 7.7 6.6 ns XC40250XV 8.9 7.8 6.7 ns XC40110XV 2.5 2.2 1.8 ns XC40150XV 2.6 2.3 1.9 ns XC40200XV 2.9 2.6 2.2 ns XC40250XV 3.0 2.7 2.3 ns XC40110XV 5.1 4.5 3.8 ns XC40150XV 5.2 4.6 3.9 ns XC40200XV 5.6 4.9 4.2 ns XC40250XV 5.7 5.0 4.3 ns XC40110XV 5.1 4.5 3.8 ns XC40150XV 5.2 4.6 3.9 ns XC40200XV 5.6 4.9 4.2 ns XC40250XV 5.7 5.0 4.3 ns Delay from pad through Global Early (GE) clock buffer to any IOB clock input for BUFGE #s 1, 2, 5, and 6. Delay from pad through Global Early (GE) clock buffer to any IOB clock input for BUFGE #s 3, 4, 7, and 8. Delay from pad through FastCLK buffer to any IOB clock input TGE_1256 TGE_3478 TFCLK Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. May 14, 1999 (Version 1.2) Advance 6-189 6 R XC4000XLA/XV Field Programmable Gate Arrays XC4000XV CLB Characteristics Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless otherwise noted. CLB Switching Characteristic Guidelines Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H' to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/H0 via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass0 CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry Net Delay, COUT to CIN Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H Hold Time after Clock K All Hold Times Clocks Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q Toggle Frequency (MHz) (for export control purposes) 6-190 Speed Grade Symbol -09 Min TILO TIHO TITO THH0O THH1O THH2O -08 Max Min -07 Max Min Max Units 1.3 2.0 2.1 1.9 1.7 1.1 1.7 1.8 1.6 1.5 1.0 1.5 1.6 1.4 1.3 ns ns ns ns ns TCBYP 1.9 1.2 1.6 1.0 1.4 0.9 ns ns TOPCY TASCY TINCY TSUM TBYP TNET 2.2 1.3 1.4 1.8 0.3 0.4 1.9 1.1 1.2 1.6 0.2 0.3 1.7 1.0 1.0 1.4 0.2 0.3 ns ns ns ns ns ns TCKO TCKLO 1.6 1.6 1.4 1.4 1.2 1.2 ns ns TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHC 0.8 1.5 1.4 1.2 1.4 0.6 0.7 0.6 1.3 2.0 0.7 1.3 1.2 1.1 1.2 0.6 0.6 0.5 1.1 1.7 0.6 1.1 1.0 0.9 1.0 0.5 0.5 0.4 1.0 1.5 ns ns ns ns ns ns ns ns ns ns 0.0 0.0 0.0 ns TCH 2.3 2.0 1.7 ns TCL 2.3 2.0 1.7 ns TRPW TRIO 3.0 TMRW TMRQ FTOG 2.8 2.6 2.5 2.3 2.0 13.4 11.7 10.2 See page 197 for TRRI values per device 224 258 296 Advance ns ns ns MHz May 14, 1999 (Version 1.2) R XC4000XLA/XV Field Programmable Gate Arrays CLB RAM Single Port Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XV devices and are expressed in nanoseconds unless otherwise noted. Single Port RAM Speed Grade -09 -08 -07 Units Size Symbol Min Max Min Max Min Max 16x2 TWCS 7.0 6.1 5.3 ns 32x1 TWCTS 7.0 6.1 5.3 ns 16x2 TWPS 3.5 3.1 2.7 ns 32x1 TWPTS 3.5 3.1 2.7 ns 16x2 TASS 1.5 1.3 1.2 ns 32x1 TASTS 1.6 1.4 1.2 ns 16x2 TAHS 0.0 0.0 0.0 ns 32x1 TAHTS 0.0 0.0 0.0 ns 16x2 TDSS 1.6 1.4 1.2 ns 32x1 TDSTS 2.0 1.7 1.5 ns 16x2 TDHS 0.0 0.0 0.0 ns 32x1 TDHTS 0.0 0.0 0.0 ns 16x2 TWSS 1.5 1.3 1.2 ns 32x1 TWSTS 1.4 1.3 1.1 ns 16x2 TWHS 0.0 0.0 0.0 ns 32x1 TWHTS 0.0 0.0 0.0 ns 16x2 TWOS 5.2 4.6 4.0 ns 32x1 TWOTS 6.2 5.4 4.7 ns 16x2 TRC 4.5 3.1 3.1 ns 32x1 TRCT 6.5 5.5 5.5 ns 16x2 TILO 1.3 1.1 1.0 ns 32x1 TIHO 2.0 1.7 1.5 ns 16x2 TICK 0.8 0.7 0.6 ns 32x1 TIHCK 1.5 1.3 1.1 ns Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Read Operation Address read cycle time Data Valid after address change (no Write Enable) Address setup time before clock K Advance May 14, 1999 (Version 1.2) 6-191 6 R XC4000XLA/XV Field Programmable Gate Arrays CLB RAM Dual Port Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Speed Grade Dual Port RAM -09 -08 -07 Units Size Symbol Min Max Min Max Address write cycle time (clock K period) 16x1 TWCDS 7.0 6.1 5.3 ns Clock K pulse width (active edge) 16x1 TWPDS 3.5 3.1 2.7 ns Address setup time before clock K 16x1 TASDS 1.5 1.3 1.2 ns Address hold time after clock K 16x1 TAHDS 0.0 0.0 0.0 ns DIN setup time before clock K 16x1 TDSDS 1.9 1.7 1.4 ns DIN hold time after clock K 16x1 TDHDS 0.0 0.0 0.0 ns WE setup time before clock K 16x1 TWSDS 1.5 1.3 1.2 ns WE hold time after clock K 16x1 TWHDS 0.0 0.0 0.0 ns Data valid after clock K 16x1 TWODS 6.0 Min 5.3 Max 4.6 ns Advance Note: Timing for 16x1 option is identical to 16x2 RAM. CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms TWPS TWPDS WCLK (K) WCLK (K) TWHS TWSS WE TWSDS TWHDS TDSDS TDHDS TASDS TAHDS WE TDHS TDSS DATA IN DATA IN TASS TAHS ADDRESS ADDRESS TILO DATA OUT TWOS OLD TILO TILO TILO TWODS DATA OUT NEW OLD NEW X6474 X6461 Single Port RAM 6-192 Dual Port RAM May 14, 1999 (Version 1.2) R XC4000XLA/XV Field Programmable Gate Arrays XC4000XV Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Global Clock Input to Output Delay Guidelines Description Global Low Skew (GLS) Clock Input to Output Speed Grade All -09 -08 -07 Symbol Device Min Max Max Max TICKOF XC40110XV 10.6 9.2 8.0 ns XC40150XV 10.7 9.3 8.1 ns XC40200XV 12.2 10.6 9.2 ns XC40250XV 12.3 10.7 9.3 ns All Devices 1.7 1.6 1.4 ns Delay using Output Flip-Flop. For output SLOW option add TSLOW Units Advance Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs in FAST mode specification. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1. 6 Low Skew FastCLK Input to Output Delay Guidelines for BUFNW, SW, NE, and SE Speed Grade All -09 -08 -07 Symbol Device Min Max Max Max TICKFOF XC40110XV 5.9 5.1 4.4 ns Flip-Flop for FastCLK buffers BUFNW, BUFSW, XC40150XV 6.0 5.2 4.5 ns BUFNE, and BUFSE. XC40200XV 6.3 5.5 4.8 ns XC40250XV 6.4 5.6 4.9 ns Description FastCLK Input to Output Delay using Output Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Units Advance Notes: Listed above are representative values where one FastCLK input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the FastCLK net. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs in FAST slew mode specification. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1. May 14, 1999 (Version 1.2) 6-193 R XC4000XLA/XV Field Programmable Gate Arrays Global Early Clock Input to Output Delay Guidelines for BUFGE #s 1, 2, 5, and 6 Description Global Clock Signal Input to Output Delay using Global Early (GE) clock buffer to clock Output Flip-Flop for BUFGE #s 1, 2, 5, and 6. Speed Grade All -09 -08 -07 Symbol Device Min Max Max Max TICKEOF_1256 XC40110XV 8.5 7.4 6.4 ns XC40150XV 8.6 7.5 6.5 ns XC40200XV 9.0 7.8 6.8 ns XC40250XV 9.1 7.9 6.9 ns Advance Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Notes: Units Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs in FAST mode specification. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1. Global Early Clock Input to Output Delay Guidelines for BUFGE #s 3, 4, 7, and 8 Description Global Clock Signal Input to Output Delay using Global Early (GE) clock buffer to clock Output Flip-Flop for BUFGE #s 3, 4, 7, and 8. Speed Grade All -09 -08 -07 Device Min Max Max Max TICKEOF_3478 XC40110XV 8.5 7.4 6.4 ns XC40150XV 8.6 7.5 6.5 ns XC40200XV 9.0 7.8 6.8 ns XC40250XV 9.1 7.9 6.9 ns Symbol Advance Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Notes: Units Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs in FAST mode specification. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1. Capacitive Load Factor Figure 1 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control. Delta Delay (ns) Figure 1 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than 50 pF. For example, if the actual load capacitance is 120 pF, add 2.5 ns to the specified delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specified output delay. 3 2 1 0 -1 -2 0 20 40 60 80 100 120 140 Capacitance (pF) X8257 Figure 1: Delay Factor at Various Capacitive Loads 6-194 May 14, 1999 (Version 1.2) R XC4000XLA/XV Field Programmable Gate Arrays XC4000XV Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Global Low Skew Clock, Set-Up and Hold Guidelines Speed Grade Description Symbol Device Input Setup and Hold Time Relative to Global Clock Input Signal No Delay XC40110XV Global Low Skew Clock and IFF TPSN/TPHN XC40150XV Global Low Skew Clock and FCL XC40200XV XC40250XV Partial Delay XC40110XV Global Low Skew Clock and IFF TPSP/TPHP XC40150XV Global Low Skew Clock and FCL XC40200XV XC40250XV Full Delay XC40110XV Global Low Skew Clock and IFF TPSD/TPHD XC40150XV XC40200XV XC40250XV -09 Min -08 Min -07 Min Units 0.0 / 6.8 0.0 / 7.5 0.0 / 8.8 0.0 / 9.8 5.5 / 0.5 6.1 / 0.5 7.9 / 0.3 8.7 / 0.0 8.0 / 0.0 8.9 / 0.0 9.4 / 0.0 9.7 / 0.0 0.0 / 5.9 0.0 / 6.6 0.0 / 6.7 0.0 / 8.5 4.8 / 0.5 5.3 / 0.5 6.8 / 0.2 7.6 / 0.0 6.9 / 0.0 7.7 / 0.0 8.2 / 0.0 8.4 / 0.0 Advance 0.0 / 5.1 0.0 / 5.7 0.0 / 6.7 0.0 / 7.4 4.1 / 0.4 4.6 / 0.4 5.9 / 0.2 6.6 / 0.0 6.0 / 0.0 6.7 / 0.0 7.1 / 0.0 7.3 / 0.0 ns ns ns ns ns ns ns ns ns ns ns ns IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions. FastCLK Input Set-Up and Hold Guidelines for BUFNW, SW, NE, and SE Description Symbol No Delay FastCLK and IFF TPSFN/TPHFN Partial Delay FastCLK and IFF TPSFP/TPHFP Full Delay FastCLK and IFF TPSFD/TPHFD Speed Grade Device XC40110XV XC40150XV XC40200XV XC40250XV XC40110XV XC40150XV XC40200XV XC40250XV XC40110XV XC40150XV XC40200XV XC40250XV -09 Min 0.8 / 4.2 0.8 / 4.6 0.8 / 4.9 0.8 / 5.3 11.0 / 0.0 11.1 / 0.0 11.4 / 0.0 11.6 / 0.0 11.7 / 0.0 11.8 / 0.0 12.4 / 0.0 12.7 / 0.0 -08 Min 0.7 / 3.7 0.7 / 4.0 0.7 / 4.3 0.7 / 4.6 9.5 / 0.0 9.7 / 0.0 9.9 / 0.0 10.1 / 0.0 10.5 / 0.0 10.6 / 0.0 10.8 / 0.0 11.0 / 0.0 Advance -07 Min 0.6 / 3.2 0.6 / 3.5 0.6 / 3.7 0.6 / 4.0 8.3 / 0.0 8.4 / 0.0 8.6 / 0.0 8.8 / 0.0 9.1 / 0.0 9.2 / 0.0 9.4 / 0.0 9.6 / 0.0 Units ns ns ns ns ns ns ns ns ns ns ns ns IFF = Input Flip-Flop or Latch Bold Face: Preliminary Values for the XC40150-09. All other values are Advance Notes: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. May 14, 1999 (Version 1.2) 6-195 6 R XC4000XLA/XV Field Programmable Gate Arrays BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-Up and Hold for IFF and FCL Guidelines Speed Grade Description Symbol Device Input Setup and Hold Time Relative to Global Clock Input Signal No Delay XC40110XV Global Early Clock and IFF TPSEN/TPHEN XC40150XV Global Early Clock and FCL TPFSEN/TPFHEN XC40200XV XC40250XV Partial Delay XC40110XV Global Early Clock and IFF TPSEP/TPHEP XC40150XV Global Early Clock and FCL TPFSEP/TPFHEP XC40200XV XC40250XV FullDelay XC40110XV Global Early Clock and IFF TPSED/TPHED XC40150XV XC40200XV XC40250XV -09 Min -08 Min -07 Min Units 0.5 / 6.1 0.6 / 6.2 1.3 / 7.3 1.5 / 7.5 7.3 / 0.0 8.1 / 0.0 10.8 / 0.0 12.0 / 0.0 10.6 / 0.0 10.7 / 0.0 11.9 / 0.0 13.1 / 0.0 0.4 / 5.3 0.5 / 5.4 1.2 / 6.3 1.3 / 6.6 6.3 / 0.0 7.0 / 0.0 9.4 / 0.0 10.5 / 0.0 9.2 / 0.0 9.3 / 0.0 10.4 / 0.0 11.4 / 0.0 Advance 0.4 / 4.6 0.4 / 4.7 1.0 / 5.5 1.1 / 5.7 5.5 / 0.0 6.1 / 0.0 8.2 / 0.0 9.1 / 0.0 8.0 / 0.0 8.1 / 0.0 9.0 / 0.0 9.9 / 0.0 ns ns ns ns ns ns ns ns ns ns ns ns IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-Up and Hold for IFF and FCL Guidelines Speed Grade Description Symbol Device Input Setup and Hold Time Relative to Global Clock Input Signal No Delay XC40110XV Global Early Clock and IFF TPSEN/TPHEN XC40150XV Global Early Clock and FCL TPFSEN/TPFHEN XC40200XV XC40250XV Partial Delay XC40110XV XC40150XV Global Early Clock and IFF TPSEP/TPHEP Global Early Clock and FCL TPFSEP/TPFHEP XC40200XV XC40250XV FullDelay XC40110XV Global Early Clock and IFF TPSED/TPHED XC40150XV XC40200XV XC40250XV IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch -09 Min -08 Min -07 Min Units 0.4 / 5.2 0.4 / 5.3 0.9 / 6.2 1.1 / 6.5 7.4 / 0.0 7.5 / 0.0 9.7 / 0.0 11.6 / 0.0 10.0 / 0.0 10.1 / 0.0 10.7 / 0.0 12.8 / 0.0 0.3 / 4.5 0.4 / 4.6 0.8 / 5.4 0.9 / 5.6 6.5 / 0.0 6.6 / 0.0 8.4 / 0.0 10.1 / 0.0 8.6 / 0.0 8.7 / 0.0 9.3 / 0.0 11.2 / 0.0 Advance 0.3 / 3.9 0.3 / 4.0 0.7 / 4.7 0.8 / 4.9 5.6 / 0.0 5.7 / 0.0 7.3 / 0.0 8.8 / 0.0 7.5 / 0.0 7.6 / 0.0 8.1 / 0.0 9.7 / 0.0 ns ns ns ns ns ns ns ns ns ns ns ns Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. 6-196 May 14, 1999 (Version 1.2) R XC4000XLA/XV Field Programmable Gate Arrays IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Description Clocks Clock Enable (EC) to Clock (IK) Delay from Fast Capture Latch enable (OK) active edge to IFF clock (IK) active edge Setup Times Pad to Clock (IK), no delay Pad to Clock (IK), via transparent Fast Capture Latch, no delay Pad to Fast Capture Latch Enable (OK), no delay Hold Times All Hold Times Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q Propagation Delays Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent FCL and input latch, no delay Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) FCL Enable (OK) active edge to I1, I2 (via transparent standard input latch) Symbol Speed Grade -09 -08 -07 Units Device Min Max Min Max Min Max TECIK TOKIK All Devices All Devices 0.0 1.3 0.0 1.2 0.0 1.0 ns ns TPICK TPICKF All Devices Al Devices 1.3 1.8 1.1 1.6 1.0 1.4 ns ns TPOCK All Devices 1.1 1.0 0.8 ns All Devices 0.0 0.0 0.0 ns All Devices XC40110XV XC40150XV XC40200XV XC40250XV 13.4 27.2 29.1 33.8 35.8 11.7 23.6 25.3 29.4 31.1 10.2 20.5 22.0 25.5 27.0 ns ns ns TMRW TRRI* ns ns TPID TPLI TPFLI All devices All devices All Devices 1.6 2.7 3.6 1.4 2.3 3.1 1.2 2.0 2.7 ns ns ns TIKRI TIKLI TOKLI All Devices All Devices All Devices 1.4 1.6 2.7 1.2 1.4 2.4 1.1 1.2 2.1 ns ns ns IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch. Advance Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. * Indicates Minimum Amount of Time to Assure Valid Data. May 14, 1999 (Version 1.2) 6-197 6 R XC4000XLA/XV Field Programmable Gate Arrays IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Description Clocks Clock High Clock Low Propagation Delays (See Note 1) Clock (OK) to Pad Output (O) to Pad 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid Clock to Pad hi-Z Clock to Pad active and valid Output (O) to Pad via Fast Output MUX Select (OK) to Pad via Fast MUX Setup and Hold Times Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup time Clock Enable (EC) to clock (OK) hold time Global Set/Reset Minimum GSR pulse width Delay from GSR input to any Pad Slew Rate Adjustment For output SLOW option add Symbol Speed Grade -09 -08 -07 Units Device Min Max Min Max Min Max TCH TCL All Devices All Devices TOKPOF TOPF TTSHZ TTSONF TOKSHZ TOKSONF TOFPF TOKFPF All Devices All Devices All Devices All Devices All Devices All Devices All Devices All Devices TOOK TOKO TECOK TOKEC All Devices All Devices All Devices All Devices TMRW TRPO* All Devices 13.4 11.7 10.2 XC40110XV 30.5 26.6 23.1 XC40150XV 32.5 28.3 24.6 XC40200XV 37.1 32.3 28.1 XC40250XV 39.1 34.0 29.6 ns ns ns All Devices ns TSLOW 2.3 2.3 2.0 2.0 3.5 3.0 3.0 3.1 4.7 4.8 4.4 4.0 0.4 0.0 0.0 0.3 * Indicates Minimum Amount of Time to Assure Valid Data. Bold Face: Preliminary Values for the XC40150-09. All other values are Advance. Note: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads. 1.7 1.7 3.0 2.6 2.6 2.7 4.1 4.2 3.8 3.5 0.4 0.0 0.0 0.2 2.3 ns ns 2.7 2.3 2.2 2.3 3.5 3.6 3.3 3.0 0.3 0.0 0.0 0.1 2.0 ns ns ns ns ns ns ns ns ns ns ns ns 1.7 ns ns Advance Revision Control Version Description 2/1/99 (1.0) Release included in 1999 data book, section 6 2/19/99 (1.1) Updated Switching Characteristics Tables 5/14/99 (1.2) Replaced Electrical Specification pages for XLA and XV families with separate updates and added URL link on placeholder page for electrical specifications/pinouts for WebLINX users. 6-198 May 14, 1999 (Version 1.2)