© Semiconductor Components Industries, LLC, 2016
February, 2017 − Rev. 5 1Publication Order Number:
AR0237CS/D
AR0237CS
AR0237CS
1/2.7‐inch 2.1 Mp/Full HD
Digital Image Sensor
The AR0237CS from ON Semiconductor is a 1/2.7-inch CMOS
digital image sensor with an active-pixel array of 1928 (H) ×
1088 (V). It captures images in either linear or high dynamic range
modes, with a rolling-shutter readout. It includes sophisticated camera
functions such as in-pixel binning, windowing and both video and
single frame modes. It is designed for both low light and high dynamic
range scene performance. It is programmable through a simple
two-wire serial interface. The AR0237 produces extraordinarily clear,
sharp digital pictures, and its ability to capture both continuous video
and single frames makes it the perfect choice for a wide range of
applications, including surveillance and HD video.
Table 1. KEY PERFORMANCE PARAMETERS
Parameter Value
Optical Format 1/2.7-inch (6.6 mm)
Active Pixels 1928 (H) × 1088 (V) (16:9 Mode)
Pixel Size 3.0 mm × 3.0 mm
Color Filter Array RGB Bayer, RGB−IR
Shutter Type Electronic Rolling Shutter and GRR
Input Clock Range 6–48 MHz
Output Clock Maximum 148.5 Mp/s (4-lane HiSPi)
74.25 Mp/s (Parallel)
Output
Serial
Parallel HiSPi 10-, 12-, 14-, 16-, or 20-bit
10-, 12-bit
Frame Rate 1080p 60 fps Linear HiSPi
30 fps Linear Parallel
30 fps Line Interleaved HiSPi
15 fps Line Interleaved Parallel
Responsivity 4.0 V/lux−sec
SNRMAX 41 dB
Max Dynamic Range Up to 96 dB
Supply Voltage
I/O
Digital
Analog
HiSPi
1.8 or 2.8 V
1.8 V
2.8 V
0.3−0.6 V (SLVS), 1.7−1.9 V (HiVCM)
Power Consumption (Typical) < 300 mW Line Interleaved 1080p30
< 190 mW 1080p30 Linear Mode
Operating Temperature –30°C to +85°C Ambient
Package Options 10 × 10 mm 80-pin iBGA
11.43 × 11.43 mm 48-pin mPLCC
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F
eatures
•Superior Low-light Performance
•Latest 3.0 mm pixel with
ON Semiconductor DR−Pixt Technology
with Dual Conversion Gain
•Full HD Support at Up to 1080p 60 fps for
Superior Video Performance
•Linear or High Dynamic Range Capture
•Supports Line Interleaved T1/T2 Readout t
o
Enable HDR Processing in ISP Chip
•Support for External Mechanical Shutter
•On-chip Phase-locked Loop (PLL)
Oscillator
•Integrated Position-based Color and Lens
Shading Correction
•Slave Mode for Precise Frame-rate Control
•Stereo/3D Camera Support
•Statistics Engine
•Data Interfaces: Four-lane Serial High-spee
d
Pixel Interface (HiSPi) Differential
Signaling (SLVS and HiVCM), or Parallel
•Auto Black Level Calibration
•High-speed Configurable Context Switchin
g
•Temperature Sensor
A
pplications
•Video Surveillance
•1080p60 (Surveillance) Video Applications
•High Dynamic Range Imaging
See detailed ordering and shipping information on page 2 o
f
this data sheet.
ORDERING INFORMATION
IBGA80
CASE 503BA PLCC48
CASE 776AQ PLCC48
CASE 776AS
AR0237CS
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ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number Product Description Orderable Product
Attribute Description
AR0237CSSC00SUEA0−DR 2 Mp 1/2.7″ Image Sensor, RGB, 0° CRA, iBGA Package,
Multi Output Drypack
AR0237CSSC00SHRA0−DR 2 Mp 1/2.7″ Image Sensor, RGB, 0° CRA, mPLCC Package,
HiSPi Output Drypack
AR0237CSSC00SPRA0−DR 2 Mp 1/2.7″ Image Sensor, RGB, 0° CRA, mPLCC Package,
Parallel Output Drypack
AR0237CSSC12SHRA0−DR 2 Mp 1/2.7″ Image Sensor, RGB, 12° CRA, mPLCC Package,
HiSPi Output Drypack
AR0237CSSC12SPRA0−DR 2 Mp 1/2.7″ Image Sensor, RGB, 12° CRA, mPLCC Package,
Parallel Output Drypack
AR0237IRSH12SHRA0−DR−E 2 Mp 1/2.7″ Image Sensor, RGB−IR, 12° CRA, mPLCC Package,
HiSPi Output Drypack
AR0237IRSH12SPRA0−DR−E 2 Mp 1/2.7″ Image Sensor, RGB−IR, 12° CRA, mPLCC Package,
Parallel Output Drypack
AR0237CSSC00SUEAH3−GEVB RGB, 0° CRA, iBGA Package, Multi Output, Headboard Headboard
AR0237CSSC00SHRAH3−GEVB RGB, 0° CRA, mPLCC Package, HiSPi Output, Headboard Headboard
AR0237CSSC00SPRAH3−GEVB RGB, 0° CRA, mPLCC Package, Parallel Output, Headboard Headboard
AR0237CSSC12SHRAH3−GEVB RGB, 12° CRA, mPLCC Package, HiSPi Output, Headboard Headboard
AR0237CSSC12SPRAH3−GEVB RGB, 12° CRA, mPLCC Package, Parallel Output, Headboard Headboard
AR0237IRSH12SHRAH3−GEVB RGB−IR, 12° CRA, mPLCC Package, HiSPi Output, Headboard Headboard
AR0237IRSH12SPRAH3−GEVB RGB−IR, 12° CRA, mPLCC Package, Parallel Output, Headboard Headboard
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
AR0237CS
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3
GENERAL DESCRIPTION
The AR0237CS from ON Semiconductor can be operated
in its default mode or programmed for frame size, exposure,
gain, and other parameters. The default mode output is
a 1080p-resolution image at 60 frames per second (fps)
through the HiSPi port. In linear mode, it outputs 12-bit or
10-bit A−Law compressed raw data, using either the parallel
or serial (HiSPi) output ports. In high dynamic range mode,
it outputs two exposure values that the ISP will combine into
an HDR image. The device may be operated in video
(master) mode or in single frame trigger mode.
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock in
parallel mode.
The AR0237 includes additional features to allow
application-specific tuning: windowing and offset, auto
black level correction, and on-board temperature sensor.
Optional register information and histogram statistic
information can be embedded in the first and last 2 lines of
the image frame.
The AR0237CS is designed to operate over a wide
temperature range of −30°C to +85°C ambient.
FUNCTIONAL OVER VIEW
The AR0237CS is a progressive-scan sensor that
generates a stream of pixel data at a constant frame rate. It
uses an on-chip, phase-locked loop (PLL) that can be
optionally enabled to generate all internal clocks from
a single master input clock running between 6 and 48 MHz.
The maximum output pixel rate is 148.5 Mp/s,
corresponding t o a clock rate of 74.25 MHz. Figure 1 shows
a block diagram of the sensor configured in linear mode, and
in HDR mode.
Figure 1. Block Diagram of AR0237CS
ADC Data
12
Row Noise Correction
Black Level Correction
Test Pattern Generator
Pixel Defect Correction
12
Digital Gain and Pedestal
10 bits
12 bits
HiSPi Parallel
A−Law Compression
User interaction with the sensor is through the two-wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor i s a 2 . 1 Mp Active-Pixel Sensor array. The timing and
control circuitry sequences through the rows of the array,
resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog-to-digital converter (ADC). The output from the
ADC is a 12-bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The sensor also offers a high dynamic range
mode of operation where two images and taken using
different exposures. These images are output in from the
sensor and the ISP must combine them into one high
dynamic range image.
AR0237CS
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TYPICAL CONFIGURATIONS
Figure 2. Serial 4-lane HiSPi Interface
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the AR0237 demo headboard
schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
Notes:
FLASH
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
VDD_PLLVDD_IO VAA VAA_PIX
AGND
DGND
VAA_PIXVAA
VDD_IO VDD
SDATA
SCLK
EXTCLK
1.5 kW2
1.5 kW2
TRIGGER
OE_BAR
RESET_BAR
TEST
To Controller
From
Controller
Master Clock
(6−48 MHz)
Digital
I/O
Power1
Digital
Core
Power1Analog
Power1Analog
Power1
Analog
Ground
Digital
Ground
SADDR
VDD_SLVS
HiSPi Power
either 0.4 V
(SLVS) or
1.8 V (HiVCM)1
VDD_PLL
PLL
Power1
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
VDD VDD_SLVS
SHUTTER
AR0237CS
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Figure 3. Parallel Pixel Data Interface
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
3. The serial interface output pads can be left unconnected if the parallel output interface is used.
4. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the AR0237 demo headboard
schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i
s
minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
7. The EXTCLK input is limited to 6−48 MHz.
Notes:
FRAME_VALID
LINE_VALID
PIXCLK
FLASH
VDD_IO VDD VAA VAA_PIX
AGND
DGND
VAA_PIXVAA
VDD_IO VDD
EXTCLK
SDATA
SCLK
1.5 kW2
1.5 kW2
TRIGGER
OE_BAR
RESET_BAR
TEST
To Controller
From
Controller
Master Clock
(6−48 MHz)
Digital
I/O
Power1
Digital
Core
Power1Analog
Power1Analog
Power1
Analog
Ground
Digital
Ground
DOUT[11:0]
SADDR
PLL
Power1
VDD_PLL
VDD_PLL
SHUTTER
AR0237CS
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PIN DESCRIPTIONS
Figure 4. 80-ball iBGA Package
A
B
C
D
E
F
G
H
J
123 567849
Top View
(Ball Down)
SLVS0_P SLVS1_P SLVSC_P SLVS2_P SLVS3_P VDD VDD_IO VDD
VDD_PLL SLVS0_N SLVS1_N SLVSC_N SLVS2_N SLVS3_N DGND DGND SHUTTER
VAA AGND DGND VDD_
SLVS VDD DGND DGND DGND Reserved
VDD DGND EXTCLK PIXCLK SADDR TRIGGER DGND AGND VAA
VDD_IO DGND SDATA FLASH FRAME_-
VALID SCLK DGND AGND VAA_PIX
VDD DGND DOUT11 DOUT10 DOUT9LINE_
VALID Reserved AGND VAA
VAA AGND DGND DOUT8D
OUT7D
OUT6D
GND DGND VDD_IO
VDD_IO DGND DGND DOUT5D
OUT4D
OUT3RESET_
BAR TEST VDD
DOUT2V
DD_IO DOUT1D
OUT0V
DD DGND VDD_IO OE_BAR VDD_IO
Table 3. PIN DESCRIPTIONS, 80-BALL IBGA
Name iBGA Pin Type Description
SLVS0_P A2 Output HiSPi serial data, lane 0, differential P
SLVS1_P A3 Output HiSPi serial data, lane 1, differential P
SLVSC_P A4 Output HiSPi serial DDR clock differential P
SLVS2_P A5 Output HiSPi serial data, lane 2, differential P
SLVS3_P A6 Output HiSPi serial data, lane 3, differential P
VDD_PLL B1 Power PLL power
SLVS0_N B2 Output HiSPi serial data, lane 0, differential N
AR0237CS
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Table 3. PIN DESCRIPTIONS, 80-BALL IBGA (continued)
Name DescriptionTypeiBGA Pin
SLVS1_N B3 Output HiSPi serial data, lane 1, differential N
SLVSC_N B4 Output HiSPi serial DDR clock differential N
SLVS2_N B5 Output HiSPi serial data, lane 2, differential N
SLVS3_N B6 Output HiSPi serial data, lane 3, differential N
SHUTTER B9 Output Control for external mechanical shutter. Can be left floating if not
used
VAA C1, G1, D9, F9 Power Analog power
AGND C2, G2, D8, E8, F8 Power Analog ground
VDD_SLVS C4 Power SLVS power 0.4 V/1.8 V depending on how R0x306E[9] is set.
0 = 0.4 V; 1 = 1.8 V
VDD C5, J5, A9, H9, A7, D1, F1 Power Digital power
Reserved C9, F7
DGND B7, C7, D7, E7, G7, B8, C8,
G8, D2, E2, F2, H2, C3,
G3, H3, C6, J6
Power Digital ground
EXTCLK D3 Input External input clock
PIXCLK D4 Output Pixel clock out. DOUT is valid on rising edge of this clock
SADDR D5 Input Two-wire Serial address select. 0: 0x20. 1: 0x30
TRIGGER D6 Input Exposure synchronization input
VAA_PIX E9 Power Pixel power
VDD_IO E1, H1, J2, J7, A8, G9, J9 Power I/O supply power
SDATA E3 I/O Two-wire Serial data I/O
FLASH E4 Output Flash control output
FRAME_VALID E5 Output Asserted when DOUT frame data is valid
SCLK E6 Input Two-wire Serial clock input
DOUT11 F3 Output Parallel pixel data output (MSB)
DOUT10 F4 Output Parallel pixel data output
DOUT9 F5 Output Parallel pixel data output
LINE_VALID F6 Output Asserted when DOUT line data is valid
DOUT8 G4 Output Parallel pixel data output
DOUT7 G5 Output Parallel pixel data output
DOUT6 G6 Output Parallel pixel data output
DOUT5 H4 Output Parallel pixel data output
DOUT4 H5 Output Parallel pixel data output
DOUT3 H6 Output Parallel pixel data output
RESET_BAR H7 Input Asynchronous reset (active LOW). All settings are restored to factory
default
TEST H8 Input Manufacturing test enable pin (connect to DGND)
DOUT2 J1 Output Parallel pixel data output
DOUT1 J3 Output Parallel pixel data output
DOUT0 J4 Output Parallel pixel data output (LSB)
OE_BAR J8 Input Output enable (active LOW)
AR0237CS
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Figure 5. 48-pin mPLCC Package HiSPi (Top Side View)
DGND
36x Thermal Connection Pads
DGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND DGND DGND DGND
DGND DGND DGND DGND DGND
DGND DGND DGND DGND
12345
6
7
8
9
10
11
12
13
14
15
16
17
1819
20 21 22 23 24 25 26 27 28 29
31
30
41
40
39
38
37
36
35
34
33
32
4342
44454647
48
VDD
DGND
AGND
VAA_PIX
VAA
Reserved
VAA
VAA_PIX
AGND
DGND
VDD
VDD_IO
VDD
SLVS3_P
SLVS3_N
SLVS2_P
SLVS2_N
SLVSC_P
SLVSC_N
SLVS1_P
SLVS1_N
SLVS0_P
SLVS0_N
VDD_SLVS
DGND
VDD_PLL
EXTCLK
VAA
AGND
VDD_IO
VDD
DGND
Reserved
VAA
AGND
DGND
VDD
VDD_IO
FLASH
TEST
SDATA
SADDR
SCLK
RESET_BAR
OE_BAR
TRIGGER
SHUTTER
VDD_IO
Table 4. PIN DESCRIPTIONS, 48-PIN MPLCC HISPI
Pin Name Type Description
1 SLVSC_N Output HiSPi serial DDR clock differential N
2 SLVS1_P Output HiSPi serial data, lane 1, differential P
3 SLVS1_N Output HiSPi serial data, lane 1, differential N
4 SLVS0_P Output HiSPi serial data, lane 0, differential P
5 SLVS0_N Output HiSPi serial data, lane 0, differential N
6 VDD_SLVS Power SLVS Power 0.4 V/1.8 V depending on how R0x306E[9] is set.
0 = 0.4 V; 1 = 1.8 V
7 DGND Power Digital ground
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Table 4. PIN DESCRIPTIONS, 48-PIN MPLCC HISPI (continued)
Pin DescriptionTypeName
8 VDD_PLL Power PLL power
9 EXTCLK Input External input clock
10 VAA Power Analog Power
11 AGND Power Analog Ground
12 VDD_IO Power I/O Power Supply
13 VDD Power Digital Power
14 DGND Power Digital ground
15 Reserved
16 VAA Power Analog Power
17 AGND Power Analog Ground
18 DGND Power Digital ground
19 VDD Power Digital Power
20 VDD_IO Power I/O Power Supply
21 FLASH Output Flash control output
22 TEST Input Manufacturing test enable pin (connect to DGND)
23 SDATA I/O Two-wire Serial data I/O
24 SADDR Input Two-wire Serial address select. 0: 0x20, 1: 0x30
25 SCLK Input Two-wire Serial clock input
26 RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default
27 OE_BAR Input Output enable (active LOW)
28 TRIGGER Input Exposure synchronization input
29 SHUTTER Output Control for external mechanical shutter. Can be left floating if not used.
30 VDD_IO Power I/O Power Supply
31 VDD Power Digital Power
32 DGND Power Digital ground
33 AGND Power Analog Ground
34 VAA_PIX Power Pixel Power
35 VAA Power Analog Power
36 Reserved
37 VAA Power Analog Power
38 VAA_PIX Power Pixel Power
39 AGND Power Analog Ground
40 DGND Power Digital ground
41 VDD Power Digital Power
42 VDD_IO Power I/O Power Supply
43 VDD Power Digital Power
44 SLSV3_P Output HiSPi serial data, lane 3, differential P
45 SLVS3_N Output HiSPi serial data, lane 3, differential N
46 SLVS2_P Output HiSPi serial data, lane 2, differential P
47 SLVS2_N Output HiSPi serial data, lane 2, differential N
48 SLVSLC_P Output HiSPi serial DDR clock differential P
AR0237CS
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Figure 6. 48-pin mPLCC Package Parallel (Top Side View)
DGND
29x Thermal Connection Pads
DGND DGND DGND DGND
12345
6
7
8
9
10
11
12
13
14
15
16
17
1819
20 21 22 23 24 25 26 27 28 29
31
30
41
40
39
38
37
36
35
34
33
32
4342
44454647
48
RESET_N
OUTPUT_
ENABLE_N
TRIGGER
SHUTTER
Reserved
AGND
VAA2V8
VAA2V8_PI
X
AGND
DGND
DVDD1V8
VDDIO2V8
R1V8
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT9
DOUT10
DOUT11
DGND
VDDIO2V8
R1V8_PLL
EXTCLK
VAA2V8
AGND
VDDIO2V8
R1V8
VDD1V8
DGND
Reserved
VAA2V8
AGND
DVDD1V8
VDDIO2V8
R1V8
FLASH
PIXCLK
FRAME_VALID
TEST
DGND
SDATA
LINE_VALID
SADDR
SCLK
VDDIO2V8
R1V8
DVDD1V8
DGND DGND DGND DGND
DGND DGND DGND DGND DGND
DGND DGND DGND DGND DGND
DGND DGND DGND DGND DGND
DGND DGND DGND DGND DGND
Table 5. PIN DESCRIPTIONS, 48-PIN MPLCC HISPI
Pin Name Type Description
1 DOUT6 Output Data output 6
2 DOUT7 Output Data output 7
3 DOUT8 Output Data output 8
4 DOUT9 Output Data output 9
5 DOUT10 Output Data output 10
6 DOUT11 Power Data output 11
7 DGND Power Digital ground
8 VDD_PLL Power PLL power
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Table 5. PIN DESCRIPTIONS, 48-PIN MPLCC HISPI (continued)
Pin DescriptionTypeName
9 EXTCLK Input External input clock
10 VAA Power Analog Power
11 AGND Power Analog Ground
12 VDD_IO Power I/O Power Supply
13 VDD Power Digital Power
14 DGND Power Digital ground
15 Reserved
16 VAA Power Analog Power
17 AGND Power Analog Ground
18 VDD Power Digital Power
19 VDD_IO Power I/O Power Supply
20 FLASH Power Flash control output
21 PIXCLK Output Pixel Clock
22 FRAME_VALID Output Frame Valid
23 TEST Input Manufacturing test enable pin (connect to DGND)
24 DGND Power Digital Ground
25 SDATA I/O Two-wire Serial data I/O
26 LINE_VALID Output Line Valid
27 SADDR Input Two-wire Serial address select. 0: 0x20, 1: 0x30
28 SCLK Input Two-wire Serial clock input
29 VDD_IO Power I/O Power Supply
30 VDD Power Digital Power
31 RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default
32 OE_BAR Input Output enable (active LOW)
33 TRIGGER Input Exposure synchronization input
34 SHUTTER Output Control for external mechanical shutter. Can be left floating if not used.
35 Reserved Input
36 AGND Power Analog Ground
37 VAA_2V8 Power Analog Power
38 VAA_PIX Power Pixel Power
39 AGND Power Analog Ground
40 DGND Power Digital ground
41 VDD Power Digital Power
42 VDD_IO Power I/O Power Supply
43 DOUT0 Output Data Output 0
44 DOUT1 Output Data Output 1
45 DOUT2 Output Data Output 2
46 DOUT3 Output Data Output 3
47 DOUT4 Output Data Output 4
48 DOUT5 Output Data Output 5
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PIXEL DATA FORMAT
Pixel Array Structure
While the sensor’s format is 1928 ×1088, additional
active columns and active rows are included for use when
horizontal or vertical mirrored readout is enabled, to allow
readout to start on the same pixel. The pixel adjustment is
always performed for monochrome or color versions. The
active area is surrounded with optically transparent dummy
pixels to improve image uniformity within the active area.
Not all dummy pixels or barrier pixels can be read out.
Figure 7. Pixel Array Description
1944
1116
Light Dummy Pixel Active Pixel
10 Barrier + 4 Border Pixels
1928 × 1088
5.78 × 3.26 mm
2 Barrier + 6 Border Pixels
10 Barrier + 4 Border Pixels
2 Barrier + 6 Border Pixels
Figure 8. Pixel Color Pattern Detail (RGB) (Top Right Corner)
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
Column Readout Direction
Row Readout Direction
Active Pixel (0, 0)
Array Pixel (0, 0)
…
…
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Figure 9. Pixel Color Pattern Detail (RGB−IR) (Top Right Corner)
GB
G
R
Column Readout Direction
Row Readout Direction
Active Pixel (0, 0)
Array Pixel (0, 0)
…
…
GBRGG
IR GIR GIR GIR
G
RGBRGG
IR GIR GIR GIR
GB
Default Readout Order
By convention, the sensor core pixel array is shown with
pixel (0,0) in the top right corner (see Figure 8). This reflects
the actual layout of the array on the die. Also, the first pixel
data read out of the sensor in default condition is that of
pixel (10, 14).
When the sensor is imaging, the active surface of the
sensor faces the scene as shown in Figure 10. When the
image is read out of the sensor, it is read one row at a time,
with the rows and columns sequenced as shown in
Figure 10.
Figure 10. Imaging a Scene
Lens
Pixel (0,0)
Row
Readout
Order
Column Readout Order
Scene
Sensor (Rear View)
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FEATURES OVERVIEW
For a complete description, recommendations, and usage
guidelines for product features, refer to the AR0237
Developer Guide.
3.0 mm Dual Conversion Gain Pixel
To improve the low light performance and keep the high
dynamic range, a lar ge (3.0 mm) dual conversion gain pixel
is implemented for better image optimization. With a dual
conversion gain pixel, the conversion gain of the pixel may
be dynamically changed to better adapt the pixel response
based on dynamic range of the scene.
HDR
By default, the sensor powers up in Linear Mode. One can
change to HDR Mode. The HDR scheme used is
multi-exposure HDR. This allows the sensor to handle up t o
96 dB of dynamic range. In HDR mode, the sensor
sequentially captures two exposures by maintaining two
separate read and reset pointers that are interleaved within
the rolling shutter readout. The exposure ratio may be set to
4×, 8 ×, 16×, or 32×. Sensor also provides flexibility to choose
any exposure ratio by setting number of t2 exposure rows
independent of the t1 exposure. The data will be output as
line interleaved data as described in the T1/T2 Line
Interleaved Mode section. There is also an option to output
either T1 only or T2 only.
Resolution
The active array supports a maximum of 1928 ×1088
pixels to support 1080p resolution. Utilizing a 3.0um pixel
will result in an optical format of 1/2.7-inch (approximately
6.6 mm diagonal).
Frame Rate
At full (1080p) resolution, the AR0237 is capable of
running up to 60 fps in linear mode and 30 fps in line
interleaved mode.
Image Acquisition Mode
The AR0237 supports two image acquisition modes:
•Electronic Rolling Shutter (ERS) Mode:
This is the normal mode of operation. When the
AR0237 is streaming, it generates frames at a fixed
rate, and each frame is integrated (exposed) using the
ERS. When ERS mode is in use, timing and control
logic within the sensor sequences through the rows of
the array, resetting and then reading each row in turn. In
the time interval between resetting a row and
subsequently reading that row, the pixels in the row
integrate incident light. The integration (exposure) time
is controlled by varying the time between row reset and
row readout. For each row in a frame, the time between
row reset and row readout is the same, leading to
a uniform integration time across the frame. When the
integration time is changed (by using the two-wire
serial interface to change register settings), the timing
and control logic controls the transition from old to new
integration time in such a way that the stream of output
frames from the AR0237 switches cleanly from the old
integration time to the new while only generating
frames with uniform integration. See “Changes to
Integration Time” in the AR0237 Register Reference.
•Global Reset Mode:
This mode can be used to acquire a single image at the
current resolution. In this mode, the end point of the
pixel integration time is controlled by an external
electromechanical shutter, and the AR0237 provides
control signals to interface to that shutter. The benefit
of using an external electromechanical shutter is that it
eliminates the visual artifacts associated with ERS
operation. Visual artifacts arise in ERS operation,
particularly at low frame rates, because an ERS image
effectively integrates each row of the pixel array at
a different point in time.
Embedded Data and Statistics
The AR0237 has the capability to output image data and
statistics embedded within the frame timing. There are two
types of information embedded within the frame readout.
•Embedded Data:
If enabled, these are displayed on the two rows
immediately before the first active pixel row is
displayed.
•Embedded Statistics:
If enabled, these are displayed on the two rows
immediately after the last active pixel row is displayed.
Multi-Camera Synchronization
The AR0237 supports advanced line synchronization
controls for multi-camera (stereo) support.
Slave Mode
The slave mode feature of the AR0237 supports triggering
the start of a frame readout from an input signal that is
supplied from an external ASIC. The slave mode signal
allows for precise control of frame rate and register change
updates.
Context Switching and Register Updates
The user has the option of using the highly configurable
context memory, or a simplified implementation in which
only a subset of registers is available for switching.
The AR0237 supports a highly configurable context
switching RAM of size 256 ×16. Within this Context
Memory, changes to any register may be stored. The register
set for each context must be the same, but the number of
contexts and registers per context are limited only by the size
of the context memory.
Alternatively, the user may switch between two
predefined register sets A and B by writing to a context
switch change bit. When the context switch is configured to
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context A the sensor will reference the context A registers.
If the context switch is changed from A to B during the
readout of frame n, the sensor will then reference the
context B coarse_integration_time registers in frame n+1
and all other context B registers at the beginning of reading
frame n+2. The sensor will show the same behavior when
changing from context B to context A. The registers listed
in Table 6 are context-switchable:
Table 6. LIST OF CONFIGURABLE RESISTORS FOR CONTEXT A AND CONTEXT B
Context A
Register Description Context B
Register Description
coarse_integration_time coarse_integration_time_cb
line_length_pck line_length_pck_cb
frame_length_lines frame_length_lines_cb
row_bin row_bin_cb
col_bin col_bin_cb
fine_gain fine_gain_cb
coarse_gain coarse_gain_cb
coarse_integration_time2 coarse_integration_time2_cb
dcg_manual_set dcg_manual_set_cb
dcg_manual_set_t1 dcg_manual_set_t1_cb
bypass_pix_comb bypass_pix_cb
coarse_gain_t1 coarse_gain_t1_cb
fine_gain_t1 fine_gain_t1_cb
x_addr_start x_addr_start_cb
y_addr_start y_addr_start_cb
x_addr_end x_addr_end_cb
y_addr_end y_addr_end_cb
y_odd_inc y_odd_inc_cb
x_odd_inc x_odd_inc_cb
green1_gain green1_gain_cb
blue_gain blue_gain_cb
red_gain red_gain_cb
green2_gain green2_gain_cb
global_gain global_gain_cb
operation_mode_ctrl operation_mode_ctrl_cb
bypass_pix_comb bypass_pix_comb_cb
Analog/Digital Gains
A programmable analog gain of 1.0× to 16× (linear and
HDR) applied simultaneously to all color channels will be
featured along with a digital gain of 1× to 16× that may be
configured on a per color channel basis. Note that with the
RGB IR sensor digital gain should only be applied to all
color channels equally since with the 4 ×4 kernel the gains
will not be applied to the proper color channel. Analog gain
can be applied per exposure in line interleaved mode.
Skipping/Binning Modes
The AR0237 supports subsampling. Subsampling allows
the sensor to read out a smaller set of active pixels by either
skipping, binning, or summing pixels within the readout
window. Horizontal binning is achieved in the digital
readout. The sensor will sample the combined 2× adjacent
pixels within the same color plane. Vertical row binning is
applied in the pixel readout. Row binning can be configured
as 2× rows within the same color plane. Pixel skipping can
be configured up to 2× in both the x-direction and
y-direction. Skipping pixels in the x-direction will not
reduce the row time. Skipping pixels in the y direction will
reduce the number of rows from the sensor effectively
reducing the frame time. Skipping will introduce image
artifacts from aliasing.
The AR0237 supports row wise vertical binning. Row
wise vertical summing is only supported in monochrome
sensors.
Binning and summing is not supported with RGB IR
sensors.
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Clocking Options
The sensor contains a phase-locked loop (PLL) that is
used for timing generation and control. The required VCO
clock frequency is attained through the use of a pre-PLL
clock divider followed by a multiplier. The PLL multiplier
should be an even integer. If an odd integer (M) is
programmed, the PLL will default to the lower (M−1) value
to maintain an even multiplier value. The multiplier is
followed by a set of dividers used to generate the output
clocks required for the sensor array, the pixel analog and
digital readout paths, and the output parallel and serial
interfaces. Use of the PLL is required when using the HiSPi
interface.
Temperature Sensor
The AR0237 sensor has a built-in PTAT-based
temperature sensor, accessible through registers, that is
capable of measuring die junction temperature. The value
read out from the temperature sensor register is an ADC
output value that needs to be converted downstream to a
final temperature value in degrees Celsius. Since the PTAT
device characteristic response is quite linear in the
temperature range of operation required, a simple linear
function can be used to convert the ADC output value to the
final temperature in degrees Celsius.
A single reference point will be made available via
register read as well as a slope for back-calculating the
junction temperature value. An error of ±5% or better over
the full specified operating range of the sensor is to be
expected.
Silicon/Firmware/Sequencer Revision Information
A revision register will be provided to read out (via I2C)
silicon and sequencer/OTPM revision information. This
will be helpful to distinguish among dif ferent lots of material
if there are future OTPM or sequencer revisions.
Lens Shading Correction
The latest lens shading correction algorithm will be
included for potential low Z height applications.
Compression
When the AR0237 is configured for linear mode
operation, the sensor can optionally compress 12-bit data to
10-bit using A−law compression. The A−law compression
is disabled by default.
Packaging
The AR0237 will be offered in a 10 ×10 80-iBGA
package (parallel and HiSPi) and a 11.43 ×1143 48 pin
mPLCC (HiSSPi) package.
Parallel Interface
The parallel pixel data interface uses these output−only
signals:
•FRAME_VALID
•LINE_VALID
•PIXCLK
•DOUT[11:0]
The parallel pixel data interface is disabled by default at
power up and after reset. It can be enabled by programming
R0x301A. When the parallel pixel data interface is in use,
the serial data output signals can be left unconnected.
High Speed Serial Pixel (HiSPi) Interface
The HiSPi interface supports three protocols,
Streaming−S, Streaming−SP, and Packetized SP. The
streaming protocols conform to a standard video application
where each line of active or intra-frame blanking provided
by the sensor is transmitted at the same length. The
Packetized SP protocol will transmit only the active data
ignoring line-to-line and frame-to-frame blanking data.
The HiSPi interface building block is a unidirectional
differential serial interface with four data and one double
data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple
lanes. The AR0237 supports serial data widths of 10 or
12 bits on one, two, or four lanes. The specification includes
a DLL to compensate for differences in group delay for each
data lane. The DLL is connected to the clock lane and each
data lane, which acts as a control master for the output delay
buffers. Once the DLL has gained phase lock, each lane can
be delayed in 1/8 unit interval (UI) steps. This additional
delay al l o w s t h e u s e r t o i n c r e a s e t h e s e t u p o r h o l d time at the
receiver circuits and can be used to compensate for skew
introduced in PCB design. Delay compensation may be set
for clock and/or data lines in the hispi_timing register
R0x31C0. If the DLL timing adjustment is not required, the
data and clock lane delay settings should be set to a default
code of 0x0000 to reduce jitter, skew, and power dissipation.
Sensor Control Interface
The two-wire serial interface bus enables read/write
access to control and status registers within the AR0237.
The interface protocol uses a master/slave model in which
a master controls one or more slave devices. The sensor acts
as a slave device. The master generates a clock (SCLK) that
is an input to the sensor and is used to synchronize transfers.
Data is transferred between the master and the slave on
a bidirectional signal (SDATA). SDATA is pulled up to
VDD_IO off-chip by a 1.5 kW resistor. Either the slave or
master device can drive SDATA LOW − the interface protocol
determines which device is allowed to drive SDATA at any
given time. The two-wire serial interface can run at 100 kHz
or 400 kHz.
T1/T2 Line Interleaved Mode
The AR0237 outputs the T1 and T2 exposures separately,
in a line interleaved format. The purpose of this is to enable
off chip HDR linear combination and processing. See the
AR0237 Developer Guide for more information.
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Figure 11. Quantum Efficiency − RGB Packaged Part
Wavelength (nm)
350
Quantum Efficiency (%)
450 550 650 750 850 950 1050 1150
0
10
20
30
40
50
60
70
Red
Green (R)
Green (B)
Blue
Figure 12. Quantum Efficiency − RGB−IR Packaged Part
Wavelength (nm)
350
Quantum Efficiency (%)
450 550 650 750 850 950 1050 1150
0
10
20
30
40
50
60
70
Red
Green (R)
Green (B)
Blue
IR
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CRA vs. Image Height Plot
Image Height CRA
(%) (mm) (deg)
Chief Ray Angle (Deg)
Image Height (%)
AR0237 CRA Characteristic
0 102030405060708090100110
0
2
4
6
8
10
12
14
16
Figure 13. Chief Ray Angle Characteristics
0 0 0
5 0.166 0.62
10 0.332 1.24
15 0.498 1.86
20 0.664 2.48
25 0.830 3.10
30 0.996 3.72
35 1.162 4.34
40 1.328 4.96
45 1.494 5.58
50 1.660 6.20
55 1.826 6.82
60 1.992 7.44
65 2.158 8.06
70 2.324 8.68
75 2.491 9.30
80 2.657 9.92
85 2.823 10.54
90 2.989 11.16
95 3.155 11.78
100 3.321 12.40
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ELECTRICAL SPECIFICATIONS
Unless otherwise stated, the following specifications
apply under the following conditions:
VDD = 1.8 V – 0.10/+0.15;
VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8 V ± 0.3 V;
VDD_SLVS = 0.4 V – 0.1/+0.2;
TA = −30°C to +85°C−40°C to +105°C;
Output load = 10 pF;
Frequency = 74.25 MHz;
HiSPi off.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial
register interface (SCLK, SDATA) are shown in Figure 14 and
Table 7.
Figure 14. Two-Wire Serial Bus Timing Parameters
SDATA
SCLK
S Sr P S
tftrtftr
tSU;DAT tHD;STA
tSU;STO
tSU;STA
tBUF
tHD;DAT tHIGH
tLOW
tHD;STA
NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued.
Table 7. TWO-WIRE SERIAL BUS CHARACTERISTICS
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V ; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25°C)
Parameter Symbol
Standard Mode Fast Mode
Unit
Min Max Min Max
SCLK Clock Frequency fSCL 0 100 0 400 kHz
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated
tHD;STA 4.0 − 0.6 − ms
LOW Period of the SCLK Clock tLOW 4.7 − 1.3 − ms
HIGH Period of the SCLK Clock tHIGH 4.0 − 0.6 − ms
Set-up Time for a Repeated
START Condition tSU;STA 4.7 − 0.6 − ms
Data Hold Time tHD;DAT 0 (Note 4) 3.45 (Note 5) 0 (Note 6) 0.9 (Note 5) ms
Data Set-up Time tSU;DAT 250 − 100 (Note 6) − ns
Rise Time of both SDATA and
SCLK Signals tr− 1000 20 + 0.1 Cb
(Note 7) 300 ns
Fall Time of both SDATA and SCLK
Signals tf− 300 20 + 0.1 Cb
(Note 7) 300 ns
Set-up Time for STOP Condition tSU;STO 4.0 − 0.6 − ms
Bus Free Time between a STOP
and START Condition tBUF 4.7 − 1.3 − ms
Capacitive Load for each Bus Line Cb − 400 − 400 pF
Serial Interface Input Pin
Capacitance CIN_SI − 3.3 − 3.3 pF
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Table 7. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V ; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25°C)
Parameter Unit
Fast ModeStandard Mode
Symbol
Parameter Unit
MaxMinMaxMin
Symbol
SDATA Max Load Capacitance CLOAD_SD − 30 − 30 pF
SDATA Pull-up Resistor RSD 1.5 4.7 1.5 4.7 kW
1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I2C-compatible.
3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1 VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT = 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period
of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the AR0237 launches pixel data, FV, and LV
with the falling edge of PIXCLK. The expectation is that the
user captures DOUT[1 1:0], F V, and LV using the rising edge
of PIXCLK.
See Figure 15 below and Table 8 for I/O timing (AC)
characteristics.
Figure 15. I/O Timing Diagram
EXTCLK
PIXCLK
Data[11:0]
LINE_VALID/
FRAME_VALID
Pxl_0 Pxl_1 Pxl_2 Pxl_n
tPF
L
tPL
L
tFP
tRP
tF
tR
90% 90% 90% 90%
10% 10% 10% 10%
tEXTCLK
tPD
tPLH
tPFH FRAME_VALID Leads LINE_VALID
by 6 PIXCLKs FRAME_VALID Trails LINE_VALID
by 6 PIXCLKs
Table 8. I/O TIMING CHARACTERISTICS
(I/O timing characteristics are measured under the following conditions: Temperature is 25°C Ambient; 10 pF Load; 1.8 V I/O Supply
Voltage)
Symbol Definition Condition Min Typ Max Unit
fEXTCLK1s Input Clock Frequency 6 – 48 MHz
tEXTCLK1 Input Clock Period 20.8 – 166 ns
tRInput Clock Rise Time – 3 – ns
tFInput Clock Fall Time – 3 – ns
tRP Pixclk Rise Time 2 3.5 5 ns
tFP Pixclk Fall Time 2 3.5 5 ns
Clock Duty Cycle 45 50 55 %
tCP EXTCLK to PIXCLK Propagation Delay Nominal Voltages, PLL Disabled 10 14 18 ns
fPIXCLK PIXCLK Frequency Default, Nominal Voltages 6 – 74.25 MHz
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Table 8. I/O TIMING CHARACTERISTICS (continued)
(I/O timing characteristics are measured under the following conditions: Temperature is 25°C Ambient; 10 pF Load; 1.8 V I/O Supply
Voltage)
Symbol UnitMaxTypMinConditionDefinition
tPD PIXCLK to Data Valid Default, Nominal Voltages 0 2.5 5 ns
tPFH PIXCLK to FV HIGH Default, Nominal Voltages −2 3 6 ns
tPLH PIXCLK to LV HIGH Default, Nominal Voltages −2 3 6 ns
tPFL PIXCLK to FV LOW Default, Nominal Voltages −2 2.5 6 ns
tPLL PIXCLK to LV LOW Default, Nominal Voltages −2 2.5 6 ns
CLOAD Output Load Capacitance –<10 – pF
CIN Input Pin Capacitance – 2.5 – pF
DC Electrical Characteristics
The DC electrical characteristics are shown in the tables
below.
Table 9. DC ELECTRICAL CHARACTERISTICS
Symbol Definition Condition Min Typ Max Unit
VDD Core Digital Voltage 1.7 1.8 1.95 V
VDD_IO I/O Digital Voltage 1.7/2.5 1.8/2.8 1.9/3.1 V
VAA Analog Voltage 2.5 2.8 3.1 V
VAA_PIX Pixel Supply Voltage 2.5 2.8 3.1 V
VDD_PLL PLL Supply Voltage 2.5 2.8 3.1 V
VDD_SLVS HiSPi Supply Voltage 0.3 0.4 0.6 V
VIH Input HIGH Voltage VDD_IO ×0.7 – – V
VIL Input LOW Voltage – – VDD_IO ×0.3 V
IIN Input leakage Current No Pull-up Resistor;
VIN = VDD_IO or DGND 20 – – mA
VOH Output HIGH Voltage VDD_IO − 0.3 – – V
VOL Output LOW Voltage – – 0.4 V
IOH Output HIGH Current At Specified VOH −22 – – mA
IOL Output LOW Current At Specified VOL – – 22 mA
Table 10. ABSOLUTE MAXIMUM RATINGS
Symbol Definition Condition Min Max Unit
VDD_MAX Core Digital Voltage –0.3 2.4 V
VDD_IO_MAX I/O Digital Voltage –0.3 4 V
VAA_MAX Analog Voltage –0.3 4 V
VAA_PIX Pixel Supply Voltage –0.3 4 V
VDD_PLL PLL Supply Voltage –0.3 4 V
VDD_SLVS_MAX HiSPi I/O Digital Voltage –0.3 2.4 V
tST Storage Temperature –40 85 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
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Table 11. 1080p30 LINEAR 74 MHZ PARALLEL 2.8 V
(Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = VDD_IO = 2.8 V; VDD = 1.8 V; PLL
Enabled and PIXCLK = 74.25 MHz; Low power mode enabled; TA = 25°C)
Definition Condition Symbol Voltage Min Typ Max Unit
Digital Operating Current Streaming 1080p30 IDD 1.8 20 34 50 mA
I/O Digital Operating Current Streaming 1080p30 IDD_IO 2.8 15 28 50 mA
Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA
Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA
PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 5.5 6.4 7 mA
Power 138.2 238.72 409.2 mW
Table 12. 1080p30 LINEAR 74 MHZ PARALLEL 1.8 V
(Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V; PLL
Enabled and PIXCLK = 74.25 MHz; Low power mode enabled; TA = 25°C Dark Image, 8× Analog Gain, HCG, 20 ms integration time)
Definition Condition Symbol Voltage Min Typ Max Unit
Digital Operating Current Streaming 1080p30 IDD 1.8 20 34 50 mA
I/O Digital Operating Current Streaming 1080p30 IDD_IO 1.8 10 14 30 mA
Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA
Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA
PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 5.5 6.4 7 mA
Power 114.2 185.52 323.2 mW
Table 13. 1080p30 LINEAR 74 MHZ HISPI SLVS
(Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V;
VDD_SLVS = 0.4 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; Low power mode enabled; TA = 25°C Dark Image,
8× Analog Gain, HCG, 20 ms integration time)
Definition Condition Symbol Voltage Min Typ Max Unit
Digital Operating Current Streaming 1080p30 IDD 1.8 25 44 65 mA
Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA
Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA
PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 6 7.5 8.5 mA
SLVS Supply Current Streaming 1080p30 IDD_SLVS 0.4 6 9.5 14 mA
Power 109 185.2 306 mW
Table 14. 1080p30 LINEAR 74 MHZ HISPI HIVCM
(Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = VDD_SLVS =
1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; Low power mode enabled; TA = 25°C Dark Image, 8× Analog Gain,
HCG, 20 ms integration time)
Definition Condition Symbol Voltage Min Typ Max Unit
Digital Operating Current Streaming 1080p30 IDD 1.8 25 44 65 mA
Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA
Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA
PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 6 7.5 8.5 mA
SLVS Supply Current Streaming 1080p30 IDD_SLVS 1.8 12 20 35 mA
Power 128.2 217.4 363.4 mW
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Table 15. 1080p60 LINEAR 74 MHZ LINEAR SLVS
(Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V;
VDD_SLVS = 0.4 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; TA= 25°C Dark Image, 8× Analog Gain, HCG, 20 ms
integration time)
Definition Condition Symbol Voltage Min Typ Max Unit
Digital Operating Current Streaming 1080p60 IDD 1.8 50 88 130 mA
Analog Operating Current Streaming 1080p60 IAA 2.8 20 36 60 mA
Pixel Supply Current Streaming 1080p60 IAA_PIX 2.8 1 4 8 mA
PLL Supply Current Streaming 1080p60 IDD_PLL 2.8 7 8.5 9.5 mA
SLVS Supply Current Streaming 1080p60 IDD_SLVS 0.4 6 9.5 14 mA
Power 170.8 298 442.6 mW
Table 16. 1080p60 LINEAR 74 MHZ LINEAR HIVCM
(Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V;
VDD_SLVS = 1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; TA= 25°C Dark Image, 8× Analog Gain, HCG, 20 ms
integration time)
Definition Condition Symbol Voltage Min Typ Max Unit
Digital Operating Current Streaming 1080p60 IDD 1.8 50 88 130 mA
Analog Operating Current Streaming 1080p60 IAA 2.8 20 36 60 mA
Pixel Supply Current Streaming 1080p60 IAA_PIX 2.8 1 4 8 mA
PLL Supply Current Streaming 1080p60 IDD_PLL 2.8 7 8.5 9.5 mA
SLVS Supply Current Streaming 1080p60 IDD_SLVS 1.8 12 20 35 mA
Power 190 330.2 500 mW
Table 17. 1080p30 LINEAR 74 MHZ LINE INTERLEAVED SLVS
(Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V;
VDD_SLVS = 0.4 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; TA= 25°C Dark Image, 8× Analog Gain, HCG, 20 ms
integration time)
Definition Condition Symbol Voltage Min Typ Max Unit
Digital Operating Current Streaming 1080p30 IDD 1.8 50 88 130 mA
Analog Operating Current Streaming 1080p30 IAA 2.8 20 36 60 mA
Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 4 8 mA
PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 7 8.5 9.5 mA
SLVS Supply Current Streaming 1080p30 IDD_SLVS 0.4 6 9.5 14 mA
Power 170.8 298 442.6 mW
Table 18. 1080p30 LINEAR 74 MHZ LINE INTERLEAVED HIVCM
(Operating currents are measured in mA at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V; VDD = VDD_IO = 1.8 V;
VDD_SLVS = 1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; 4-lane HiSPi mode; TA= 25°C Dark Image, 8× Analog Gain, HCG, 20 ms
integration time)
Definition Condition Symbol Voltage Min Typ Max Unit
Digital Operating Current Streaming 1080p30 IDD 1.8 50 88 130 mA
Analog Operating Current Streaming 1080p30 IAA 2.8 20 36 60 mA
Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 4 8 mA
PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 7 8.5 9.5 mA
SLVS Supply Current Streaming 1080p30 IDD_SLVS 1.8 12 20 35 mA
Power 190 330.2 500 mW
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HiSPi Electrical Specifications
The ON Semiconductor AR0237 sensor supports both
SLVS and HiVCM HiSPi modes. Refer to the High-Speed
Serial Pixel (HiSPi) Interface Physical Layer Specification
v2.00.00 for electrical definitions, specifications, and
timing information. The VDD_SLVS supply in this datasheet
corresponds to VDD_TX in the HiSPi Physical Layer
Specification. Similarly, VDD is equivalent to VDD_HiSPi
as referenced in the specification. The DLL as implemented
on AR0237 is limited in the number of available delay steps
and differs from the HiSPi specification as described in this
section.
Table 19. CHANNEL SKEW
(Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.4 V; Data Rate = 480 Mbps; DLL set to 0)
Definition Symbol Value Unit
Data Lane Skew in Reference to Clock tCHSKEW1PHY −150 ps
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POWER-ON RESET AND STANDBY TIMING
Power-Up Sequence
The recommended power-up sequence for the AR0237 is
shown i n Figure 16. The available power supplies (VDD_IO,
VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have
the separation specified below.
1. Turn on VDD_PLL power supply.
2. After 100 ms, turn on VAA and VAA_PIX power
supply.
3. After 100 ms, turn on VDD_IO power supply.
4. After 100 ms, turn on VDD power supply.
5. After 100 ms, turn on VDD_SLVS power supply.
6. After the last power supply is stable, enable
EXTCLK.
7. Assert RESET_BAR for at least 1 ms. The parallel
interface will be tri-stated during this time.
8. Wait 15,0000 EXTCLKs (for internal initialization
into software standby.
9. Configure PLL, output, and image settings to
desired values.
10. Wait 1 ms for the PLL to lock.
11. Set streaming mode (R0x301a[2] = 1).
Figure 16. Power Up
EXTCLK
VDD_SLVS (0.4)
VAA_PIX
VAA (2.8)
VDD_IO (1.8/2.8)
VDD (1.8)
VDD_PLL (2.8) t0
t1
t2
t3
t4t5t6
tXHard
Reset Internal
Initialization Software
Standby PLL Lock Streaming
RESET_BAR
Table 20. POWER-UP SEQUENCE
Symbol Definition Min Typ Max Unit
t0VDD_PLL to VAA/VAA_PIX (Note 3) 0 100 – ms
t1VAA/VAA_PIX to VDD_IO 0 100 – ms
t2VDD_IO to VDD 0 100 – ms
t3VDD to VDD_SLVS 0 100 – ms
tXXtal Settle Time –30 (Note 1) – ms
t4Hard Reset 1 (Note 2) – – ms
t5Internal Initialization 150000 – – EXTCLKs
t6PLL Lock Time 1 – – ms
1. Xtal settling time is component-dependent, usually taking about 10–100 ms.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
others. If the case happens that VDD_PLL is powered after other supplies then the sensor may have functionality issues and will experience
high current draw on this supply.
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Power-Down Sequence
The recommended power-down sequence for the AR0237
is shown in Figure 17. The available power supplies
(VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX)
must have the separation specified below.
1. Disable streaming if output is active by setting
standby R0x301a[2] = 0.
2. The soft standby state is reached after the current
row or frame, depending on configuration, has
ended.
3. Turn off VDD_SLVS.
4. Turn off V DD.
5. Turn off V DD_IO.
6. Turn off VAA/VAA_PIX.
7. Turn off VDD_PLL.
Figure 17. Power Down
EXTCLK
VDD_PLL (2.8)
VDD_IO (1.8/2.8)
VDD (1.8)
VDD_SLVS (0.4) t0
Power Down until Next
Power Up Cycle
t1
t2
t3
t4
VAA_PIX
VAA (2.8)
Table 21. POWER-DOWN SEQUENCE
Symbol Parameter Min Typ Max Unit
t0VDD_SLVS to VDD 0 – – ms
t1VDD to VDD_IO 0 – – ms
t2VDD_IO to VAA/VAA_PIX 0 – – ms
t3VAA/VAA_PIX to VDD_PLL 0 – – ms
t4Power Down until Next Power Up Time 100 – – ms
1. t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
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PACKAGE DIMENSIONS
PLCC48 11.43x11.43 (Parallel)
CASE 776AS
ISSUE O
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