dsPIC30F6011A/6012A/6013A/6014A
DS70143B-page 228 © 2005 Microchip Technology Inc.
D
Data Accumulators and Adder/Subtractor...........................21
Data Space Write Saturatio n .... ................... ...............23
Overflow and Saturation ......... .... .... ........... .... .... .........21
Round Logic................................................................22
Write Back...................................................................22
Data Address Space...........................................................31
Alignment....................................................................34
Alignment (Figure) ......................................................35
Effect of Invalid Memory Accesses (Table) .................34
MCU and DSP (MAC Class) Instructions Example.....34
Memory Map...............................................................31
Memory Map for dsPIC30F6011A/6013A...................32
Memory Map for dsPIC30F6012A/6014A...................33
Near Data Space ........................................................35
Softwa re Stack......... ....................... ................... .........35
Spaces........................................................................31
Width...........................................................................34
Data Converter Interface (DCI) Module .... ........................123
Data EEPROM Memory......................................................57
Erasing........................................................................58
Erasing, Block.............................................................58
Erasing, Word.............................................................58
Protection Agai n s t Spurious Write ............... ...............61
Reading.......................................................................57
Write Verify .................................................................61
Writing.........................................................................59
Writing , Block.................... ................... .......................60
Writing , Wo rd ..... ............... ................... ................... ....59
DC Characteristics............................................................175
Brown-out Reset ...............................................185, 186
I/O Pin Input Specifications.......................................183
I/O Pin Output Specifications....................................184
Idle Current (IIDLE) ....................................................180
Low-Voltage Detect...................................................184
LVDL.........................................................................185
Operating Current (IDD).............................................177
Power-Down Current (IPD)........................................182
Program and EEPROM.............................................186
DCI Module
Bit Clock Generator.......................................... .... .....127
Buffer Alignment with Data Frames..........................129
Buffe r Con trol............................ ................... .............123
Buffe r Data Alignment........................ .................. .....123
Buffer Length Control.................... ....... .... .. .. .... .. .......129
COFS Pin........................ ................... .................. .....123
CSCK Pin........................ ................... .................. .....123
CSDI Pin........ ............... .............. ............... ...............123
CSDO Mode Bit ........................................................130
CSDO Pin .................................................................123
Data Justification Control Bit.....................................128
Device Frequencies for Common Codec
CSCK Frequencies (Table)...............................127
Digital Loopback Mode ............................ .... .. .... .......130
Enable.......................................................................125
Frame Sync Generator .............................................125
Frame Sync Mode Control Bits.................................125
I/O Pi n s...... .............. ....................... ........................ ..123
Interrupts...................................................................130
Introduction ...............................................................123
Master Frame Sync Operation..................................125
Operation ..................................................................125
Operation During CPU Idle Mode.............................130
Operation During CPU Sleep Mode..........................130
Receive Slot Enable Bits............................ .... .. .... .....128
Receive St a tu s Bits............... ................... ................. 129
Register Map ..... ................... ................... ................. 132
Sample Clock Edge Control Bit ................. ....... .... .. .. 128
Slave Fra me Sync Opera tion..... .................. ............. 12 6
Slot Enable Bits Operation with Frame Sync . ........... 128
Slot St a tus Bits......... ................... ....................... ......130
Synchronous Data Transfers.................................... 128
Timing Characteristics
AC-Li n k Mode............... ....................... ............. 200
Multichannel, I2S Modes................ .. .... ..... .. .. .. .. 198
Timing Requirements
AC-Li n k Mode............... ....................... ............. 200
Multichannel, I2S Modes................ .. .... ..... .. .. .. .. 199
Transmit Slot Enable Bits ......................................... 128
Transmit Status Bits.................................................. 129
Transmit/Receive Shift Register............................... 123
Underflow Mode Control Bit................... .. .... ....... .. .. ..130
Word Size Selection Bits.......................................... 125
Development Support....................................................... 171
Device Configuration
Register Map ..... ................... ....................... ............. 161
Device Configuration Registers........................................ 159
FBORPOR................................................................ 159
FGS .......................................................................... 159
FOSC........................................................................ 159
FWDT ....................................................................... 159
Device Overview1, 9, 15, 25, 39, 45, 51, 57, 63, 69, 73, 79, 83,
87, 91, 95, 103, 111, 123, 133, 163
Disabling th e UART.......... .............. ............... ............... .... 105
Divide Support . .. .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. 18
Instruction s (Ta b l e )......... ................... ................... ...... 18
DSP Engine.................... ....................... ....................... ...... 1 9
Multiplier ..................................................................... 21
Dual Output Compare Match Mod e........................ ............ 88
Continuous Pulse Mode....................... .... .. ....... .... .... .. 88
Single Pulse Mode ...................................................... 88
E
Electrical Characteristics .................................................. 175
AC............................................................................. 187
DC ............................................................................ 175
Enabling and Setting Up UART
Setting Up Data, Parity and Stop Bit Selections....... 105
Enabling the UART........................................................... 105
Equations
ADC Convers io n Cl o ck..... ........... ................... .......... 135
Baud Rate................................................................. 107
Bit Clock Frequency................................... ........... .... 127
COFSG Perio d ...................... ....................... ............. 125
Serial Clock Rate...................................................... 100
Time Quantum for Clock Generation...................... .. 117
Errata.................................................................................... 8
External Clock Timing Characteristics
Type A, B and C Timer............................................. 194
Exter n a l C l o c k Timi n g Requireme n ts ....... ...... ...... ..... ...... . 188
Type A Timer............................................................ 194
Type B Timer............................................................ 195
Type C Timer............................................................ 195
External Interrupt Requests................................................ 49