EFM32 Leopard Gecko Family EFM32LG Data Sheet The EFM32 Leopard Gecko MCUs are the world's most energyfriendly microcontrollers. The EFM32LG offers unmatched performance and ultra low power consumption in both active and sleep modes. EFM32LG devices consume as little as 0.65 A in Stop mode and 211 A/MHz in Run mode. It also features autonomous peripherals, high overall chip and analog integration, and the performance of the industry standard 32-bit ARM CortexM3 processor, making it perfect for battery-powered systems and systems with high-performance, low-energy requirements. ARM Cortex M3 processor Clock Management Memory Protection Unit Flash Program Memory Debug w/ ETM RAM Memory DMA Controller * Ultra low power operation * 0.65 A current in Stop (EM3), with brown-out detection and RAM retention * 63 A/MHz in EM1 * 211 A/MHz in Run mode (EM0) * Hardware cryptography (AES) * Alarm and security systems * Industrial and home automation Core / Memory TM * ARM Cortex-M3 at 48 MHz * Fast wake-up time of 2 s EFM32LG applications include the following: * Energy, gas, water and smart metering * Health and fitness applications * Smart accessories KEY FEATURES * Up to 256 kB of Flash and 32 kB of RAM Energy Management High Frequency Crystal Oscillator High Frequency RC Oscillator Voltage Regulator Voltage Comparator Auxiliary High Freq. RC Osc. Low Freq. RC Oscillator Brown-out Detector Power-on Reset Low Frequency Crystal Oscillator Ultra Low Freq. RC Oscillator Back-up Power Domain Security Hardware AES 32-bit bus Peripheral Reflex System Serial Interfaces USART Low Energy UARTTM UART I2C USB I/O Ports External Bus Interface Timers and Triggers TFT Driver External Interrupts General Purpose I/O Pin Reset Pin Wakeup Timer/Counter LESENSE Low Energy Timer Real Time Counter Pulse Counter Watchdog Timer Analog Interfaces ADC LCD Controller DAC Operational Amplifier Analog Comparator Back-up RTC Lowest power mode with peripheral operational: EM0 - Active silabs.com | Building a more connected world. EM1 - Sleep EM2 - Deep Sleep EM3 - Stop EM4 - Shutoff Rev. 2.20 EFM32LG Data Sheet Feature List 1. Feature List * ARM Cortex-M3 CPU platform * High Performance 32-bit processor @ up to 48 MHz * Memory Protection Unit * Wake-up Interrupt Controller * SysTick System Timer * Flexible Energy Management System * 20 nA @ 3 V Shutoff Mode * 0.4 A @ 3 V Shutoff Mode with RTC * 0.65 A @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention * 0.95 A @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU retention * 63 A/MHz @ 3 V Sleep Mode * 211 A/MHz @ 3 V Run Mode, with code executed from flash * 256/128/64 kB Flash * 32 kB RAM * Up to 93 General Purpose I/O pins * Configurable push-pull, open-drain, pull-up/down, input filter, drive strength * Configurable peripheral I/O locations * 16 asynchronous external interrupts * Output state retention and wake-up from Shutoff Mode * 12 Channel DMA Controller * 12 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling * Hardware AES with 128/256-bit keys in 54/75 cycles * Timers/Counters * 4x 16-bit Timer/Counter * 4x3 Compare/Capture/PWM channels * Dead-Time Insertion on TIMER0 * 16-bit Low Energy Timer * 1x 24-bit Real-Time Counter and 1x 32-bit Real-Time Counter * 3x 16/8-bit Pulse Counter * Watchdog Timer with dedicated RC oscillator @ 50 nA * Integrated LCD Controller for up to 8x36 segments * Voltage boost, adjustable contrast and autonomous animation * Backup Power Domain * RTC and retention registers in a separate power domain, available in all energy modes * Operation from backup battery when main power drains out * External Bus Interface for up to 4x256 MB of external memory mapped space * TFT Controller with Direct Drive * Communication interfaces * Up to 3x Universal Synchronous/Asynchronous Receiver/Transmitter * UART/SPI/SmartCard (ISO 7816)/IrDA/I2S * 2x Universal Asynchronous Receiver/Transmitter * 2x Low Energy UART * Autonomous operation with DMA in Deep Sleep Mode * 2x I2C Interface with SMBus support * Address recognition in Stop Mode * Universal Serial Bus (USB) with Host & OTG support * Fully USB 2.0 compliant * On-chip PHY and embedded 5V to 3.3V regulator silabs.com | Building a more connected world. Rev. 2.20 | 2 EFM32LG Data Sheet Feature List * Ultra low power precision analog peripherals * 12-bit 1 Msamples/s Analog to Digital Converter * 8 single-ended channels/4 differential channels * On-chip temperature sensor * 12-bit 500 ksamples/s Digital to Analog Converter * 2 single-ended channels/1 differential channel * Up to 2x Analog Comparator * Capacitive sensing with up to 16 inputs * 3x Operational Amplifier * 6.1 MHz GBW, Rail-to-rail, Programmable Gain * Supply Voltage Comparator * Low Energy Sensor Interface (LESENSE) * Autonomous sensor monitoring in Deep Sleep Mode * Wide range of sensors supported, including LC sensors and capacitive buttons * Ultra efficient Power-on Reset and Brown-Out Detector * Debug Interface * 2-pin Serial Wire Debug interface * 1-pin Serial Wire Viewer * Embedded Trace Module v3.5 (ETM) * Pre-Programmed USB/UART Bootloader * Temperature range -40 to 85 C * Single power supply 1.98 to 3.8 V * Packages: * BGA112 * BGA120 * CSP81 * LQFP100 * TQFP64 * QFN64 * Full wafer silabs.com | Building a more connected world. Rev. 2.20 | 3 EFM32LG Data Sheet Ordering Information 2. Ordering Information The following table shows the available EFM32LG devices. Table 2.1. Ordering Information Flash (kB) RAM (kB) Max Speed (MHz) Supply Voltage (V) Temperature (C) Package EFM32LG230F64G-E-QFN64 64 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG230F128G-E-QFN64 128 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG230F256G-E-QFN64 256 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG232F64G-E-QFP64 64 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG232F128G-E-QFP64 128 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG232F256G-E-QFP64 256 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG280F64G-E-QFP100 64 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG280F128G-E-QFP100 128 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG280F256G-E-QFP100 256 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG290F64G-E-BGA112 64 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG290F128G-E-BGA112 128 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG290F256G-E-BGA112 256 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG295F64G-E-BGA120 64 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG295F128G-E-BGA120 128 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG295F256G-E-BGA120 256 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG330F64G-E-QFN64 64 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG330F128G-E-QFN64 128 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG330F256G-E-QFN64 256 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG332F64G-E-QFP64 64 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG332F128G-E-QFP64 128 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG332F256G-E-QFP64 256 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG360F64G-E-CSP81 64 32 48 1.98 - 3.8 -40 - 85 CSP81 EFM32LG360F128G-E-CSP81 128 32 48 1.98 - 3.8 -40 - 85 CSP81 EFM32LG360F256G-E-CSP81 256 32 48 1.98 - 3.8 -40 - 85 CSP81 EFM32LG380F64G-E-QFP100 64 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG380F128G-E-QFP100 128 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG380F256G-E-QFP100 256 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG390F64G-E-BGA112 64 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG390F128G-E-BGA112 128 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG390F256G-E-BGA112 256 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG395F64G-E-BGA120 64 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG395F128G-E-BGA120 128 32 48 1.98 - 3.8 -40 - 85 BGA120 Ordering Code silabs.com | Building a more connected world. Rev. 2.20 | 4 EFM32LG Data Sheet Ordering Information Flash (kB) RAM (kB) Max Speed (MHz) Supply Voltage (V) Temperature (C) Package EFM32LG395F256G-E-BGA120 256 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG840F64G-E-QFN64 64 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG840F128G-E-QFN64 128 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG840F256G-E-QFN64 256 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG842F64G-E-QFP64 64 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG842F128G-E-QFP64 128 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG842F256G-E-QFP64 256 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG880F64G-E-QFP100 64 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG880F128G-E-QFP100 128 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG880F256G-E-QFP100 256 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG890F64G-E-BGA112 64 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG890F128G-E-BGA112 128 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG890F256G-E-BGA112 256 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG895F64G-E-BGA120 64 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG895F128G-E-BGA120 128 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG895F256G-E-BGA120 256 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG900F256G-E-D1I 256 32 48 1.98 - 3.8 -40 - 85 Wafer EFM32LG940F64G-E-QFN64 64 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG940F128G-E-QFN64 128 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG940F256G-E-QFN64 256 32 48 1.98 - 3.8 -40 - 85 QFN64 EFM32LG942F64G-E-QFP64 64 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG942F128G-E-QFP64 128 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG942F256G-E-QFP64 256 32 48 1.98 - 3.8 -40 - 85 TQFP64 EFM32LG980F64G-E-QFP100 64 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG980F128G-E-QFP100 128 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG980F256G-E-QFP100 256 32 48 1.98 - 3.8 -40 - 85 LQFP100 EFM32LG990F64G-E-BGA112 64 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG990F128G-E-BGA112 128 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG990F256G-E-BGA112 256 32 48 1.98 - 3.8 -40 - 85 BGA112 EFM32LG995F64G-E-BGA120 64 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG995F128G-E-BGA120 128 32 48 1.98 - 3.8 -40 - 85 BGA120 EFM32LG995F256G-E-BGA120 256 32 48 1.98 - 3.8 -40 - 85 BGA120 Ordering Code silabs.com | Building a more connected world. Rev. 2.20 | 5 EFM32LG Data Sheet Ordering Information EFM32 LG 995 F 256 G - E - BGA 120 R Tape and Reel (Optional) Pin Count Package Revision Temperature Grade - G (-40 to +85 C) Memory Size in kB Memory Type (Flash) Feature Set Code Leopard Gecko Energy Friendly Microcontroller 32-bit Figure 2.1. Ordering Code Decoder Adding the suffix 'R' to the part number (e.g. EFM32LGF256G-E-BGA120R) denotes tape and reel. Visit http://www.silabs.com for information on global distributors and representatives. silabs.com | Building a more connected world. Rev. 2.20 | 6 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. System Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 System Introduction . . . . . . . . . . . . . . . . . . . 3.1.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . 3.1.2 Debug Interface (DBG) . . . . . . . . . . . . . . . . . 3.1.3 Memory System Controller (MSC) . . . . . . . . . . . . . 3.1.4 Direct Memory Access Controller (DMA) . . . . . . . . . . . 3.1.5 Reset Management Unit (RMU) . . . . . . . . . . . . . . 3.1.6 Energy Management Unit (EMU) . . . . . . . . . . . . . 3.1.7 Clock Management Unit (CMU) . . . . . . . . . . . . . . 3.1.8 Watchdog (WDOG) . . . . . . . . . . . . . . . . . . 3.1.9 Peripheral Reflex System (PRS) . . . . . . . . . . . . . 3.1.10 External Bus Interface (EBI) . . . . . . . . . . . . . . 3.1.11 TFT Direct Drive . . . . . . . . . . . . . . . . . . 3.1.12 Universal Serial Bus Controller (USB) . . . . . . . . . . . 3.1.13 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . 3.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 3.1.15 Pre-Programmed USB/UART Bootloader . . . . . . . . . . 3.1.16 Universal Asynchronous Receiver/Transmitter (UART) . . . . . 3.1.17 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) 3.1.18 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . 3.1.19 Real Time Counter (RTC) . . . . . . . . . . . . . . . 3.1.20 Backup Real Time Counter (BURTC) . . . . . . . . . . . 3.1.21 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . 3.1.22 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . 3.1.23 Analog Comparator (ACMP) . . . . . . . . . . . . . . 3.1.24 Voltage Comparator (VCMP) . . . . . . . . . . . . . . 3.1.25 Analog to Digital Converter (ADC) . . . . . . . . . . . . 3.1.26 Digital to Analog Converter (DAC) . . . . . . . . . . . . 3.1.27 Operational Amplifier (OPAMP) . . . . . . . . . . . . . 3.1.28 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . 3.1.29 Backup Power Domain . . . . . . . . . . . . . . . . 3.1.30 Advanced Encryption Standard Accelerator (AES) . . . . . . . 3.1.31 General Purpose Input/Output (GPIO) . . . . . . . . . . . 3.1.32 Liquid Crystal Display Driver (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 .13 .13 .13 .13 .13 .14 .14 .14 .14 .14 .14 .14 .14 .14 .15 .15 .15 .15 .15 .15 .15 .15 .15 .15 .16 .16 .16 .16 .16 .16 .16 .16 3.2 Configuration Summary 3.2.1 EFM32LG230 . . 3.2.2 EFM32LG232 . . 3.2.3 EFM32LG280 . . 3.2.4 EFM32LG290 . . 3.2.5 EFM32LG295 . . 3.2.6 EFM32LG330 . . 3.2.7 EFM32LG332 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 .17 .19 .21 .23 .25 .27 .29 . . . . . . . . silabs.com | Building a more connected world. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 2.20 | 7 3.2.8 EFM32LG360 . 3.2.9 EFM32LG380 . 3.2.10 EFM32LG390 3.2.11 EFM32LG395 3.2.12 EFM32LG840 3.2.13 EFM32LG842 3.2.14 EFM32LG880 3.2.15 EFM32LG890 3.2.16 EFM32LG895 3.2.17 EFM32LG900 3.2.18 EFM32LG940 3.2.19 EFM32LG942 3.2.20 EFM32LG980 3.2.21 EFM32LG990 3.2.22 EFM32LG995 3.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 .33 .35 .37 .39 .41 .43 .45 .47 .49 .51 .53 .55 .57 .59 . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1 Test Conditions . . . . . . . . 4.1.1 Typical Values . . . . . . 4.1.2 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 .63 .63 4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .63 4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .63 4.4 Backup Supply Domain . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.5 Current Consumption . . . . 4.5.1 EM1 Current Consumption 4.5.2 EM2 Current Consumption 4.5.3 EM3 Current Consumption 4.5.4 EM4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 .67 .70 .71 .71 4.6 Transition between Energy Modes . . . . . . . . . . . . . . . . . . . . . . .72 4.7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.8 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.9 General Purpose Input Output . . . . . . . . . . . . . . . . . . . . . . . . .74 4.10 Oscillators . . 4.10.1 LFXO . . 4.10.2 HFXO . . 4.10.3 LFRCO . 4.10.4 HFRCO . 4.10.5 AUXHFRCO 4.10.6 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 .82 .82 .83 .84 .89 .89 4.11 Analog Digital Converter (ADC) . 4.11.1 Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 .96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Digital Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . 101 4.13 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . 103 silabs.com | Building a more connected world. Rev. 2.20 | 8 4.14 Analog Comparator (ACMP) . . 4.15 Voltage Comparator (VCMP) . 4.16 EBI 4.17 LCD 4.18 I2C . . . . . . . . 4.19 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 . 118 . . . . 1 . 19 . 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 Digital Peripherals .129 5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.1 EFM32LG230 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 30 5.1.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 134 . 5.1.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.1.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .139 5.2 EFM32LG232 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . 140 . 5.2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 40 5.2.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 144 . 5.2.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.2.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .149 5.3 EFM32LG280 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .150 5.3.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 50 5.3.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 156 . 5.3.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.3.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .163 5.4 EFM32LG290 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . 164 . 5.4.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 64 5.4.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 170 . 5.4.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.4.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .177 5.5 EFM32LG295 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . 178 . 5.5.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 78 5.5.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 184 . 5.5.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.5.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .191 5.6 EFM32LG330 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 192 5.6.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 92 5.6.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 196 . 5.6.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.6.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .201 5.7 EFM32LG332 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . 202 . 5.7.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 02 5.7.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 206 . 5.7.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 210 5.7.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .211 5.8 EFM32LG360 (CSP81) . silabs.com | Building a more connected world. . . . . . . . . . . . . . . . . . . . . . . . . . 212 Rev. 2.20 | 9 5.8.1 5.8.2 5.8.3 5.8.4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 12 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 217 . GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 222 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .222 5.9 EFM32LG380 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .223 5.9.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 23 5.9.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 228 . 5.9.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 235 5.9.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .235 5.10 EFM32LG390 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .236 5.10.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.10.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .242 5.10.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2 . 49 5.10.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 249 5.11 EFM32LG395 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . .250 5.11.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 5.11.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .256 5.11.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2 . 63 5.11.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 263 5.12 EFM32LG840 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . 264 . 5.12.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 5.12.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .268 5.12.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2 . 74 5.12.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 274 5.13 EFM32LG842 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . .275 5.13.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 5.13.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .279 5.13.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2 . 84 5.13.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 285 5.14 EFM32LG880 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . 286 5.14.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 5.14.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .292 5.14.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3 . 01 5.14.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 301 5.15 EFM32LG890 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .302 5.15.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 5.15.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .308 5.15.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3 . 17 5.15.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 317 5.16 EFM32LG895 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . .318 5.16.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 5.16.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .324 5.16.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3 . 33 5.16.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 333 5.17 EFM32LG900 (Wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . 334 5.17.1 Padout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 silabs.com | Building a more connected world. Rev. 2.20 | 10 5.17.2 Alternate Functionality Padout . . . . . . . . . . . . . . . . . . . . . . 340 5.17.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3 . 49 5.17.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 350 5.18 EFM32LG940 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . 351 . 5.18.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 5.18.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .355 5.18.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3 . 61 5.18.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 361 5.19 EFM32LG942 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . .362 5.19.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 5.19.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .366 5.19.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3 . 71 5.19.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 372 5.20 EFM32LG980 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . 373 5.20.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 5.20.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .379 5.20.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3 . 88 5.20.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 388 5.21 EFM32LG990 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .389 5.21.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 5.21.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .395 5.21.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 4 . 04 5.21.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 404 5.22 EFM32LG995 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . .405 5.22.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 5.22.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .411 5.22.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 4 . 20 5.22.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 421 6. BGA112 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .422 6.1 BGA112 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 422 6.2 BGA112 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 6.3 BGA112 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 425 7. BGA120 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .426 7.1 BGA120 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 426 7.2 BGA120 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 7.3 BGA120 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 429 8. CSP81 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . 430 8.1 CSP81 Package Dimensions 8.2 CSP81 PCB Layout . . 8.3 CSP81 Package Marking 8.4 CSP81 Environmental . . . . . . . . . . . . . . . . . . . . . . . . .430 . . . . . . . . . . . . . . . . . . . . . . . . .432 . . . . . . . . . . . . . . . . . . . . . . . . 4 . 35 . . . . . . . . . . . . . . . . . . . . . . . . 4. 35 9. LQFP100 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 436 silabs.com | Building a more connected world. Rev. 2.20 | 11 9.1 LQFP100 Package Dimensions 9.2 LQFP100 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 38 . . . . . . . . . . . . . . . . . . . . . . . 440 . 9.3 LQFP100 Package Marking 10. QFN64 Package Specifications .436 . . . . . . . . . . . . . . . . . . . . . . .441 10.1 QFN64 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 441 10.2 QFN64 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 10.3 QFN64 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 445 11. TQFP64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 446 11.1 TQFP64 Package Dimensions 11.2 TQFP64 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . .446 . . . . . . . . . . . . . . . . . . . . . . . .448 . . . . . . . . . . . . . . . . . . . . . . . 4. 50 11.3 TQFP64 Package Marking 12. Wafer Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .451 12.1 Bonding Instructions . 12.2 Wafer Description 12.2.1 Environmental . . . . . . . . . . 12.4 Failure Analysis (FA) Guidelines . . . 13.2 Soldering Information . . . . . . . . . . . . . . . . . . 451 . . . . . . . . . . . . . . . . . . . . . . 452 . . . . . . . . . . . . . . . . . . . . . 452 . 13. Chip Revision, Solder Information, Errata 13.3 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 51 . . . . . . . . . . . . . . . . . . . . . . . . . . .451 12.3 Wafer Storage Guidelines . 13.1 Chip Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 . . .453 . 453 . 14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 14.1 Revision 2.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 14.2 Revision 2.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 14.3 Revision 2.00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 14.4 Revision 1.31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 14.5 Revision 1.30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 14.6 Revision 1.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 14.7 Revision 1.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 14.8 Revision 1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 14.9 Revision 1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 14.10 Revision 1.00 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. 63 14.11 Revision 0.92 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. 63 14.12 Revision 0.90 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. 64 silabs.com | Building a more connected world. Rev. 2.20 | 12 EFM32LG Data Sheet System Summary 3. System Summary 3.1 System Introduction The EFM32 MCUs are the world's most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM CortexM3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32LG microcontroller is well suited for any battery operated application as well as other systems requiring high performance and low-energy consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of the configuration for the EFM32LG devices. For a complete feature set and in-depth information on the modules, the reader is referred to the EFM32LG Reference Manual. A block diagram of the EFM32LG is shown in the following figure. Core / Memory ARM CortexTM M3 processor Clock Management Memory Protection Unit Flash Program Memory Debug w/ ETM RAM Memory DMA Controller Energy Management High Frequency Crystal Oscillator High Frequency RC Oscillator Voltage Regulator Voltage Comparator Auxiliary High Freq. RC Osc. Low Freq. RC Oscillator Brown-out Detector Power-on Reset Low Frequency Crystal Oscillator Ultra Low Freq. RC Oscillator Back-up Power Domain Security Hardware AES 32-bit bus Peripheral Reflex System Serial Interfaces USART Low Energy UARTTM I/O Ports Timers and Triggers UART External Bus Interface TFT Driver I2C External Interrupts General Purpose I/O Pin Reset Pin Wakeup USB Timer/Counter LESENSE Low Energy Timer Real Time Counter Pulse Counter Watchdog Timer Analog Interfaces ADC LCD Controller DAC Operational Amplifier Analog Comparator Back-up RTC Lowest power mode with peripheral operational: EM0 - Active EM1 - Sleep EM2 - Deep Sleep EM3 - Stop EM4 - Shutoff Figure 3.1. Block Diagram 3.1.1 ARM Cortex-M3 Core The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32LG Reference Manual. 3.1.2 Debug Interface (DBG) This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data trace and software-generated messages. 3.1.3 Memory System Controller (MSC) The Memory System Controller (MSC) is the program memory unit of the EFM32LG microcontroller. The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in the energy modes EM0 and EM1. 3.1.4 Direct Memory Access Controller (DMA) The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 DMA controller licensed from ARM. 3.1.5 Reset Management Unit (RMU) The RMU is responsible for handling the reset functionality of the EFM32LG. silabs.com | Building a more connected world. Rev. 2.20 | 13 EFM32LG Data Sheet System Summary 3.1.6 Energy Management Unit (EMU) The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32LG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks. 3.1.7 Clock Management Unit (CMU) The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32LG. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive. 3.1.8 Watchdog (WDOG) The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a software failure. 3.1.9 Peripheral Reflex System (PRS) The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but edge triggers and other functionality can be applied by the PRS. 3.1.10 External Bus Interface (EBI) The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The interface is memory mapped into the address bus of the Cortex-M3. This enables seamless access from software without manually manipulating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is limited to asynchronous devices. 3.1.11 TFT Direct Drive The EBI contains a TFT controller which can drive a TFT via a 565 RGB interface. The TFT controller supports programmable display and port sizes and offers accurate control of frequency and setup and hold timing. Direct Drive is supported for TFT displays which do not have their own frame buffer. In that case TFT Direct Drive can transfer data from either on-chip memory or from an external memory device to the TFT at low CPU load. Automatic alpha-blending and masking is also supported for transfers through the EBI interface. 3.1.12 Universal Serial Bus Controller (USB) The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device, On-the-Go (OTG) Dual Role Device, or Host-only configuration. In OTG mode, the USB supports both Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The device supports both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) operation. The USB device includes an internal, dedicated Descriptor-Based Scatter/Gather DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in addition to endpoint 0. The on-chip PHY includes all OTG features, except for the voltage booster for supplying 5V to VBUS when operating as a host. 3.1.13 Inter-Integrated Circuit Interface (I2C) The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system. The interface provided to software by the I2C module, allows both fine-grained control of the transmission process and close to automatic transfers. Automatic recognition of slave addresses is provided in all energy modes. 3.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices. silabs.com | Building a more connected world. Rev. 2.20 | 14 EFM32LG Data Sheet System Summary 3.1.15 Pre-Programmed USB/UART Bootloader The bootloader presented in application note AN0042 is pre-programmed in the device at factory. The bootloader enables users to program the EFM32 through a UART or a USB CDC class virtual UART without the need for a debugger. The autobaud feature, interface and commands are described further in the application note. 3.1.16 Universal Asynchronous Receiver/Transmitter (UART) The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module. It supports full- and half-duplex asynchronous UART communication. 3.1.17 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support to make asynchronous serial communication possible with minimum of software intervention and energy consumption. 3.1.18 Timer/Counter (TIMER) The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse- Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications. 3.1.19 Real Time Counter (RTC) The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where most of the device is powered down. 3.1.20 Backup Real Time Counter (BURTC) The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy Modes and it can also run in backup mode, making it operational even if the main power should drain out. 3.1.21 Low Energy Timer (LETIMER) The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start counting on compare matches from the RTC. 3.1.22 Pulse Counter (PCNT) The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3. 3.1.23 Analog Comparator (ACMP) The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current consumption can be configured by altering the current supply to the comparator. 3.1.24 Voltage Comparator (VCMP) The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by altering the current supply to the comparator. silabs.com | Building a more connected world. Rev. 2.20 | 15 EFM32LG Data Sheet System Summary 3.1.25 Analog to Digital Converter (ADC) The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per second. The integrated input mux can select inputs from 8 external pins and 6 internal signals. 3.1.26 Digital to Analog Converter (DAC) The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail, with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used for a number of different applications such as sensor interfaces or sound output. 3.1.27 Operational Amplifier (OPAMP) The EFM32LG features up to 3 Operational Amplifiers. The Operational Amplifier is a versatile general purpose amplifier with rail-to-rail differential input and rail-to-rail single-ended output. The input can be set to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable and the OPAMP has various internal configurations such as unity gain, programmable gain using internal resistors etc. 3.1.28 Low Energy Sensor Interface (LESENSE) The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE is capable of supporting a wide range of sensors and measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable FSM which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget. 3.1.29 Backup Power Domain The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC, and a set of retention registers, available in all energy modes. This power domain can be configured to automatically change power source to a backup battery when the main power drains out. The backup power domain enables the EFM32LG to keep track of time and retain data, even if the main power source should drain out. 3.1.30 Advanced Encryption Standard Accelerator (AES) The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit operations are not supported. 3.1.31 General Purpose Input/Output (GPIO) In the EFM32LG, there are up to 93 General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each. These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other peripherals. 3.1.32 Liquid Crystal Display Driver (LCD) The LCD driver is capable of driving a segmented LCD display with up to 8x36 segments. A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter interrupt that can wake-up the device on a regular basis for updating data. silabs.com | Building a more connected world. Rev. 2.20 | 16 EFM32LG Data Sheet System Summary 3.2 Configuration Summary 3.2.1 EFM32LG230 The features of the EFM32LG230 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.1. EFM32LG230 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT silabs.com | Building a more connected world. Rev. 2.20 | 17 EFM32LG Data Sheet System Summary Module Configuration Pin Connections OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 56 pins Available pins are shown in 5.1.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 18 EFM32LG Data Sheet System Summary 3.2.2 EFM32LG232 The features of the EFM32LG232 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.2. EFM32LG232 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx silabs.com | Building a more connected world. Rev. 2.20 | 19 EFM32LG Data Sheet System Summary Module Configuration Pin Connections AES Full configuration NA GPIO 53 pins Available pins are shown in 5.2.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 20 EFM32LG Data Sheet System Summary 3.2.3 EFM32LG280 The features of the EFM32LG280 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.3. EFM32LG280 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O silabs.com | Building a more connected world. Rev. 2.20 | 21 EFM32LG Data Sheet System Summary Module Configuration Pin Connections VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 85 pins Available pins are shown in 5.3.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 22 EFM32LG Data Sheet System Summary 3.2.4 EFM32LG290 The features of the EFM32LG290 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.4. EFM32LG290 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O silabs.com | Building a more connected world. Rev. 2.20 | 23 EFM32LG Data Sheet System Summary Module Configuration Pin Connections VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 90 pins Available pins are shown in 5.4.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 24 EFM32LG Data Sheet System Summary 3.2.5 EFM32LG295 The features of the EFM32LG295 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.5. EFM32LG295 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O silabs.com | Building a more connected world. Rev. 2.20 | 25 EFM32LG Data Sheet System Summary Module Configuration Pin Connections VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 93 pins Available pins are shown in 5.5.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 26 EFM32LG Data Sheet System Summary 3.2.6 EFM32LG330 The features of the EFM32LG330 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.6. EFM32LG330 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT silabs.com | Building a more connected world. Rev. 2.20 | 27 EFM32LG Data Sheet System Summary Module Configuration Pin Connections OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 53 pins Available pins are shown in 5.6.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 28 EFM32LG Data Sheet System Summary 3.2.7 EFM32LG332 The features of the EFM32LG332 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.7. EFM32LG332 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT silabs.com | Building a more connected world. Rev. 2.20 | 29 EFM32LG Data Sheet System Summary Module Configuration Pin Connections OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 50 pins Available pins are shown in 5.7.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 30 EFM32LG Data Sheet System Summary 3.2.8 EFM32LG360 The features of the EFM32LG360 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.8. EFM32LG360 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA silabs.com | Building a more connected world. Rev. 2.20 | 31 EFM32LG Data Sheet System Summary Module Configuration Pin Connections ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 65 pins Available pins are shown in 5.8.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 32 EFM32LG Data Sheet System Summary 3.2.9 EFM32LG380 The features of the EFM32LG380 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.9. EFM32LG380 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O silabs.com | Building a more connected world. Rev. 2.20 | 33 EFM32LG Data Sheet System Summary Module Configuration Pin Connections ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 83 pins Available pins are shown in 5.9.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 34 EFM32LG Data Sheet System Summary 3.2.10 EFM32LG390 The features of the EFM32LG390 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.10. EFM32LG390 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O silabs.com | Building a more connected world. Rev. 2.20 | 35 EFM32LG Data Sheet System Summary Module Configuration Pin Connections ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 86 pins Available pins are shown in 5.10.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 36 EFM32LG Data Sheet System Summary 3.2.11 EFM32LG395 The features of the EFM32LG395 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.11. EFM32LG395 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O silabs.com | Building a more connected world. Rev. 2.20 | 37 EFM32LG Data Sheet System Summary Module Configuration Pin Connections ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 93 pins Available pins are shown in 5.11.3 GPIO Pinout Overview silabs.com | Building a more connected world. Rev. 2.20 | 38 EFM32LG Data Sheet System Summary 3.2.12 EFM32LG840 The features of the EFM32LG840 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.12. EFM32LG840 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx silabs.com | Building a more connected world. Rev. 2.20 | 39 EFM32LG Data Sheet System Summary Module Configuration Pin Connections AES Full configuration NA GPIO 56 pins Available pins are shown in 5.12.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[19:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 40 EFM32LG Data Sheet System Summary 3.2.13 EFM32LG842 The features of the EFM32LG842 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.13. EFM32LG842 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx silabs.com | Building a more connected world. Rev. 2.20 | 41 EFM32LG Data Sheet System Summary Module Configuration Pin Connections AES Full configuration NA GPIO 53 pins Available pins are shown in 5.13.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 42 EFM32LG Data Sheet System Summary 3.2.14 EFM32LG880 The features of the EFM32LG880 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.14. EFM32LG880 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O silabs.com | Building a more connected world. Rev. 2.20 | 43 EFM32LG Data Sheet System Summary Module Configuration Pin Connections VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 85 pins Available pins are shown in 5.14.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 44 EFM32LG Data Sheet System Summary 3.2.15 EFM32LG890 The features of the EFM32LG890 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.15. EFM32LG890 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O silabs.com | Building a more connected world. Rev. 2.20 | 45 EFM32LG Data Sheet System Summary Module Configuration Pin Connections VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 90 pins Available pins are shown in 5.15.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 46 EFM32LG Data Sheet System Summary 3.2.16 EFM32LG895 The features of the EFM32LG895 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.16. EFM32LG895 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O silabs.com | Building a more connected world. Rev. 2.20 | 47 EFM32LG Data Sheet System Summary Module Configuration Pin Connections VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 93 pins Available pins are shown in Table 4.3 (p. 70) LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 48 EFM32LG Data Sheet System Summary 3.2.17 EFM32LG900 The features of the EFM32LG900 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.17. EFM32LG900 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O silabs.com | Building a more connected world. Rev. 2.20 | 49 EFM32LG Data Sheet System Summary Module Configuration Pin Connections ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 93 pins Available pins are shown in 5.17.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 50 EFM32LG Data Sheet System Summary 3.2.18 EFM32LG940 The features of the EFM32LG940 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.18. EFM32LG940 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O ACMP1 Full configuration ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT silabs.com | Building a more connected world. Rev. 2.20 | 51 EFM32LG Data Sheet System Summary Module Configuration Pin Connections OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 53 pins Available pins are shown in 5.18.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 52 EFM32LG Data Sheet System Summary 3.2.19 EFM32LG942 The features of the EFM32LG942 is a subset of the feature set described in the EFM32LG Reference Manual. The following table device specific implementation of the features. Table 3.19. EFM32LG942 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O ACMP1 Full configuration ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT silabs.com | Building a more connected world. Rev. 2.20 | 53 EFM32LG Data Sheet System Summary Module Configuration Pin Connections OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 50 pins Available pins are shown in 5.19.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[15:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 54 EFM32LG Data Sheet System Summary 3.2.20 EFM32LG980 The features of the EFM32LG980 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.20. EFM32LG980 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O silabs.com | Building a more connected world. Rev. 2.20 | 55 EFM32LG Data Sheet System Summary Module Configuration Pin Connections ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 81 pins Available pins are shown in 5.20.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[33:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 56 EFM32LG Data Sheet System Summary 3.2.21 EFM32LG990 The features of the EFM32LG990 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.21. EFM32LG990 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O silabs.com | Building a more connected world. Rev. 2.20 | 57 EFM32LG Data Sheet System Summary Module Configuration Pin Connections ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 86 pins Available pins are shown in 5.21.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[33:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 58 EFM32LG Data Sheet System Summary 3.2.22 EFM32LG995 The features of the EFM32LG995 is a subset of the feature set described in the EFM32LG Reference Manual. The following table describes device specific implementation of the features. Table 3.22. EFM32LG995 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O silabs.com | Building a more connected world. Rev. 2.20 | 59 EFM32LG Data Sheet System Summary Module Configuration Pin Connections ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx AES Full configuration NA GPIO 93 pins Available pins are shown in 5.22.3 GPIO Pinout Overview LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.20 | 60 EFM32LG Data Sheet System Summary 3.3 Memory Map The EFM32LG memory map is shown in the following figure, with RAM and Flash sizes for the largest memory configuration. Figure 3.2. System Address Space with Core and Code Space Listing silabs.com | Building a more connected world. Rev. 2.20 | 61 EFM32LG Data Sheet System Summary Figure 3.3. System Address Space with Peripheral Listing silabs.com | Building a more connected world. Rev. 2.20 | 62 EFM32LG Data Sheet Electrical Characteristics 4. Electrical Characteristics 4.1 Test Conditions 4.1.1 Typical Values The typical data are based on TAMB=25C and VDD=3.0 V, as defined in 4.3 General Operating Conditions, unless otherwise specified. 4.1.2 Minimum and Maximum Values The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined in 4.3 General Operating Conditions, unless otherwise specified. 4.2 Absolute Maximum Ratings The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond the limits specified in the following table may affect the device reliability or cause permanent damage to the device. Functional operating conditions are given in 4.3 General Operating Conditions. Table 4.1. Absolute Maximum Ratings Parameter Symbol Storage temperature range TSTG Maximum soldering temperature TS External main supply voltage VDDMAX Voltage on any I/O pin VIOPIN Current per I/O pin (sink) Test Condition Min Typ Max Unit -40 -- 150 C -- -- 260 C 0 -- 3.8 V -0.3 -- VDD+0.3 V IIOMAX_SINK -- -- 100 mA Current per I/O pin (source) IIOMAX_SOURCE -- -- -100 mA Junction temperature TJ -40 -- 105 C Latest IPC/JEDEC JSTD-020 Standard -G grade devices 4.3 General Operating Conditions Table 4.2. General Operating Conditions Parameter Symbol Min Typ Max Unit Ambient temperature range TAMB -40 -- 85 C Operating supply voltage VDDOP 1.98 -- 3.8 V Internal APB clock frequency fAPB -- -- 48 MHz Internal AHB clock frequency fAHB -- -- 48 MHz silabs.com | Building a more connected world. Rev. 2.20 | 63 EFM32LG Data Sheet Electrical Characteristics 4.4 Backup Supply Domain Table 4.3. Backup Supply Domain Parameter Symbol Test Condition Min Typ Max Unit 1.8 -- 3.8 V EMU_PWRCONF_PWRRES = RES0 4234 4485 4786 EMU_PWRCONF_PWRRES = RES1 2208 2363 2528 EMU_PWRCONF_PWRRES = RES2 1166 1297 1433 EMU_PWRCONF_PWRRES = RES3 295 344 399 EMU_PWRCONF_VOUTSTRONG = 1, EMU_PWRCONF_VOUTMED = 0, EMU_PWRCONF_VOUTWEAK = 0 49 63 80 EMU_PWRCONF_VOUTSTRONG = 0, EMU_PWRCONF_VOUTMED = 1, EMU_PWRCONF_VOUTWEAK = 0 522 670 844 EMU_PWRCONF_VOUTSTRONG = 0, EMU_PWRCONF_VOUTMED = 0, EMU_PWRCONF_VOUTWEAK = 1 5161 6743 7853 BU_VIN not powering backup domain -- 3.4 6.5 nA BU_VIN powering backup domain -- 197 1050 nA Backup supply voltage range VBU_VIN PWRRES resistor Output impedance between BU_VIN and BU_VOUT 1 Supply current RPWRRES RBU_VOUT IBU_VIN Note: 1. BU_VOUT and BU_STAT signals are not available in all package configurations. Check the device pinout for availability. silabs.com | Building a more connected world. Rev. 2.20 | 64 EFM32LG Data Sheet Electrical Characteristics 4.5 Current Consumption Table 4.4. Current Consumption Parameter Symbol Test Condition EM0 current. No prescaling. Running prime number calculation code from Flash. (Production test condition = 14 MHz) IEM0 silabs.com | Building a more connected world. Min Typ Max Unit 48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 211 225 A/MHz 48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 211 230 A/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 212 220 A/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 213 223 A/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 214 224 A/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 215 226 A/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 216 231 A/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 217 237 A/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 218 239 A/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 219 239 A/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 224 245 A/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 224 258 A/MHz 1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 257 285 A/MHz 1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 261 293 A/MHz Rev. 2.20 | 65 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition EM1 current (Production test condition = 14 MHz) IEM1 EM2 current EM3 current EM4 current IEM2 IEM3 IEM4 Min Typ Max Unit 48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 63 75 A/MHz 48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 65 76 A/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 64 75 A/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 65 77 A/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 65 76 A/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 66 78 A/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 67 79 A/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 68 82 A/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 68 81 A/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 70 83 A/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 74 87 A/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 76 89 A/MHz 1.2 MHz HFRCO. all peripheral clocks disabled, VDD= 3.0 V, TAMB=25C -- 106 120 A/MHz 1.2 MHz HFRCO. all peripheral clocks disabled, VDD= 3.0 V, TAMB=85C -- 112 129 A/MHz EM2 current with RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=25C -- 0.951 1.71 A EM2 current with RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=85C -- 3.01 4.01 A VDD= 3.0 V, TAMB=25C -- 0.65 1.3 A VDD= 3.0 V, TAMB=85C -- 2.65 4.0 A VDD= 3.0 V, TAMB=25C -- 0.020 0.055 A VDD= 3.0 V, TAMB=85C -- 0.44 0.90 A Note: 1. Using backup RTC. silabs.com | Building a more connected world. Rev. 2.20 | 66 EFM32LG Data Sheet Electrical Characteristics 4.5.1 EM1 Current Consumption 3.10 3.10 3.05 3.05 Idd [mA] 3.15 Idd [mA] 3.15 3.00 3.00 -40C -15C 5C 25C 45C 65C 85C 2.95 2.90 2.0 2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 2.95 2.90 -40 3.8 -15 5 25 Temperature [C] 45 65 85 Figure 4.1. EM1 Current Consumption with all Peripheral Clocks Disabled and HFXO Running at 48 MHz 1.80 1.80 1.75 1.75 Idd [mA] 1.85 Idd [mA] 1.85 1.70 1.70 -40C -15C 5C 25C 45C 65C 85C 1.65 1.60 2.0 2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 1.65 3.8 1.60 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.2. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 28 MHz silabs.com | Building a more connected world. Rev. 2.20 | 67 EFM32LG Data Sheet 1.42 1.42 1.40 1.40 1.38 1.38 1.36 1.36 1.34 1.34 Idd [mA] Idd [mA] Electrical Characteristics 1.32 -40C -15C 5C 25C 45C 65C 85C 1.30 1.28 1.26 1.24 2.0 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V 1.32 1.30 1.28 1.26 1.24 -40 3.8 -15 5 25 Temperature [C] 45 65 85 0.98 0.98 0.96 0.96 0.94 0.94 Idd [mA] Idd [mA] Figure 4.3. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 21 MHz 0.92 -40C -15C 5C 25C 45C 65C 85C 0.90 0.88 0.86 2.0 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V 0.92 0.90 0.88 3.8 0.86 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.4. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 14 MHz silabs.com | Building a more connected world. Rev. 2.20 | 68 EFM32LG Data Sheet 0.78 0.78 0.76 0.76 Idd [mA] Idd [mA] Electrical Characteristics 0.74 -40C -15C 5C 25C 45C 65C 85C 0.72 0.70 2.0 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V 0.74 0.72 0.70 3.8 -40 -15 5 25 Temperature [C] 45 65 85 0.52 0.52 0.51 0.51 0.50 0.50 0.49 0.49 Idd [mA] Idd [mA] Figure 4.5. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 11 MHz 0.48 -40C -15C 5C 25C 45C 65C 85C 0.47 0.46 0.45 2.0 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V 0.48 0.47 0.46 3.8 0.45 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.6. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 6.6 MHz silabs.com | Building a more connected world. Rev. 2.20 | 69 EFM32LG Data Sheet Electrical Characteristics 0.160 0.138 -40C -15C 5C 25C 45C 65C 85C 0.136 0.134 0.150 0.145 Idd [mA] Idd [mA] 0.132 0.155 0.130 0.140 2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V 0.135 0.128 0.130 0.126 0.125 0.124 0.122 2.0 0.120 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.8 0.115 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.7. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 1.2 MHz 4.5.2 EM2 Current Consumption 3.5 3.5 -40.0C -15.0C 5.0C 25.0C 45.0C 65.0C 85.0C 3.0 2.5 Idd [uA] Idd [uA] 2.5 3.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 2.0 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.8 0.5 -40 Vdd=2.0V Vdd=2.2V Vdd=2.4V Vdd=2.6V Vdd=2.8V Vdd=3.0V Vdd=3.2V Vdd=3.4V Vdd=3.6V Vdd=3.8V -20 0 20 40 Temperature [C] 60 80 Figure 4.8. EM2 Current Consumption, RTC1 prescaled to 1 kHz, 32.768 kHz LFRCO Note: 1. Using backup RTC. silabs.com | Building a more connected world. Rev. 2.20 | 70 EFM32LG Data Sheet Electrical Characteristics 4.5.3 EM3 Current Consumption 3.0 3.0 -40.0C -15.0C 5.0C 25.0C 45.0C 65.0C 85.0C 2.5 2.0 Idd [uA] Idd [uA] 2.0 2.5 1.5 1.5 1.0 1.0 0.5 0.5 0.0 2.0 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 0.0 -40 3.8 Vdd=2.0V Vdd=2.2V Vdd=2.4V Vdd=2.6V Vdd=2.8V Vdd=3.0V Vdd=3.2V Vdd=3.4V Vdd=3.6V Vdd=3.8V -20 0 20 40 Temperature [C] 60 80 0 20 40 Temperature [C] 60 80 Figure 4.9. EM3 Current Consumption 4.5.4 EM4 Current Consumption 0.7 0.6 0.6 0.5 0.4 Idd [uA] Idd [uA] 0.5 0.7 -40.0C -15.0C 5.0C 25.0C 45.0C 65.0C 85.0C 0.3 0.4 0.3 0.2 0.2 0.1 0.1 0.0 2.0 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.8 Vdd=2.0V Vdd=2.2V Vdd=2.4V Vdd=2.6V Vdd=2.8V Vdd=3.0V Vdd=3.2V Vdd=3.4V Vdd=3.6V Vdd=3.8V 0.0 -40 -20 Figure 4.10. EM4 Current Consumption silabs.com | Building a more connected world. Rev. 2.20 | 71 EFM32LG Data Sheet Electrical Characteristics 4.6 Transition between Energy Modes The transition times are measured from the trigger to the first clock edge in the CPU. Table 4.5. Energy Modes Transitions Parameter Symbol Min Typ Max Unit Transition time from EM1 to EM0 tEM10 -- 0 -- HFCORECLK cycles Transition time from EM2 to EM0 tEM20 -- 2 -- s Transition time from EM3 to EM0 tEM30 -- 2 -- s Transition time from EM4 to EM0 tEM40 -- 163 -- s 4.7 Power Management The EFM32LG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with optional filter) at the PCB level. For practical schematic recommendations, please see the application note, AN0002 EFM32 Hardware Design Considerations. Table 4.6. Power Management Parameter Symbol BOD threshold on falling external supply voltage Test Condition Min Typ Max Unit VBODextthr- 1.74 -- 1.96 V BOD threshold on rising external supply voltage VBODextthr+ -- 1.85 1.98 V Power-on Reset (POR) threshold on rising external supply voltage VPORthr+ -- -- 1.98 V Delay from reset is released un- tRESET til program execution starts Applies to Power-on Reset, Brownout Reset and pin reset. -- 163 -- s Voltage regulator decoupling capacitor. CDECOUPLE X5R capacitor recommended. Apply between DECOUPLE pin and GROUND -- 1 -- F USB voltage regulator out decoupling capacitor. CUSB_VREGO X5R capacitor recommended. Apply between USB_VREGO pin and GROUND -- 1 -- F X5R capacitor recommended. Apply between USB_VREGI pin and GROUND -- 4.7 -- F USB voltage regulator in decou- CUSB_VREGI pling capacitor. silabs.com | Building a more connected world. Rev. 2.20 | 72 EFM32LG Data Sheet Electrical Characteristics 4.8 Flash Table 4.7. Flash Parameter Symbol Flash erase cycles before failure ECFLASH Flash data retention RETFLASH Word (32-bit) programming time tW_PROG Test Condition Min Typ Max Unit 20000 -- -- cycles TAMB<150 C 10000 -- -- h TAMB<85 C 10 -- -- years TAMB<70 C 20 -- -- years 20 -- -- s Page erase time1 tPERASE 20.7 22.0 24.8 ms Device erase time2 tDERASE 41.8 45.0 49.2 ms Erase current IERASE -- -- 73 mA Write current IWRITE -- -- 73 mA Supply voltage during flash erase and write VFLASH 1.98 -- 3.8 V Note: 1. From setting ERASEPAGE bit in MSC_WRITECMD to 1 to reading 1 in ERASE bit in MSC_IF. Internal setup and hold times for flash control signals are included. 2. From setting DEVICEERASE bit in AAP_CMD to 1 to reading 0 in ERASEBUSY bit in AAP_STATUS. Internal setup and hold times for flash control signals are included. 3. Measured at 25 C. silabs.com | Building a more connected world. Rev. 2.20 | 73 EFM32LG Data Sheet Electrical Characteristics 4.9 General Purpose Input Output Table 4.8. GPIO Parameter Symbol Test Condition Min Typ Max Unit Input low voltage VIOIL -- -- 0.30xVDD V Input high voltage VIOIH 0.70xVDD -- -- V Output high voltage (Production test condition = 3.0V, DRIVEMODE = STANDARD) VIOOH Sourcing 0.1 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = LOWEST -- 0.80xVDD -- V Sourcing 0.1 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = LOWEST -- 0.90xVDD -- V Sourcing 1 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = LOW -- 0.85xVDD -- V Sourcing 1 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = LOW -- 0.90xVDD -- V Sourcing 6 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = STANDARD 0.75xVDD -- -- V Sourcing 6 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = STANDARD 0.85xVDD -- -- V Sourcing 20 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = HIGH 0.60xVDD -- -- V Sourcing 20 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = HIGH 0.80xVDD -- -- V Sinking 0.1 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = LOWEST -- 0.20xVDD -- V Sinking 0.1 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = LOWEST -- 0.10xVDD -- V Sinking 1 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = LOW -- 0.10xVDD -- V Sinking 1 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = LOW -- 0.05xVDD -- V Sinking 6 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = STANDARD -- -- 0.30xVDD V Sinking 6 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = STANDARD -- -- 0.20xVDD V Sinking 20 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = HIGH -- -- 0.35xVDD V Sinking 20 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = HIGH -- -- 0.25xVDD V Output low voltage (Production test condition = 3.0V, DRIVEMODE = STANDARD) VIOOL silabs.com | Building a more connected world. Rev. 2.20 | 74 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Min Typ Max Unit Input leakage current IIOLEAK -40 0.1 40 nA I/O pin pull-up resistor RPU -- 40 -- k I/O pin pull-down resistor RPD -- 40 -- k RIOESD -- 200 -- tIO- 10 -- 50 ns GPIO_Px_CTRL DRIVEMODE = LOWEST and load capacitance CL=12.5-25pF. 20+0.1xCL -- 250 ns GPIO_Px_CTRL DRIVEMODE = LOW and load capacitance CL=350-600pF 20+0.1xCL -- 250 ns 0.10xVDD -- -- V Internal ESD series resistor Pulse width of pulses to be removed by the glitch suppression filter Output fall time I/O pin hysteresis (VIOTHR+ VIOTHR-) VSS < Vin < VDD; pin configured as input or disabled, pullup and pull-down are disabled GLITCH tIOOF VIOHYST VDD = 1.98 - 3.8 V silabs.com | Building a more connected world. Rev. 2.20 | 75 EFM32LG Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW 5 0.20 4 Low-Level Output Current [mA] Low-Level Output Current [mA] 0.15 0.10 3 2 0.05 1 -40C 25C 85C 0.00 0.0 0.5 1.0 Low-Level Output Voltage [V] 1.5 -40C 25C 85C 0 0.0 2.0 GPIO_Px_CTRL DRIVEMODE = STANDARD 0.5 1.0 Low-Level Output Voltage [V] 1.5 2.0 GPIO_Px_CTRL DRIVEMODE = HIGH 45 20 40 35 Low-Level Output Current [mA] Low-Level Output Current [mA] 15 10 30 25 20 15 5 10 5 -40C 25C 85C 0 0.0 0.5 1.0 Low-Level Output Voltage [V] 1.5 2.0 0 0.0 -40C 25C 85C 0.5 1.0 Low-Level Output Voltage [V] 1.5 2.0 Figure 4.11. Typical Low-Level Output Current, 2V Supply Voltage silabs.com | Building a more connected world. Rev. 2.20 | 76 EFM32LG Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW 0.00 0.0 -40C 25C 85C -40C 25C 85C -0.5 High-Level Output Current [mA] High-Level Output Current [mA] -0.05 -0.10 -1.0 -1.5 -0.15 -2.0 -0.20 0.0 0.5 1.0 High-Level Output Voltage [V] 1.5 2.0 -2.5 0.0 GPIO_Px_CTRL DRIVEMODE = STANDARD 0.5 1.0 High-Level Output Voltage [V] 1.5 2.0 GPIO_Px_CTRL DRIVEMODE = HIGH 0 0 -40C 25C 85C -40C 25C 85C -10 High-Level Output Current [mA] High-Level Output Current [mA] -5 -10 -20 -30 -15 -40 -20 0.0 0.5 1.0 High-Level Output Voltage [V] 1.5 2.0 -50 0.0 0.5 1.0 High-Level Output Voltage [V] 1.5 2.0 Figure 4.12. Typical High-Level Output Current, 2 V Supply Voltage silabs.com | Building a more connected world. Rev. 2.20 | 77 EFM32LG Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOW 10 0.4 8 Low-Level Output Current [mA] Low-Level Output Current [mA] GPIO_Px_CTRL DRIVEMODE = LOWEST 0.5 0.3 0.2 0.1 6 4 2 -40C 25C 85C 0.0 0.0 0.5 1.5 1.0 2.0 Low-Level Output Voltage [V] 2.5 -40C 25C 85C 0 0.0 3.0 GPIO_Px_CTRL DRIVEMODE = STANDARD 0.5 1.5 1.0 2.0 Low-Level Output Voltage [V] 2.5 3.0 GPIO_Px_CTRL DRIVEMODE = HIGH 40 50 35 40 Low-Level Output Current [mA] Low-Level Output Current [mA] 30 25 20 15 30 20 10 10 5 0 0.0 -40C 25C 85C 0.5 1.5 1.0 2.0 Low-Level Output Voltage [V] 2.5 -40C 25C 85C 3.0 0 0.0 0.5 1.5 1.0 2.0 Low-Level Output Voltage [V] 2.5 3.0 Figure 4.13. Typical Low-Level Output Current, 3 V Supply Voltage silabs.com | Building a more connected world. Rev. 2.20 | 78 EFM32LG Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW 0 0.0 -40C 25C 85C -40C 25C 85C -1 High-Level Output Current [mA] High-Level Output Current [mA] -0.1 -0.2 -0.3 -2 -3 -4 -0.4 -5 -0.5 0.0 0.5 1.5 1.0 2.0 High-Level Output Voltage [V] 2.5 -6 0.0 3.0 GPIO_Px_CTRL DRIVEMODE = STANDARD 2.5 3.0 0 -40C 25C 85C -40C 25C 85C -10 High-Level Output Current [mA] -10 High-Level Output Current [mA] 1.5 1.0 2.0 High-Level Output Voltage [V] GPIO_Px_CTRL DRIVEMODE = HIGH 0 -20 -30 -40 -50 0.0 0.5 -20 -30 -40 0.5 1.5 1.0 2.0 High-Level Output Voltage [V] 2.5 3.0 -50 0.0 0.5 1.5 1.0 2.0 High-Level Output Voltage [V] 2.5 3.0 Figure 4.14. Typical High-Level Output Current, 3 V Supply Voltage silabs.com | Building a more connected world. Rev. 2.20 | 79 EFM32LG Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW 0.8 14 0.7 12 0.6 Low-Level Output Current [mA] Low-Level Output Current [mA] 10 0.5 0.4 0.3 8 6 4 0.2 2 0.1 0.0 0.0 -40C 25C 85C 0.5 1.5 1.0 2.0 2.5 Low-Level Output Voltage [V] 3.0 -40C 25C 85C 0 0.0 3.5 50 40 40 30 20 10 1.5 1.0 2.0 2.5 Low-Level Output Voltage [V] 3.0 30 20 10 -40C 25C 85C 0 0.0 3.5 GPIO_Px_CTRL DRIVEMODE = HIGH 50 Low-Level Output Current [mA] Low-Level Output Current [mA] GPIO_Px_CTRL DRIVEMODE = STANDARD 0.5 0.5 1.5 1.0 2.0 2.5 Low-Level Output Voltage [V] 3.0 3.5 -40C 25C 85C 0 0.0 0.5 1.5 1.0 2.0 2.5 Low-Level Output Voltage [V] 3.0 3.5 Figure 4.15. Typical Low-Level Output Current, 3.8 V Supply Voltage silabs.com | Building a more connected world. Rev. 2.20 | 80 EFM32LG Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW 0.0 -0.1 0 -40C 25C 85C -1 -40C 25C 85C -2 High-Level Output Current [mA] High-Level Output Current [mA] -0.2 -0.3 -0.4 -0.5 -3 -4 -5 -6 -0.6 -7 -0.7 -0.8 0.0 -8 0.5 1.5 1.0 2.0 2.5 High-Level Output Voltage [V] 3.0 -9 0.0 3.5 GPIO_Px_CTRL DRIVEMODE = STANDARD 3.0 3.5 0 -40C 25C 85C -40C 25C 85C -10 High-Level Output Current [mA] -10 High-Level Output Current [mA] 1.5 1.0 2.0 2.5 High-Level Output Voltage [V] GPIO_Px_CTRL DRIVEMODE = HIGH 0 -20 -30 -40 -50 0.0 0.5 -20 -30 -40 0.5 1.5 1.0 2.0 2.5 High-Level Output Voltage [V] 3.0 3.5 -50 0.0 0.5 1.5 1.0 2.0 2.5 High-Level Output Voltage [V] 3.0 3.5 Figure 4.16. Typical High-Level Output Current, 3.8 V Supply Voltage silabs.com | Building a more connected world. Rev. 2.20 | 81 EFM32LG Data Sheet Electrical Characteristics 4.10 Oscillators 4.10.1 LFXO Table 4.9. LFXO Parameter Symbol Supported nominal crystal frequency Test Condition Min Typ Max Unit fLFXO -- 32.768 -- kHz Supported crystal equivalent series resistance (ESR) ESRLFXO -- 30 120 k Supported crystal external load range CLFXOL X1 -- 25 pF Current consumption for core ILFXO and buffer after startup. ESR=30 k, CL=10 pF, LFXOBOOST in CMU_CTRL is 1 -- 190 -- nA Start- up time. ESR=30 k, CL=10 pF, 40% - 60% duty cycle has been reached, LFXOBOOST in CMU_CTRL is 1 -- 400 -- ms tLFXO Note: 1. See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in Configurator in Simplicity Studio. For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help users configure both load capacitance and software settings for using the LFXO. For details regarding the crystal configuration, the reader is referred to application note AN0016 EFM32 Oscillator Design Consideration. 4.10.2 HFXO Table 4.10. HFXO Parameter Symbol Supported nominal crystal Frequency fHFXO Supported crystal equivalent series resistance (ESR) ESRHFXO The transconductance of the gmHFXO HFXO input transistor at crystal startup Supported crystal external load range CHFXOL Current consumption for HFXO after startup IHFXO Startup time tHFXO silabs.com | Building a more connected world. Test Condition Min Typ Max Unit 4 -- 48 MHz Crystal frequency 48 MHz -- -- 50 Crystal frequency 32 MHz -- 30 60 Crystal frequency 4 MHz -- 400 1500 HFXOBOOST in CMU_CTRL equals 0b11 20 -- -- mS 5 -- 25 pF 4 MHz: ESR=400 , CL=20 pF, HFXOBOOST in CMU_CTRL equals 0b11 -- 85 -- A 32 MHz: ESR=30 , CL=10 pF, HFXOBOOST in CMU_CTRL equals 0b11 -- 165 -- A 32 MHz: ESR=30 , CL=10 pF, HFXOBOOST in CMU_CTRL equals 0b11 -- 400 -- s Rev. 2.20 | 82 EFM32LG Data Sheet Electrical Characteristics 4.10.3 LFRCO Table 4.11. LFRCO Parameter Symbol Test Condition Min Typ Max Unit Oscillation frequency fLFRCO VDD= 3.0 V, TAMB=25C 31.29 32.768 34.28 kHz Over full supply and temperature range 26.0 32.768 46.2 kHz Startup time not including software calibration tLFRCO -- 150 -- s Current consumption ILFRCO -- 300 -- nA Frequency step for LSB change in TUNING value TUNESTEPLFRCO -- 1.5 -- % Voltage drift VDRIFT -- -123291 -- ppm/V Temperature drift TDRIFT -- 610 -- ppm/C Figure 4.17. Calibrated LFRCO Frequency vs Temperature and Supply Voltage silabs.com | Building a more connected world. Rev. 2.20 | 83 EFM32LG Data Sheet Electrical Characteristics 4.10.4 HFRCO Table 4.12. HFRCO Parameter Symbol Test Condition Min Typ Max Unit Oscillation frequency, all packages except CSP, VDD= 3.0 V, TAMB=25C fHFRCO fHFRCO = 28 MHz 27.5 28.0 28.5 MHz fHFRCO = 21 MHz 20.6 21.0 21.4 MHz fHFRCO = 14 MHz 13.7 14.0 14.3 MHz fHFRCO = 11 MHz 10.8 11.0 11.2 MHz fHFRCO = 6.6 MHz 6.481 6.61 6.721 MHz fHFRCO = 1.2 MHz 1.152 1.22 1.252 MHz fHFRCO = 28 MHz 24.9 28.0 31.1 MHz fHFRCO = 21 MHz 18.8 21.0 23.3 MHz fHFRCO = 14 MHz 12.4 14.0 15.6 MHz fHFRCO = 11 MHz 9.9 11.0 12.2 MHz fHFRCO = 6.6 MHz 5.91 6.61 7.41 MHz fHFRCO = 1.2 MHz 0.82 1.22 1.62 MHz fHFRCO = 28 MHz -- 28.0 -- MHz fHFRCO = 21 MHz -- 21.0 -- MHz fHFRCO = 14 MHz -- 14.0 -- MHz fHFRCO = 11 MHz -- 11.0 -- MHz fHFRCO = 6.6 MHz -- 6.61 -- MHz fHFRCO = 1.2 MHz -- 1.22 -- MHz fHFRCO = 28 MHz -- 28.0 -- MHz fHFRCO = 21 MHz -- 21.0 -- MHz fHFRCO = 14 MHz -- 14.0 -- MHz fHFRCO = 11 MHz -- 11.0 -- MHz fHFRCO = 6.6 MHz -- 6.61 -- MHz fHFRCO = 1.2 MHz -- 1.22 -- MHz Oscillation frequency, all packages except CSP, over full supply and temperature range Oscillation frequency, CSP devices, VDD= 3.0 V, TAMB=25C Oscillation frequency, CSP devices, over full supply and temperature range fHFRCO fHFRCO fHFRCO Settling time after start-up tHFRCO_settling fHFRCO = 14 MHz -- 0.6 -- Cycles Current consumption IHFRCO fHFRCO = 28 MHz -- 165 215 A fHFRCO = 21 MHz -- 134 175 A fHFRCO = 14 MHz -- 106 140 A fHFRCO = 11 MHz -- 94 125 A fHFRCO = 6.6 MHz -- 77 105 A fHFRCO = 1.2 MHz -- 25 40 A silabs.com | Building a more connected world. Rev. 2.20 | 84 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Voltage drift VHFRCO_DRIFT Temperature drift THFRCO_DRIFT Frequency step for LSB change in TUNING value TUNESTEPHFRCO Min Typ Max Unit fHFRCO = 28 MHz -- 10768 -- ppm/V fHFRCO = 21 MHz -- 8939 -- ppm/V fHFRCO = 14 MHz -- 8040 -- ppm/V fHFRCO = 11 MHz -- 7719 -- ppm/V fHFRCO = 6.6 MHz -- 8491 -- ppm/V fHFRCO = 1.2 MHz -- -124035 -- ppm/V fHFRCO = 28 MHz -- 91 -- ppm/C fHFRCO = 21 MHz -- 88 -- ppm/C fHFRCO = 14 MHz -- 43 -- ppm/C fHFRCO = 11 MHz -- 50 -- ppm/C fHFRCO = 6.6 MHz -- -50 -- ppm/C fHFRCO = 1.2 MHz -- 83 -- ppm/C -- 0.33 -- % Note: 1. For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable. 2. For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable. 3. The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions. Figure 4.18. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature silabs.com | Building a more connected world. Rev. 2.20 | 85 EFM32LG Data Sheet Electrical Characteristics Figure 4.19. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature Figure 4.20. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature silabs.com | Building a more connected world. Rev. 2.20 | 86 EFM32LG Data Sheet Electrical Characteristics Figure 4.21. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature Figure 4.22. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature silabs.com | Building a more connected world. Rev. 2.20 | 87 EFM32LG Data Sheet Electrical Characteristics Figure 4.23. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature silabs.com | Building a more connected world. Rev. 2.20 | 88 EFM32LG Data Sheet Electrical Characteristics 4.10.5 AUXHFRCO Table 4.13. AUXHFRCO Parameter Symbol Test Condition Min Typ Max Unit Oscillation frequency, all packages except CSP, VDD= 3.0 V, TAMB=25C fAUXHFRCO fAUXHFRCO = 28 MHz 27.5 28.0 28.5 MHz fAUXHFRCO = 21 MHz 20.6 21.0 21.4 MHz fAUXHFRCO = 14 MHz 13.7 14.0 14.3 MHz fAUXHFRCO = 11 MHz 10.8 11.0 11.2 MHz fAUXHFRCO = 6.6 MHz 6.481 6.601 6.721 MHz fAUXHFRCO = 1.2 MHz 1.152 1.202 1.252 MHz fAUXHFRCO = 28 MHz -- 28.0 -- MHz fAUXHFRCO = 21 MHz -- 21.0 -- MHz fAUXHFRCO = 14 MHz -- 14.0 -- MHz fAUXHFRCO = 11 MHz -- 11.0 -- MHz fAUXHFRCO = 6.6 MHz -- 6.601 -- MHz fAUXHFRCO = 1.2 MHz -- 1.202 -- MHz fAUXHFRCO = 14 MHz -- 0.6 -- Cycles -- 0.33 -- % Oscillation frequency, CSP devices, VDD= 3.0 V, TAMB=25C fAUXHFRCO Settling time after start-up tAUXHFRCO_settling Frequency step for LSB change in TUNING value TUNESTEPAUXHFRCO Note: 1. For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable. 2. For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable. 3. The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. There is enough adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions. 4.10.6 ULFRCO Table 4.14. ULFRCO Parameter Symbol Test Condition Min Typ Max Unit Oscillation frequency fULFRCO 25C, 3V 0.7 -- 1.75 kHz Temperature coefficient TCULFRCO -- 0.05 -- %/C Supply voltage coefficient VCULFRCO -- -18.2 -- %/V silabs.com | Building a more connected world. Rev. 2.20 | 89 EFM32LG Data Sheet Electrical Characteristics 4.11 Analog Digital Converter (ADC) Table 4.15. ADC Parameter Symbol Test Condition Input voltage range VADCIN Single-ended Differential Input range of external reference voltage, single-ended and differential VADCREFIN Min Typ Max Unit 0 -- VREF V -VREF/2 -- VREF/2 V 1.25 -- VDD V Input range of external negative VADCREFIN_CH7 reference voltage on channel 7 See VADCREFIN 0 -- VDD - 1.1 V Input range of external positive reference voltage on channel 6 VADCREFIN_CH6 See VADCREFIN 0.625 -- VDD V Common mode input range VADCCMIN 0 -- VDD V Input current IADCIN -- <100 -- nA Analog input common mode rejection ratio CMRRADC -- 65 -- dB Average active current IADC 1 MSamples/s, 12-bit, external reference -- 351 1 -- A 10 kSamples/s 12-bit, internal 1.25 V reference, WARMUPMODE in ADCn_CTRL set to 0b00 -- 67 1 -- A 10 kSamples/s 12-bit, internal 1.25 V reference, WARMUPMODE in ADCn_CTRL set to 0b01 -- 63 1 -- A 10 kSamples/s 12-bit, internal 1.25 V reference, WARMUPMODE in ADCn_CTRL set to 0b10 -- 64 1 -- A 2 pF sampling capacitors Input capacitance CADCIN -- 2 -- pF Input ON resistance RADCIN 1 -- -- M Input RC filter resistance RADCFILT -- 10 -- k Input RC filter/decoupling capacitance CADCFILT -- 250 -- fF Input bias current IADCBIASIN VSS < VIN < VDD -40 -- 40 nA Input offset current IADCOFFSETIN VSS < VIN < VDD -40 -- 40 nA ADC Clock Frequency fADCCLK -- -- 13 MHz Conversion time tADCCONV 6-bit 7 -- -- ADCCLK Cycles 8-bit 11 -- -- ADCCLK Cycles 12-bit 13 -- -- ADCCLK Cycles silabs.com | Building a more connected world. Rev. 2.20 | 90 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Min Typ Max Unit Acquisition time tADCACQ Programmable 1 -- 256 ADCCLK Cycles Required acquisition time for VDD/3 reference tADCACQVDD3 2 -- -- s Startup time of reference gener- tADCSTART ator and ADC core NORMAL mode -- 5 -- s KEEPADCWARM mode -- 1 -- s Signal-to-Noise Ratio (SNR) 1 MSamples/s, 12-bit, singleended, internal 1.25 V reference -- 59 -- dB 1 MSamples/s, 12-bit, singleended, internal 2.5 V reference -- 63 -- dB 1 MSamples/s, 12-bit, singleended, VDD reference -- 65 -- dB 1 MSamples/s, 12-bit, differential, internal 1.25 V reference -- 60 -- dB 1 MSamples/s, 12-bit, differential, internal 2.5 V reference -- 65 -- dB 1 MSamples/s, 12-bit, differential, 5 V reference -- 54 -- dB 1 MSamples/s, 12-bit, differential, VDD reference -- 67 -- dB 1 MSamples/s, 12-bit, differential, 2xVDD reference -- 69 -- dB 200 kSamples/s, 12-bit, singleended, internal 1.25 V reference -- 62 -- dB 200 kSamples/s, 12-bit, singleended, internal 2.5 V reference -- 63 -- dB 200 kSamples/s, 12-bit, singleended, VDD reference -- 67 -- dB 200 kSamples/s, 12-bit, differential, internal 1.25 V reference -- 63 -- dB 200 kSamples/s, 12-bit, differential, internal 2.5 V reference -- 66 -- dB 200 kSamples/s, 12-bit, differential, 5 V reference -- 66 -- dB 200 kSamples/s, 12-bit, differential, VDD reference 63 66 -- dB 200 kSamples/s, 12-bit, differential, 2xVDD reference -- 70 -- dB SNRADC silabs.com | Building a more connected world. Rev. 2.20 | 91 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Signal-to-Noise And Distortion Ratio (SINAD) SINADADC silabs.com | Building a more connected world. Min Typ Max Unit 1 MSamples/s, 12-bit, singleended, internal 1.25V reference -- 58 -- dB 1 MSamples/s, 12-bit, singleended, internal 2.5 V reference -- 62 -- dB 1 MSamples/s, 12-bit, singleended, VDD reference -- 64 -- dB 1 MSamples/s, 12-bit, differential, internal 1.25 V reference -- 60 -- dB 1 MSamples/s, 12-bit, differential, internal 2.5 V reference -- 64 -- dB 1 MSamples/s, 12-bit, differential, 5 V reference -- 54 -- dB 1 MSamples/s, 12-bit, differential, VDD reference -- 66 -- dB 1 MSamples/s, 12-bit, differential, 2xVDD reference -- 68 -- dB 200 kSamples/s, 12-bit, singleended, internal 1.25 V reference -- 61 -- dB 200 kSamples/s, 12-bit, singleended, internal 2.5 V reference -- 65 -- dB 200 kSamples/s, 12-bit, singleended, VDD reference -- 66 -- dB 200 kSamples/s, 12-bit, differential, internal 1.25 V reference -- 63 -- dB 200 kSamples/s, 12-bit, differential, internal 2.5 V reference -- 66 -- dB 200 kSamples/s, 12-bit, differential, 5V reference -- 66 -- dB 200 kSamples/s, 12-bit, differential, VDD reference 62 66 -- dB 200 kSamples/s, 12-bit, differential, 2xVDD reference -- 69 -- dB Rev. 2.20 | 92 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Spurious-Free Dynamic Range (SFDR) SFDRADC Offset voltage VADCOFFSET Min Typ Max Unit 1 MSamples/s, 12-bit, singleended, internal 1.25 V reference -- 64 -- dBc 1 MSamples/s, 12-bit, singleended, internal 2.5 V reference -- 76 -- dBc 1 MSamples/s, 12-bit, singleended, VDD reference -- 73 -- dBc 1 MSamples/s, 12-bit, differential, internal 1.25 V reference -- 66 -- dBc 1 MSamples/s, 12-bit, differential, internal 2.5 V reference -- 77 -- dBc 1 MSamples/s, 12-bit, differential, VDD reference -- 76 -- dBc 1 MSamples/s, 12-bit, differential, 2xVDD reference -- 75 -- dBc 1 MSamples/s, 12-bit, differential, 5 V reference -- 69 -- dBc 200 kSamples/s, 12-bit, singleended, internal 1.25 V reference -- 75 -- dBc 200 kSamples/s, 12-bit, singleended, internal 2.5 V reference -- 75 -- dBc 200 kSamples/s, 12-bit, singleended, VDD reference -- 76 -- dBc 200 kSamples/s, 12-bit, differential, internal 1.25 V reference -- 79 -- dBc 200 kSamples/s, 12-bit, differential, internal 2.5 V reference -- 79 -- dBc 200 kSamples/s, 12-bit, differential, 5 V reference -- 78 -- dBc 200 kSamples/s, 12-bit, differential, VDD reference 68 79 -- dBc 200 kSamples/s, 12-bit, differential, 2xVDD reference -- 79 -- dBc After calibration, single-ended -3.5 0.3 3 mV -- 0.3 -- mV -- -1.92 -- mV/C -- -6.3 -- ADC Codes/C After calibration, differential Thermometer output gradient TGRADADCTH Differential non-linearity (DNL) DNLADC VDD= 3.0 V, external 2.5V reference -1 0.7 4 LSB Integral non-linearity (INL), End point method INLADC VDD= 3.0 V, external 2.5V reference -- 1.2 3 LSB Missing codes MCADC 11.999 2 12 -- bits Gain error drift GAINED 1.25 V reference -- 0.01 3 0.033 4 %/C 2.5 V reference -- 0.01 3 0.03 4 %/C silabs.com | Building a more connected world. Rev. 2.20 | 93 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Min Typ Max Unit Offset error drift OFFSETED 1.25 V reference -- 0.2 3 0.7 4 LSB/C 2.5 V reference -- 0.2 3 0.62 4 LSB/C 1.25 V reference 1.2 1.25 1.3 V 2.5 V reference 2.4 2.5 2.6 V 1.25 V reference -12.4 2.9 18.2 mV/V 2.5 V reference, VDD > 2.5 V -24.6 5.7 35.2 mV/V 1.25 V reference -132 272 677 V/C 2.5 V reference -231 545 1271 V/C 1.25 V reference -- 67 97 A 2.5 V reference -- 55 72 A 1.25 V reference -- 99.85 -- % 2.5 V reference -- 100.01 -- % VREF voltage VREF voltage drift VREF temperature drift VREF current consumption ADC and DAC VREF matching VREF VREF_VDRIFT VREF_TDRIFT IVREF VREF_MATCH Note: 1. Includes required contribution from the voltage reference. 2. On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is missing, the neighbor codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full-scale input for chips that have the missing code issue. 3. Typical numbers given by abs(Mean) / (85 - 25). 4. Max number given by (abs(Mean) + 3x stddev) / (85 - 25). The integral non-linearity (INL) and differential non-linearity parameters are explained in the following two figures. Digital output code 4095 4094 4093 4092 INL=|[(VD-VSS)/VLSBIDEAL] - D| where 0 < D < 2N- 1 Actual ADC tranfer function before offset and gain correction Actual ADC tranfer function after offset and gain correction INL Error (End Point INL) 3 Ideal transfer curve 2 1 VOFFSET 0 Analog Input Figure 4.24. Integral Non-Linearity (INL) silabs.com | Building a more connected world. Rev. 2.20 | 94 EFM32LG Data Sheet Electrical Characteristics Digital output code DNL=|[(VD+1 - VD)/VLSBIDEAL] - 1| where 0 < D < 2N- 2 Full Scale Range 4095 4094 Example: Adjacent input value VD+1 corrresponds to digital output code D+1 4093 4092 Code width =2 LSB DNL=1 LSB Ideal transfer curve 5 Actual transfer function with one missing code. Example: Input value VDcorrresponds to digital output code D 0.5 LSB Ideal spacing between two adjacent codes VLSBIDEAL=1 LSB 4 3 2 1 Ideal 50% Transition Point Ideal Code Center 0 Analog Input Figure 4.25. Differential Non-Linearity (DNL) silabs.com | Building a more connected world. Rev. 2.20 | 95 EFM32LG Data Sheet Electrical Characteristics 4.11.1 Typical Performance 1.25V Reference 2.5V Reference 2XVDDVSS Reference 5VDIFF Reference VDD Reference Figure 4.26. ADC Frequency Spectrum, VDD = 3 V, Temp = 25 C silabs.com | Building a more connected world. Rev. 2.20 | 96 EFM32LG Data Sheet Electrical Characteristics 1.25V Reference 2.5V Reference 2XVDDVSS Reference 5VDIFF Reference VDD Reference Figure 4.27. ADC Integral Linearity Error vs Code, VDD = 3 V, Temp = 25 C silabs.com | Building a more connected world. Rev. 2.20 | 97 EFM32LG Data Sheet Electrical Characteristics 1.25V Reference 2.5V Reference 2XVDDVSS Reference 5VDIFF Reference VDD Reference Figure 4.28. ADC Differential Linearity Error vs Code, VDD = 3 V, Temp = 25 C silabs.com | Building a more connected world. Rev. 2.20 | 98 EFM32LG Data Sheet Electrical Characteristics Offset vs Supply Voltage, Temp = 25C 5 2.0 Vref=1V25 Vref=2V5 Vref=2XVDDVSS Vref=5VDIFF Vref=VDD 4 3 VRef=1V25 VRef=2V5 VRef=2XVDDVSS VRef=5VDIFF VRef=VDD 1.5 1.0 Actual Offset [LSB] 2 Actual Offset [LSB] Offset vs Temperature, VDD = 3V 1 0 -1 0.5 0.0 -2 -0.5 -3 -4 2.0 2.2 2.4 2.6 2.8 3.0 Vdd (V) 3.2 3.4 3.6 -1.0 -40 3.8 -15 5 25 Temp (C) 45 65 85 Figure 4.29. ADC Absolute Offset, Common Mode = VDD/2 Signal to Noise Ratio (SNR) 71 79.4 Spurious-Free Dynamic Range (SFDR) 2XVDDVSS 70 1V25 79.2 Vdd 69 79.0 67 5VDIFF 2V5 66 SFDR [dB] SNR [dB] 68 Vdd 2V5 78.8 78.6 2XVDDVSS 78.4 65 78.2 64 63 -40 -15 5 25 Temperature [C] 45 65 1V25 85 5VDIFF 78.0 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.30. ADC Dynamic Performance vs Temperature for all ADC References, VDD = 3 V silabs.com | Building a more connected world. Rev. 2.20 | 99 EFM32LG Data Sheet Electrical Characteristics 2600 Vdd=2.0 Vdd=3.0 Vdd=3.8 Sensor readout 2500 2400 2300 2200 2100 -40 -25 -15 -5 5 15 25 35 Temperature [C] 45 55 65 75 85 Figure 4.31. ADC Temperature Sensor Readout silabs.com | Building a more connected world. Rev. 2.20 | 100 EFM32LG Data Sheet Electrical Characteristics 4.12 Digital Analog Converter (DAC) Table 4.16. DAC Parameter Symbol Test Condition Min Typ Max Unit Output voltage range VDACOUT VDD voltage reference, single-ended 0 -- VDD V -VDD -- VDD V 0 -- VDD V 500 kSamples/s, 12-bit, internal 1.25 V reference, Continuous Mode -- 4001 -- A 100 kSamples/s, 12-bit, internal 1.25 V reference, Sample/Hold Mode -- 2001 -- A 1 kSamples/s 12-bit, internal 1.25 V reference, Sample/Off Mode -- 171 -- A -- -- 500 ksamples/ s Continuous Mode -- -- 1000 kHz Sample/Hold Mode -- -- 250 kHz Sample/Off Mode -- -- 250 kHz -- 2 -- cycles VDD voltage reference, differential Output common mode voltage range VDACCM Average active current IDAC Sample rate SRDAC DAC clock frequency fDAC Clock cycles per conversion CYCDACCONV Conversion time tDACCONV 2 -- -- s Settling time tDACSET- -- 5 -- s 500 kSamples/s, 12-bit, single-ended, internal 1.25V reference -- 58 -- dB 500 kSamples/s, 12-bit, single-ended, internal 2.5V reference -- 59 -- dB 500 kSamples/s, 12-bit, differential, internal 1.25V reference -- 58 -- dB 500 kSamples/s, 12-bit, differential, internal 2.5V reference -- 58 -- dB 500 kSamples/s, 12-bit, differential, VDD reference -- 59 -- dB SNDRDAC 500 kSamples/s, 12-bit, single-ended, internal 1.25V reference -- 57 -- dB 500 kSamples/s, 12-bit, single-ended, internal 2.5V reference -- 54 -- dB 500 kSamples/s, 12-bit, differential, internal 1.25V reference -- 56 -- dB 500 kSamples/s, 12-bit, differential, internal 2.5V reference -- 53 -- dB 500 kSamples/s, 12-bit, differential, VDD reference -- 55 -- dB TLE Signal-to-Noise Ratio (SNR) Signal-to-Noise plus Distortion Ratio (SNDR) SNRDAC silabs.com | Building a more connected world. Rev. 2.20 | 101 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Spurious-Free Dynamic Range (SFDR) Test Condition Min Typ Max Unit SFDRDAC 500 kSamples/s, 12-bit, single-ended, internal 1.25V reference -- 62 -- dBc 500 kSamples/s, 12-bit, single-ended, internal 2.5V reference -- 56 -- dBc 500 kSamples/s, 12-bit, differential, internal 1.25V reference -- 61 -- dBc 500 kSamples/s, 12-bit, differential, internal 2.5V reference -- 55 -- dBc 500 kSamples/s, 12-bit, differential, VDD reference -- 60 -- dBc Offset voltage, all packages except CSP VDACOFF- After calibration, single-ended -- 2 9 mV SET -- 2 -- mV Offset voltage, CSP devices VDACOFF- After calibration, single-ended -- 2 -- mV SET -- 2 -- mV After calibration, differential After calibration, differential Differential non-linearity DNLDAC -- 1 -- LSB Integral non-linearity INLDAC -- 5 -- LSB No missing codes MCDAC -- 12 -- bits Load current ILOAD_DC -- -- 11 mA VREF voltage VREF 1.25 V reference 1.2 1.25 1.3 V 2.5 V reference 2.4 2.5 2.6 V VREF_VDR 1.25 V reference -12.4 2.3 18.2 mV/V IFT -24.6 5.3 35.2 mV/V VREF voltage drift VREF temperature drift VREF current consumption ADC and DAC VREF matching 2.5 V reference, VDD > 2.5 V VREF_TDR 1.25 V reference -132 242 677 V/C IFT 2.5 V reference -231 507 1271 V/C IVREF 1.25 V reference -- 67 97 A 2.5 V reference -- 55 72 A VREF_MAT 1.25 V reference -- 99.85 -- % CH -- 100.01 -- % 2.5 V reference Note: 1. Measured with a static input code and no loading on the output. Includes required contribution from the voltage reference. silabs.com | Building a more connected world. Rev. 2.20 | 102 EFM32LG Data Sheet Electrical Characteristics 4.13 Operational Amplifier (OPAMP) Table 4.17. OPAMP Parameter Symbol Test Condition Active Current IOPAMP Open Loop Gain GOL silabs.com | Building a more connected world. Min Typ Max Unit (OPA2)BIASPROG=0xF,(OPA2)HALFBIAS=0x0, Unity Gain -- 370 460 A (OPA2)BIASPROG=0x7,(OPA2)HALFBIAS=0x1, Unity Gain -- 95 135 A (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, Unity Gain -- 13 25 A (OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, UnityGain -- 63 87 A (OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, UnityGain -- 18 27 A (OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, UnityGain -- 68 96 A (OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, UnityGain -- 18 27 A (OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, UnityGain -- 67 96 A (OPA2)BIASPROG=0xF,(OPA2)HALFBIAS=0x0 -- 101 -- dB (OPA2)BIASPROG=0x7,(OPA2)HALFBIAS=0x1 -- 98 -- dB (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1 -- 91 -- dB Rev. 2.20 | 103 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Gain Bandwidth Product GBWOPAMP silabs.com | Building a more connected world. Min Typ Max Unit (OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, DC bias = 0.3 V -- 0.3931 -- MHz (OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, DC bias = 1 V -- 0.4871 -- MHz (OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, DC bias = 2 V -- 0.3921 -- MHz (OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, DC bias = 2.7 V -- 0.3181 -- MHz (OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, DC bias = 0.3 V -- 1.5951 -- MHz (OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, DC bias = 1 V -- 2.6611 -- MHz (OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, DC bias = 2 V -- 2.5661 -- MHz (OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, DC bias = 2.7 V -- 1.7871 -- MHz (OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, DC bias = 0.3 V -- 0.4601 -- MHz (OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, DC bias = 1 V -- 0.4471 -- MHz (OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, DC bias = 2 V -- 0.3721 -- MHz (OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, DC bias = 2.7 V -- 0.2951 -- MHz (OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, DC bias = 0.3 V -- 1.8901 -- MHz (OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, DC bias = 1 V -- 2.8491 -- MHz (OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, DC bias = 2 V -- 2.5611 -- MHz (OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, DC bias = 2.7 V -- 1.7051 -- MHz (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, DC bias = 0.3 V -- 0.3391 -- MHz (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, DC bias = 1 V -- 0.4321 -- MHz (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, DC bias = 2 V -- 0.3471 -- MHz (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, DC bias = 2.7 V -- 0.2861 -- MHz (OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, DC bias = 0.3 V -- 1.2711 -- MHz (OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, DC bias = 1 V -- 1.4291 -- MHz (OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, DC bias = 2 V -- 1.2831 -- MHz Rev. 2.20 | 104 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Gain Bandwidth Product GBWOPAMP Phase Margin PMOPAMP Input Resistance RINPUT Load Resistance RLOAD DC Load Current ILOAD_DC Input Voltage VINPUT Output Voltage Min Typ Max Unit (OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, DC bias = 2.7 V -- 1.1361 -- MHz (OPA2)BIASPROG=0xF,(OPA2)HALFBIAS=0x0, DC bias = 1.5 V -- 6.12 -- MHz (OPA2)BIASPROG=0x7,(OPA2)HALFBIAS=0x1, DC bias = 1.5 V -- 1.82 -- MHz (OPA2)BIASPROG=0xF,(OPA2)HALFBIAS=0x0, CL=75 pF -- 64 -- (OPA2)BIASPROG=0x7,(OPA2)HALFBIAS=0x1, CL=75 pF -- 58 -- (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, CL=75 pF -- 58 -- -- 100 -- M OPA0/1 200 -- -- OPA/2 1000 -- -- -- -- 11 mA OPAxHCMDIS=0 VSS -- VDD V OPAxHCMDIS=1 VSS -- VDD-1.2 V VSS -- VDD V (OPA0) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 -13 0 11 mV (OPA1) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 -13 0.1 11 mV (OPA2) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 -13 0 11 mV (OPA2) Unity Gain, VSS<Vin<VDD-1.2,OPAxHCMDIS=1 -- 1 -- mV (OPA0) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 -- 0 -- mV (OPA1) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 -- 0.1 -- mV (OPA2) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 -13 0 11 mV (OPA2) Unity Gain, VSS<Vin<VDD-1.2,OPAxHCMDIS=1 -- 1 -- mV -- -- 0.02 mV/C VOUTPUT Input Offset Voltage, VOFFSET all packages except CSP Input Offset Voltage, VOFFSET CSP devices Input Offset Voltage Drift VOFFSET_DRIFT Input bias current I OPAMPBIASIN VSS < VIN < VDD -40 -- 40 nA Input offset current I OPAMPOFFSETI VSS < VIN < VDD -40 -- 40 nA silabs.com | Building a more connected world. Rev. 2.20 | 105 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Slew Rate SROPAMP Voltage Noise NOPAMP silabs.com | Building a more connected world. Min Typ Max Unit (OPA2)BIASPROG=0xF,(OPA2)HALFBIAS=0x0, 70 pF load Rising (Simulated at 25 C and VDD=3 V) -- 3.2 -- V/s (OPA2)BIASPROG=0x7,(OPA2)HALFBIAS=0x1, 70 pF load, Rising (Simulated at 25 Cand VDD=3 V) -- 0.8 -- V/s (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, 70 pF load, Rising -- 178 -- V/s (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, 70 pF load, Falling -- 198 -- V/s (OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, 70 pF load, Rising -- 969 -- V/s (OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, 70 pF load, Falling -- 969 -- V/s (OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, 70 pF load, Rising -- 166 -- V/s (OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, 70 pF load, Falling -- 180 -- V/s (OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, 70 pF load, Rising -- 918 -- V/s (OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, 70 pF load, Falling -- 937 -- V/s (OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, 70 pF load, Rising -- 173 -- V/s (OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, 70 pF load, Falling -- 191 -- V/s (OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, 70 pF load, Rising -- 935 -- V/s (OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, 70 pF load, Falling -- 950 -- V/s Vout=1V, RESSEL=0, 0.1 Hz<f<10 kHz, OPAxHCMDIS=0 -- 101 -- VRMS Vout=1V, RESSEL=0, 0.1 Hz<f<10 kHz, OPAxHCMDIS=1 -- 141 -- VRMS Vout=1V, RESSEL=0, 0.1 Hz<f<1 MHz, OPAxHCMDIS=0 -- 196 -- VRMS Vout=1V, RESSEL=0, 0.1 Hz<f<1 MHz, OPAxHCMDIS=1 -- 229 -- VRMS RESSEL=7, 0.1 Hz<f<10 kHz, OPAxHCMDIS=0 -- 1230 -- VRMS RESSEL=7, 0.1 Hz<f<10 kHz, OPAxHCMDIS=1 -- 2130 -- VRMS RESSEL=7, 0.1 Hz<f<1 MHz, OPAxHCMDIS=0 -- 1630 -- VRMS RESSEL=7, 0.1 Hz<f<1 MHz, OPAxHCMDIS=1 -- 2590 -- VRMS Rev. 2.20 | 106 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Min Typ Max Unit Note: 1. Measured with 70 pF load capacitance, 25 C, and 3 V, using a 100 mV p-p amplitude on the input signal. 2. Simulated with 70 pF load capacitance, 25 C, and 3 V, using a 1 mV p-p amplitude on the input signal. Figure 4.32. OPAMP Common Mode Rejection Ratio Figure 4.33. OPAMP Positive Power Supply Rejection Ratio silabs.com | Building a more connected world. Rev. 2.20 | 107 EFM32LG Data Sheet Electrical Characteristics Figure 4.34. OPAMP Negative Power Supply Rejection Ratio Figure 4.35. OPAMP Voltage Noise Spectral Density(Unity Gain) Vout=1V silabs.com | Building a more connected world. Rev. 2.20 | 108 EFM32LG Data Sheet Electrical Characteristics Figure 4.36. OPAMP Voltage Noise Spectral Density(Non-Unity Gain) silabs.com | Building a more connected world. Rev. 2.20 | 109 EFM32LG Data Sheet Electrical Characteristics 4.14 Analog Comparator (ACMP) Table 4.18. ACMP Parameter Symbol Input voltage range VACMPIN Input bias current I ACMPBIASIN Input offset current IACMPOFFSETIN ACMP Common Mode voltage range VACMPCM Active current IACMP Current consumption of internal voltage reference IACMPREF silabs.com | Building a more connected world. Test Condition Min Typ Max Unit 0 -- VDD V VSS < VIN < VDD -40 -- 40 nA VSS < VIN < VDD -40 -- 40 nA 0 -- VDD V BIASPROG=0b0000, FULLBIAS=0 and HALFBIAS=1 in ACMPn_CTRL register -- 0.11 0.41 A BIASPROG=0b1111, FULLBIAS= 0 and HALFBIAS=0 in ACMPn_CTRL register -- 2.871 151 A BIASPROG=0b1111, FULLBIAS= 1 and HALFBIAS=0 in ACMPn_CTRL register -- 1951 5201 A BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1 in ACMPn_CTRL register -- 0.81 2.21 A BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1 inACMPn_CTRL register -- 2.71 8.11 A Internal voltage reference off. Using external voltage reference -- 0 -- A Internal voltage reference -- 5 -- A Rev. 2.20 | 110 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Negative response time t RESPONSE_N silabs.com | Building a more connected world. Min Typ Max Unit BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=0 -- 353 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=1 -- 547 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=2 -- 578 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=3 -- 627 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=4 -- 670 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=5 -- 741 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=6 -- 811 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=7 -- 926 -- ns Rev. 2.20 | 111 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Negative response time t RESPONSE_N silabs.com | Building a more connected world. Min Typ Max Unit BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=0 -- 843 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=1 -- 1499 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=2 -- 1590 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=3 -- 1746 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=4 -- 1876 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=5 -- 2104 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=6 -- 2323 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=7 -- 2691 -- ns Rev. 2.20 | 112 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Positive response time t RESPONSE_P silabs.com | Building a more connected world. Min Typ Max Unit BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=0 -- 451 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=1 -- 643 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=2 -- 679 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=3 -- 725 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=4 -- 761 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=5 -- 826 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=6 -- 909 -- ns BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=7 -- 1021 -- ns Rev. 2.20 | 113 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Positive response time t RESPONSE_P Offset voltage VACMPOFFSET silabs.com | Building a more connected world. Min Typ Max Unit BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=0 -- 1014 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=1 -- 1671 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=2 -- 1786 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=3 -- 1933 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=4 -- 2046 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=5 -- 2262 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=6 -- 2531 -- ns BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=7 -- 2907 -- ns BIASPROG= 0b1010, FULLBIAS=0 and HALFBIAS=0 in ACMPn_CTRL register -12 0 12 mV BIASPROG= 0b0100, FULLBIAS=0, HALFBIAS=1, and LPREF=0 in ACMPn_CTRL register -14.4 0.4 14.8 mV BIASPROG= 0b1111, FULLBIAS=0, HALFBIAS=1, and LPREF=0 in ACMPn_CTRL register -13.3 0.3 13.2 mV Rev. 2.20 | 114 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Min Typ Max Unit Negative hysteresis VACMPHYST_N BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=0 -0.3 1.2 4.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=1 -18.0 -12.2 -4.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=2 -25.0 -17.6 -9.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=3 -33.0 -22.8 -13.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=4 -40.0 -27.8 -16.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=5 -46.0 -33.4 -21.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=6 -56.0 -39.9 -25.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=7 -65.0 -46.4 -29.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=0 -0.3 1.2 4.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=1 4.0 12.2 21.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=2 9.0 17.1 25.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=3 13.0 22.3 33.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=4 17.0 28.2 42.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=5 20.0 34.0 49.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=6 25.0 39.8 58.0 mV BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=7 29.4 46.4 68.0 mV Positive hysteresis VACMPHYST_P silabs.com | Building a more connected world. Rev. 2.20 | 115 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol Test Condition Capacitive Sense Internal Resistance RCSRES Startup time tACMPSTART VDD_SCALED input accuracy V VDDSCALED Min Typ Max Unit CSRESSEL=0b00 in ACMPn_INPUTSEL -- 39 -- k CSRESSEL=0b01 in ACMPn_INPUTSEL -- 71 -- k CSRESSEL=0b10 in ACMPn_INPUTSEL -- 104 -- k CSRESSEL=0b11 in ACMPn_INPUTSEL -- 136 -- k -- -- 10 s VDD_SCALED=9,BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, HYSTSEL=0, LPREF=0 -- -10.8 -- mV VDD_SCALED=9,BIASPROG=0b0000, FULLBIAS=0, HALFBIAS=1, HYSTSEL=0, LPREF=1 -- 1.3 -- mV Note: 1. Reference current not included. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given in in the following equation. IACMPREF is zero if an external voltage reference is used. I ACMPTOTAL = I ACMP + I ACMPREF silabs.com | Building a more connected world. Rev. 2.20 | 116 EFM32LG Data Sheet Electrical Characteristics Current Consumption, HYSTSEL = 4 2.5 Response Time 4.5 HYSTSEL=0.0 HYSTSEL=2.0 HYSTSEL=4.0 HYSTSEL=6.0 4.0 3.5 Response Time [us] Current [uA] 2.0 1.5 1.0 3.0 2.5 2.0 1.5 1.0 0.5 0.5 0.0 4 8 ACMP_CTRL_BIASPROG 0 12 0.0 0 2 4 6 8 10 ACMP_CTRL_BIASPROG 12 14 Hysteresis 100 BIASPROG=0.0 BIASPROG=4.0 BIASPROG=8.0 BIASPROG=12.0 Hysteresis [mV] 80 60 40 20 0 0 1 2 4 3 ACMP_CTRL_HYSTSEL 5 6 7 Figure 4.37. ACMP Characteristics, Vdd = 3 V, Temp = 25 C, FULLBIAS = 0, HALFBIAS = 1 silabs.com | Building a more connected world. Rev. 2.20 | 117 EFM32LG Data Sheet Electrical Characteristics 4.15 Voltage Comparator (VCMP) Table 4.19. VCMP Parameter Symbol Input voltage range Test Condition Min Typ Max Unit VVCMPIN -- VDD -- V VCMP Common Mode voltage range VVCMPCM -- VDD -- V Active current IVCMP BIASPROG=0b0000 and HALFBIAS=1 in VCMPn_CTRL register -- 0.31 0.61 A BIASPROG=0b1111 and HALFBIAS=0 in VCMPn_CTRL register. LPREF=0. -- 221 351 A Startup time reference generator tVCMPREF NORMAL -- 10 -- s Offset voltage VVCMPOFFSET Single-ended -- 10 -- mV Differential -- 10 -- mV Negative hysteresis VVCMPHYST_N BIASPROG=0b0000, HALFBIAS=1, LPREF=1 -46.6 -15.6 11.4 mV Positive hysteresis VVCMPHYST_P BIASPROG=0b0000, HALFBIAS=1, LPREF=1 -7.5 23.4 46.6 mV Hysteresis delta VVCMPHYST_DELTA BIASPROG=0b0000, HALFBIAS=1, LPREF=1 4.2 35.2 70.0 mV Startup time tVCMPSTART -- -- 10 s Negative response time tRESPONSE_N BIASPROG=0b0000, HALFBIAS=1, LPREF=1, HYSTSEL=0 -- 372.3 -- s Positive response time t RESPONSE_P BIASPROG=0b0000, HALFBIAS=1, LPREF=1, HYSTSEL=0 -- 865.7 -- s Note: 1. Includes required contribution from the voltage reference. The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in accordance with the following equation: V DD Trigger Level = 1.667V + 0.034 x TRIGLEVEL silabs.com | Building a more connected world. Rev. 2.20 | 118 EFM32LG Data Sheet Electrical Characteristics 4.16 EBI WRSETUP (0, 1, 2, ...) EBI_BL[N-1:0] WRSTRB (1, 2, 3, ...) WRHOLD (0, 1, 2, ...) Z EBI_BL tOSU_WEn EBI_A[N-1:0] tOH_WEn Z EBI_A tOSU_WEn EBI_AD[15:0] tOH_WEn Z DATA[15:0] tOSU_WEn tOH_WEn tOSU_WEn tOH_WEn EBI_CSn tWIDTH_WEn EBI_WEn Figure 4.38. EBI Write Enable Timing Table 4.20. EBI Write Enable Timing Parameter Symbol Output hold time, from trailing EBI_WEn/EBI_NAND- tOH_WEn 1 2 3 4 WEn edge to EBI_AD, EBI_A, EBI_CSn, EBI_BLn invalid Min Typ Max Unit -6.00 + (WRHOLD x tHFCORECLK) -- -- ns Output setup time, from EBI_AD, EBI_A, EBI_CSn, EBI_BLn valid to leading EBI_WEn/EBI_NANDWEn edge tOSU_WEn 1 2 3 4 5 -14.00 + (WRSETUP x tHFCORECLK) -- -- ns EBI_WEn/EBI_NANDWEn pulse width tWIDTH_WEn 1 2 3 4 -7.00 + ((WRSTRB + 1) x tHFCORECLK) -- -- ns 5 Note: 1. Applies for all addressing modes (figure only shows D16 addressing mode) 2. Applies for both EBI_WEn and EBI_NANWEn (figure only shows EBI_WEn) 3. Applies for all polarities (figure only shows active low signals) 4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD) 5. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFWE=0. The leading edge of EBI_WEn can be moved to the right by setting HALFWE=1. This decreases the length of tWIDTH_WEn and increases the length of tOSU_WEn by 1/2 x tHFCLKNODIV. silabs.com | Building a more connected world. Rev. 2.20 | 119 EFM32LG Data Sheet Electrical Characteristics ADDRSETUP (1, 2, 3, ...) EBI_AD[15:0] ADDRHOLD (0, 1, 2, ...) WRSETUP (0, 1, 2, ...) WRSTRB (1, 2, 3, ...) ADDR[16:1] WRHOLD (0, 1, 2, ...) DATA[15:0] Z tWIDTH_ALEn EBI_ALE tWIDTH_ALEn tOSU_ALEn EBI_CSn EBI_WEn Figure 4.39. EBI Address Latch Enable Related Output Timing Table 4.21. EBI Address Latch Enable Related Output Timing Parameter Symbol Output hold time, from trailing tOH_ALEn 1 2 3 4 EBI_ALE edge to EBI_AD invalid Output setup time, from EBI_AD valid to leading EBI_ALE edge tOSU_ALEn 1 2 4 EBI_ALEn pulse width tWIDTH_ALEn 1 2 3 4 Min Typ Max Unit -6.00 + (ADDRHOLD5 x tHFCORECLK) -- -- ns -13.00 + (0 x tHFCORECLK) -- -- ns -7.00 + ((ADDRSETUP + 1) x tHFCORECLK) -- -- ns Note: 1. Applies to addressing modes D8A24ALE and D16A16ALE (figure only shows D16A16ALE) 2. Applies for all polarities (figure only shows active low signals) 3. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFALE=0. The trailing edge of EBI_ALE can be moved to the left by setting HALFALE=1. This decreases the length of tWIDTH_ALEn and increases the length of tOH_ALEn by tHFCORECLK - 1/2 x tHFCLKNODIV. 4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD) 5. Figure only shows a write operation. For a multiplexed read operation the address hold time is controlled via the RDSETUP state instead of via the ADDRHOLD state. silabs.com | Building a more connected world. Rev. 2.20 | 120 EFM32LG Data Sheet Electrical Characteristics RDSETUP (0, 1, 2, ...) EBI_BL[1:0] RDSTRB (1, 2, 3, ...) RDHOLD (0, 1, 2, ...) EBI_BL Z tSU_REn EBI_A[27:0] tH_REn EBI_A Z tH_REn tSU_REn EBI_AD[15:8] ADDR[7:0] Z tSU_REn tH_REn tSU_REn tH_REn EBI_CSn EBI_AD[7:0] EBI_REn Z DATA[7:0] Z tWIDTH_REn Figure 4.40. EBI Read Enable Related Output Timing Table 4.22. EBI Read Enable Related Output Timing Parameter Symbol Min Typ Max Unit Output hold time, from trailing tOH_REn 1 2 3 4 EBI_REn/EBI_NANDREn edge to EBI_AD, EBI_A, EBI_CSn, EBI_BLn invalid -10.00 + (RDHOLD x tHFCORECLK) -- -- ns Output setup time, from EBI_AD, EBI_A, EBI_CSn, EBI_BLn valid to leading EBI_REn/ EBI_NANDREn edge tOSU_REn 1 2 3 4 5 -10.00 + (RDSETUP x tHFCORECLK) -- -- ns EBI_REn pulse width tWIDTH_REn 1 2 3 4 5 6 -9.00 + ((RDSTRB + 1) x tHFCORECLK) -- -- ns Note: 1. Applies for all addressing modes (figure only shows D8A8. Output timing for EBI_AD only applies to multiplexed addressing modes D8A24ALE and D16A16ALE) 2. Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn) 3. Applies for all polarities (figure only shows active low signals) 4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD) 5. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFRE=0. The leading edge of EBI_REn can be moved to the right by setting HALFRE=1. This decreases the length of tWIDTH_REn and increases the length of tOSU_REn by 1/2 x tHFCLKNODIV. 6. When page mode is used, RDSTRB is replaced by RDPA for page hits. silabs.com | Building a more connected world. Rev. 2.20 | 121 EFM32LG Data Sheet Electrical Characteristics RDHOLD (0, 1, 2, ...) RDSTRB (1, 2, 3, ...) RDSETUP (0, 1, 2, ...) EBI_A[N-1:0] ADDR[N:1] EBI_AD[15:0] Z Z DATA[15:0] Z EBI_CSn tSU_REn EBI_REn tH_REn Figure 4.41. EBI Read Enable Related Timing Requirements Table 4.23. EBI Read Enable Related Timing Requirements Parameter Symbol Min Typ Max Unit Setup time, from EBI_AD valid to trailing EBI_REn edge tSU_REn 1 2 3 4 37 -- -- ns Hold time, from trailing EBI_REn edge to EBI_AD invalid tH_REn 1 2 3 4 -1 -- -- ns Note: 1. Applies for all addressing modes (figure only shows D16A8). 2. Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn) 3. Applies for all polarities (figure only shows active low signals) 4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD) RDSETUP (0, 1, 2, ...) RDSTRB (1, 2, 3, ...) SYNC (3) RDHOLD (0, 1, 2, ...) EBI_RDY EBI_AD[15:0] Z DATA[15:0] EBI_CSn tSU_ARDY EBI_REn tH_ARDY Figure 4.42. EBI Ready/Wait Related Timing Requirements silabs.com | Building a more connected world. Rev. 2.20 | 122 EFM32LG Data Sheet Electrical Characteristics Table 4.24. EBI Ready/Wait Related Timing Requirements Parameter Symbol Min Typ Max Unit Setup time, from EBI_ARDY valid to trailing EBI_REn, EBI_WEn edge tSU_ARDY 1 2 3 4 37 + (3 x tHFCORECLK) -- -- ns Hold time, from trailing EBI_REn, EBI_WEn edge to EBI_ARDY invalid tH_ARDY 1 2 3 4 -1 + (3 x tHFCORECLK) -- -- ns Note: 1. Applies for all addressing modes (figure only shows D16A8.) 2. Applies for EBI_REn, EBI_WEn (figure only shows EBI_REn) 3. Applies for all polarities (figure only shows active low signals) 4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD) silabs.com | Building a more connected world. Rev. 2.20 | 123 EFM32LG Data Sheet Electrical Characteristics 4.17 LCD Table 4.25. LCD Parameter Symbol Frame rate Min Typ Max Unit fLCDFR 30 -- 200 Hz Number of segments supported NUMSEG -- 36x8 -- seg LCD supply voltage range VLCD Internal boost circuit enabled 2.0 -- 3.8 V Steady state current consumption. ILCD Display disconnected, static mode, framerate 32 Hz, all segments on. -- 250 -- nA Display disconnected, quadruplex mode, framerate 32 Hz, all segments on, bias mode to ONETHIRD in LCD_DISPCTRL register. -- 550 -- nA Internal voltage boost off -- 0 -- A Internal voltage boost on, boosting from 2.2 V to 3.0 V. -- 8.4 -- A VBLEV of LCD_DISPCTRL register to LEVEL0 -- 3.02 -- V VBLEV of LCD_DISPCTRL register to LEVEL1 -- 3.15 -- V VBLEV of LCD_DISPCTRL register to LEVEL2 -- 3.28 -- V VBLEV of LCD_DISPCTRL register to LEVEL3 -- 3.41 -- V VBLEV of LCD_DISPCTRL register to LEVEL4 -- 3.54 -- V VBLEV of LCD_DISPCTRL register to LEVEL5 -- 3.67 -- V VBLEV of LCD_DISPCTRL register to LEVEL6 -- 3.73 -- V VBLEV of LCD_DISPCTRL register to LEVEL7 -- 3.74 -- V Steady state Current contribution of internal boost. ILCDBOOST Boost Voltage VBOOST Test Condition The total LCD current is given by the following equation. ILCDBOOST is zero if internal boost is off. I LCDTOTAL = I LCD + I LCDBOOST silabs.com | Building a more connected world. Rev. 2.20 | 124 EFM32LG Data Sheet Electrical Characteristics 4.18 I2C Table 4.26. I2C Standard-mode (Sm) Parameter Symbol Min Typ Max Unit SCL clock frequency fSCL 0 -- 1001 kHz SCL clock low time tLOW 4.7 -- -- s SCL clock high time tHIGH 4.0 -- -- s SDA set-up time tSU,DAT 250 -- -- ns SDA hold time tHD,DAT 8 -- 34502,3 ns Repeated START condition set-up time tSU,STA 4.7 -- -- s (Repeated) START condition hold time tHD,STA 4.0 -- -- s STOP condition set-up time tSU,STO 4.0 -- -- s Bus free time between a STOP and a START condition tBUF 4.7 -- -- s Note: 1. For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32LG Reference Manual. 2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). 3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4). Table 4.27. I2C Fast-mode (Fm) Parameter Symbol Min Typ Max Unit SCL clock frequency fSCL 0 4001 kHz SCL clock low time tLOW 1.3 s SCL clock high time tHIGH 0.6 s SDA set-up time tSU,DAT 100 ns SDA hold time tHD,DAT 8 Repeated START condition set-up time tSU,STA 0.6 s (Repeated) START condition hold time tHD,STA 0.6 s STOP condition set-up time tSU,STO 0.6 s Bus free time between a STOP and a START condition tBUF 1.3 s 9002,3 ns Note: 1. For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32LG Reference Manual. 2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). 3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4). silabs.com | Building a more connected world. Rev. 2.20 | 125 EFM32LG Data Sheet Electrical Characteristics Table 4.28. I2C Fast-mode Plus (Fm+) Parameter Symbol Min Typ Max Unit SCL clock frequency fSCL 0 10001 kHz SCL clock low time tLOW 0.5 s SCL clock high time tHIGH 0.26 s SDA set-up time tSU,DAT 50 ns SDA hold time tHD,DAT 8 ns Repeated START condition set-up time tSU,STA 0.26 s (Repeated) START condition hold time tHD,STA 0.26 s STOP condition set-up time tSU,STO 0.26 s Bus free time between a STOP and a START condition tBUF 0.5 s Note: 1. For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32LG Reference Manual. silabs.com | Building a more connected world. Rev. 2.20 | 126 EFM32LG Data Sheet Electrical Characteristics 4.19 USART SPI CS tCS_MO tSCKL_MO SCLK CLKPOL = 0 tSCLK SCLK CLKPOL = 1 MOSI tSU_MI tH_MI MISO Figure 4.43. SPI Master Timing Table 4.29. SPI Master Timing Parameter Symbol SCLK period tSCLK1 2 CS to MOSI Test Condition Min Typ Max Unit 2 x tHFPERCLK -- -- ns tCS_MO 1 2 -2.00 -- 2.00 ns SCLK to MOSI tSCLK_MO 1 2 -1.00 -- 3.00 ns MISO setup time tSU_MI 1 2 36.00 -- -- ns MISO hold time tH_MI 1 2 -6.00 -- -- ns Min Typ Max Unit 2 x tHFPERCLK -- -- ns IOVDD = 3.0 V Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD) Table 4.30. SPI Master Timing with SSSEARLY and SMSDELAY Parameter Symbol Test Condition SCLK period tSCLK1 2 CS to MOSI tCS_MO 1 2 -2.00 -- 2.00 ns SCLK to MOSI tSCLK_MO 1 2 -1.00 -- 3.00 ns MISO setup time tSU_MI 1 2 -32.00 -- -- ns MISO hold time tH_MI 1 2 63.00 -- -- ns IOVDD = 3.0 V Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD) silabs.com | Building a more connected world. Rev. 2.20 | 127 EFM32LG Data Sheet Electrical Characteristics CS tCS_ACT_MI tCS_DIS_MI SCLK CLKPOL = 0 tSCLK_HI SCLK tSU_MO CLKPOL = 1 tSCLK_LO tSCLK tH_MO MOSI tSCLK_MI MISO Figure 4.44. SPI Slave Timing Table 4.31. SPI Slave Timing Parameter Symbol Min Typ Max Unit SCKL period tSCLK_sl1 2 6 x tHFPERCLK -- -- ns SCLK high period tSCLK_hi 1 2 3 x tHFPERCLK -- -- ns SCLK low period tSCLK_lo 1 2 3 x tHFPERCLK -- -- ns CS active to MISO tCS_ACT_MI 1 2 5.00 -- 35.00 ns CS disable to MISO high-impedance tCS_DIS_MI 1 2 5.00 -- 35.00 ns MOSI setup time tSU_MO 1 2 5.00 -- -- ns MOSI hold time tH_MO 1 2 2 + 2 x tHFPERCLK -- -- ns SCLK to MISO tSCLK_MI 1 2 7 + tHFPERCLK -- 42 + 2 x tHFPERCLK ns Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD) Table 4.32. SPI Slave Timing with SSSEARLY and SMSDELAY Parameter Symbol Min Typ Max Unit SCKL period tSCLK_sl1 2 6 x tHFPERCLK -- -- ns SCLK high period tSCLK_hi 1 2 3 x tHFPERCLK -- -- ns SCLK low period tSCLK_lo 1 2 3 x tHFPERCLK -- -- ns CS active to MISO tCS_ACT_MI 1 2 5.00 -- 35.00 ns CS disable to MISO tCS_DIS_MI 1 2 5.00 -- 35.00 ns MOSI setup time tSU_MO 1 2 5.00 -- -- ns MOSI hold time tH_MO 1 2 2 + 2 x tHFPERCLK -- -- ns silabs.com | Building a more connected world. Rev. 2.20 | 128 EFM32LG Data Sheet Electrical Characteristics Parameter Symbol SCLK to MISO tSCLK_MI 1 2 Min Typ Max Unit -264 + tHFPERCLK -- -234 + 2 x tHFPERCLK ns Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD) 4.20 Digital Peripherals Table 4.33. Digital Peripherals Parameter Symbol Test Condition Min Typ Max Unit USART current IUSART USART idle current, clock enabled -- 4.0 -- A/MHz UART current IUART UART idle current, clock enabled -- 3.8 -- A/MHz LEUART current ILEUART LEUART idle current, clock enabled -- 194.0 -- nA I2C current II2C I2C idle current, clock enabled -- 7.6 -- A/MHz TIMER current ITIMER TIMER_0 idle current, clock enabled -- 6.5 -- A/MHz LETIMER current ILETIMER LETIMER idle current, clock enabled -- 85.8 -- nA PCNT current IPCNT PCNT idle current, clock enabled -- 91.4 -- nA RTC current IRTC RTC idle current, clock enabled -- 54.6 -- nA LCD current ILCD LCD idle current, clock enabled -- 72.7 -- nA AES current IAES AES idle current, clock enabled -- 1.8 -- A/MHz GPIO current IGPIO GPIO idle current, clock enabled -- 3.4 -- A/MHz EBI current IEBI EBI idle current, clock enabled -- 6.5 -- A/MHz PRS current IPRS PRS idle current -- 3.9 -- A/MHz DMA current IDMA Clock enable -- 10.9 -- A/MHz LE Peripheral Interface Clock current ILFCLK Using LFXO, LFA clock tree -- 12.2 -- A/MHz Using LFXO, LFB clock tree -- 4.3 -- A/MHz silabs.com | Building a more connected world. Rev. 2.20 | 129 EFM32LG Data Sheet Pin Definitions 5. Pin Definitions Note: Please refer to the application note AN0002 EFM32 Hardware Design Considerations for guidelines on designing Printed Circuit Boards (PCBs) for the EFM32LG. 5.1 EFM32LG230 (QFN64) 5.1.1 Pinout The EFM32LG230 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.1. EFM32LG230 Pinout (top view, not to scale) silabs.com | Building a more connected world. Rev. 2.20 | 130 EFM32LG Data Sheet Pin Definitions Table 5.1. Device Pinout QFN64 Pin# and Name Pin # Pin Name 0 VSS 1 Pin Alternate Functionality / Description Analog Timers Communication Other PA0 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 TIM0_CC2 #0/1 CMU_CLK0 #0 ETM_TD0 #3 4 PA3 TIM0_CDTI0 #0 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 TIM0_CDTI1 #0 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 TIM0_CDTI2 #0 7 PA6 8 IOVDD_0 Digital IO power supply 0. 9 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2 I2C0_SDA #4 #0 10 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3 I2C0_SCL #4 #0 11 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 12 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 13 PC4 ACMP0_CH4 / OPAMP_P0 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 14 PC5 ACMP0_CH5 / OPAMP_N0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 15 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 17 PA8 TIM2_CC0 #0 18 PA9 TIM2_CC1 #0 19 PA10 TIM2_CC2 #0 20 RESETn 21 PB11 Ground. LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. DAC0_OUT0 / OPAMP_OUT0 silabs.com | Building a more connected world. TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 Rev. 2.20 | 131 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 22 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 23 AVDD_1 Analog power supply 1. 24 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 25 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. 28 PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 33 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 34 PD6 ADC0_CH6 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 35 PD7 ADC0_CH7 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 36 PD8 BU_VIN 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0 #2 #2 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 44 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0 45 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT silabs.com | Building a more connected world. Other CMU_CLK1 #1 LES_CH6 #0 ETM_TCLK #2 CMU_CLK0 #1 LES_CH12 #0 Rev. 2.20 | 132 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog Timers Communication Other 46 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 47 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 LES_CH14 #0 48 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 LES_CH15 #0 DBG_SWO #1 49 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 50 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 51 PF2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 52 PF3 TIM0_CDTI0 #2/5 PRS_CH0 #1 ETM_TD3 #1 53 PF4 TIM0_CDTI1 #2/5 PRS_CH1 #1 54 PF5 TIM0_CDTI2 #2/5 PRS_CH2 #1 55 IOVDD_5 56 PE8 PCNT2_S0IN #1 PRS_CH3 #1 57 PE9 PCNT2_S1IN #1 58 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX 59 PE11 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 60 PE12 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 61 PE13 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 62 PE14 TIM3_CC0 #0 LEU0_TX #2 63 PE15 TIM3_CC1 #0 LEU0_RX #2 64 PA15 TIM3_CC2 #0 LES_CH13 #0 Digital IO power supply 5. silabs.com | Building a more connected world. Rev. 2.20 | 133 EFM32LG Data Sheet Pin Definitions 5.1.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.2. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 134 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_VIN PD8 Battery input for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A PC12 LT Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 ETM_TCLK PC15 PD1 PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. PD7 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. PF3 silabs.com | Building a more connected world. Rev. 2.20 | 135 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 4 5 I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 I2C1 Serial Data input / output. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. silabs.com | Building a more connected world. 3 6 Description Rev. 2.20 | 136 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PD0 Operational Amplifier 2 output. silabs.com | Building a more connected world. Timer 3 Capture Compare input / output channel 0. Rev. 2.20 | 137 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 Timer 3 Capture Compare input / output channel 2. US0_CLK PE12 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PC8 PC14 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PC10 PC11 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD0 PD6 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 US2_CLK PC4 USART2 clock input / output. US2_CS PC5 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX US2_TX PC3 PC2 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.20 | 138 EFM32LG Data Sheet Pin Definitions 5.1.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG230 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.3. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A PA15 -- -- -- -- PA10 PA9 PA8 -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B -- -- -- PB8 PB7 -- -- -- -- -- -- -- PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 -- -- -- -- -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0 Port C Port D Port E Port F PB14 PB13 PA12 PB11 PC15 PC14 PC13 PC12 PC11 PC10 -- -- -- -- -- -- PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- -- -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 5.1.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG230 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.2. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 139 EFM32LG Data Sheet Pin Definitions 5.2 EFM32LG232 (TQFP64) 5.2.1 Pinout The EFM32LG232 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.3. EFM32LG232 Pinout (top view, not to scale) Table 5.4. Device Pinout QFP64 Pin# and Name Pin # Pin Name 1 Pin Alternate Functionality / Description Analog Timers Communication Other PA0 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 TIM0_CC2 #0/1 silabs.com | Building a more connected world. CMU_CLK0 #0 ETM_TD0 #3 Rev. 2.20 | 140 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 4 PA3 TIM0_CDTI0 #0 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 TIM0_CDTI1 #0 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 TIM0_CDTI2 #0 7 IOVDD_0 8 VSS 9 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2 I2C0_SDA #4 #0 10 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3 I2C0_SCL #4 #0 11 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 12 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 13 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 14 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 15 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 17 PA8 TIM2_CC0 #0 18 PA9 TIM2_CC1 #0 19 PA10 TIM2_CC2 #0 20 RESETn 21 PB11 22 VSS 23 AVDD_1 Analog power supply 1. 24 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 25 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. LEU1_TX #1 Other LES_ALTEX4 #0 ETM_TD3 #3 Digital IO power supply 0. Ground. Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 Ground. silabs.com | Building a more connected world. Rev. 2.20 | 141 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog Timers Communication 28 PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 33 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 34 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 35 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 36 PD8 BU_VIN 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0 #2 #2 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 44 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0 45 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT 46 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 47 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 LES_CH14 #0 48 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 LES_CH15 #0 DBG_SWO #1 silabs.com | Building a more connected world. Other CMU_CLK1 #1 LES_CH6 #0 ETM_TCLK #2 CMU_CLK0 #1 LES_CH12 #0 LES_CH13 #0 Rev. 2.20 | 142 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin # Pin Name 49 Pin Alternate Functionality / Description Analog Timers Communication Other PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 50 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 51 PF2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 52 PF3 TIM0_CDTI0 #2/5 PRS_CH0 #1 ETM_TD3 #1 53 PF4 TIM0_CDTI1 #2/5 PRS_CH1 #1 54 PF5 TIM0_CDTI2 #2/5 PRS_CH2 #1 55 IOVDD_5 56 VSS 57 PE8 PCNT2_S0IN #1 PRS_CH3 #1 58 PE9 PCNT2_S1IN #1 59 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX 60 PE11 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 61 PE12 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 62 PE13 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 63 PE14 TIM3_CC0 #0 LEU0_TX #2 64 PE15 TIM3_CC1 #0 LEU0_RX #2 Digital IO power supply 5. Ground. silabs.com | Building a more connected world. Rev. 2.20 | 143 EFM32LG Data Sheet Pin Definitions 5.2.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.5. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 144 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_VIN PD8 Battery input for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. DAC0_OUT1ALT / OPAMP_OUT1A PC12 LT PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. DBG_SWCLK PF0 PF0 PF0 PF0 DBG_SWDIO PF1 PF1 PF1 PF1 DBG_SWO PF2 PC15 PD1 PD2 ETM_TCLK PD7 PC6 ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 Debug-interface Serial Wire clock input. Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. PF3 silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Embedded Trace Module ETM clock . I2C1 Serial Clock Line input / output. Rev. 2.20 | 145 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 PB11 5 6 Description I2C1_SDA PC4 LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 LETIM0_OUT1 PD7 LEU0_RX PD5 LEU0_TX PD4 LEU1_RX PC7 LEU1_TX PC6 LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PB11 I2C1 Serial Data input / output. PF0 PC4 Low Energy Timer LETIM0, output channel 0. PF1 PC5 Low Energy Timer LETIM0, output channel 1. PB14 PE15 PF1 PA0 LEUART0 Receive input. PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEUART1 Receive input. PA5 silabs.com | Building a more connected world. LEUART1 Transmit output. Also used as receive input in half duplex communication. Rev. 2.20 | 146 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1. US0_CLK PE12 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PC8 PC14 PB14 PB14 USART0 chip select input / output. PD0 Operational Amplifier 2 output. silabs.com | Building a more connected world. Rev. 2.20 | 147 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 PB8 PC1 6 Description USART0 Asynchronous Receive. US0_RX PE11 PC10 PC11 PE12 PE13 PB7 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PC0 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. US1_RX PC1 PD1 PD6 USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. PD0 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD7 US2_CLK PC4 USART2 clock input / output. US2_CS PC5 USART2 chip select input / output. US2_RX PC3 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_TX USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PC2 USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.2.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG232 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.6. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A -- -- -- -- -- PA10 PA9 PA8 -- -- PA5 PA4 PA3 PA2 PA1 PA0 Port B -- -- PB11 -- -- PB8 PB7 -- -- -- -- -- -- -- PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 -- -- -- -- -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0 Port C Port D Port E Port F PB14 PB13 PC15 PC14 PC13 PC12 PC11 PC10 -- -- -- -- -- -- PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- -- silabs.com | Building a more connected world. -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.20 | 148 EFM32LG Data Sheet Pin Definitions 5.2.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG232 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.4. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 149 EFM32LG Data Sheet Pin Definitions 5.3 EFM32LG280 (LQFP100) 5.3.1 Pinout The EFM32LG280 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.5. EFM32LG280 Pinout (top view, not to scale) silabs.com | Building a more connected world. Rev. 2.20 | 150 EFM32LG Data Sheet Pin Definitions Table 5.7. Device Pinout LQFP100 Pin# and Name Pin # Pin Name 1 Pin Alternate Functionality / Description EBI Timers Communication Other PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 4 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 7 PA6 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 8 IOVDD_0 9 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2 10 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2 11 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2 12 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 13 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 14 PB5 EBI_A21 #0/1/2 US2_CLK #1 15 PB6 EBI_A22 #0/1/2 US2_CS #1 16 VSS 17 IOVDD_1 18 19 20 21 Analog CMU_CLK0 #0 ETM_TD0 #3 Digital IO power supply 0. Ground. Digital IO power supply 1. PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 silabs.com | Building a more connected world. Rev. 2.20 | 151 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other 22 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 23 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 24 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 25 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 26 PA7 EBI_CSTFT #0/1/2 27 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0 28 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0 29 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0 30 PA11 EBI_HSNC #0/1/2 31 IOVDD_2 32 VSS 33 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1 34 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1 35 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1 36 RESETn 37 PB9 EBI_A03 #0/1/2 U1_TX #2 38 PB10 EBI_A04 #0/1/2 U1_RX #2 39 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 40 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 41 AVDD_1 42 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 43 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 44 IOVDD_3 Digital IO power supply 3. 45 AVDD_0 Analog power supply 0. 46 PD0 Digital IO power supply 2. Ground. Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. Analog power supply 1. ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 silabs.com | Building a more connected world. PCNT2_S0IN #0 US1_TX #1 Rev. 2.20 | 152 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog 47 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT 48 PD2 ADC0_CH2 49 PD3 ADC0_CH3 OPAMP_N2 50 PD4 51 52 EBI Timers Communication Other TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 53 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 54 PD8 BU_VIN 55 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 56 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 57 VDD_DREG 58 VSS 59 DECOUPLE 60 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 61 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 62 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 63 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1 64 PE4 EBI_A11 #0/1/2 US0_CS #1 65 PE5 EBI_A12 #0/1/2 US0_CLK #1 66 PE6 EBI_A13 #0/1/2 US0_RX #1 67 PE7 EBI_A14 #0/1/2 US0_TX #1 68 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 69 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 70 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 71 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0 EBI_A27 #0/1/2 CMU_CLK1 #1 Power supply for on-chip voltage regulator. Ground. Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. silabs.com | Building a more connected world. Rev. 2.20 | 153 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Alternate Functionality / Description Communication Other U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 U1_RX #0 LES_CH13 #0 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 U0_TX #3 LES_CH14 #0 75 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 76 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 77 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 78 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 79 PF3 EBI_ALE #0 TIM0_CDTI0 #2/5 PRS_CH0 #1 ETM_TD3 #1 80 PF4 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1 81 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1 82 IOVDD_5 83 VSS 84 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0 85 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0 86 PF8 EBI_WEn #1 TIM0_CC2 #2 87 PF9 EBI_REn #1 88 PD9 EBI_CS0 #0/1/2 89 PD10 EBI_CS1 #0/1/2 90 PD11 EBI_CS2 #0/1/2 91 PD12 EBI_CS3 #0/1/2 92 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 93 PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1 94 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX 95 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 72 73 74 Pin Name Analog PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT EBI Timers Digital IO power supply 5. Ground. silabs.com | Building a more connected world. ETM_TCLK #1 ETM_TD0 #1 PRS_CH3 #1 Rev. 2.20 | 154 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Name 96 Pin Alternate Functionality / Description Analog EBI Timers Communication Other PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 97 PE13 EBI_AD05 #0/1/2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 98 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 99 PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 100 PA15 EBI_AD08 #0/1/2 TIM3_CC2 #0 silabs.com | Building a more connected world. Rev. 2.20 | 155 EFM32LG Data Sheet Pin Definitions 5.3.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.8. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 156 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A PC12 LT Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 PD1 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. silabs.com | Building a more connected world. PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 157 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 158 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 PF3 silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 159 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 silabs.com | Building a more connected world. PC4 Low Energy Timer LETIM0, output channel 0. Rev. 2.20 | 160 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 PB7 PD6 PD0 Operational Amplifier 2 output. silabs.com | Building a more connected world. Timer 1 Capture Compare input / output channel 0. Rev. 2.20 | 161 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PB10 PE3 UART1 Receive input. U1_TX PC12 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX PC3 PB4 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.20 | 162 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality US2_TX 0 1 PC2 2 3 4 5 6 Description USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PB3 USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.3.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG280 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.9. GPIO Pinout Port Port A Port B Port C Port D Port E Port F Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 PA15 PA14 PA13 PA12 PA11 PA10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 -- -- -- -- -- -- -- -- -- -- 5.3.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG280 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.6. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 163 EFM32LG Data Sheet Pin Definitions 5.4 EFM32LG290 (BGA112) 5.4.1 Pinout The EFM32LG290 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.7. EFM32LG290 Pinout (top view, not to scale) Table 5.10. Device Pinout BGA112 Pin# and Name Pin # Pin Name A1 Pin Alternate Functionality / Description Analog EBI Timers Communication PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 A2 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 A3 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 silabs.com | Building a more connected world. Other CMU_CLK1 #2 LES_ALTEX6 #0 Rev. 2.20 | 164 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin # Pin Name A4 Pin Alternate Functionality / Description Analog EBI Timers Communication Other PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1 A5 PD10 EBI_CS1 #0/1/2 A6 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 A7 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1 A8 PF4 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1 A9 PE4 EBI_A11 #0/1/2 U0_RX #0 US0_CS #1 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 U0_TX #3 LES_CH14 #0 A11 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 B1 PA15 EBI_AD08 #0/1/2 B2 PE13 EBI_AD05 #0/1/2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 B3 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX B4 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1 B5 PD11 EBI_CS2 #0/1/2 B6 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1 B7 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 B8 PF3 B9 PE5 A10 EBI_ALE #0 TIM3_CC2 #0 PC12 B11 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT C1 PA1 C2 PRS_CH0 #1 ETM_TD3 #1 TIM0_CDTI0 #2/5 EBI_A12 #0/1/2 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT U0_TX #0 US0_CLK #1 U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 U1_RX #0 LES_CH13 #0 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 C3 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX C4 PD13 C5 PD12 EBI_CS3 #0/1/2 C6 PF9 EBI_REn #1 B10 silabs.com | Building a more connected world. ETM_TD1 #1 ETM_TD0 #1 Rev. 2.20 | 165 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin # Pin Name C7 VSS C8 Pin Alternate Functionality / Description Analog EBI Timers Communication Other PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 C9 PE6 EBI_A13 #0/1/2 C10 PC10 ACMP1_CH2 EBI_A10 #1/2 C11 PC11 ACMP1_CH3 EBI_ALE #1/2 D1 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 D2 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 D3 PB15 D4 VSS D5 IOVDD_6 D6 PD9 D7 IOVDD_5 D8 PF1 D9 PE7 D10 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 D11 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 E1 PA6 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 E2 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 E3 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 E4 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2 E8 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 E9 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 E10 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 E11 PE3 F1 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2 F2 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2 F3 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 Ground. US0_RX #1 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 US0_TX #2 LES_CH11 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1 Ground. Digital IO power supply 6. EBI_CS0 #0/1/2 Digital IO power supply 5. TIM0_CC1 #5 LETIM0_OUT1 #2 EBI_A14 #0/1/2 BU_STAT silabs.com | Building a more connected world. US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 US0_TX #1 EBI_A10 #0 U1_RX #3 ACMP1_O #1 US2_TX #1 Rev. 2.20 | 166 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name F4 PB4 F8 VDD_DREG Power supply for on-chip voltage regulator. F9 VSS_DREG Ground for on-chip voltage regulator. F10 PE2 F11 DECOUPLE G1 PB5 EBI_A21 #0/1/2 US2_CLK #1 G2 PB6 EBI_A22 #0/1/2 US2_CS #1 G3 VSS G4 IOVDD_0 Digital IO power supply 0. G8 IOVDD_4 Digital IO power supply 4. G9 VSS G10 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 G11 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 H2 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 H3 PD14 H4 PA7 EBI_CSTFT #0/1/2 H5 PA8 EBI_DCLK #0/1/2 H6 VSS H7 IOVDD_3 H8 PD8 BU_VIN H9 PD5 ADC0_CH5 OPAMP_OUT2 #0 H10 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT H1 H11 J1 Analog EBI Timers Communication EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 TIM3_CC2 #1 U1_TX #3 BU_VOUT EBI_A09 #0 Other ACMP0_O #1 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. Ground. Ground. I2C0_SDA #3 TIM2_CC0 #0 Ground. Digital IO power supply 3. silabs.com | Building a more connected world. CMU_CLK1 #1 EBI_A24 #0/1/2 LEU0_RX #0 ETM_TD3 #0/2 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 Rev. 2.20 | 167 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog EBI Timers Communication Other J2 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 J3 PD15 J4 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1 J5 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0 J6 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0 J7 PB9 EBI_A03 #0/1/2 U1_TX #2 J8 PB10 EBI_A04 #0/1/2 U1_RX #2 J9 PD2 ADC0_CH2 J10 PD3 ADC0_CH3 OPAMP_N2 J11 PD4 ADC0_CH4 OPAMP_P2 K1 PB7 LFXTAL_P K2 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 K3 PA13 K4 VSS K5 PA11 K6 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. K7 AVSS_1 Analog ground 1. K8 AVDD_2 Analog power supply 2. K9 AVDD_1 Analog power supply 1. K10 AVSS_0 Analog ground 0. I2C0_SCL #3 EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 LEU0_TX #0 ETM_TD2 #0/2 TIM1_CC0 #3 US0_TX #4 US1_CLK #0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 EBI_A01 #0/1/2 TIM2_CC1 #1 LES_CH4 #0 Ground. EBI_HSNC #0/1/2 K11 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT L1 PB8 LFXTAL_N L2 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 L3 PA14 L4 IOVDD_1 L5 PB11 TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 TIM1_CC1 #3 US0_RX #4 US1_CS #0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 EBI_A02 #0/1/2 TIM2_CC2 #1 DBG_SWO #2 LES_CH5 #0 Digital IO power supply 1. DAC0_OUT0 / OPAMP_OUT0 silabs.com | Building a more connected world. TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 Rev. 2.20 | 168 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog L6 PB12 DAC0_OUT1 / OPAMP_OUT1 L7 AVSS_2 L8 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 L9 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 L10 AVDD_0 L11 PD0 EBI Timers Communication LETIM0_OUT1 #1 I2C1_SCL #1 Other Analog ground 2. Analog power supply 0. ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 silabs.com | Building a more connected world. PCNT2_S0IN #0 US1_TX #1 Rev. 2.20 | 169 EFM32LG Data Sheet Pin Definitions 5.4.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.11. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 170 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A PC12 LT Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 PD1 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. silabs.com | Building a more connected world. PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 171 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 172 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 173 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 silabs.com | Building a more connected world. PC4 Low Energy Timer LETIM0, output channel 0. Rev. 2.20 | 174 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 PB7 PD6 PD0 Operational Amplifier 2 output. silabs.com | Building a more connected world. Timer 1 Capture Compare input / output channel 0. Rev. 2.20 | 175 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PB10 PE3 UART1 Receive input. U1_TX PC12 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX PC3 PB4 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.20 | 176 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality US2_TX 0 1 PC2 2 3 4 5 6 Description USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PB3 USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.4.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG290 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.12. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port F -- -- -- -- -- -- 5.4.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG290 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.8. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 177 EFM32LG Data Sheet Pin Definitions 5.5 EFM32LG295 (BGA120) 5.5.1 Pinout The EFM32LG295 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.9. EFM32LG295 Pinout (top view, not to scale) Table 5.13. Device Pinout BGA120 Pin# and Name Pin # Pin Name A1 Pin Alternate Functionality / Description Analog EBI Timers Communication PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 A2 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 A3 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 silabs.com | Building a more connected world. Other CMU_CLK1 #2 LES_ALTEX6 #0 Rev. 2.20 | 178 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin # Pin Name A4 Pin Alternate Functionality / Description Analog EBI Timers Communication Other PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1 A5 PD11 EBI_CS2 #0/1/2 A6 PD9 EBI_CS0 #0/1/2 A7 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 A8 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1 A9 PF4 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1 A10 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 A11 USB_VREGI Input to internal 3.3V USB regulator A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator A13 PF11 B1 PA15 EBI_AD08 #0/1/2 B2 PE13 EBI_AD05 #0/1/2 B3 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 B4 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1 B5 PD12 EBI_CS3 #0/1/2 B6 PD10 EBI_CS1 #0/1/2 B7 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1 B8 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 B9 PF3 EBI_ALE #0 TIM0_CDTI0 #2/5 B10 PF1 B11 PF12 B12 USB_VBUS B13 PF10 C1 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 C2 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 C3 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX C4 PD13 C5 VSS C6 IOVDD_0 C7 PF9 U0_RX #0 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 U1_RX #1 TIM3_CC2 #0 TIM0_CC1 #5 LETIM0_OUT1 #2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 US0_RX #0 LES_ALTEX5 #0 BOOT_RX U0_TX #0 PRS_CH0 #1 ETM_TD3 #1 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 USB 5.0 V VBUS input. U1_TX #1 ETM_TD1 #1 Ground. Digital IO power supply 0. silabs.com | Building a more connected world. EBI_REn #1 ETM_TD0 #1 Rev. 2.20 | 179 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin # Pin Name C8 VSS C9 IOVDD_1 C10 PF0 C11 PE4 Pin Alternate Functionality / Description Analog EBI Timers Communication Other TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 Ground. Digital IO power supply 1. EBI_A11 #0/1/2 US0_CS #1 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 U0_TX #3 LES_CH14 #0 C13 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 D1 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 D2 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 D3 PB15 D11 PE5 C12 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1 EBI_A12 #0/1/2 US0_CLK #1 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT D13 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT E1 PA6 EBI_AD15 #0/1/2 E2 PA5 EBI_AD14 #0/1/2 E3 PA4 EBI_AD13 #0/1/2 E11 PE6 EBI_A13 #0/1/2 E12 PC10 ACMP1_CH2 EBI_A10 #1/2 E13 PC11 ACMP1_CH3 EBI_ALE #1/2 F1 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2 F2 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2 F3 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2 F11 PE7 EBI_A14 #0/1/2 F12 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 F13 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 D12 silabs.com | Building a more connected world. U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 U1_RX #0 LES_CH13 #0 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 US0_RX #1 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 US0_TX #2 LES_CH11 #0 US0_TX #1 Rev. 2.20 | 180 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin # Pin Name G1 Pin Alternate Functionality / Description Analog EBI Timers Communication PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 G2 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 G3 IOVDD_2 G11 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 G12 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 G13 PE3 H1 Other Digital IO power supply 2. BU_STAT EBI_A10 #0 U1_RX #3 PB5 EBI_A21 #0/1/2 US2_CLK #1 H2 PB6 EBI_A22 #0/1/2 US2_CS #1 H3 VSS H11 VDD_DREG H12 PE2 BU_VOUT EBI_A09 #0 H13 PC7 ACMP0_CH7 EBI_A06 #0/1/2 J1 PD14 I2C0_SDA #3 J2 PD15 I2C0_SCL #3 J3 VSS J11 IOVDD_3 J12 PC6 J13 DECOUPLE ACMP1_O #1 Ground. Power supply for on-chip voltage regulator. TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 Ground. Digital IO power supply 3. ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 EBI_A05 #0/1/2 LES_CH6 #0 ETM_TCLK #2 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 K2 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 K3 IOVDD_4 K11 VSS Ground. K12 VSS Ground. K13 PD8 BU_VIN PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT K1 L1 Digital IO power supply 4. silabs.com | Building a more connected world. CMU_CLK1 #1 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 Rev. 2.20 | 181 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog EBI Timers Communication Other L2 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 L3 PA7 L4 IOVDD_5 L5 VSS Ground. L6 VSS Ground. L7 IOVDD_6 L8 PB9 EBI_A03 #0/1/2 U1_TX #2 L9 PB10 EBI_A04 #0/1/2 U1_RX #2 EBI_CSTFT #0/1/2 Digital IO power supply 5. Digital IO power supply 6. PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 L11 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 L12 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 L13 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 M1 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 M2 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 M3 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0 M4 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0 M5 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1 M6 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1 M7 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. M8 AVSS_1 Analog ground 1. M9 AVDD_2 Analog power supply 2. M10 AVDD_1 Analog power supply 1. M11 AVSS_0 Analog ground 0. M12 PD3 L10 ADC0_CH3 OPAMP_N2 silabs.com | Building a more connected world. TIM0_CC2 #3 US1_CS #1 LES_CH4 #0 ETM_TD1 #0/2 Rev. 2.20 | 182 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog M13 PD6 N1 EBI Timers Communication Other ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 N2 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 N3 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0 N4 PA11 EBI_HSNC #0/1/2 N5 PA12 EBI_A00 #0/1/2 N6 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 N7 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 N8 AVSS_2 N9 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 N10 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 N11 AVDD_0 N12 PD2 ADC0_CH2 N13 PD5 ADC0_CH5 OPAMP_OUT2 #0 LES_CH5 #0 TIM2_CC0 #1 Analog ground 2. Analog power supply 0. silabs.com | Building a more connected world. EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 LEU0_RX #0 ETM_TD3 #0/2 Rev. 2.20 | 183 EFM32LG Data Sheet Pin Definitions 5.5.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.14. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 184 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. DAC0_OUT0 / OPAMP_OUT0 PB11 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. DAC0_OUT0ALT / OPAMP_OUT0ALT PC0 DAC0_OUT1 / OPAMP_OUT1 PB12 DAC0_OUT1ALT / OPAMP_OUT1ALT PC12 PC13 OPAMP_OUT2 PD5 PD0 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1. PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Operational Amplifier 2 output. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 PD1 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. silabs.com | Building a more connected world. PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 185 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 186 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 187 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. silabs.com | Building a more connected world. Rev. 2.20 | 188 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 silabs.com | Building a more connected world. Timer 2 Capture Compare input / output channel 0. Rev. 2.20 | 189 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PF11 PB10 PE3 UART1 Receive input. U1_TX PC12 PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX US2_TX PC3 PC2 PB4 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.20 | 190 EFM32LG Data Sheet Pin Definitions 5.5.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG295 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.15. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port F -- -- -- PF12 PF11 PF10 5.5.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG295 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.10. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 191 EFM32LG Data Sheet Pin Definitions 5.6 EFM32LG330 (QFN64) 5.6.1 Pinout The EFM32LG330 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.11. EFM32LG330 Pinout (top view, not to scale) Table 5.16. Device Pinout QFN64 Pin# and Name Pin # Pin Name 0 VSS 1 2 Pin Alternate Functionality / Description Analog Timers Communication Other PA0 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 Ground. silabs.com | Building a more connected world. Rev. 2.20 | 192 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 3 PA2 TIM0_CC2 #0/1 CMU_CLK0 #0 ETM_TD0 #3 4 PA3 TIM0_CDTI0 #0 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 TIM0_CDTI1 #0 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 TIM0_CDTI2 #0 7 PA6 8 IOVDD_0 Digital IO power supply 0. 9 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2 I2C0_SDA #4 #0 10 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3 I2C0_SCL #4 #0 11 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 12 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 13 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 14 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 15 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 17 PA8 TIM2_CC0 #0 18 PA9 TIM2_CC1 #0 19 PA10 TIM2_CC2 #0 20 RESETn 21 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 22 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 23 AVDD_1 Analog power supply 1. 24 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 25 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. silabs.com | Building a more connected world. Rev. 2.20 | 193 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. 28 PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 30 PD2 ADC0_CH2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 33 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 34 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 35 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 36 PD8 BU_VIN 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0 #2 #2 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 44 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0 45 USB_VREGI Input to internal 3.3V USB regulator 46 USB_VREGO Output and decoupling for internal 3.3V USB regulator 47 PF10 USB_DM 48 PF11 USB_DP 49 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 50 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 silabs.com | Building a more connected world. Other CMU_CLK1 #1 LES_CH6 #0 ETM_TCLK #2 Rev. 2.20 | 194 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 51 PF2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 52 USB_VBUS 53 PF12 54 PF5 55 IOVDD_5 56 PE8 PCNT2_S0IN #1 57 PE9 PCNT2_S1IN #1 58 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX 59 PE11 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 60 PE12 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 61 PE13 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 62 PE14 TIM3_CC0 #0 LEU0_TX #2 63 PE15 TIM3_CC1 #0 LEU0_RX #2 64 PA15 TIM3_CC2 #0 USB 5.0 V VBUS input. USB_ID TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1 Digital IO power supply 5. silabs.com | Building a more connected world. PRS_CH3 #1 Rev. 2.20 | 195 EFM32LG Data Sheet Pin Definitions 5.6.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.17. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_VIN PD8 Battery input for Backup Power Domain PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 196 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 CMU_CLK0 PA2 CMU_CLK1 PA1 DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 1 PD8 2 3 4 5 6 Description PD7 Clock Management Unit, clock output number 0. PE12 Clock Management Unit, clock output number 1. Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PD0 Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A LT Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. PD1 Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 DBG_SWDIO PF1 PF1 PF1 PF1 DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. ETM_TCLK PD7 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 I2C1 Serial Data input / output. LES_ALTEX0 PD6 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. silabs.com | Building a more connected world. LESENSE alternate exite output 0. Rev. 2.20 | 197 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. PD0 silabs.com | Building a more connected world. 3 4 5 6 Description Operational Amplifier 2 output. Rev. 2.20 | 198 EFM32LG Data Sheet Pin Definitions Alternate Functionality OPAMP_P2 LOCATION 0 1 2 3 4 5 PD4 6 Description Operational Amplifier 2 external positive input. PCNT0_S0IN PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC2 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC3 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PF5 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PE12 PB11 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 Timer 3 Capture Compare input / output channel 2. US0_CLK PE12 PC9 PB13 PB13 USART0 clock input / output. US0_CS PE13 PC8 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX US0_TX PE11 PE10 PC10 PC11 silabs.com | Building a more connected world. PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. USART0 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.20 | 199 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART1 Asynchronous Receive. US1_RX PC1 PD1 PD0 PD6 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 US2_CLK PC4 USART2 clock input / output. US2_CS PC5 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX PC3 USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. US2_TX PC2 USB_DM PF10 USB D- pin. USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_V BUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_V REGI USB Input to internal 3.3 V regulator USB_VREGO USB_V REGO USB Decoupling for internal 3.3 V USB regulator and regulator output silabs.com | Building a more connected world. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.20 | 200 EFM32LG Data Sheet Pin Definitions 5.6.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG330 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.18. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A PA15 -- -- -- -- PA10 PA9 PA8 -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B -- -- -- PB8 PB7 -- -- -- -- -- -- -- Port C -- -- -- -- PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 -- -- -- -- -- -- -- -- -- -- -- -- PF5 -- -- PF2 PF1 PF0 Port E Port F PB14 PB13 PB12 PB11 PC11 PC10 -- -- PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- PF12 PF11 PF10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 5.6.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG330 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.12. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 201 EFM32LG Data Sheet Pin Definitions 5.7 EFM32LG332 (TQFP64) 5.7.1 Pinout The EFM32LG332 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.13. EFM32LG332 Pinout (top view, not to scale) Table 5.19. Device Pinout QFP64 Pin# and Name Pin # Pin Name 1 Pin Alternate Functionality / Description Analog Timers Communication Other PA0 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 TIM0_CC2 #0/1 silabs.com | Building a more connected world. CMU_CLK0 #0 ETM_TD0 #3 Rev. 2.20 | 202 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 4 PA3 TIM0_CDTI0 #0 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 TIM0_CDTI1 #0 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 TIM0_CDTI2 #0 7 IOVDD_0 8 VSS 9 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2 I2C0_SDA #4 #0 10 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3 I2C0_SCL #4 #0 11 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 12 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 13 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 14 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 15 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 17 PA8 TIM2_CC0 #0 18 PA9 TIM2_CC1 #0 19 PA10 TIM2_CC2 #0 20 RESETn 21 PB11 22 VSS 23 AVDD_1 Analog power supply 1. 24 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 25 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. LEU1_TX #1 Other LES_ALTEX4 #0 ETM_TD3 #3 Digital IO power supply 0. Ground. Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 Ground. silabs.com | Building a more connected world. Rev. 2.20 | 203 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog Timers Communication 28 PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 30 PD2 ADC0_CH2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 33 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 34 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 35 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 36 PD8 BU_VIN 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0 #2 #2 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 44 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0 45 USB_VREGI Input to internal 3.3V USB regulator 46 USB_VREGO Output and decoupling for internal 3.3V USB regulator 47 PF10 USB_DM 48 PF11 USB_DP 49 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 50 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 51 PF2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 silabs.com | Building a more connected world. Other CMU_CLK1 #1 LES_CH6 #0 ETM_TCLK #2 Rev. 2.20 | 204 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 52 USB_VBUS USB 5.0 V VBUS input. 53 PF12 54 PF5 55 IOVDD_5 56 VSS 57 PE8 PCNT2_S0IN #1 58 PE9 PCNT2_S1IN #1 59 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX 60 PE11 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 61 PE12 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 62 PE13 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 63 PE14 TIM3_CC0 #0 LEU0_TX #2 64 PE15 TIM3_CC1 #0 LEU0_RX #2 USB_ID TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1 Digital IO power supply 5. Ground. silabs.com | Building a more connected world. PRS_CH3 #1 Rev. 2.20 | 205 EFM32LG Data Sheet Pin Definitions 5.7.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.20. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_VIN PD8 Battery input for Backup Power Domain PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 206 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 CMU_CLK0 PA2 CMU_CLK1 PA1 DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT 1 PD8 2 3 4 5 6 Description PD7 Clock Management Unit, clock output number 0. PE12 Clock Management Unit, clock output number 1. Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 DAC0_OUT1ALT / OPAMP_OUT1A LT PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PD1 PD2 ETM_TCLK PD7 PC6 ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 I2C1_SDA PC4 LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. Note that this function is not enabled after reset, and must be enabled by software to be used. Embedded Trace Module ETM clock . I2C1 Serial Clock Line input / output. PB11 silabs.com | Building a more connected world. I2C1 Serial Data input / output. Rev. 2.20 | 207 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LETIM0_OUT0 PD6 LETIM0_OUT1 PD7 LEU0_RX PD5 LEU0_TX PD4 LEU1_RX PC7 LEU1_TX PC6 LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. OPAMP_OUT2 PD5 PB11 2 3 4 5 6 Description PF0 PC4 Low Energy Timer LETIM0, output channel 0. PF1 PC5 Low Energy Timer LETIM0, output channel 1. PB14 PE15 PF1 PA0 LEUART0 Receive input. PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEUART1 Receive input. LEUART1 Transmit output. Also used as receive input in half duplex communication. PA5 PD0 Operational Amplifier 2 output. PCNT0_S0IN PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC1 PD7 Pulse Counter PCNT0 input number 1. silabs.com | Building a more connected world. Rev. 2.20 | 208 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC2 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC3 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PF5 4 PC4 5 PF5 6 Description Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PE12 PB11 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1. US0_CLK PE12 PC9 PB13 PB13 USART0 clock input / output. US0_CS PE13 PC8 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PC10 PC11 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 silabs.com | Building a more connected world. USART1 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.20 | 209 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 PD0 3 4 5 6 Description USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD7 US2_CLK PC4 USART2 clock input / output. US2_CS PC5 USART2 chip select input / output. US2_RX PC3 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. US2_TX PC2 USB_DM PF10 USB D- pin. USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_V BUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_V REGI USB Input to internal 3.3 V regulator USB_VREGO USB_V REGO USB Decoupling for internal 3.3 V USB regulator and regulator output USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.7.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG332 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.21. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A - - - - - PA10 PA9 PA8 - - PA5 PA4 PA3 PA2 PA1 PA0 Port B - - PB11 - - PB8 PB7 - - - - - - - Port C - - - - PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D - - - - - PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 - - - - - - - - - - - - PF5 - - PF2 PF1 PF0 Port E Port F PB14 PB13 - - PE15 PE14 PE13 PE12 PE11 PE10 - - - PF12 PF11 PF10 silabs.com | Building a more connected world. Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.20 | 210 EFM32LG Data Sheet Pin Definitions 5.7.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG332 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.14. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 211 EFM32LG Data Sheet Pin Definitions 5.8 EFM32LG360 (CSP81) 5.8.1 Pinout The EFM32LG360 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.15. EFM32LG360 Pinout (top view, not to scale) Table 5.22. Device Pinout CSP81 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog A1 PF10 U1_TX #1 USB_DM A2 PF11 U1_RX #1 USB_DP A3 PF2 silabs.com | Building a more connected world. Timers TIM0_CC2 #5 Communication LEU0_TX #4 Other ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 Rev. 2.20 | 212 EFM32LG Data Sheet Pin Definitions CSP81 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other A4 VSS A5 IOVDD_5 A6 PE9 PCNT2_S1IN #1 A7 PE11 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX A8 PE12 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 A9 PA15 TIM3_CC2 #0 B1 USB_VREGI Input to internal 3.3V USB regulator B2 USB_VBUS USB 5.0 V VBUS input. B3 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 B4 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 B5 PF5 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1 B6 PE8 PCNT2_S0IN #1 B7 PE13 B8 PA0 TIM0_CC0 #0/1/4 B9 PA2 TIM0_CC2 #0/1 C1 USB_VREGO Ground. Digital IO power supply 5. PRS_CH3 #1 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 CMU_CLK0 #0 ETM_TD0 #3 Output and decoupling for internal 3.3V USB regulator TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 U1_RX #0 LES_CH13 #0 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 U0_TX #3 LES_CH14 #0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 C2 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT C3 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT C4 PF0 C5 PF12 C6 PE10 TIM1_CC0 #1 US0_TX #0 C7 PE14 TIM3_CC0 #0 LEU0_TX #2 C8 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 C9 PA3 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 D1 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 D2 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0 USB_ID silabs.com | Building a more connected world. BOOT_TX Rev. 2.20 | 213 EFM32LG Data Sheet Pin Definitions CSP81 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog D3 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT D4 PC9 ACMP1_CH1 D5 PC8 ACMP1_CH0 D6 Communication Other U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 PA4 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 D7 PA5 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 D8 PA6 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 D9 IOVDD_0 E1 PE4 US0_CS #1 E2 PE5 US0_CLK #1 E3 PE3 BU_STAT E4 PC7 ACMP0_CH7 E5 PE15 E6 PB5 E7 PB3 PCNT1_S0IN #1 US2_TX #1 E8 PB4 PCNT1_S1IN #1 US2_RX #1 E9 VSS F1 DECOUPLE F2 PE2 BU_VOUT F3 PC6 ACMP0_CH6 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 F5 PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 F6 PA8 F7 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT TIM0_CDTI0 #4 F8 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT TIM0_CC1 #4 PCNT0_S0IN #2 F9 PB6 F4 Timers Digital IO power supply 0. U1_RX #3 ACMP1_O #1 LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0 #2 #2 TIM3_CC1 #0 LEU0_RX #2 US2_CLK #1 Ground. Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 PCNT2_S0IN #0 US1_TX #1 TIM2_CC0 #0 silabs.com | Building a more connected world. US2_TX #0 LES_CH2 #0 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2 I2C0_SDA #4 #0 US2_CS #1 Rev. 2.20 | 214 EFM32LG Data Sheet Pin Definitions CSP81 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other G1 VDD_DREG Power supply for on-chip voltage regulator. G2 VSS_DREG Ground for on-chip voltage regulator. G3 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 G4 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 G5 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 G6 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 G7 PA9 G8 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 G9 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT TIM0_CC2 #4 PCNT0_S1IN #2 H1 PD8 BU_VIN H2 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 H3 PD2 ADC0_CH2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 H4 VSS H5 AVSS_0 Analog ground 0. H6 AVDD_0 Analog power supply 0. H7 PA10 H8 PC5 ACMP0_CH5 DAC0_N0 / PD6OPAMP_N0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 H9 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 J1 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 J2 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT US1_RX #1 DBG_SWO #2 J3 IOVDD_3 Digital IO power supply 3. J4 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 J5 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 J6 AVDD_1 Analog power supply 1. J7 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. TIM2_CC1 #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3 I2C0_SCL #4 #0 CMU_CLK1 #1 Ground. TIM2_CC2 #0 silabs.com | Building a more connected world. TIM0_CC0 #3 PCNT2_S1IN #0 Rev. 2.20 | 215 EFM32LG Data Sheet Pin Definitions CSP81 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication J8 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 J9 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 silabs.com | Building a more connected world. Other Rev. 2.20 | 216 EFM32LG Data Sheet Pin Definitions 5.8.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.23. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 217 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A PC12 LT Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 ETM_TCLK PC15 PD1 PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. PD7 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. Rev. 2.20 | 218 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 I2C1 Serial Data input / output. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 silabs.com | Building a more connected world. LEUART1 Receive input. Rev. 2.20 | 219 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LEU1_TX PC6 PA5 LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PC13 PC2 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PC14 PC3 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PC15 PC4 TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2. LEUART1 Transmit output. Also used as receive input in half duplex communication. PD0 Operational Amplifier 2 output. PF5 silabs.com | Building a more connected world. PF5 Timer 0 Complimentary Deat Time Insertion channel 2. Rev. 2.20 | 220 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PA4 PC15 UART0 Receive input. U0_TX PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PF11 PE3 UART1 Receive input. U1_TX PC12 PF10 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. US0_RX PE11 PC10 PE12 PB8 PC1 USART0 Asynchronous Receive. PC11 PE13 PB7 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX PC3 PB4 PB3 USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. US2_TX PC2 USB_DM PF10 USB D- pin. USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. silabs.com | Building a more connected world. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.20 | 221 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USB_VBUS USB_V BUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_V REGI USB Input to internal 3.3 V regulator USB_VREGO USB_V REGO USB Decoupling for internal 3.3 V USB regulator and regulator output 5.8.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG360 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.24. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A PA15 - - - - PA10 PA9 PA8 - PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B - - - PB8 PB7 PB6 PB5 PB4 PB3 - - - PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 - PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 - - PE5 PE4 PE3 PE2 - - - - - - PF5 - - PF2 PF1 PF0 Port C Port D Port E Port F PB14 PB13 PB12 PB11 PC15 PC14 PC13 PC12 PC11 PC10 - - - - - - PE15 PE14 PE13 PE12 PE11 PE10 - - - PF12 PF11 PF10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 5.8.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG360 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.16. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 222 EFM32LG Data Sheet Pin Definitions 5.9 EFM32LG380 (LQFP100) 5.9.1 Pinout The EFM32LG380 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.17. EFM32LG380 Pinout (top view, not to scale) silabs.com | Building a more connected world. Rev. 2.20 | 223 EFM32LG Data Sheet Pin Definitions Table 5.25. Device Pinout LQFP100 Pin# and Name Pin # Pin Name 1 Pin Alternate Functionality / Description EBI Timers Communication Other PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 4 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 7 PA6 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 8 IOVDD_0 9 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2 10 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2 11 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2 12 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 13 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 14 PB5 EBI_A21 #0/1/2 US2_CLK #1 15 PB6 EBI_A22 #0/1/2 US2_CS #1 16 VSS 17 IOVDD_1 18 19 20 21 Analog CMU_CLK0 #0 ETM_TD0 #3 Digital IO power supply 0. Ground. Digital IO power supply 1. PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 silabs.com | Building a more connected world. Rev. 2.20 | 224 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other 22 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 23 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 24 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 25 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 26 PA7 EBI_CSTFT #0/1/2 27 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0 28 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0 29 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0 30 PA11 EBI_HSNC #0/1/2 31 IOVDD_2 32 VSS 33 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1 34 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1 35 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1 36 RESETn 37 PB9 EBI_A03 #0/1/2 U1_TX #2 38 PB10 EBI_A04 #0/1/2 U1_RX #2 39 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 40 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 41 AVDD_1 42 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 43 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 44 IOVDD_3 Digital IO power supply 3. 45 AVDD_0 Analog power supply 0. 46 PD0 Digital IO power supply 2. Ground. Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. Analog power supply 1. ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 silabs.com | Building a more connected world. PCNT2_S0IN #0 US1_TX #1 Rev. 2.20 | 225 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog 47 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT 48 PD2 ADC0_CH2 49 PD3 ADC0_CH3 OPAMP_N2 50 PD4 51 52 EBI Timers Communication Other TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 53 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 54 PD8 BU_VIN 55 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 56 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 57 VDD_DREG 58 VSS 59 DECOUPLE 60 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 61 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 62 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 63 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1 64 PE4 EBI_A11 #0/1/2 US0_CS #1 65 PE5 EBI_A12 #0/1/2 US0_CLK #1 66 PE6 EBI_A13 #0/1/2 US0_RX #1 67 PE7 EBI_A14 #0/1/2 US0_TX #1 68 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 69 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 70 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 71 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0 EBI_A27 #0/1/2 CMU_CLK1 #1 Power supply for on-chip voltage regulator. Ground. Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. silabs.com | Building a more connected world. Rev. 2.20 | 226 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI 72 USB_VREGI Input to internal 3.3V USB regulator 73 USB_VREGO Output and decoupling for internal 3.3V USB regulator 74 PF10 U1_TX #1 USB_DM 75 PF11 U1_RX #1 USB_DP 76 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 77 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 78 PF2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 79 USB_VBUS 80 PF12 81 PF5 82 IOVDD_5 83 VSS 84 PF6 85 EBI_ARDY #0/1/2 Timers Communication Other USB 5.0 V VBUS input. USB_ID EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0 86 PF8 EBI_WEn #1 TIM0_CC2 #2 87 PF9 EBI_REn #1 88 PD9 EBI_CS0 #0/1/2 89 PD10 EBI_CS1 #0/1/2 90 PD11 EBI_CS2 #0/1/2 91 PD12 EBI_CS3 #0/1/2 92 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 93 PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1 94 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX 95 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 96 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 97 PE13 EBI_AD05 #0/1/2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 98 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 99 PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 100 PA15 EBI_AD08 #0/1/2 TIM3_CC2 #0 Digital IO power supply 5. Ground. silabs.com | Building a more connected world. ETM_TCLK #1 ETM_TD0 #1 PRS_CH3 #1 Rev. 2.20 | 227 EFM32LG Data Sheet Pin Definitions 5.9.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.26. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 228 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 CMU_CLK1 PA1 DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 PD8 PD7 Clock Management Unit, clock output number 0. PE12 Clock Management Unit, clock output number 1. Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A LT PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PD1 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. silabs.com | Building a more connected world. PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 229 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 230 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ALE 3 4 5 6 Description EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF8 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. Rev. 2.20 | 231 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 silabs.com | Building a more connected world. Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. Rev. 2.20 | 232 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PD0 Operational Amplifier 2 output. PCNT0_S0IN PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC2 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC3 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PF5 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PE12 PB2 PB11 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 silabs.com | Building a more connected world. UART0 Receive input. Rev. 2.20 | 233 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 PF6 PE0 PA3 U1_RX PF11 PB10 PE3 UART1 Receive input. U1_TX PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. U0_TX 3 4 5 6 Description UART0 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX PC3 PB4 PB3 USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. US2_TX PC2 USB_DM PF10 USB D- pin. USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_V BUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_V REGI USB Input to internal 3.3 V regulator silabs.com | Building a more connected world. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.20 | 234 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 USB_VREGO USB_V REGO 2 3 4 5 6 Description USB Decoupling for internal 3.3 V USB regulator and regulator output 5.9.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG380 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.27. GPIO Pinout Port Port A Pin 15 Pin 14 Pin 13 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 -- -- PF2 PF1 PF0 -- Port C -- -- -- Port D -- -- -- Port F Pin 11 PA15 PA14 PA13 PA12 PA11 PA10 Port B Port E Pin 12 -- PB14 PB13 PB12 PB11 PB10 -- -- -- PF12 PF11 PF10 5.9.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG380 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.18. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 235 EFM32LG Data Sheet Pin Definitions 5.10 EFM32LG390 (BGA112) 5.10.1 Pinout The EFM32LG390 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.19. EFM32LG390 Pinout (top view, not to scale) Table 5.28. Device Pinout BGA112 Pin# and Name Pin # Pin Name A1 Pin Alternate Functionality / Description Analog EBI Timers Communication PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 A2 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 A3 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 silabs.com | Building a more connected world. Other CMU_CLK1 #2 LES_ALTEX6 #0 Rev. 2.20 | 236 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin # Pin Name A4 Pin Alternate Functionality / Description Analog EBI Timers Communication Other PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1 A5 PD10 EBI_CS1 #0/1/2 A6 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0 A7 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 A8 PF12 A9 PE4 A10 PF10 U1_TX #1 USB_DM A11 PF11 U1_RX #1 USB_DP B1 PA15 EBI_AD08 #0/1/2 B2 PE13 EBI_AD05 #0/1/2 B3 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 B4 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1 B5 PD11 EBI_CS2 #0/1/2 B6 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1 B7 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 B8 USB_VBUS B9 PE5 B10 USB_VREGI Input to internal 3.3V USB regulator B11 USB_VREGO Output and decoupling for internal 3.3V USB regulator C1 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 C2 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 C3 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX C4 PD13 C5 PD12 EBI_CS3 #0/1/2 C6 PF9 EBI_REn #1 C7 VSS C8 PF2 EBI_ARDY #0/1/2 C9 PE6 EBI_A13 #0/1/2 C10 PC10 ACMP1_CH2 EBI_A10 #1/2 C11 PC11 ACMP1_CH3 EBI_ALE #1/2 D1 PA3 PRS_CH2 #1 USB_ID EBI_A11 #0/1/2 US0_CS #1 TIM3_CC2 #0 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 US0_RX #0 LES_ALTEX5 #0 BOOT_RX U0_TX #0 USB 5.0 V VBUS input. EBI_A12 #0/1/2 US0_CLK #1 ETM_TD1 #1 ETM_TD0 #1 Ground. silabs.com | Building a more connected world. EBI_AD12 #0/1/2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 US0_RX #1 TIM2_CC2 #2 TIM0_CDTI0 #0 US0_RX #2 LES_CH10 #0 US0_TX #2 LES_CH11 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 Rev. 2.20 | 237 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers EBI_AD11 #0/1/2 TIM0_CC2 #0/1 Communication Other D2 PA2 D3 PB15 D4 VSS D5 IOVDD_6 D6 PD9 D7 IOVDD_5 D8 PF1 D9 PE7 D10 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 D11 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 E1 PA6 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 E2 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 E3 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 E4 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2 E8 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 E9 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 E10 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 E11 PE3 F1 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2 F2 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2 F3 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 F4 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 F8 VDD_DREG Power supply for on-chip voltage regulator. F9 VSS_DREG Ground for on-chip voltage regulator. F10 PE2 TIM3_CC2 #1 U1_TX #3 F11 DECOUPLE G1 PB5 EBI_A21 #0/1/2 US2_CLK #1 G2 PB6 EBI_A22 #0/1/2 US2_CS #1 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1 Ground. Digital IO power supply 6. EBI_CS0 #0/1/2 Digital IO power supply 5. TIM0_CC1 #5 LETIM0_OUT1 #2 EBI_A14 #0/1/2 BU_STAT BU_VOUT DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 US0_TX #1 EBI_A10 #0 EBI_A09 #0 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 U1_RX #3 ACMP1_O #1 ACMP0_O #1 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. silabs.com | Building a more connected world. Rev. 2.20 | 238 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Communication Other G3 VSS G4 IOVDD_0 Digital IO power supply 0. G8 IOVDD_4 Digital IO power supply 4. G9 VSS G10 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 G11 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 H2 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 H3 PD14 H4 PA7 EBI_CSTFT #0/1/2 H5 PA8 EBI_DCLK #0/1/2 H6 VSS H7 IOVDD_3 H8 PD8 BU_VIN H9 PD5 ADC0_CH5 OPAMP_OUT2 #0 H10 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT J2 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT J3 PD15 J4 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1 J5 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0 J6 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0 J7 PB9 EBI_A03 #0/1/2 H1 H11 J1 Analog EBI Timers Ground. Ground. I2C0_SDA #3 TIM2_CC0 #0 Ground. Digital IO power supply 3. silabs.com | Building a more connected world. CMU_CLK1 #1 LEU0_RX #0 ETM_TD3 #0/2 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 I2C0_SCL #3 U1_TX #2 Rev. 2.20 | 239 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers J8 PB10 J9 PD2 ADC0_CH2 J10 PD3 ADC0_CH3 OPAMP_N2 J11 PD4 ADC0_CH4 OPAMP_P2 K1 PB7 LFXTAL_P K2 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 K3 PA13 K4 VSS K5 PA11 K6 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. K7 AVSS_1 Analog ground 1. K8 AVDD_2 Analog power supply 2. K9 AVDD_1 Analog power supply 1. K10 AVSS_0 Analog ground 0. EBI_A04 #0/1/2 EBI_A27 #0/1/2 Communication Other U1_RX #2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 LEU0_TX #0 ETM_TD2 #0/2 TIM1_CC0 #3 US0_TX #4 US1_CLK #0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 EBI_A01 #0/1/2 TIM2_CC1 #1 LES_CH4 #0 Ground. EBI_HSNC #0/1/2 K11 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT L1 PB8 LFXTAL_N L2 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 L3 PA14 L4 IOVDD_1 L5 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 L6 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 L7 AVSS_2 L8 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 L9 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 L10 AVDD_0 TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 TIM1_CC1 #3 US0_RX #4 US1_CS #0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 EBI_A02 #0/1/2 TIM2_CC2 #1 DBG_SWO #2 LES_CH5 #0 Digital IO power supply 1. Analog ground 2. Analog power supply 0. silabs.com | Building a more connected world. Rev. 2.20 | 240 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin # L11 Pin Alternate Functionality / Description Pin Name Analog PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 silabs.com | Building a more connected world. EBI Timers Communication PCNT2_S0IN #0 US1_TX #1 Other Rev. 2.20 | 241 EFM32LG Data Sheet Pin Definitions 5.10.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.29. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 242 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 CMU_CLK1 PA1 DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 PD8 PD7 Clock Management Unit, clock output number 0. PE12 Clock Management Unit, clock output number 1. Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A LT PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PD1 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. silabs.com | Building a more connected world. PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 243 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 244 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ALE 3 4 5 6 Description EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF8 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. Rev. 2.20 | 245 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 silabs.com | Building a more connected world. Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. Rev. 2.20 | 246 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PD0 Operational Amplifier 2 output. PCNT0_S0IN PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC2 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC3 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PF5 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PE12 PB2 PB11 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 silabs.com | Building a more connected world. UART0 Receive input. Rev. 2.20 | 247 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 PF6 PE0 PA3 U1_RX PF11 PB10 PE3 UART1 Receive input. U1_TX PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. U0_TX 3 4 5 6 Description UART0 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX PC3 PB4 PB3 USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. US2_TX PC2 USB_DM PF10 USB D- pin. USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_V BUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_V REGI USB Input to internal 3.3 V regulator silabs.com | Building a more connected world. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.20 | 248 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 USB_VREGO USB_V REGO 2 3 4 5 6 Description USB Decoupling for internal 3.3 V USB regulator and regulator output 5.10.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG390 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.30. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 -- -- PF2 PF1 PF0 Port C Port F -- -- -- -- -- -- -- PF12 PF11 PF10 5.10.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG390 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PD0 PD1 PD5 Figure 5.20. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 249 EFM32LG Data Sheet Pin Definitions 5.11 EFM32LG395 (BGA120) 5.11.1 Pinout The EFM32LG395 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.21. EFM32LG395 Pinout (top view, not to scale) Table 5.31. Device Pinout BGA120 Pin# and Name Pin # Pin Name A1 Pin Alternate Functionality / Description Analog EBI Timers Communication PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 A2 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 A3 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 silabs.com | Building a more connected world. Other CMU_CLK1 #2 LES_ALTEX6 #0 Rev. 2.20 | 250 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin # Pin Name A4 Pin Alternate Functionality / Description Analog EBI Timers Communication Other PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1 A5 PD11 EBI_CS2 #0/1/2 A6 PD9 EBI_CS0 #0/1/2 A7 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0 A8 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 A9 PF4 EBI_WEn #0/2 TIM0_CDTI1 #2/5 A10 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 A11 USB_VREGI Input to internal 3.3V USB regulator A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator A13 PF11 B1 PA15 EBI_AD08 #0/1/2 B2 PE13 EBI_AD05 #0/1/2 B3 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 B4 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1 B5 PD12 EBI_CS3 #0/1/2 B6 PD10 EBI_CS1 #0/1/2 B7 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1 B8 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 B9 PF3 EBI_ALE #0 TIM0_CDTI0 #2/5 B10 PF1 B11 PF12 B12 USB_VBUS B13 PF10 C1 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 C2 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 C3 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX C4 PD13 C5 VSS C6 IOVDD_0 C7 PF9 PRS_CH2 #1 PRS_CH1 #1 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 U1_RX #1 USB_DP TIM3_CC2 #0 TIM0_CC1 #5 LETIM0_OUT1 #2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 US0_RX #0 LES_ALTEX5 #0 BOOT_RX U0_TX #0 PRS_CH0 #1 ETM_TD3 #1 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 USB_ID USB 5.0 V VBUS input. U1_TX #1 USB_DM ETM_TD1 #1 Ground. Digital IO power supply 0. silabs.com | Building a more connected world. EBI_REn #1 ETM_TD0 #1 Rev. 2.20 | 251 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin # Pin Name C8 VSS C9 IOVDD_1 C10 PF0 C11 PE4 Pin Alternate Functionality / Description Analog EBI Timers Communication Other TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 Ground. Digital IO power supply 1. EBI_A11 #0/1/2 US0_CS #1 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 U0_TX #3 LES_CH14 #0 C13 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 D1 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 D2 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 D3 PB15 D11 PE5 C12 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1 EBI_A12 #0/1/2 US0_CLK #1 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT D13 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT E1 PA6 EBI_AD15 #0/1/2 E2 PA5 EBI_AD14 #0/1/2 E3 PA4 EBI_AD13 #0/1/2 E11 PE6 EBI_A13 #0/1/2 E12 PC10 ACMP1_CH2 EBI_A10 #1/2 E13 PC11 ACMP1_CH3 EBI_ALE #1/2 F1 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2 F2 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2 F3 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2 F11 PE7 EBI_A14 #0/1/2 F12 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 F13 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 D12 silabs.com | Building a more connected world. U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 U1_RX #0 LES_CH13 #0 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 US0_RX #1 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 US0_TX #2 LES_CH11 #0 US0_TX #1 Rev. 2.20 | 252 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin # Pin Name G1 Pin Alternate Functionality / Description Analog EBI Timers Communication PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 G2 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 G3 IOVDD_2 G11 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 G12 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 G13 PE3 H1 Other Digital IO power supply 2. BU_STAT EBI_A10 #0 U1_RX #3 PB5 EBI_A21 #0/1/2 US2_CLK #1 H2 PB6 EBI_A22 #0/1/2 US2_CS #1 H3 VSS H11 VDD_DREG H12 PE2 BU_VOUT EBI_A09 #0 H13 PC7 ACMP0_CH7 EBI_A06 #0/1/2 J1 PD14 I2C0_SDA #3 J2 PD15 I2C0_SCL #3 J3 VSS J11 IOVDD_3 J12 PC6 J13 DECOUPLE ACMP1_O #1 Ground. Power supply for on-chip voltage regulator. TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 Ground. Digital IO power supply 3. ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 EBI_A05 #0/1/2 LES_CH6 #0 ETM_TCLK #2 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 K2 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 K3 IOVDD_4 K11 VSS Ground. K12 VSS Ground. K13 PD8 BU_VIN PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT K1 L1 Digital IO power supply 4. silabs.com | Building a more connected world. CMU_CLK1 #1 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 Rev. 2.20 | 253 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog EBI Timers Communication Other L2 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 L3 PA7 L4 IOVDD_5 L5 VSS Ground. L6 VSS Ground. L7 IOVDD_6 L8 PB9 EBI_A03 #0/1/2 U1_TX #2 L9 PB10 EBI_A04 #0/1/2 U1_RX #2 EBI_CSTFT #0/1/2 Digital IO power supply 5. Digital IO power supply 6. PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 L11 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 L12 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 L13 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 M1 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 M2 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 M3 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0 M4 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0 M5 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1 M6 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1 M7 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. M8 AVSS_1 Analog ground 1. M9 AVDD_2 Analog power supply 2. M10 AVDD_1 Analog power supply 1. M11 AVSS_0 Analog ground 0. M12 PD3 L10 ADC0_CH3 OPAMP_N2 silabs.com | Building a more connected world. TIM0_CC2 #3 US1_CS #1 LES_CH4 #0 ETM_TD1 #0/2 Rev. 2.20 | 254 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog M13 PD6 N1 EBI Timers Communication Other ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 N2 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 N3 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0 N4 PA11 EBI_HSNC #0/1/2 N5 PA12 EBI_A00 #0/1/2 N6 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 N7 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 N8 AVSS_2 N9 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 N10 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 N11 AVDD_0 N12 PD2 ADC0_CH2 N13 PD5 ADC0_CH5 OPAMP_OUT2 #0 LES_CH5 #0 TIM2_CC0 #1 Analog ground 2. Analog power supply 0. silabs.com | Building a more connected world. EBI_A27 #0/1/2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 LEU0_RX #0 ETM_TD3 #0/2 Rev. 2.20 | 255 EFM32LG Data Sheet Pin Definitions 5.11.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.32. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 256 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0ALT PC0 DAC0_OUT1 / OPAMP_OUT1 PB12 DAC0_OUT1ALT / OPAMP_OUT1ALT PC12 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 DBG_SWDIO PF1 PF1 PF1 PF1 DBG_SWO PF2 PC15 PD1 PD2 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 257 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 258 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 259 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 silabs.com | Building a more connected world. PA0 LEUART0 Receive input. Rev. 2.20 | 260 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 PE14 3 4 PF0 PF2 5 6 Description LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU0_TX PD4 PB13 LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2. PD0 Operational Amplifier 2 output. silabs.com | Building a more connected world. Rev. 2.20 | 261 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PF11 PB10 PE3 UART1 Receive input. U1_TX PC12 PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Asynchronous Receive. PE13 PB7 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. US1_RX PC1 PD1 PD6 USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. US2_RX PC3 PB4 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_TX PC2 USB_DM PF10 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). USB D- pin. Rev. 2.20 | 262 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_ VBUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_ VREGI USB Input to internal 3.3 V regulator USB_VREGO USB_ VREGO USB Decoupling for internal 3.3 V USB regulator and regulator output 5.11.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG395 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.33. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port F -- -- -- PF12 PF11 PF10 5.11.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG395 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.22. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 263 EFM32LG Data Sheet Pin Definitions 5.12 EFM32LG840 (QFN64) 5.12.1 Pinout The EFM32LG840 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.23. EFM32LG840 Pinout (top view, not to scale) Table 5.34. Device Pinout QFN64 Pin# and Name Pin # Pin Name 0 VSS 1 2 Pin Alternate Functionality / Description Analog Timers Communication Other PA0 LCD_SEG13 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 Ground. silabs.com | Building a more connected world. Rev. 2.20 | 264 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 3 PA2 LCD_SEG15 TIM0_CC2 #0/1 CMU_CLK0 #0 ETM_TD0 #3 4 PA3 LCD_SEG16 TIM0_CDTI0 #0 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 LCD_SEG17 TIM0_CDTI1 #0 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 LCD_SEG18 TIM0_CDTI2 #0 7 PA6 LCD_SEG19 8 IOVDD_0 Digital IO power supply 0. 9 PB3 LCD_SEG20/ LCD_COM4 PCNT1_S0IN #1 US2_TX #1 10 PB4 LCD_SEG21/ LCD_COM5 PCNT1_S1IN #1 US2_RX #1 11 PB5 LCD_SEG22/ LCD_COM6 US2_CLK #1 12 PB6 LCD_SEG23/ LCD_COM7 US2_CS #1 13 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 14 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 15 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 17 PA12 LCD_BCAP_P TIM2_CC0 #1 18 PA13 LCD_BCAP_N TIM2_CC1 #1 19 PA14 LCD_BEXT TIM2_CC2 #1 20 RESETn 21 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 22 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 23 AVDD_1 Analog power supply 1. 24 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 25 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. silabs.com | Building a more connected world. Rev. 2.20 | 265 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog Timers Communication 28 PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 33 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 34 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 35 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 36 PD8 BU_VIN 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0 #2 #2 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PE4 LCD_COM0 US0_CS #1 42 PE5 LCD_COM1 US0_CLK #1 43 PE6 LCD_COM2 US0_RX #1 44 PE7 LCD_COM3 US0_TX #1 45 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT 46 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 47 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 LES_CH14 #0 48 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 LES_CH15 #0 DBG_SWO #1 49 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 silabs.com | Building a more connected world. Other CMU_CLK1 #1 LES_CH6 #0 ETM_TCLK #2 CMU_CLK0 #1 LES_CH12 #0 LES_CH13 #0 Rev. 2.20 | 266 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin # Pin Name 50 PF1 51 PF2 52 Pin Alternate Functionality / Description Analog Timers Communication Other TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 LCD_SEG0 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 PF3 LCD_SEG1 TIM0_CDTI0 #2/5 PRS_CH0 #1 ETM_TD3 #1 53 PF4 LCD_SEG2 TIM0_CDTI1 #2/5 PRS_CH1 #1 54 PF5 LCD_SEG3 TIM0_CDTI2 #2/5 PRS_CH2 #1 55 IOVDD_5 Digital IO power supply 5. 56 PE8 LCD_SEG4 PCNT2_S0IN #1 PRS_CH3 #1 57 PE9 LCD_SEG5 PCNT2_S1IN #1 58 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX 59 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 60 PE12 LCD_SEG8 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 61 PE13 LCD_SEG9 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 62 PE14 LCD_SEG10 TIM3_CC0 #0 LEU0_TX #2 63 PE15 LCD_SEG11 TIM3_CC1 #0 LEU0_RX #2 64 PA15 LCD_SEG12 TIM3_CC2 #0 silabs.com | Building a more connected world. Rev. 2.20 | 267 EFM32LG Data Sheet Pin Definitions 5.12.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.35. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_VIN PD8 Battery input for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. Rev. 2.20 | 268 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 DAC0_OUT0ALT / OPAMP_OUT0A LT DAC0_OUT1 / OPAMP_OUT1 4 5 6 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PD0 Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A PC12 LT Description PC13 PC14 PC15 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. PD1 Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 ETM_TCLK PD1 PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. PD7 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 I2C1 Serial Data input / output. LCD_BCAP_N LCD_BCAP_P PC15 PF3 PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. silabs.com | Building a more connected world. Rev. 2.20 | 269 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. silabs.com | Building a more connected world. Rev. 2.20 | 270 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 silabs.com | Building a more connected world. LEUART1 Receive input. Rev. 2.20 | 271 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LEU1_TX PC6 PA5 LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PE8 Peripheral Reflex System PRS, channel 3. LEUART1 Transmit output. Also used as receive input in half duplex communication. PD0 Operational Amplifier 2 output. TIM0_CC0 PA0 PA0 PD1 TIM0_CC1 PA1 PA1 TIM0_CC2 PA2 PA2 TIM0_CDTI0 PA3 PC13 TIM0_CDTI1 PA4 TIM0_CDTI2 PA0 PF0 Timer 0 Capture Compare input / output channel 0. PD2 PF1 Timer 0 Capture Compare input / output channel 1. PD3 PF2 Timer 0 Capture Compare input / output channel 2. PF3 PC13 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. PC14 PF4 PC14 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2. silabs.com | Building a more connected world. Rev. 2.20 | 272 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 Timer 3 Capture Compare input / output channel 2. US0_CLK PE12 PE5 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC14 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PE12 PE13 PB8 PB7 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PD1 US1_TX PD0 PD6 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. USART1 Synchronous mode Master Output / Slave Input (MOSI). US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART2 Asynchronous Receive. US2_RX US2_TX PB4 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.20 | 273 EFM32LG Data Sheet Pin Definitions 5.12.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG840 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.36. GPIO Pinout Port Port A Port B Port C Port D Port E Port F Pin 15 Pin 14 Pin 13 Pin 12 PA15 PA14 PA13 PA12 -- Pin 10 -- -- -- -- -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0 PB14 PB13 PB12 PB11 PC15 PC14 PC13 PC12 -- Pin 11 -- -- -- PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- -- -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 5.12.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG840 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.24. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 274 EFM32LG Data Sheet Pin Definitions 5.13 EFM32LG842 (TQFP64) 5.13.1 Pinout The EFM32LG842 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.25. EFM32LG842 Pinout (top view, not to scale) Table 5.37. Device Pinout QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 1 PA0 LCD_SEG13 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 LCD_SEG15 TIM0_CC2 #0/1 silabs.com | Building a more connected world. CMU_CLK0 #0 ETM_TD0 #3 Rev. 2.20 | 275 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers 4 PA3 LCD_SEG16 TIM0_CDTI0 #0 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 LCD_SEG17 TIM0_CDTI1 #0 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1 7 IOVDD_0 Digital IO power supply 0. 8 VSS 9 PB3 LCD_SEG20/ LCD_COM4 PCNT1_S0IN #1 US2_TX #1 10 PB4 LCD_SEG21/ LCD_COM5 PCNT1_S1IN #1 US2_RX #1 11 PB5 LCD_SEG22/ LCD_COM6 US2_CLK #1 12 PB6 LCD_SEG23/ LCD_COM7 US2_CS #1 13 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 14 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 15 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 17 PA12 LCD_BCAP_P TIM2_CC0 #1 18 PA13 LCD_BCAP_N TIM2_CC1 #1 19 PA14 LCD_BEXT TIM2_CC2 #1 20 RESETn 21 PB11 22 VSS 23 AVDD_1 Analog power supply 1. 24 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 25 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 28 Communication Other LES_ALTEX4 #0 ETM_TD3 #3 Ground. Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 Ground. silabs.com | Building a more connected world. PCNT2_S0IN #0 US1_TX #1 Rev. 2.20 | 276 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 29 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 33 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 34 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 35 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 36 PD8 BU_VIN 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0 #2 #2 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PE4 LCD_COM0 US0_CS #1 42 PE5 LCD_COM1 US0_CLK #1 43 PE6 LCD_COM2 US0_RX #1 44 PE7 LCD_COM3 US0_TX #1 45 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT 46 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 47 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 LES_CH14 #0 48 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 LES_CH15 #0 DBG_SWO #1 49 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 50 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 silabs.com | Building a more connected world. CMU_CLK1 #1 LES_CH6 #0 ETM_TCLK #2 CMU_CLK0 #1 LES_CH12 #0 LES_CH13 #0 Rev. 2.20 | 277 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 51 PF2 LCD_SEG0 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 52 PF3 LCD_SEG1 TIM0_CDTI0 #2/5 PRS_CH0 #1 ETM_TD3 #1 53 PF4 LCD_SEG2 TIM0_CDTI1 #2/5 PRS_CH1 #1 54 PF5 LCD_SEG3 TIM0_CDTI2 #2/5 PRS_CH2 #1 55 IOVDD_5 Digital IO power supply 5. 56 VSS 57 PE8 LCD_SEG4 PCNT2_S0IN #1 PRS_CH3 #1 58 PE9 LCD_SEG5 PCNT2_S1IN #1 59 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX 60 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 61 PE12 LCD_SEG8 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 62 PE13 LCD_SEG9 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 63 PE14 LCD_SEG10 TIM3_CC0 #0 LEU0_TX #2 64 PE15 LCD_SEG11 TIM3_CC1 #0 LEU0_RX #2 Ground. silabs.com | Building a more connected world. Rev. 2.20 | 278 EFM32LG Data Sheet Pin Definitions 5.13.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.38. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_VIN PD8 Battery input for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. Rev. 2.20 | 279 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 DAC0_OUT0ALT / OPAMP_OUT0A LT DAC0_OUT1ALT / OPAMP_OUT1A PC12 LT PC13 PC14 PC15 DBG_SWCLK PF0 PF0 PF0 4 5 6 Description PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 ETM_TCLK PD7 PC6 ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 I2C1_SDA PC4 LCD_BCAP_N LCD_BCAP_P PC15 PF3 PD1 PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Embedded Trace Module ETM clock . I2C1 Serial Clock Line input / output. PB11 I2C1 Serial Data input / output. PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. silabs.com | Building a more connected world. Rev. 2.20 | 280 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. silabs.com | Building a more connected world. Rev. 2.20 | 281 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 LETIM0_OUT1 PD7 LEU0_RX PD5 LEU0_TX PD4 LEU1_RX PC7 LEU1_TX PC6 LFXTAL_N PB8 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. PF1 PC5 Low Energy Timer LETIM0, output channel 1. PB14 PE15 PF1 PA0 LEUART0 Receive input. PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEUART1 Receive input. PA5 silabs.com | Building a more connected world. LEUART1 Transmit output. Also used as receive input in half duplex communication. Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. Rev. 2.20 | 282 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PE8 Peripheral Reflex System PRS, channel 3. PD0 Operational Amplifier 2 output. TIM0_CC0 PA0 PA0 PD1 TIM0_CC1 PA1 PA1 TIM0_CC2 PA2 PA2 TIM0_CDTI0 PA3 PC13 TIM0_CDTI1 PA4 TIM0_CDTI2 PA0 PF0 Timer 0 Capture Compare input / output channel 0. PD2 PF1 Timer 0 Capture Compare input / output channel 1. PD3 PF2 Timer 0 Capture Compare input / output channel 2. PF3 PC13 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. PC14 PF4 PC14 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1. US0_CLK PE12 PE5 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC14 PB14 PB14 USART0 chip select input / output. silabs.com | Building a more connected world. Rev. 2.20 | 283 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USART0 Asynchronous Receive. US0_RX PE11 PE6 PE12 PE13 PB8 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PB7 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. PD1 PD6 USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX US1_TX PD0 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. PD7 USART1 Synchronous mode Master Output / Slave Input (MOSI). US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART2 Asynchronous Receive. US2_RX PB4 US2_TX USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PB3 USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.13.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG842 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.39. GPIO Pinout Port Pin 15 Port A -- PA14 PA13 PA12 Port B -- PB14 PB13 Port C Port D Port E Port F Pin 14 Pin 13 Pin 12 -- PC15 PC14 PC13 PC12 -- -- -- -- Pin 11 Pin 10 -- -- -- -- -- -- PA5 PA4 PA3 PA2 PA1 PA0 PB11 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0 PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- -- silabs.com | Building a more connected world. -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.20 | 284 EFM32LG Data Sheet Pin Definitions 5.13.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG842 is shown in the following figure. PB11 PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.26. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 285 EFM32LG Data Sheet Pin Definitions 5.14 EFM32LG880 (LQFP100) 5.14.1 Pinout The EFM32LG880 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.27. EFM32LG880 Pinout (top view, not to scale) silabs.com | Building a more connected world. Rev. 2.20 | 286 EFM32LG Data Sheet Pin Definitions Table 5.40. Device Pinout LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other 1 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 4 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 7 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 8 IOVDD_0 9 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2 10 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2 11 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2 12 PB3 LCD_SEG20/ LCD_COM4 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 13 PB4 LCD_SEG21/ LCD_COM5 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 14 PB5 LCD_SEG22/ LCD_COM6 EBI_A21 #0/1/2 US2_CLK #1 15 PB6 LCD_SEG23/ LCD_COM7 EBI_A22 #0/1/2 US2_CS #1 16 VSS 17 IOVDD_1 18 19 20 CMU_CLK0 #0 ETM_TD0 #3 Digital IO power supply 0. Ground. Digital IO power supply 1. PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 silabs.com | Building a more connected world. Rev. 2.20 | 287 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog EBI Timers Communication Other 21 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 22 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 23 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 24 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 25 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 26 PA7 LCD_SEG35 EBI_CSTFT #0/1/2 27 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0 28 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0 29 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0 30 PA11 LCD_SEG39 EBI_HSNC #0/1/2 31 IOVDD_2 32 VSS 33 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1 34 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1 35 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1 36 RESETn 37 PB9 EBI_A03 #0/1/2 U1_TX #2 38 PB10 EBI_A04 #0/1/2 U1_RX #2 39 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 40 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 41 AVDD_1 42 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 43 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 44 IOVDD_3 Digital IO power supply 3. 45 AVDD_0 Analog power supply 0. Digital IO power supply 2. Ground. Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. Analog power supply 1. silabs.com | Building a more connected world. Rev. 2.20 | 288 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Alternate Functionality / Description Timers Communication PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 47 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 48 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 49 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 50 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 51 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 52 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 53 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 54 PD8 BU_VIN 55 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 56 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 57 VDD_DREG 58 VSS 59 DECOUPLE 60 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 61 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 62 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 63 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1 64 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1 65 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1 66 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1 67 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1 68 PC8 ACMP1_CH0 EBI_A15 #0/1/2 46 Pin Name Analog EBI EBI_A27 #0/1/2 Other CMU_CLK1 #1 Power supply for on-chip voltage regulator. Ground. Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. silabs.com | Building a more connected world. TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 Rev. 2.20 | 289 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other 69 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 70 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 71 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 U1_RX #0 LES_CH13 #0 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 U0_TX #3 LES_CH14 #0 75 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 76 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 77 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 78 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 79 PF3 LCD_SEG1 EBI_ALE #0 TIM0_CDTI0 #2/5 PRS_CH0 #1 ETM_TD3 #1 80 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1 81 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1 82 IOVDD_5 83 VSS 84 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0 85 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0 86 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 87 PF9 LCD_SEG27 EBI_REn #1 88 PD9 LCD_SEG28 EBI_CS0 #0/1/2 89 PD10 LCD_SEG29 EBI_CS1 #0/1/2 90 PD11 LCD_SEG30 EBI_CS2 #0/1/2 91 PD12 LCD_SEG31 EBI_CS3 #0/1/2 92 PE8 LCD_SEG4 EBI_AD00 #0/1/2 72 73 74 Digital IO power supply 5. Ground. silabs.com | Building a more connected world. ETM_TCLK #1 ETM_TD0 #1 PCNT2_S0IN #1 PRS_CH3 #1 Rev. 2.20 | 290 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other 93 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1 94 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX 95 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 96 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 97 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 98 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 99 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 100 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0 silabs.com | Building a more connected world. Rev. 2.20 | 291 EFM32LG Data Sheet Pin Definitions 5.14.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.41. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 292 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A PC12 LT Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 PD1 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. silabs.com | Building a more connected world. PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 293 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 294 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 PF3 silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 295 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LCD_BCAP_N LCD_BCAP_P PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. silabs.com | Building a more connected world. Rev. 2.20 | 296 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6. silabs.com | Building a more connected world. Rev. 2.20 | 297 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. silabs.com | Building a more connected world. Rev. 2.20 | 298 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PD0 Operational Amplifier 2 output. silabs.com | Building a more connected world. Rev. 2.20 | 299 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description PRS_CH3 PC1 PE8 TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PB10 PE3 UART1 Receive input. U1_TX PC12 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. Peripheral Reflex System PRS, channel 3. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 silabs.com | Building a more connected world. USART1 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.20 | 300 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 PD7 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. US2_RX PC3 PB4 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_TX PC2 USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PB3 USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.14.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG880 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.42. GPIO Pinout Port Port A Port B Port C Port D Port E Port F Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 PA15 PA14 PA13 PA12 PA11 PA10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 -- -- -- -- -- -- -- -- -- -- 5.14.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG880 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PD0 PD1 PD5 Figure 5.28. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 301 EFM32LG Data Sheet Pin Definitions 5.15 EFM32LG890 (BGA112) 5.15.1 Pinout The EFM32LG890 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.29. EFM32LG890 Pinout (top view, not to scale) silabs.com | Building a more connected world. Rev. 2.20 | 302 EFM32LG Data Sheet Pin Definitions Table 5.43. Device Pinout BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication A1 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 A2 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 A3 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 A4 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1 A5 PD10 LCD_SEG29 EBI_CS1 #0/1/2 A6 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 A7 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1 A8 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1 A9 PE4 LCD_COM0 EBI_A11 #0/1/2 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 U0_TX #3 LES_CH14 #0 A11 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 B1 PA15 LCD_SEG12 EBI_AD08 #0/1/2 B2 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 B3 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX B4 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1 B5 PD11 LCD_SEG30 EBI_CS2 #0/1/2 B6 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1 B7 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 B8 PF3 B9 PE5 LCD_COM1 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT A10 B10 B11 LCD_SEG1 silabs.com | Building a more connected world. EBI_ALE #0 Other CMU_CLK1 #2 LES_ALTEX6 #0 U0_RX #0 US0_CS #1 TIM3_CC2 #0 U0_TX #0 PRS_CH0 #1 ETM_TD3 #1 TIM0_CDTI0 #2/5 EBI_A12 #0/1/2 US0_CLK #1 TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 U1_RX #0 LES_CH13 #0 Rev. 2.20 | 303 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other C1 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 C2 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 C3 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX C4 PD13 C5 PD12 LCD_SEG31 EBI_CS3 #0/1/2 C6 PF9 LCD_SEG27 EBI_REn #1 C7 VSS C8 PF2 LCD_SEG0 EBI_ARDY #0/1/2 C9 PE6 LCD_COM2 EBI_A13 #0/1/2 C10 PC10 ACMP1_CH2 EBI_A10 #1/2 C11 PC11 ACMP1_CH3 EBI_ALE #1/2 D1 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 D2 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 D3 PB15 D4 VSS D5 IOVDD_6 D6 PD9 D7 IOVDD_5 D8 PF1 D9 PE7 LCD_COM3 EBI_A14 #0/1/2 D10 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 D11 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 E1 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 E2 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 E3 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 E4 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2 E8 PF0 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 ETM_TD1 #1 ETM_TD0 #1 Ground. TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 US0_RX #1 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 US0_TX #2 LES_CH11 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1 Ground. Digital IO power supply 6. LCD_SEG28 EBI_CS0 #0/1/2 Digital IO power supply 5. TIM0_CC1 #5 LETIM0_OUT1 #2 silabs.com | Building a more connected world. US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 US0_TX #1 TIM0_CC0 #5 LETIM0_OUT0 #2 Rev. 2.20 | 304 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin # Pin Name E9 Pin Alternate Functionality / Description EBI Timers Communication PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 E10 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 E11 PE3 BU_STAT EBI_A10 #0 F1 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2 F2 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2 F3 PB3 LCD_SEG20/ LCD_COM4 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 F4 PB4 LCD_SEG21/ LCD_COM5 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 F8 VDD_DREG Power supply for on-chip voltage regulator. F9 VSS_DREG Ground for on-chip voltage regulator. F10 PE2 TIM3_CC2 #1 U1_TX #3 F11 DECOUPLE G1 PB5 LCD_SEG22/ LCD_COM6 EBI_A21 #0/1/2 US2_CLK #1 G2 PB6 LCD_SEG23/ LCD_COM7 EBI_A22 #0/1/2 US2_CS #1 G3 VSS G4 IOVDD_0 Digital IO power supply 0. G8 IOVDD_4 Digital IO power supply 4. G9 VSS G10 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 G11 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 H2 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 H3 PD14 H4 PA7 LCD_SEG35 EBI_CSTFT #0/1/2 H5 PA8 LCD_SEG36 EBI_DCLK #0/1/2 H6 VSS H7 IOVDD_3 H8 PD8 H1 Analog BU_VOUT EBI_A09 #0 U1_RX #3 Other ACMP1_O #1 ACMP0_O #1 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. Ground. Ground. I2C0_SDA #3 TIM2_CC0 #0 Ground. Digital IO power supply 3. BU_VIN silabs.com | Building a more connected world. CMU_CLK1 #1 Rev. 2.20 | 305 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog H9 PD5 ADC0_CH5 OPAMP_OUT2 #0 H10 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT J2 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT J3 PD15 J4 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1 J5 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0 J6 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0 J7 PB9 EBI_A03 #0/1/2 U1_TX #2 J8 PB10 EBI_A04 #0/1/2 U1_RX #2 J9 PD2 ADC0_CH2 J10 PD3 ADC0_CH3 OPAMP_N2 J11 PD4 ADC0_CH4 OPAMP_P2 K1 PB7 LFXTAL_P K2 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 K3 PA13 LCD_BCAP_N K4 VSS K5 PA11 K6 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. K7 AVSS_1 Analog ground 1. K8 AVDD_2 Analog power supply 2. K9 AVDD_1 Analog power supply 1. K10 AVSS_0 Analog ground 0. H11 J1 EBI Timers Communication Other LEU0_RX #0 ETM_TD3 #0/2 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 I2C0_SCL #3 EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 LEU0_TX #0 ETM_TD2 #0/2 TIM1_CC0 #3 US0_TX #4 US1_CLK #0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 EBI_A01 #0/1/2 TIM2_CC1 #1 LES_CH4 #0 Ground. LCD_SEG39 silabs.com | Building a more connected world. EBI_HSNC #0/1/2 Rev. 2.20 | 306 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog K11 Timers Communication Other PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 L1 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 L2 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 L3 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1 L4 IOVDD_1 L5 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 L6 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 L7 AVSS_2 L8 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 L9 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 L10 AVDD_0 L11 PD0 EBI LES_CH5 #0 Digital IO power supply 1. Analog ground 2. Analog power supply 0. ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 silabs.com | Building a more connected world. PCNT2_S0IN #0 US1_TX #1 Rev. 2.20 | 307 EFM32LG Data Sheet Pin Definitions 5.15.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.44. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 308 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A PC12 LT Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 PD1 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. silabs.com | Building a more connected world. PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 309 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 310 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 311 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LCD_BCAP_N LCD_BCAP_P PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. silabs.com | Building a more connected world. Rev. 2.20 | 312 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6. silabs.com | Building a more connected world. Rev. 2.20 | 313 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. silabs.com | Building a more connected world. Rev. 2.20 | 314 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PD0 Operational Amplifier 2 output. silabs.com | Building a more connected world. Rev. 2.20 | 315 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description PRS_CH3 PC1 PE8 TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PB10 PE3 UART1 Receive input. U1_TX PC12 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. Peripheral Reflex System PRS, channel 3. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 silabs.com | Building a more connected world. USART1 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.20 | 316 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 PD7 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. US2_RX PC3 PB4 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_TX PC2 USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PB3 USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.15.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG890 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.45. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port F -- -- -- -- -- -- 5.15.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG890 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.30. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 317 EFM32LG Data Sheet Pin Definitions 5.16 EFM32LG895 (BGA120) 5.16.1 Pinout The EFM32LG895 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.31. EFM32LG895 Pinout (top view, not to scale) silabs.com | Building a more connected world. Rev. 2.20 | 318 EFM32LG Data Sheet Pin Definitions Table 5.46. Device Pinout BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other A1 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 A2 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 A3 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 A4 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1 A5 PD11 LCD_SEG30 EBI_CS2 #0/1/2 A6 PD9 LCD_SEG28 EBI_CS0 #0/1/2 A7 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 A8 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1 A9 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1 A10 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 A11 USB_VREGI Input to internal 3.3V USB regulator A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator A13 PF11 B1 PA15 LCD_SEG12 EBI_AD08 #0/1/2 B2 PE13 LCD_SEG9 EBI_AD05 #0/1/2 B3 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 B4 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1 B5 PD12 LCD_SEG31 EBI_CS3 #0/1/2 B6 PD10 LCD_SEG29 EBI_CS1 #0/1/2 B7 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1 B8 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 B9 PF3 LCD_SEG1 EBI_ALE #0 TIM0_CDTI0 #2/5 B10 PF1 B11 PF12 B12 USB_VBUS B13 PF10 C1 PA1 CMU_CLK1 #2 LES_ALTEX6 #0 U0_RX #0 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 U1_RX #1 TIM3_CC2 #0 TIM0_CC1 #5 LETIM0_OUT1 #2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 US0_RX #0 LES_ALTEX5 #0 BOOT_RX U0_TX #0 PRS_CH0 #1 ETM_TD3 #1 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 USB 5.0 V VBUS input. U1_TX #1 LCD_SEG14 silabs.com | Building a more connected world. EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 Rev. 2.20 | 319 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other C2 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 C3 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX C4 PD13 C5 VSS C6 IOVDD_0 C7 PF9 C8 VSS C9 IOVDD_1 C10 PF0 C11 PE4 LCD_COM0 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 U0_TX #3 LES_CH14 #0 C13 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 D1 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 D2 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 D3 PB15 D11 PE5 LCD_COM1 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT D13 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT E1 PA6 LCD_SEG19 EBI_AD15 #0/1/2 E2 PA5 LCD_SEG18 EBI_AD14 #0/1/2 E3 PA4 LCD_SEG17 EBI_AD13 #0/1/2 E11 PE6 LCD_COM2 EBI_A13 #0/1/2 E12 PC10 ACMP1_CH2 EBI_A10 #1/2 E13 PC11 ACMP1_CH3 EBI_ALE #1/2 C12 D12 ETM_TD1 #1 Ground. Digital IO power supply 0. LCD_SEG27 EBI_REn #1 ETM_TD0 #1 Ground. Digital IO power supply 1. TIM0_CC0 #5 LETIM0_OUT0 #2 EBI_A11 #0/1/2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 US0_CS #1 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1 silabs.com | Building a more connected world. EBI_A12 #0/1/2 US0_CLK #1 U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 U1_RX #0 LES_CH13 #0 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 US0_RX #1 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 US0_TX #2 LES_CH11 #0 Rev. 2.20 | 320 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers F1 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2 F2 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2 F3 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2 F11 PE7 LCD_COM3 EBI_A14 #0/1/2 F12 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 F13 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 G1 PB3 LCD_SEG20/ LCD_COM4 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 G2 PB4 LCD_SEG21/ LCD_COM5 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 G3 IOVDD_2 G11 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 G12 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 G13 PE3 BU_STAT EBI_A10 #0 U1_RX #3 H1 PB5 LCD_SEG22/ LCD_COM6 EBI_A21 #0/1/2 US2_CLK #1 H2 PB6 LCD_SEG23/ LCD_COM7 EBI_A22 #0/1/2 US2_CS #1 H3 VSS H11 VDD_DREG H12 PE2 BU_VOUT EBI_A09 #0 H13 PC7 ACMP0_CH7 EBI_A06 #0/1/2 J1 PD14 I2C0_SDA #3 J2 PD15 I2C0_SCL #3 J3 VSS J11 IOVDD_3 J12 PC6 J13 DECOUPLE K1 K2 Communication Other US0_TX #1 Digital IO power supply 2. ACMP1_O #1 Ground. Power supply for on-chip voltage regulator. TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 Ground. Digital IO power supply 3. ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 EBI_A05 #0/1/2 LES_CH6 #0 ETM_TCLK #2 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 silabs.com | Building a more connected world. Rev. 2.20 | 321 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name K3 IOVDD_4 K11 VSS Ground. K12 VSS Ground. K13 PD8 BU_VIN PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 L2 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 L3 PA7 LCD_SEG35 EBI_CSTFT #0/1/2 L4 IOVDD_5 L5 VSS Ground. L6 VSS Ground. L7 IOVDD_6 L8 PB9 EBI_A03 #0/1/2 U1_TX #2 L9 PB10 EBI_A04 #0/1/2 U1_RX #2 L1 Analog EBI Timers Communication Other Digital IO power supply 4. CMU_CLK1 #1 Digital IO power supply 5. Digital IO power supply 6. PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 L11 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 L12 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 L13 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 M1 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 M2 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 M3 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0 M4 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0 M5 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1 M6 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1 L10 silabs.com | Building a more connected world. LES_CH4 #0 Rev. 2.20 | 322 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other M7 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. M8 AVSS_1 Analog ground 1. M9 AVDD_2 Analog power supply 2. M10 AVDD_1 Analog power supply 1. M11 AVSS_0 Analog ground 0. M12 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 M13 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 N1 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 N2 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 N3 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0 N4 PA11 LCD_SEG39 EBI_HSNC #0/1/2 N5 PA12 LCD_BCAP_P EBI_A00 #0/1/2 N6 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 N7 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 N8 AVSS_2 N9 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 N10 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 N11 AVDD_0 N12 PD2 ADC0_CH2 N13 PD5 ADC0_CH5 OPAMP_OUT2 #0 LES_CH5 #0 TIM2_CC0 #1 Analog ground 2. Analog power supply 0. silabs.com | Building a more connected world. EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3 LEU0_RX #0 ETM_TD3 #0/2 Rev. 2.20 | 323 EFM32LG Data Sheet Pin Definitions 5.16.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.47. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 324 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0ALT PC0 DAC0_OUT1 / OPAMP_OUT1 PB12 DAC0_OUT1ALT / OPAMP_OUT1ALT PC12 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 DBG_SWDIO PF1 PF1 PF1 PF1 DBG_SWO PF2 PC15 PD1 PD2 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 325 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 326 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 327 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LCD_BCAP_N LCD_BCAP_P PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. silabs.com | Building a more connected world. Rev. 2.20 | 328 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6. silabs.com | Building a more connected world. Rev. 2.20 | 329 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. silabs.com | Building a more connected world. Rev. 2.20 | 330 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD0 Operational Amplifier 2 output. PF6 silabs.com | Building a more connected world. PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. Rev. 2.20 | 331 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PF11 PB10 PE3 UART1 Receive input. U1_TX PC12 PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 silabs.com | Building a more connected world. USART1 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.20 | 332 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 PD7 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. US2_RX PC3 PB4 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_TX PC2 USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PB3 USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.16.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG895 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.48. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port F -- -- -- PF12 PF11 PF10 5.16.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG895 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.32. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 333 EFM32LG Data Sheet Pin Definitions 5.17 EFM32LG900 (Wafer) 5.17.1 Padout PF2 PF1 PF0 iovss_7 PF3 100 99 98 97 96 usb_vbus 101 51 52 53 54 55 56 57 58 59 PF9 PF8 PF7 PF6 iovdd_5 iovss_5 PF5 PF12 PF4 110 109 108 107 106 105 104 103 102 iovss_3 iovdd_3 avss_0 avdd_0 PD0 PD1 PD2 PD3 PD4 NC 111 43 44 45 46 47 48 49 50 PE8 PB15 PD13 PD12 PD11 PD10 PD9 118 117 116 115 114 113 112 PB11 PB12 avss_2 avdd_2 avdd_1 avss_1 PB13 PB14 29 42 28 PB8 41 PB7 PB10 26 27 40 PC4 PC5 PB9 24 25 reset PC2 PC3 39 22 23 38 PC0 PC1 PA14 20 21 PA13 iovss_1 iovdd_1 36 18 19 37 17 PB5 PB6 PA12 PB4 35 15 16 iovss_2 NC PB3 iovdd_2 14 PE12 iovss_6 iovdd_6 PE11 PE10 PE9 PB2 124 123 122 121 120 119 9 10 11 12 13 34 iovss_0 PD14 PD15 PB0 PB1 33 8 PA11 7 iovdd_0 32 6 PA6 PA9 5 PA5 PA10 4 PA4 PA15 PE15 PE14 PE13 3 PA3 30 PA2 31 2 PA7 1 PA1 PA8 PA0 128 127 126 125 The EFM32LG900 padout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pad are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. 95 94 93 92 91 90 89 88 87 86 PF11 PC15 PF10 PC14 usb_vrego_1 usb_vrego_0 usb_vregi_1 usb_vregi_0 PC13 PC12 85 84 83 82 81 80 79 PC11 PC10 PC9 PC8 PE7 PE6 PE5 78 77 76 75 74 73 72 PE4 PE3 PE2 PE1 PE0 iovss_4 NC 71 70 69 68 67 66 65 64 63 62 61 60 dec_2 dec_1 dec_0 iovdd_4 vdd_dreg vss_dreg PC7 PC6 PD8 PD7 PD6 PD5 Figure 5.33. EFM32LG900 Padout (top view, not to scale) Table 5.49. Device Padout Water Pads Pad Alternative Functionality / Description Pad # Pad Name Analog EBI Timers Communication Other 1 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 4 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 silabs.com | Building a more connected world. CMU_CLK0 #0 ETM_TD0 #3 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 Rev. 2.20 | 334 EFM32LG Data Sheet Pin Definitions Water Pads Pad Alternative Functionality / Description Pad # Pad Name Analog EBI Timers Communication Other 5 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 7 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 8 IOVDD_0 Digital IO power supply 0. 9 IOVSS_0 Digital IO ground 0. 10 PD14 I2C0_SDA #3 11 PD15 I2C0_SCL #3 12 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2 13 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2 14 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2 15 NC Do not connect. 16 PB3 LCD_SEG20/ LCD_COM4 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 17 PB4 LCD_SEG21/ LCD_COM5 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 18 PB5 LCD_SEG22/ LCD_COM6 EBI_A21 #0/1/2 US2_CLK #1 19 PB6 LCD_SEG23/ LCD_COM7 EBI_A22 #0/1/2 US2_CS #1 20 IOVSS_1 Digital IO ground 1. 21 IOVDD_1 Digital IO power supply 1. 22 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 23 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 24 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 25 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 26 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 silabs.com | Building a more connected world. Rev. 2.20 | 335 EFM32LG Data Sheet Pin Definitions Water Pads Pad Alternative Functionality / Description Pad # Pad Name Analog EBI Timers Communication Other 27 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 28 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 29 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 30 PA7 LCD_SEG35 EBI_CSTFT #0/1/2 31 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0 32 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0 33 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0 34 PA11 LCD_SEG39 EBI_HSNC #0/1/2 35 IOVDD_2 Digital IO power supply 2. 36 IOVSS_2 Digital IO ground 2. 37 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1 38 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1 39 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1 40 RESETn 41 PB9 EBI_A03 #0/1/2 U1_TX #2 42 PB10 EBI_A04 #0/1/2 U1_RX #2 43 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 44 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 45 AVSS_2 Analog ground 2. 46 AVDD_2 Analog power supply 2. 47 AVDD_1 Analog power supply 1. 48 AVSS_1 Analog ground 1. 49 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 50 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 51 IOVSS_3 Digital IO ground 3. 52 IOVDD_3 Digital IO power supply 3. 53 AVSS_0 Analog ground 0. 54 AVDD_0 Analog power supply 0. Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. silabs.com | Building a more connected world. Rev. 2.20 | 336 EFM32LG Data Sheet Pin Definitions Water Pads Pad Alternative Functionality / Description Pad # Pad Name Analog 55 PD0 56 EBI Timers Communication ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 57 PD2 ADC0_CH2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 58 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 59 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 60 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 61 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 62 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 63 PD8 BU_VIN 64 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 65 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 66 VSS_DREG Ground for on-chip voltage regulator. 67 VDD_DREG Power supply for on-chip voltage regulator. 68 IOVDD_4 69 DEC_0 Decouple output for on-chip voltage regulator. 70 DEC_1 Decouple output for on-chip voltage regulator. 71 DEC_2 Decouple output for on-chip voltage regulator. 72 NC 73 IOVSS_4 74 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 75 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 76 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 77 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1 78 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1 EBI_A27 #0/1/2 Other CMU_CLK1 #1 Digital IO power supply 4. Do not connect. Digital IO ground 4. silabs.com | Building a more connected world. Rev. 2.20 | 337 EFM32LG Data Sheet Pin Definitions Water Pads Pad Alternative Functionality / Description Pad # Pad Name Analog EBI Timers Communication 79 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1 80 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1 81 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1 82 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 83 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 84 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 85 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0 86 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 87 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT U1_RX #0 LES_CH13 #0 88 USB_VREGI_0 Input to internal 3.3V USB regulator 89 USB_VREGI_1 Input to internal 3.3V USB regulator 90 USB_VREGO_0 Output and decoupling for internal 3.3V USB regulator 91 USB_VREGO_1 Output and decoupling for internal 3.3V USB regulator 92 PC14 US0_CS #3 U0_TX #3 LES_CH14 #0 93 PF10 94 PC15 95 PF11 96 IOVSS_7 97 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 98 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 99 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 100 PF3 LCD_SEG1 EBI_ALE #0 TIM0_CDTI0 #2/5 101 USB_VBUS TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 Other U1_TX #1 USB_DM ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 U1_RX #1 USB_DP Digital IO ground 7. silabs.com | Building a more connected world. PRS_CH0 #1 ETM_TD3 #1 USB 5.0 V VBUS input. Rev. 2.20 | 338 EFM32LG Data Sheet Pin Definitions Water Pads Pad Alternative Functionality / Description Pad # Pad Name Analog EBI Timers 102 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 103 PF12 104 PF5 LCD_SEG3 105 IOVSS_5 Digital IO ground 5. 106 IOVDD_5 Digital IO power supply 5. 107 PF6 LCD_SEG24 108 PF7 109 Communication Other PRS_CH1 #1 USB_ID EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 110 PF9 LCD_SEG27 EBI_REn #1 111 NC 112 PD9 LCD_SEG28 EBI_CS0 #0/1/2 113 PD10 LCD_SEG29 EBI_CS1 #0/1/2 114 PD11 LCD_SEG30 EBI_CS2 #0/1/2 115 PD12 LCD_SEG31 EBI_CS3 #0/1/2 116 PD13 ETM_TD1 #1 117 PB15 ETM_TD2 #1 118 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 119 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1 120 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX 121 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 122 IOVDD_6 Digital IO power supply 6. 123 IOVSS_6 Digital IO ground 6. 124 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 125 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 126 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 127 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 128 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0 ETM_TCLK #1 ETM_TD0 #1 Do not connect. silabs.com | Building a more connected world. PRS_CH3 #1 Rev. 2.20 | 339 EFM32LG Data Sheet Pin Definitions 5.17.2 Alternate Functionality Padout A wide selection of alternate functionality is available for multiplexing to various pads. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the padout is shown in the column corresponding to LOCATION 0. Table 5.50. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 340 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0ALT PC0 DAC0_OUT1 / OPAMP_OUT1 PB12 DAC0_OUT1ALT / OPAMP_OUT1ALT PC12 Digital to Analog Converter DAC0_OUT0 / OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 DBG_SWDIO PF1 PF1 PF1 PF1 DBG_SWO PF2 PC15 PD1 PD2 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 341 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 342 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 343 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LCD_BCAP_N LCD_BCAP_P PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. silabs.com | Building a more connected world. Rev. 2.20 | 344 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6. silabs.com | Building a more connected world. Rev. 2.20 | 345 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. silabs.com | Building a more connected world. Rev. 2.20 | 346 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD0 Operational Amplifier 2 output. PF6 silabs.com | Building a more connected world. PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. Rev. 2.20 | 347 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PF11 PB10 PE3 UART1 Receive input. U1_TX PC12 PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 silabs.com | Building a more connected world. USART1 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.20 | 348 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 PD7 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. US2_RX PC3 PB4 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. US2_TX PC2 PB3 USB_DM PF10 USB D- pin. USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_ VBUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_ VREGI USB Input to internal 3.3 V regulator USB_VREGO USB_ VREGO USB Decoupling for internal 3.3 V USB regulator and regulator output USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.17.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG900 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.51. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port F -- -- -- PF12 PF11 PF10 silabs.com | Building a more connected world. Rev. 2.20 | 349 EFM32LG Data Sheet Pin Definitions 5.17.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG900 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.34. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 350 EFM32LG Data Sheet Pin Definitions 5.18 EFM32LG940 (QFN64) 5.18.1 Pinout The EFM32LG940 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.35. EFM32LG940 Pinout (top view, not to scale) silabs.com | Building a more connected world. Rev. 2.20 | 351 EFM32LG Data Sheet Pin Definitions Table 5.52. Device Pinout QFN64 Pin# and Name Pin # Pin Name 0 VSS 1 Pin Alternate Functionality / Description Analog Timers Communication Other PA0 LCD_SEG13 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 LCD_SEG15 TIM0_CC2 #0/1 CMU_CLK0 #0 ETM_TD0 #3 4 PA3 LCD_SEG16 TIM0_CDTI0 #0 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 LCD_SEG17 TIM0_CDTI1 #0 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 LCD_SEG18 TIM0_CDTI2 #0 7 PA6 LCD_SEG19 8 IOVDD_0 Digital IO power supply 0. 9 PB3 LCD_SEG20/ LCD_COM4 PCNT1_S0IN #1 US2_TX #1 10 PB4 LCD_SEG21/ LCD_COM5 PCNT1_S1IN #1 US2_RX #1 11 PB5 LCD_SEG22/ LCD_COM6 US2_CLK #1 12 PB6 LCD_SEG23/ LCD_COM7 US2_CS #1 13 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 14 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 15 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 17 PA12 LCD_BCAP_P TIM2_CC0 #1 18 PA13 LCD_BCAP_N TIM2_CC1 #1 19 PA14 LCD_BEXT TIM2_CC2 #1 20 RESETn 21 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 22 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 Ground. LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. silabs.com | Building a more connected world. Rev. 2.20 | 352 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog 23 AVDD_1 Analog power supply 1. 24 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 25 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. 28 PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 30 PD2 ADC0_CH2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 33 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 34 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 35 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 36 PD8 BU_VIN 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0 #2 #2 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PE4 LCD_COM0 US0_CS #1 42 PE5 LCD_COM1 US0_CLK #1 43 PE6 LCD_COM2 US0_RX #1 44 PE7 LCD_COM3 US0_TX #1 45 USB_VREGI Input to internal 3.3V USB regulator 46 USB_VREGO Output and decoupling for internal 3.3V USB regulator 47 PF10 USB_DM 48 PF11 USB_DP silabs.com | Building a more connected world. Timers Communication Other CMU_CLK1 #1 LES_CH6 #0 ETM_TCLK #2 Rev. 2.20 | 353 EFM32LG Data Sheet Pin Definitions QFN64 Pin# and Name Pin # Pin Name 49 Pin Alternate Functionality / Description Analog Timers Communication Other PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 50 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 51 PF2 LCD_SEG0 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 52 USB_VBUS USB 5.0 V VBUS input. 53 PF12 54 PF5 LCD_SEG3 55 IOVDD_5 Digital IO power supply 5. 56 PE8 LCD_SEG4 PCNT2_S0IN #1 57 PE9 LCD_SEG5 PCNT2_S1IN #1 58 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX 59 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 60 PE12 LCD_SEG8 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 61 PE13 LCD_SEG9 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 62 PE14 LCD_SEG10 TIM3_CC0 #0 LEU0_TX #2 63 PE15 LCD_SEG11 TIM3_CC1 #0 LEU0_RX #2 64 PA15 LCD_SEG12 TIM3_CC2 #0 USB_ID silabs.com | Building a more connected world. TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1 PRS_CH3 #1 Rev. 2.20 | 354 EFM32LG Data Sheet Pin Definitions 5.18.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.53. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output. ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output. ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_VIN PD8 Battery input for Backup Power Domain CMU_CLK0 PA2 CMU_CLK1 PA1 DAC0_OUT0 / OPAMP_OUT0 PB11 PD8 2 4 5 6 Description PD7 Clock Management Unit, clock output number 0. PE12 Clock Management Unit, clock output number 1. DAC0_OUT0ALT / OPAMP_OUT0A LT DAC0_OUT1 / OPAMP_OUT1 3 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PD0 PB12 silabs.com | Building a more connected world. Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1. Rev. 2.20 | 355 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 DAC0_OUT1ALT / OPAMP_OUT1A LT 4 5 6 Description Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. PD1 Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. ETM_TCLK PD7 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 I2C1 Serial Data input / output. LCD_BCAP_N LCD_BCAP_P PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. silabs.com | Building a more connected world. Rev. 2.20 | 356 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. silabs.com | Building a more connected world. Rev. 2.20 | 357 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. silabs.com | Building a more connected world. Rev. 2.20 | 358 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description OPAMP_OUT2 PD5 PD0 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. Operational Amplifier 2 output. PCNT0_S0IN PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1. PRS_CH2 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD1 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PF5 PA0 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PE12 PB11 TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2. Timer 1 Capture Compare input / output channel 2. TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 Timer 3 Capture Compare input / output channel 2. US0_CLK PE12 PE5 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 silabs.com | Building a more connected world. PE12 PB8 USART0 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.20 | 359 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 PE13 4 PB7 5 6 Description USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. PD1 PD6 USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX US1_TX PD0 PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. USART1 Synchronous mode Master Output / Slave Input (MOSI). US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART2 Asynchronous Receive. US2_RX PB4 US2_TX PB3 USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). USB_DM PF10 USB D- pin. USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_V BUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_V REGI USB Input to internal 3.3 V regulator USB_VREGO USB_V REGO USB Decoupling for internal 3.3 V USB regulator and regulator output silabs.com | Building a more connected world. Rev. 2.20 | 360 EFM32LG Data Sheet Pin Definitions 5.18.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG940 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.54. GPIO Pinout Port Port A Pin 15 Pin 14 Pin 13 Pin 12 PA15 PA14 PA13 PA12 Pin 11 Pin 10 -- -- -- -- -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- Port B -- Port C -- -- -- -- -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- Port D -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- -- PF5 -- -- PF2 PF1 PF0 Port E Port F PB14 PB13 PB12 PB11 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- PF12 PF11 PF10 5.18.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG940 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.36. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 361 EFM32LG Data Sheet Pin Definitions 5.19 EFM32LG942 (TQFP64) 5.19.1 Pinout The EFM32LG942 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.37. EFM32LG942 Pinout (top view, not to scale) Table 5.55. Device Pinout QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 1 PA0 LCD_SEG13 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 LCD_SEG15 TIM0_CC2 #0/1 silabs.com | Building a more connected world. CMU_CLK0 #0 ETM_TD0 #3 Rev. 2.20 | 362 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers 4 PA3 LCD_SEG16 TIM0_CDTI0 #0 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 LCD_SEG17 TIM0_CDTI1 #0 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1 7 IOVDD_0 Digital IO power supply 0. 8 VSS 9 PB3 LCD_SEG20/ LCD_COM4 PCNT1_S0IN #1 US2_TX #1 10 PB4 LCD_SEG21/ LCD_COM5 PCNT1_S1IN #1 US2_RX #1 11 PB5 LCD_SEG22/ LCD_COM6 US2_CLK #1 12 PB6 LCD_SEG23/ LCD_COM7 US2_CS #1 13 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 14 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 15 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 17 PA12 LCD_BCAP_P TIM2_CC0 #1 18 PA13 LCD_BCAP_N TIM2_CC1 #1 19 PA14 LCD_BEXT TIM2_CC2 #1 20 RESETn 21 PB11 22 VSS 23 AVDD_1 Analog power supply 1. 24 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 25 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 28 Communication Other LES_ALTEX4 #0 ETM_TD3 #3 Ground. Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 Ground. silabs.com | Building a more connected world. PCNT2_S0IN #0 US1_TX #1 Rev. 2.20 | 363 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 29 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 30 PD2 ADC0_CH2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 33 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 34 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 35 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 36 PD8 BU_VIN 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0 #2 #2 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PE4 LCD_COM0 US0_CS #1 42 PE5 LCD_COM1 US0_CLK #1 43 PE6 LCD_COM2 US0_RX #1 44 PE7 LCD_COM3 US0_TX #1 45 USB_VREGI Input to internal 3.3V USB regulator 46 USB_VREGO Output and decoupling for internal 3.3V USB regulator 47 PF10 USB_DM 48 PF11 USB_DP 49 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 50 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 51 PF2 LCD_SEG0 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 52 USB_VBUS USB 5.0 V VBUS input. 53 PF12 54 PF5 LCD_SEG3 55 IOVDD_5 Digital IO power supply 5. CMU_CLK1 #1 LES_CH6 #0 ETM_TCLK #2 USB_ID silabs.com | Building a more connected world. TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1 Rev. 2.20 | 364 EFM32LG Data Sheet Pin Definitions QFP64 Pin# and Name Pin # Pin Name 56 VSS 57 Pin Alternate Functionality / Description Analog Timers Communication Other PE8 LCD_SEG4 PCNT2_S0IN #1 58 PE9 LCD_SEG5 PCNT2_S1IN #1 59 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX 60 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 61 PE12 LCD_SEG8 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 62 PE13 LCD_SEG9 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 63 PE14 LCD_SEG10 TIM3_CC0 #0 LEU0_TX #2 64 PE15 LCD_SEG11 TIM3_CC1 #0 LEU0_RX #2 Ground. silabs.com | Building a more connected world. PRS_CH3 #1 Rev. 2.20 | 365 EFM32LG Data Sheet Pin Definitions 5.19.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.56. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output. ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output. ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_VIN PD8 Battery input for Backup Power Domain CMU_CLK0 PA2 CMU_CLK1 PA1 DAC0_OUT0 / OPAMP_OUT0 PB11 PD8 2 3 4 5 6 Description PD7 Clock Management Unit, clock output number 0. PE12 Clock Management Unit, clock output number 1. Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. DAC0_OUT0ALT / OPAMP_OUT0A LT PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. DAC0_OUT1ALT / OPAMP_OUT1A LT PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. silabs.com | Building a more connected world. Rev. 2.20 | 366 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description DBG_SWCLK PF0 PF0 PF0 PF0 DBG_SWDIO PF1 PF1 PF1 PF1 DBG_SWO PF2 PD1 PD2 ETM_TCLK PD7 PC6 ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 I2C1_SDA PC4 Debug-interface Serial Wire clock input. Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. LCD_BCAP_N LCD_BCAP_P Note that this function is not enabled after reset, and must be enabled by software to be used. Embedded Trace Module ETM clock . I2C1 Serial Clock Line input / output. PB11 I2C1 Serial Data input / output. PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. silabs.com | Building a more connected world. Rev. 2.20 | 367 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 silabs.com | Building a more connected world. Rev. 2.20 | 368 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LETIM0_OUT0 PD6 LETIM0_OUT1 PD7 LEU0_RX PD5 LEU0_TX PD4 LEU1_RX PC7 LEU1_TX PC6 LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PB11 2 3 4 5 6 Description PF0 PC4 Low Energy Timer LETIM0, output channel 0. PF1 PC5 Low Energy Timer LETIM0, output channel 1. PB14 PE15 PF1 PA0 LEUART0 Receive input. PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEUART1 Receive input. LEUART1 Transmit output. Also used as receive input in half duplex communication. PA5 PD0 Operational Amplifier 2 output. PCNT0_S0IN PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. silabs.com | Building a more connected world. Rev. 2.20 | 369 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1. PRS_CH2 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD1 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PF5 PA0 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PE12 PB11 TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2. Timer 1 Capture Compare input / output channel 2. TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1. US0_CLK PE12 PE5 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PE12 PE13 PB8 PB7 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PD1 US1_TX US2_CLK PD0 PC4 PD6 PD7 PB5 silabs.com | Building a more connected world. USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 clock input / output. Rev. 2.20 | 370 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality US2_CS 0 1 PC5 PB6 2 3 4 5 6 Description USART2 chip select input / output. USART2 Asynchronous Receive. US2_RX PB4 US2_TX USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PB3 USART2 Synchronous mode Master Output / Slave Input (MOSI). USB_DM PF10 USB D- pin. USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_V BUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_V REGI USB Input to internal 3.3 V regulator USB_VREGO USB_V REGO USB Decoupling for internal 3.3 V USB regulator and regulator output 5.19.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG942 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.57. GPIO Pinout Port Pin 15 Port A -- PA14 PA13 PA12 Port B -- PB14 PB13 Port C -- -- Port D -- -- Port E Port F Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 -- -- -- -- -- -- PA5 PA4 PA3 PA2 PA1 PA0 -- PB11 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- -- -- -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- -- PF5 -- -- PF2 PF1 PF0 PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- PF12 PF11 PF10 silabs.com | Building a more connected world. Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.20 | 371 EFM32LG Data Sheet Pin Definitions 5.19.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG942 is shown in the following figure. PB11 PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.38. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 372 EFM32LG Data Sheet Pin Definitions 5.20 EFM32LG980 (LQFP100) 5.20.1 Pinout The EFM32LG980 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.39. EFM32LG980 Pinout (top view, not to scale) silabs.com | Building a more connected world. Rev. 2.20 | 373 EFM32LG Data Sheet Pin Definitions Table 5.58. Device Pinout LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other 1 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 2 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 3 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 4 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 5 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 6 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 7 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 8 IOVDD_0 9 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2 10 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2 11 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2 12 PB3 LCD_SEG20/ LCD_COM4 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 13 PB4 LCD_SEG21/ LCD_COM5 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 14 PB5 LCD_SEG22/ LCD_COM6 EBI_A21 #0/1/2 US2_CLK #1 15 PB6 LCD_SEG23/ LCD_COM7 EBI_A22 #0/1/2 US2_CS #1 16 VSS 17 IOVDD_1 18 19 20 CMU_CLK0 #0 ETM_TD0 #3 Digital IO power supply 0. Ground. Digital IO power supply 1. PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 silabs.com | Building a more connected world. Rev. 2.20 | 374 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog EBI Timers Communication Other 21 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 22 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 LES_CH4 #0 23 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 LES_CH5 #0 24 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 25 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 26 PA7 LCD_SEG35 EBI_CSTFT #0/1/2 27 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0 28 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0 29 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0 30 PA11 LCD_SEG39 EBI_HSNC #0/1/2 31 IOVDD_2 32 VSS 33 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1 34 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1 35 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1 36 RESETn 37 PB9 EBI_A03 #0/1/2 U1_TX #2 38 PB10 EBI_A04 #0/1/2 U1_RX #2 39 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 40 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 41 AVDD_1 42 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 43 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 44 IOVDD_3 Digital IO power supply 3. 45 AVDD_0 Analog power supply 0. Digital IO power supply 2. Ground. Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. Analog power supply 1. silabs.com | Building a more connected world. Rev. 2.20 | 375 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Alternate Functionality / Description Timers Communication PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 47 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 48 PD2 ADC0_CH2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 49 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 50 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 51 PD5 ADC0_CH5 OPAMP_OUT2 #0 LEU0_RX #0 ETM_TD3 #0/2 52 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 53 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 54 PD8 BU_VIN 55 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 56 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 57 VDD_DREG 58 VSS 59 DECOUPLE 60 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 61 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 62 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 63 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1 64 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1 65 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1 66 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1 67 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1 68 PC8 ACMP1_CH0 EBI_A15 #0/1/2 46 Pin Name Analog EBI EBI_A27 #0/1/2 Other CMU_CLK1 #1 Power supply for on-chip voltage regulator. Ground. Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. silabs.com | Building a more connected world. TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 Rev. 2.20 | 376 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other 69 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 70 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 71 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0 72 USB_VREGI Input to internal 3.3V USB regulator 73 USB_VREGO Output and decoupling for internal 3.3V USB regulator 74 PF10 U1_TX #1 USB_DM 75 PF11 U1_RX #1 USB_DP 76 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 77 PF1 TIM0_CC1 #5 LETIM0_OUT1 #2 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 78 PF2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 79 USB_VBUS 80 PF12 81 PF5 82 IOVDD_5 83 VSS 84 PF6 LCD_SEG24 85 PF7 86 LCD_SEG0 EBI_ARDY #0/1/2 USB 5.0 V VBUS input. USB_ID LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 87 PF9 LCD_SEG27 EBI_REn #1 88 PD9 LCD_SEG28 EBI_CS0 #0/1/2 89 PD10 LCD_SEG29 EBI_CS1 #0/1/2 90 PD11 LCD_SEG30 EBI_CS2 #0/1/2 91 PD12 LCD_SEG31 EBI_CS3 #0/1/2 92 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 93 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1 94 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX 95 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0 BOOT_RX 96 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 CMU_CLK1 #2 LES_ALTEX6 #0 Digital IO power supply 5. Ground. silabs.com | Building a more connected world. ETM_TCLK #1 ETM_TD0 #1 PRS_CH3 #1 Rev. 2.20 | 377 EFM32LG Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI 97 PE13 LCD_SEG9 EBI_AD05 #0/1/2 98 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 99 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 100 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0 silabs.com | Building a more connected world. Timers Communication Other US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 Rev. 2.20 | 378 EFM32LG Data Sheet Pin Definitions 5.20.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.59. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 379 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 CMU_CLK1 PA1 DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 PD8 PD7 Clock Management Unit, clock output number 0. PE12 Clock Management Unit, clock output number 1. Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A LT PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PD1 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. silabs.com | Building a more connected world. PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 380 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 381 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ALE 3 4 5 6 Description EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF8 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. Rev. 2.20 | 382 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LCD_BCAP_N LCD_BCAP_P PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. silabs.com | Building a more connected world. Rev. 2.20 | 383 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7. silabs.com | Building a more connected world. Rev. 2.20 | 384 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 silabs.com | Building a more connected world. PA0 LEUART0 Receive input. Rev. 2.20 | 385 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 PE14 3 4 PF0 PF2 5 6 Description LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU0_TX PD4 PB13 LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PD0 Operational Amplifier 2 output. PCNT0_S0IN PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC2 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC3 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PF5 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PE12 PB2 PB11 silabs.com | Building a more connected world. Timer 1 Capture Compare input / output channel 2. Rev. 2.20 | 386 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 UART0 Receive input. U0_TX PF6 PE0 PA3 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PF11 PB10 PE3 UART1 Receive input. U1_TX PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PB14 PB14 USART0 chip select input / output. US0_RX PE11 PE6 PC10 PB8 PC1 USART0 Asynchronous Receive. PE12 PE13 PB7 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. US1_RX PC1 PD1 PD6 USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. US2_RX PC3 PB4 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_TX PC2 USB_DM PF10 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). USB D- pin. Rev. 2.20 | 387 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_V BUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_V REGI USB Input to internal 3.3 V regulator USB_VREGO USB_V REGO USB Decoupling for internal 3.3 V USB regulator and regulator output 5.20.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG980 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.60. GPIO Pinout Port Port A Pin 15 Pin 14 Pin 13 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 -- -- PF2 PF1 PF0 -- Port C -- -- -- Port D -- -- -- Port F Pin 11 PA15 PA14 PA13 PA12 PA11 PA10 Port B Port E Pin 12 -- PB14 PB13 PB12 PB11 PB10 -- -- -- PF12 PF11 PF10 5.20.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG980 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PD0 PD1 PD5 Figure 5.40. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 388 EFM32LG Data Sheet Pin Definitions 5.21 EFM32LG990 (BGA112) 5.21.1 Pinout The EFM32LG990 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.41. EFM32LG990 Pinout (top view, not to scale) Table 5.61. Device Pinout BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication A1 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 A2 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 A3 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 silabs.com | Building a more connected world. Other CMU_CLK1 #2 LES_ALTEX6 #0 Rev. 2.20 | 389 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other A4 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1 A5 PD10 LCD_SEG29 EBI_CS1 #0/1/2 A6 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0 A7 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 A8 PF12 A9 PE4 A10 PF10 U1_TX #1 USB_DM A11 PF11 U1_RX #1 USB_DP B1 PA15 LCD_SEG12 EBI_AD08 #0/1/2 B2 PE13 LCD_SEG9 EBI_AD05 #0/1/2 B3 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 B4 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1 B5 PD11 LCD_SEG30 EBI_CS2 #0/1/2 B6 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1 B7 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 B8 USB_VBUS B9 PE5 B10 USB_VREGI Input to internal 3.3V USB regulator B11 USB_VREGO Output and decoupling for internal 3.3V USB regulator C1 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 C2 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 C3 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX C4 PD13 C5 PD12 LCD_SEG31 EBI_CS3 #0/1/2 C6 PF9 LCD_SEG27 EBI_REn #1 C7 VSS C8 PF2 LCD_SEG0 EBI_ARDY #0/1/2 C9 PE6 LCD_COM2 EBI_A13 #0/1/2 C10 PC10 ACMP1_CH2 EBI_A10 #1/2 C11 PC11 ACMP1_CH3 EBI_ALE #1/2 D1 PA3 LCD_SEG16 EBI_AD12 #0/1/2 PRS_CH2 #1 USB_ID LCD_COM0 EBI_A11 #0/1/2 US0_CS #1 TIM3_CC2 #0 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 US0_RX #0 LES_ALTEX5 #0 BOOT_RX U0_TX #0 USB 5.0 V VBUS input. LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1 ETM_TD1 #1 ETM_TD0 #1 Ground. silabs.com | Building a more connected world. TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 US0_RX #1 TIM2_CC2 #2 TIM0_CDTI0 #0 US0_RX #2 LES_CH10 #0 US0_TX #2 LES_CH11 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 Rev. 2.20 | 390 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other D2 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 D3 PB15 D4 VSS D5 IOVDD_6 D6 PD9 D7 IOVDD_5 D8 PF1 D9 PE7 LCD_COM3 EBI_A14 #0/1/2 D10 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 D11 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 E1 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 E2 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 E3 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 E4 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2 E8 PF0 TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 E9 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 E10 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 E11 PE3 BU_STAT EBI_A10 #0 F1 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2 F2 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2 F3 PB3 LCD_SEG20/ LCD_COM4 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 F4 PB4 LCD_SEG21/ LCD_COM5 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 F8 VDD_DREG Power supply for on-chip voltage regulator. F9 VSS_DREG Ground for on-chip voltage regulator. F10 PE2 TIM3_CC2 #1 U1_TX #3 F11 DECOUPLE G1 PB5 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1 Ground. Digital IO power supply 6. LCD_SEG28 EBI_CS0 #0/1/2 Digital IO power supply 5. TIM0_CC1 #5 LETIM0_OUT1 #2 BU_VOUT EBI_A09 #0 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 US0_TX #1 U1_RX #3 ACMP1_O #1 ACMP0_O #1 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. LCD_SEG22/ LCD_COM6 silabs.com | Building a more connected world. EBI_A21 #0/1/2 US2_CLK #1 Rev. 2.20 | 391 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI G2 PB6 LCD_SEG23/ LCD_COM7 EBI_A22 #0/1/2 G3 VSS G4 IOVDD_0 Digital IO power supply 0. G8 IOVDD_4 Digital IO power supply 4. G9 VSS G10 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 I2C0_SDA #2 LES_CH6 #0 ETM_TCLK #2 G11 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 H2 PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 H3 PD14 H4 PA7 LCD_SEG35 EBI_CSTFT #0/1/2 H5 PA8 LCD_SEG36 EBI_DCLK #0/1/2 H6 VSS H7 IOVDD_3 H8 PD8 BU_VIN H9 PD5 ADC0_CH5 OPAMP_OUT2 #0 H10 PD6 ADC0_CH6 DAC0_P1 / OPAMP_P1 PD7 ADC0_CH7 DAC0_N1 / OPAMP_N1 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT J2 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT J3 PD15 J4 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1 J5 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0 H1 H11 J1 Timers Communication Other US2_CS #1 Ground. Ground. I2C0_SDA #3 TIM2_CC0 #0 Ground. Digital IO power supply 3. CMU_CLK1 #1 LEU0_RX #0 ETM_TD3 #0/2 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 I2C0_SCL #3 silabs.com | Building a more connected world. Rev. 2.20 | 392 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers J6 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0 J7 PB9 EBI_A03 #0/1/2 U1_TX #2 J8 PB10 EBI_A04 #0/1/2 U1_RX #2 J9 PD2 ADC0_CH2 J10 PD3 ADC0_CH3 OPAMP_N2 J11 PD4 ADC0_CH4 OPAMP_P2 K1 PB7 LFXTAL_P K2 PC4 ACMP0_CH4 DAC0_P0 / OPAMP_P0 K3 PA13 LCD_BCAP_N K4 VSS K5 PA11 K6 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. K7 AVSS_1 Analog ground 1. K8 AVDD_2 Analog power supply 2. K9 AVDD_1 Analog power supply 1. K10 AVSS_0 Analog ground 0. EBI_A27 #0/1/2 Communication Other TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2 LEU0_TX #0 ETM_TD2 #0/2 TIM1_CC0 #3 US0_TX #4 US1_CLK #0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 EBI_A01 #0/1/2 TIM2_CC1 #1 LES_CH4 #0 Ground. LCD_SEG39 EBI_HSNC #0/1/2 K11 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT L1 PB8 LFXTAL_N L2 PC5 ACMP0_CH5 DAC0_N0 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 L3 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1 L4 IOVDD_1 L5 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 L6 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 L7 AVSS_2 L8 PB13 TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 TIM1_CC1 #3 US0_RX #4 US1_CS #0 US2_CS #0 I2C1_SCL #0 DBG_SWO #2 LES_CH5 #0 Digital IO power supply 1. Analog ground 2. HFXTAL_P silabs.com | Building a more connected world. US0_CLK #4/5 LEU0_TX #1 Rev. 2.20 | 393 EFM32LG Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog L9 PB14 HFXTAL_N L10 AVDD_0 L11 PD0 EBI Timers Communication Other US0_CS #4/5 LEU0_RX #1 Analog power supply 0. ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 silabs.com | Building a more connected world. PCNT2_S0IN #0 US1_TX #1 Rev. 2.20 | 394 EFM32LG Data Sheet Pin Definitions 5.21.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.62. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 395 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 CMU_CLK1 PA1 DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0A PC0 LT DAC0_OUT1 / OPAMP_OUT1 PD8 PD7 Clock Management Unit, clock output number 0. PE12 Clock Management Unit, clock output number 1. Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1. PB12 DAC0_OUT1ALT / OPAMP_OUT1A LT PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PD1 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. silabs.com | Building a more connected world. PD2 Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 396 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 397 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ALE 3 4 5 6 Description EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF8 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. Rev. 2.20 | 398 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LCD_BCAP_N LCD_BCAP_P PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. silabs.com | Building a more connected world. Rev. 2.20 | 399 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7. silabs.com | Building a more connected world. Rev. 2.20 | 400 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 silabs.com | Building a more connected world. PA0 LEUART0 Receive input. Rev. 2.20 | 401 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 PE14 3 4 PF0 PF2 5 6 Description LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU0_TX PD4 PB13 LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PD0 Operational Amplifier 2 output. PCNT0_S0IN PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC2 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC3 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PF5 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PE12 PB2 PB11 silabs.com | Building a more connected world. Timer 1 Capture Compare input / output channel 2. Rev. 2.20 | 402 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 UART0 Receive input. U0_TX PF6 PE0 PA3 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PF11 PB10 PE3 UART1 Receive input. U1_TX PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PB14 PB14 USART0 chip select input / output. US0_RX PE11 PE6 PC10 PB8 PC1 USART0 Asynchronous Receive. PE12 PE13 PB7 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. US1_RX PC1 PD1 PD6 USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. PD7 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. US2_RX PC3 PB4 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_TX PC2 USB_DM PF10 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). USB D- pin. Rev. 2.20 | 403 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_V BUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_V REGI USB Input to internal 3.3 V regulator USB_VREGO USB_V REGO USB Decoupling for internal 3.3 V USB regulator and regulator output 5.21.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG990 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.63. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 -- -- PF2 PF1 PF0 Port C Port F -- -- -- -- -- -- -- PF12 PF11 PF10 5.21.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG990 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 - + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PD0 PD1 PD5 Figure 5.42. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 404 EFM32LG Data Sheet Pin Definitions 5.22 EFM32LG995 (BGA120) 5.22.1 Pinout The EFM32LG995 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.43. EFM32LG995 Pinout (top view, not to scale) Table 5.64. Device Pinout BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication A1 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2 A2 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2 A3 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 US0_CLK #0 I2C0_SDA #6 silabs.com | Building a more connected world. Other CMU_CLK1 #2 LES_ALTEX6 #0 Rev. 2.20 | 405 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other A4 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1 A5 PD11 LCD_SEG30 EBI_CS2 #0/1/2 A6 PD9 LCD_SEG28 EBI_CS0 #0/1/2 A7 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0 A8 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 A9 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 A10 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 A11 USB_VREGI Input to internal 3.3V USB regulator A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator A13 PF11 B1 PA15 LCD_SEG12 EBI_AD08 #0/1/2 B2 PE13 LCD_SEG9 EBI_AD05 #0/1/2 B3 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 B4 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1 B5 PD12 LCD_SEG31 EBI_CS3 #0/1/2 B6 PD10 LCD_SEG29 EBI_CS1 #0/1/2 B7 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1 B8 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 B9 PF3 LCD_SEG1 EBI_ALE #0 TIM0_CDTI0 #2/5 B10 PF1 B11 PF12 B12 USB_VBUS B13 PF10 C1 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1 #0 C2 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 I2C0_SDA #0 PRS_CH0 #0 GPIO_EM4WU0 C3 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX C4 PD13 C5 VSS C6 IOVDD_0 C7 PF9 PRS_CH2 #1 PRS_CH1 #1 LEU0_TX #4 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4 U1_RX #1 USB_DP TIM3_CC2 #0 TIM0_CC1 #5 LETIM0_OUT1 #2 US0_TX #3 US0_CS #0 I2C0_SCL #6 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5 US0_RX #0 LES_ALTEX5 #0 BOOT_RX U0_TX #0 PRS_CH0 #1 ETM_TD3 #1 US1_CS #2 LEU0_RX #3 I2C0_SCL #5 DBG_SWDIO #0/1/2/3 GPIO_EM4WU3 USB_ID USB 5.0 V VBUS input. U1_TX #1 USB_DM ETM_TD1 #1 Ground. Digital IO power supply 0. LCD_SEG27 silabs.com | Building a more connected world. EBI_REn #1 ETM_TD0 #1 Rev. 2.20 | 406 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name C8 VSS C9 IOVDD_1 C10 PF0 C11 PE4 LCD_COM0 PC14 ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 US0_CS #3 U0_TX #3 LES_CH14 #0 C13 PC15 ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT TIM0_CDTI2 #1/3 TIM1_CC2 #0 US0_CLK #3 U0_RX #3 LES_CH15 #0 DBG_SWO #1 D1 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0 ETM_TD1 #3 D2 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 D3 PB15 D11 PE5 LCD_COM1 PC12 ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT D13 PC13 ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT E1 PA6 LCD_SEG19 EBI_AD15 #0/1/2 E2 PA5 LCD_SEG18 EBI_AD14 #0/1/2 E3 PA4 LCD_SEG17 EBI_AD13 #0/1/2 E11 PE6 LCD_COM2 EBI_A13 #0/1/2 E12 PC10 ACMP1_CH2 EBI_A10 #1/2 E13 PC11 ACMP1_CH3 EBI_ALE #1/2 F1 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2 F2 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2 F3 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2 F11 PE7 LCD_COM3 EBI_A14 #0/1/2 F12 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0 F13 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0 GPIO_EM4WU2 C12 D12 Analog EBI Timers Communication Other TIM0_CC0 #5 LETIM0_OUT0 #2 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5 DBG_SWCLK #0/1/2/3 Ground. Digital IO power supply 1. EBI_A11 #0/1/2 US0_CS #1 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1 silabs.com | Building a more connected world. EBI_A12 #0/1/2 US0_CLK #1 U1_TX #0 CMU_CLK0 #1 LES_CH12 #0 U1_RX #0 LES_CH13 #0 LEU1_RX #1 ETM_TCLK #3 GPIO_EM4WU1 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0 ETM_TD3 #3 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0 ETM_TD2 #3 TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4 PCNT0_S0IN #0 US0_RX #1 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0 US0_TX #2 LES_CH11 #0 US0_TX #1 Rev. 2.20 | 407 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication G1 PB3 LCD_SEG20/ LCD_COM4 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1 G2 PB4 LCD_SEG21/ LCD_COM5 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1 G3 IOVDD_2 G11 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 PCNT0_S0IN #1 U0_TX #1 I2C1_SDA #2 G12 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 PCNT0_S1IN #1 U0_RX #1 I2C1_SCL #2 G13 PE3 BU_STAT EBI_A10 #0 U1_RX #3 H1 PB5 LCD_SEG22/ LCD_COM6 EBI_A21 #0/1/2 US2_CLK #1 H2 PB6 LCD_SEG23/ LCD_COM7 EBI_A22 #0/1/2 US2_CS #1 H3 VSS H11 VDD_DREG H12 PE2 BU_VOUT EBI_A09 #0 H13 PC7 ACMP0_CH7 EBI_A06 #0/1/2 J1 PD14 I2C0_SDA #3 J2 PD15 I2C0_SCL #3 J3 VSS J11 IOVDD_3 J12 PC6 J13 DECOUPLE Other Digital IO power supply 2. ACMP1_O #1 Ground. Power supply for on-chip voltage regulator. TIM3_CC2 #1 U1_TX #3 ACMP0_O #1 LEU1_RX #0 I2C0_SCL #2 LES_CH7 #0 ETM_TD0 #2 Ground. Digital IO power supply 3. ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 EBI_A05 #0/1/2 LES_CH6 #0 ETM_TCLK #2 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. PC0 ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT EBI_A23 #0/1/2 TIM0_CC1 #4 PCNT0_S0IN #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 LES_CH0 #0 PRS_CH2 #0 K2 PC1 ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT EBI_A24 #0/1/2 TIM0_CC2 #4 PCNT0_S1IN #2 US0_RX #5 US1_RX #0 I2C0_SCL #4 LES_CH1 #0 PRS_CH3 #0 K3 IOVDD_4 K11 VSS Ground. K12 VSS Ground. K13 PD8 BU_VIN PC2 ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT K1 L1 Digital IO power supply 4. silabs.com | Building a more connected world. CMU_CLK1 #1 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0 Rev. 2.20 | 408 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin # Pin Alternate Functionality / Description Pin Name Analog EBI Timers Communication Other L2 PC3 ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT EBI_NANDREn #0/1/2 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0 L3 PA7 LCD_SEG35 EBI_CSTFT #0/1/2 L4 IOVDD_5 L5 VSS Ground. L6 VSS Ground. L7 IOVDD_6 L8 PB9 EBI_A03 #0/1/2 U1_TX #2 L9 PB10 EBI_A04 #0/1/2 U1_RX #2 Digital IO power supply 5. Digital IO power supply 6. PD0 ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT OPAMP_OUT2 #1 PCNT2_S0IN #0 US1_TX #1 L11 PD1 ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 DBG_SWO #2 L12 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2 L13 PD7 ADC0_CH7 / OPAMP_N1 TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3 US1_TX #2 I2C0_SCL #1 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 M1 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4 US1_CLK #0 M2 PC4 ACMP0_CH4 / OPAMP_P0 EBI_A26 #0/1/2 TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 I2C1_SDA #0 M3 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0 M4 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0 M5 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1 M6 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1 M7 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. M8 AVSS_1 Analog ground 1. M9 AVDD_2 Analog power supply 2. M10 AVDD_1 Analog power supply 1. M11 AVSS_0 Analog ground 0. M12 PD3 L10 ADC0_CH3 OPAMP_N2 silabs.com | Building a more connected world. TIM0_CC2 #3 US1_CS #1 LES_CH4 #0 ETM_TD1 #0/2 Rev. 2.20 | 409 EFM32LG Data Sheet Pin Definitions BGA120 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog M13 PD6 N1 EBI Timers Communication Other ADC0_CH6 / OPAMP_P1 TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3 US1_RX #2 I2C0_SDA #1 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0 N2 PC5 ACMP0_CH5 / OPAMP_N0 EBI_NANDWEn #0/1/2 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 I2C1_SCL #0 N3 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0 N4 PA11 LCD_SEG39 EBI_HSNC #0/1/2 N5 PA12 LCD_BCAP_P EBI_A00 #0/1/2 N6 PB11 DAC0_OUT0 / OPAMP_OUT0 TIM1_CC2 #3 LETIM0_OUT0 #1 I2C1_SDA #1 N7 PB12 DAC0_OUT1 / OPAMP_OUT1 LETIM0_OUT1 #1 I2C1_SCL #1 N8 AVSS_2 N9 PB13 HFXTAL_P US0_CLK #4/5 LEU0_TX #1 N10 PB14 HFXTAL_N US0_CS #4/5 LEU0_RX #1 N11 AVDD_0 N12 PD2 ADC0_CH2 N13 PD5 ADC0_CH5 OPAMP_OUT2 #0 LES_CH5 #0 TIM2_CC0 #1 Analog ground 2. Analog power supply 0. silabs.com | Building a more connected world. EBI_A27 #0/1/2 TIM0_CC1 #3 USB_DMPU #0 US1_CLK #1 DBG_SWO #3 LEU0_RX #0 ETM_TD3 #0/2 Rev. 2.20 | 410 EFM32LG Data Sheet Pin Definitions 5.22.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.65. Alternate functionality overview Alternate LOCATION Functionality 0 1 ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. PE2 PE3 2 PD6 PD7 silabs.com | Building a more connected world. 3 4 5 6 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.20 | 411 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. BU_STAT PE3 Backup Power Domain status, whether or not the system is in backup mode BU_VIN PD8 Battery input for Backup Power Domain BU_VOUT PE2 Power output for Backup Power Domain CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1. DAC0_OUT0 / OPAMP_OUT0 PB11 DAC0_OUT0ALT / OPAMP_OUT0ALT PC0 DAC0_OUT1 / OPAMP_OUT1 PB12 DAC0_OUT1ALT / OPAMP_OUT1ALT PC12 Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0. PC1 PC2 PC3 PD0 Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0. Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1. PC13 PC14 PC15 PD1 Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 PF0 PF0 DBG_SWDIO PF1 PF1 PF1 PF1 DBG_SWO PF2 PC15 PD1 PD2 EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00. EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01. EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02. EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03. EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04. EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05. EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06. EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07. EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08. EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09. EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10. EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11. EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12. Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.20 | 412 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13. EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14. EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15. EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16. EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17. EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18. EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19. EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20. EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21. EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22. EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23. EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24. EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25. EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26. EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27. EBI_AD00 PE8 PE8 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 PE9 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 PE10 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 PE11 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 PE12 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 PE13 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 PE14 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 PE15 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 PA15 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 PA0 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 PA1 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 PA2 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 PA3 PA3 External Bus Interface (EBI) address and data input / output pin 12. silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 413 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 EBI_AD13 PA4 PA4 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 PA5 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 PA6 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 PC11 PC11 External Bus Interface (EBI) Address Latch Enable output. EBI_ARDY PF2 PF2 PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_BL0 PF6 PF6 PF6 External Bus Interface (EBI) Byte Lane/Enable pin 0. EBI_BL1 PF7 PF7 PF7 External Bus Interface (EBI) Byte Lane/Enable pin 1. EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_CSTFT PA7 PA7 PA7 External Bus Interface (EBI) Chip Select output TFT. EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin. EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin. EBI_HSNC PA11 PA11 PA11 External Bus Interface (EBI) TFT Horizontal Synchronization pin. EBI_NANDREn PC3 PC3 PC3 External Bus Interface (EBI) NAND Read Enable output. EBI_NANDWEn PC5 PC5 PC5 External Bus Interface (EBI) NAND Write Enable output. EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output. EBI_VSNC PA10 PA10 PA10 External Bus Interface (EBI) TFT Vertical Synchronization pin. EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output. ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock . ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0. ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1. ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2. ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3. GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4 GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4 GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4 GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4 silabs.com | Building a more connected world. 3 4 5 6 Description Rev. 2.20 | 414 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4 GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output. I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output. I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output. LCD_BCAP_N LCD_BCAP_P PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. silabs.com | Building a more connected world. Rev. 2.20 | 415 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20/ LCD_COM4 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4 LCD_SEG21/ LCD_COM5 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5 LCD_SEG22/ LCD_COM6 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6 LCD_SEG23/ LCD_COM7 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7 LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6. silabs.com | Building a more connected world. Rev. 2.20 | 416 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LES_ALTEX0 PD6 LESENSE alternate exite output 0. LES_ALTEX1 PD7 LESENSE alternate exite output 1. LES_ALTEX2 PA3 LESENSE alternate exite output 2. LES_ALTEX3 PA4 LESENSE alternate exite output 3. LES_ALTEX4 PA5 LESENSE alternate exite output 4. LES_ALTEX5 PE11 LESENSE alternate exite output 5. LES_ALTEX6 PE12 LESENSE alternate exite output 6. LES_ALTEX7 PE13 LESENSE alternate exite output 7. LES_CH0 PC0 LESENSE channel 0. LES_CH1 PC1 LESENSE channel 1. LES_CH2 PC2 LESENSE channel 2. LES_CH3 PC3 LESENSE channel 3. LES_CH4 PC4 LESENSE channel 4. LES_CH5 PC5 LESENSE channel 5. LES_CH6 PC6 LESENSE channel 6. LES_CH7 PC7 LESENSE channel 7. LES_CH8 PC8 LESENSE channel 8. silabs.com | Building a more connected world. Rev. 2.20 | 417 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description LES_CH9 PC9 LESENSE channel 9. LES_CH10 PC10 LESENSE channel 10. LES_CH11 PC11 LESENSE channel 11. LES_CH12 PC12 LESENSE channel 12. LES_CH13 PC13 LESENSE channel 13. LES_CH14 PC14 LESENSE channel 14. LES_CH15 PC15 LESENSE channel 15. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 PF0 PF2 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. OPAMP_N0 PC5 Operational Amplifier 0 external negative input. OPAMP_N1 PD7 Operational Amplifier 1 external negative input. OPAMP_N2 PD3 Operational Amplifier 2 external negative input. OPAMP_OUT2 PD5 OPAMP_P0 PC4 Operational Amplifier 0 external positive input. OPAMP_P1 PD6 Operational Amplifier 1 external positive input. OPAMP_P2 PD4 Operational Amplifier 2 external positive input. PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0. PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1. PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2. PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3. TIM0_CC0 PA0 PA0 PD0 Operational Amplifier 2 output. PF6 silabs.com | Building a more connected world. PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0. Rev. 2.20 | 418 EFM32LG Data Sheet Pin Definitions Alternate Functionality LOCATION 0 1 2 3 4 5 6 Description TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0. TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1. TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. U1_RX PC13 PF11 PB10 PE3 UART1 Receive input. U1_TX PC12 PF10 PB9 PE2 UART1 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output. US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PE12 PE13 PB8 PB7 PC1 PC0 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 PC11 US1_CLK PB7 PD2 PF0 USART1 clock input / output. US1_CS PB8 PD3 PF1 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 PD6 silabs.com | Building a more connected world. USART1 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.20 | 419 EFM32LG Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 4 5 6 Description USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 PD7 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. US2_RX PC3 PB4 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. US2_TX PC2 PB3 USB_DM PF10 USB D- pin. USB_DMPU PD2 USB D- Pullup control. USB_DP PF11 USB D+ pin. USB_ID PF12 USB ID pin. Used in OTG mode. USB_VBUS USB_ VBUS USB 5 V VBUS input. USB_VBUSEN PF5 USB 5 V VBUS enable. USB_VREGI USB_ VREGI USB Input to internal 3.3 V regulator USB_VREGO USB_ VREGO USB Decoupling for internal 3.3 V USB regulator and regulator output USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.22.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG995 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.66. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port F -- -- -- PF12 PF11 PF10 silabs.com | Building a more connected world. Rev. 2.20 | 420 EFM32LG Data Sheet Pin Definitions 5.22.4 Opamp Pinout Overview The specific opamp terminals available in EFM32LG995 is shown in the following figure. PC4 PC5 PD4 PD3 PD6 PD7 OUT0ALT + OPA0 OUT0 + OPA2 OUT2 OUT1ALT + OPA1 OUT1 - PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5 Figure 5.44. Opamp Pinout silabs.com | Building a more connected world. Rev. 2.20 | 421 EFM32LG Data Sheet BGA112 Package Specifications 6. BGA112 Package Specifications Rev: 97SPP01315A_X03_06Jun11 6.1 BGA112 Package Dimensions BOTTOM VIEW TOP VIEW SIDE VIEW Figure 6.1. BGA112 Note: 1. The dimensions in parenthesis are reference. 2. Datum 'C' and seating plane are defined by the crown of the solder balls. 3. All dimensions are in millimeters. silabs.com | Building a more connected world. Rev. 2.20 | 422 EFM32LG Data Sheet BGA112 Package Specifications 6.2 BGA112 PCB Layout b a e d Figure 6.2. BGA112 PCB Land Pattern Table 6.1. BGA112 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.35 b 0.80 d 8.00 e 8.00 b a e d Figure 6.3. BGA112 PCB Solder Mask Table 6.2. BGA112 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.48 b 0.80 d 8.00 e 8.00 silabs.com | Building a more connected world. Rev. 2.20 | 423 EFM32LG Data Sheet BGA112 Package Specifications b a e d Figure 6.4. BGA112 PCB Stencil Design Table 6.3. BGA112 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.33 b 0.80 d 8.00 e 8.00 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.20 | 424 EFM32LG Data Sheet BGA112 Package Specifications 6.3 BGA112 Package Marking In the illustration below package fields and position are shown. Figure 6.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.20 | 425 EFM32LG Data Sheet BGA120 Package Specifications 7. BGA120 Package Specifications Rev: 97SPP01321A_XO1_06APR2011 7.1 BGA120 Package Dimensions Figure 7.1. BGA120 Note: 1. The dimensions in parenthesis are reference. 2. Datum "C" and seating plane are defined by the crown of the soldier balls. 3. All dimensions are in millimeters. silabs.com | Building a more connected world. Rev. 2.20 | 426 EFM32LG Data Sheet BGA120 Package Specifications 7.2 BGA120 PCB Layout b a e d Figure 7.2. BGA120 PCB Land Pattern Table 7.1. BGA120 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.25 b 0.50 d 6.00 e 6.00 b a e d Figure 7.3. BGA120 PCB Solder Mask Table 7.2. BGA120 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.35 b 0.50 d 6.00 e 6.00 silabs.com | Building a more connected world. Rev. 2.20 | 427 EFM32LG Data Sheet BGA120 Package Specifications b a e d Figure 7.4. BGA120 PCB Stencil Design Table 7.3. BGA120 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.25 b 0.50 d 6.00 e 6.00 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.20 | 428 EFM32LG Data Sheet BGA120 Package Specifications 7.3 BGA120 Package Marking In the illustration below package fields and position are shown. Figure 7.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.20 | 429 EFM32LG Data Sheet CSP81 Package Specifications 8. CSP81 Package Specifications 8.1 CSP81 Package Dimensions Figure 8.1. CSP81 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Primary datum "C" and seating plane are defined by the spherical crowns of the solder balls. 4. Dimension "b" is measured at the maximum solder bump diameter, parallel to primary datum "C". 5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. silabs.com | Building a more connected world. Rev. 2.20 | 430 EFM32LG Data Sheet CSP81 Package Specifications Table 8.1. CSP81 (Dimensions in mm) Symbol Min Nom Max A 0.491 0.55 0.609 A1 0.17 -- 0.23 A2 0.036 -- 0.044 b 0.23 -- 0.29 S 0.3075 0.31 0.3125 D 4.355 BSC. E 4.275 BSC. e 0.40 BSC. D1 3.20 BSC. E1 3.20 BSC. n 81 aaa 0.05 bbb 0.10 ccc 0.075 ddd 0.15 eee 0.05 silabs.com | Building a more connected world. Rev. 2.20 | 431 EFM32LG Data Sheet CSP81 Package Specifications 8.2 CSP81 PCB Layout Figure 8.2. CSP81 PCB Land Pattern Table 8.2. CSP81 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) X 0.20 C1 3.20 C2 3.20 E1 0.40 E2 0.40 silabs.com | Building a more connected world. Rev. 2.20 | 432 EFM32LG Data Sheet CSP81 Package Specifications Figure 8.3. CSP81 PCB Solder Mask Table 8.3. CSP81 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) X 0.26 C1 3.20 C2 3.20 E1 0.40 E2 0.40 silabs.com | Building a more connected world. Rev. 2.20 | 433 EFM32LG Data Sheet CSP81 Package Specifications Figure 8.4. CSP81 PCB Stencil Design Table 8.4. CSP81 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) X 0.20 C1 3.20 C2 3.20 E1 0.40 E2 0.40 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.20 | 434 EFM32LG Data Sheet CSP81 Package Specifications 8.3 CSP81 Package Marking In the illustration below package fields and position are shown. Figure 8.5. Example Chip Marking (Top View) 8.4 CSP81 Environmental WLCSP devices can be handled and soldered using industry standard surface mount assembly techniques. However, because WLCSP devices are essentially a piece of silicon and are not encapsulated in plastic, they are susceptible to mechanical damage and may be sensitive to light. When WLCSPs must be used in an environment exposed to light, it may be necessary to cover the top and sides withan opaque material. silabs.com | Building a more connected world. Rev. 2.20 | 435 EFM32LG Data Sheet LQFP100 Package Specifications 9. LQFP100 Package Specifications Rev: 98A0100QP043_03MAY2007 9.1 LQFP100 Package Dimensions Figure 9.1. LQFP100 Note: 1. Datum 'T', 'U' and 'Z' to be determined at datum plane 'H' 2. Datum 'D' and 'E' to be determined at seating plane datum 'Y'. 3. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25 per side. Dimensions 'D1' and 'E1' do include mold mismatch and are determined at datum plane datum 'H'. 4. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 5. Exact shape of each corner is optional. silabs.com | Building a more connected world. Rev. 2.20 | 436 EFM32LG Data Sheet LQFP100 Package Specifications Table 9.1. LQFP100 (Dimensions in mm) SYMBOL MIN NOM MAX total thickness A -- -- 1.6 stand off A1 0.05 -- 0.15 mold thickness A2 1.35 1.4 1.45 lead width (plating) b 0.17 0.2 0.27 lead width b1 0.17 -- 0.23 L/F thickness (plating) c 0.09 -- 0.2 lead thickness c1 0.09 -- 0.16 body size x D 16 BSC y E 16 BSC x D1 14 BSC y E1 14 BSC e 0.5 BSC lead pitch L footprint 0.45 L1 0.6 0.75 1 REF 0 3.5 7 1 0 -- -- 2 11 12 13 3 11 12 13 R1 0.08 -- -- R1 0.08 -- 0.2 S 0.2 -- -- package edge tolerance aaa 0.2 lead edge tolerance bbb 0.2 coplanarity ccc 0.08 lead offset ddd 0.08 mold flatness eee 0.05 silabs.com | Building a more connected world. Rev. 2.20 | 437 EFM32LG Data Sheet LQFP100 Package Specifications 9.2 LQFP100 PCB Layout a p8 b p7 p6 p1 e c p2 p5 p3 p4 d Figure 9.2. LQFP100 PCB Land Pattern Table 9.2. LQFP100 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number a 1.45 P1 1 P6 75 b 0.30 P2 25 P7 76 c 0.50 P3 26 P8 100 d 15.40 P4 50 e 15.40 P5 51 a b e c d Figure 9.3. LQFP100 PCB Solder Mask Table 9.3. LQFP100 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.57 b 0.42 c 0.50 d 15.40 e 15.40 silabs.com | Building a more connected world. Rev. 2.20 | 438 EFM32LG Data Sheet LQFP100 Package Specifications a b e c d Figure 9.4. LQFP100 PCB Stencil Design Table 9.4. LQFP100 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.35 b 0.20 c 0.50 d 15.40 e 15.40 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.20 | 439 EFM32LG Data Sheet LQFP100 Package Specifications 9.3 LQFP100 Package Marking In the illustration below package fields and position are shown. Figure 9.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.20 | 440 EFM32LG Data Sheet QFN64 Package Specifications 10. QFN64 Package Specifications 10.1 QFN64 Package Dimensions 49 64 48 33 16 32 17 m m Rev: 98SPP64048A_XO1_08MAR2011 1 Figure 10.1. QFN64 Note: 1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1 mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. silabs.com | Building a more connected world. Rev. 2.20 | 441 EFM32LG Data Sheet QFN64 Package Specifications Table 10.1. QFN64 (Dimensions in mm) Symbol Min Nom Max A 0.80 0.85 0.90 A1 0.00 -- 0.05 A3 b 0.203 REF 0.20 0.25 D 9.00 BSC E 9.00 BSC 0.30 D2 7.10 7.20 7.30 E2 7.10 7.20 7.30 e 0.50 BSC L 0.40 0.45 0.50 L1 0.00 -- 0.10 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 silabs.com | Building a more connected world. Rev. 2.20 | 442 EFM32LG Data Sheet QFN64 Package Specifications 10.2 QFN64 PCB Layout a p8 b p7 p1 p6 e g p9 c p2 p5 p3 p4 f d Figure 10.2. QFN64 PCB Land Pattern Table 10.2. QFN64 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number a 0.85 P1 1 P8 64 b 0.30 P2 16 P9 0 c 0.50 P3 17 d 8.90 P4 32 e 8.90 P5 33 f 7.20 P6 48 g 7.20 P7 49 a b e g c f d Figure 10.3. QFN64 PCB Solder Mask Table 10.3. QFN64 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Dim. (mm) a 0.97 e 8.90 b 0.42 f 7.32 c 0.50 g 7.32 silabs.com | Building a more connected world. Rev. 2.20 | 443 EFM32LG Data Sheet QFN64 Package Specifications Symbol Dim. (mm) Symbol Dim. (mm) d 8.90 - - a b x y e z c d Figure 10.4. QFN64 PCB Stencil Design Table 10.4. QFN64 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Dim. (mm) a 0.75 e 8.90 b 0.22 x 2.70 c 0.50 y 2.70 d 8.90 z 0.80 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.20 | 444 EFM32LG Data Sheet QFN64 Package Specifications 10.3 QFN64 Package Marking In the illustration below package fields and position are shown. Figure 10.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.20 | 445 EFM32LG Data Sheet TQFP64 Package Specifications 11. TQFP64 Package Specifications Rev: 98SPP64023A_XO1_17MAR2011 11.1 TQFP64 Package Dimensions F CL Figure 11.1. TQFP64 Note: 1. All dimensions & tolerancing confirm to ASME Y14.5M-1994. 2. The top package body size may be smaller than the bottom package body size. 3. Datum 'A,B', and 'B' to be determined at datum plane 'H'. 4. To be determined at seating place 'C'. 5. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side. 'D1' and 'E1' are maximum plastic body size dimension including mold mismatch. Dimension 'D1' and 'E1' shall be determined at datum plane 'H'. 6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated. 7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 8. Exact shape of each corner is optional. 9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 10. All dimensions are in millimeters. silabs.com | Building a more connected world. Rev. 2.20 | 446 EFM32LG Data Sheet TQFP64 Package Specifications Table 11.1. QFP64 (Dimensions in mm) DIM MIN NOM MAX DIM A -- 1.10 1.20 L1 A1 0.05 -- 0.15 R1 0.08 -- -- A2 0.95 1.00 1.05 R2 0.08 -- 0.20 b 0.17 0.22 0.27 S 0.20 -- -- b1 0.17 0.20 0.23 0 3.5 7 c 0.09 -- 0.20 1 0 -- -- C1 0.09 -- 0.16 2 11 12 13 3 11 12 13 D 12.0 BSC D1 10.0 BSC e 0.50 BSC E 12.0 BSC E1 10.0 BSC L 0.45 0.60 silabs.com | Building a more connected world. MIN NOM MAX -- 0.75 Rev. 2.20 | 447 EFM32LG Data Sheet TQFP64 Package Specifications 11.2 TQFP64 PCB Layout a p8 b p7 p6 p1 e c p2 p5 p3 p4 d Figure 11.2. TQFP64 PCB Land Pattern Table 11.2. TQFP64 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number a 1.60 P1 1 P6 48 b 0.30 P2 16 P7 49 c 0.50 P3 17 P8 64 d 11.50 P4 32 e 11.50 P5 33 a b e c d Figure 11.3. TQFP64 PCB Solder Mask Table 11.3. TQFP64 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.72 b 0.42 c 0.50 d 11.50 e 11.50 silabs.com | Building a more connected world. Rev. 2.20 | 448 EFM32LG Data Sheet TQFP64 Package Specifications a b e c d Figure 11.4. TQFP64 PCB Stencil Design Table 11.4. TQFP64 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.50 b 0.20 c 0.50 d 11.50 e 11.50 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.20 | 449 EFM32LG Data Sheet TQFP64 Package Specifications 11.3 TQFP64 Package Marking In the illustration below package fields and position are shown. Figure 11.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.20 | 450 EFM32LG Data Sheet Wafer Specifications 12. Wafer Specifications 12.1 Bonding Instructions All pads should be bonded out, with the exception of the pads labeled "NC" and listed as "Do not connect" in Padout. Gold bond wires are recommended for these devices. All three voltage regulator output decouple pads (DEC_0, DEC_1, DEC_2) must be bonded out and electrically connected on the PCB. In the packaged devices, these three pads are all bonded to a single DECOUPLE pin. If the USB feature of EFM32LG900 will be used, all of the USB pads must be bonded out, and * both USB_VREGO_0 and USB_VREGO_1 must be bonded out and electrically connected on the PCB. In the packaged devices, these two pads are both bonded to a single USB_VREGO pin. * both USB_VREGI_0 and USB_VREGI_1 must be bonded out and electrically connected on the PCB. In the packaged devices, these two pads are both bonded to a single USB_VREGI pin. 12.2 Wafer Description Table 12.1. Wafer and Die Information Parameter Device Family Wafer Diameter Die Dimensions (Outer edge of seal ring) Wafer Thickness (No backgrind) Value EFM32LG (Leopard Gecko) 8 in Contact sales for information 725 m 15 m (28.54 mil 1 mil) Wafer Identification Notch Scribe Street Width 80 m x 160 m Die Per Wafer1 Contact sales for information Passivation Standard Wafer Packaging Detail Wafer Jar Bond Pad Dimensions 65 m (parallel to die edge) x 66 m Bond Pad Pitch Minimum 76 m Maximum Processing Temperature 250C Electronic Die Map Format .txt Note: 1. This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer). 12.2.1 Environmental Bare silicon die are susceptible to mechanical damage and may be sensitive to light. When bare die must be used in an environment exposed to light, it may be necessary to cover the top and sides with an opaque material. Further quality and environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx. silabs.com | Building a more connected world. Rev. 2.20 | 451 EFM32LG Data Sheet Wafer Specifications 12.3 Wafer Storage Guidelines It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination. * Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs. * Wafers must be stored at a temperature of 18 - 24 C. * Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%. * Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air). 12.4 Failure Analysis (FA) Guidelines Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in wafer form. * In order to conduct failure analysis on a device in a customer-provided package, Silicon Laboratories must be provided with die assembled in an industry standard package that is pin compatible with existing packages Silicon Laboratories offers for the device. Initial response time for FA requests that meet these requirements will follow the standard FA guidelines for packaged parts. * If retest of the entire wafer is requested, Silicon Laboratories must be provided with the whole wafer. Silicon Laboratories cannot retest any wafers that have been sawed, diced, backgrind or are on tape. Initial response time for FA requests that meet these requirements will be 3 weeks. silabs.com | Building a more connected world. Rev. 2.20 | 452 EFM32LG Data Sheet Chip Revision, Solder Information, Errata 13. Chip Revision, Solder Information, Errata 13.1 Chip Revision The revision of a chip can be determined from the "Revision" field in the package marking. 13.2 Soldering Information The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed. The packages have a Moisture Sensitivity Level rating of 3. Please see the latest IPC/JEDEC J-STD-033 standard for MSL description and level 3 bake conditions. 13.3 Errata Please see the errata document for description and resolution of device errata. This document is available in Simplicity Studio and online at: http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit silabs.com | Building a more connected world. Rev. 2.20 | 453 EFM32LG Data Sheet Revision History 14. Revision History 14.1 Revision 2.20 April 2019 Key Features stop mode current changed to match value specified in 4.5 Current Consumption. 2. Ordering Information corrected to show that the package for the EFM32LG942 is the TQFP64 and not the BGA120. Spelling and punctuation errors fixed in 3.1.12 Universal Serial Bus Controller (USB). Corrected available ACMP0 and ACMP1 channels in the following Configuration Summary sections: * 3.2.6 EFM32LG330 * 3.2.7 EFM32LG332 * 3.2.9 EFM32LG380 * 3.2.10 EFM32LG390 * 3.2.12 EFM32LG840 * 3.2.13 EFM32LG842 * 3.2.18 EFM32LG940 * 3.2.19 EFM32LG942 * 3.2.20 EFM32LG980 * 3.2.21 EFM32LG990 GPIO count in Table 3.6 EFM32LG330 Configuration Summary on page 27 increased from 52 to 53. GPIO count in Table 3.18 EFM32LG940 Configuration Summary on page 51 increased from 52 to 53. Added TJ parameter to Table 4.1 Absolute Maximum Ratings on page 63. Added 4.4 Backup Supply Domain specifications to 4. Electrical Characteristics. Capitalization of figure titles made consistent in 4.5.1 EM1 Current Consumption. Restored figure title for Figure 4.7 EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 1.2 MHz on page 70. Restored note to 4.5.2 EM2 Current Consumption indicating use of Backup RTC (BURTC). Updated the following 4.8 Flash specifications and added relevant notes: * Page erase time (tPERASE) * Device erase time (tDERASE) Added load current (ILOAD_DC) maximum to 4.12 Digital Analog Converter (DAC) specifications. Updated the load resistance (RLOAD) in 4.13 Operational Amplifier (OPAMP) specifications. Corrected the following 4.16 EBI parameters: * Minimum tOH_ALEn equation to use ADDRHOLD instead of WRHOLD. * Minimum tH_ARDY equation to include addition of (3 * tHFCORECLK) term. Title of Figure 4.44 SPI Slave Timing on page 128 corrected to specify slave (not master) timing. Restored the analog description of USB_VREGI and USB_VREGO as follows: * Pins A11 and A12 in the Table 5.13 Device Pinout on page 178 for EFM32LG295. * Pin s 45 and 46 in the Table 5.13 Device Pinout on page 178 for EFM32LG330. * Pin s 45 and 46 in the Table 5.19 Device Pinout on page 202 for EFM32LG332. * Pins A11 and A12 in the Table 5.64 Device Pinout on page 405 for EFM32LG995. * Pins B1 and C1 in the Table 5.22 Device Pinout on page 212 for EFM32LG360. * Pins 72 and 73 in the Table 5.25 Device Pinout on page 224 for EFM32LG380. * Pins B10 and B11 in the Table 5.28 Device Pinout on page 236 for EFM32LG390. * Pins A11 and A12 in the Table 5.31 Device Pinout on page 250 for EFM32LG395. * Pins A11 and A12 in the Table 5.46 Device Pinout on page 319 for EFM32LG895. silabs.com | Building a more connected world. Rev. 2.20 | 454 EFM32LG Data Sheet Revision History * * * * * Pins 45 and 46 in the Table 5.52 Device Pinout on page 352 for EFM32LG940. Pins 45 and 46 in the Table 5.55 Device Pinout on page 362 for EFM32LG942. Pins 72 and 73 in the Table 5.58 Device Pinout on page 374 for EFM32LG980. Pins B10 and B11 in the Table 5.61 Device Pinout on page 389 for EFM32LG990. Pins A11 and A12 in the Table 5.64 Device Pinout on page 405 for EFM32LG995. Changed pin #8 in Table 5.1 Device Pinout on page 131 from VSS to IOVDD_0 to match Figure 5.1 EFM32LG232 on page 130. Restored PC1 and PC0 as 4th alternate locations of I2C0_SCL and I2C0_SDA, respectively in 5.2.2 Alternate Functionality Pinout for the EFM32LG232. Removed USB_DMPU #0 from the Communication column of pin 48 in Table 5.7 Device Pinout on page 151 for the EFM32LG280. Restored PC15 as the 1st alternate location of DBG_SWO in 5.4.2 Alternate Functionality Pinout for the EFM32LG290. Corrected 5.5.3 GPIO Pinout Overview text to reflect that the information shown is for the EFM32LG295 and not the EFM32LG395. Restored the signal descriptions of DAC0_OUT1 /OPAMP_OUT1 in 5.6.2 Alternate Functionality Pinout for the EFM32LG330. Restored the following signals in 5.12.2 Alternate Functionality Pinout for the EFM32LG840: * GPIO_EM4WU1 * PA6 as 4th location of ETM_CLK * PC13 as the 4th location of TIM1_CC2 Restored PC13 as the 4th location of TIM1_CC2 in 5.13.2 Alternate Functionality Pinout for the EFM32LG842. Removed USB_DMPU #0 from the Communication column of pin 48 in Table 5.40 Device Pinout on page 287 for the EFM32LG880. Restored PF3 as the 0th (primary) location of EBI_ALE in 5.14.2 Alternate Functionality Pinout for the EFM32LG880. Restored PC15 as the 1st location of DBG_SWO in 5.15.2 Alternate Functionality Pinout for the EFM32LG890. Restored U1_RX #1 to the Communication column of pin A13 in Table 5.46 Device Pinout on page 319 for the EFM32LG895. Pad 117 changed from PD15 to PB15 in Table 5.49 Device Padout on page 334 for the EFM32LG900. Added TIM3_CC2 to 5.19.2 Alternate Functionality Pinout for the EFM32LG940. Restored moisture sensitivity information to 13.2 Soldering Information. Corrected symbol b in 10.1 QFN64 Package Dimensions. Corrected the pin number for symbol P9 in 10.2 QFN64 PCB Layout. Statements regarding packaging materials have been removed. The most current device quality and environmental information can be found at http://www.silabs.com/support/quality/pages/default.aspx. 14.2 Revision 2.10 September 20th, 2017 In 4.10.5 AUXHFRCO, updated test conditions for oscillation frequency. In 4.11 Analog Digital Converter (ADC): * Added footnote for average active current. * Updated conditions for INL and DNL. * Updated parameter description for VREF. * Updated VREF current consumption max for 1.25V and 2.5V reference. In 4.12 Digital Analog Converter (DAC): * Updated parameter description and test conditions for IDAC. * Updated parameter description for VREF. Corrected pinout diagram for EFM32LG230 in 5.1.1 Pinout. Spelling and formatting updates throughout. silabs.com | Building a more connected world. Rev. 2.20 | 455 EFM32LG Data Sheet Revision History 14.3 Revision 2.00 April 17th, 2017 Consolidated all EFM32LG data sheets: * EFM32LG230 * EFM32LG232 * EFM32LG280 * EFM32LG290 * EFM32LG295 * EFM32LG330 * EFM32LG332 * EFM32LG360 * EFM32LG380 * EFM32LG390 * EFM32LG395 * EFM32LG840 * EFM32LG842 * EFM32LG880 * EFM32LG890 * EFM32LG895 * EFM32LG900 * EFM32LG940 * EFM32LG942 * EFM32LG980 * EFM32LG990 * EFM32LG995 Added a Feature List section. 2. Ordering Information - Added ordering code decoder. 3.3 Memory Map - Separated the Memory Map into two figures - one for core and code space listing and one for peripheral listing. 4.2 Absolute Maximum Ratings - Removed the footnote about storage temperature and added max source/sink current per I/O pin. Environmental - Removed this section. Environmental specifications are available in the qualification report. 4.5 Current Consumption - Added maximum current specifications for the highest energy mode, IEM0. 4.9 General Purpose Input Output - Reduced maximum input leakage current (IIOLEAK, max). 4.10.1 LFXO - Replaced "energyAware Designer" with "Configurator tool". 4.10.3 LFRCO - Added (min, typ, max) specifications for oscillation frequency over full power supply and full temperature range. Also added typical voltage drift and temperature drift specs. 4.10.3 LFRCO - Updated graphs for calibrated LFRCO Frequency vs. Temperature and Supply Range, and also fixed y-axis unit [kHz]. 4.10.4 HFRCO - Added specifications for oscillation frequency over full power supply and temperature range, added typical voltage drift and temperature drift specs at each frequency band, and removed the duty cycle spec (DCHFRCO). 4.10.4 HFRCO - Updated all HFRCO graphs (various frequency bands). 4.10.6 ULFRCO - Removed the duty cycle spec for AUXHFRCO (DCAUXHFRCO). 4.11 Analog Digital Converter (ADC) - Added the following specs: * Input bias current (IADCBIASIN) - added max (source and sink). * Input offset current (IADCOFFSETIN) - added max (source and sink). * VREF output voltage (VREF) - added min, typ, max. * VREF voltage drift (VREF_VDRIFT) - added min, typ, max. * VREF temperature drift (VREF_TDRIFT) - added min, typ, max. silabs.com | Building a more connected world. Rev. 2.20 | 456 EFM32LG Data Sheet Revision History * VREF current consumption (IVREF) - added typ, max, replacing IADCREF. * ADC and DAC VREF matching (VREF_MATCH) - added typical. 4.12 Digital Analog Converter (DAC) - Updated the footnote for active average current (IDAC), and added the following new VREF specs at each voltage reference: * VREF output voltage (VREF) - added min, typ, max. * VREF voltage drift (VREF_VDRIFT) - added min, typ, max. * VREF temperature drift (VREF_TDRIFT) - added min, typ, max. * VREF current consumption (IVREF) - added typ, max. * ADC and DAC VREF matching (VREF_MATCH) - added typical. 4.13 Operational Amplifier (OPAMP) - Removed note specifying that OPAMP specs stem from simulations, and added new specifications for the following: * Active Current (IOPAMP) - new specifications at various (new) bias program settings. * Gain Bandwidth Product (GBWOPAMP) - new (typ) specifications at new bias program settings and DC bias settings. * Input Offset Voltage (VOFFSET) - specified min, typ, max for Op Amps (OPA0-1). * Input Bias Current (IOPAMPBIASIN) - new min and max specifications. * Input Offset Current (IOPAMPOFF-SETIN) - new min and max specifications. * Slew Rate (SROPAMP) - new specifications at new bias program settings. * Updated footnote. 4.14 Analog Comparator (ACMP) - Added new specifications for the following: * Input Bias Current (IACMPBIASIN) - added min and max. * Input Offset Current (IACMPOFFSETIN) - added min and max. * Active Current (IACMP) - added two new condition settings, and footnote. * Negative Response Time (tRESPONSE_N) - added new specifications. * Positive Response Times (tRESPONSE_P) - added new specifications. * Offset Voltage (VACMPOFFSET) - added specifications at new bias program settings. * ACMP Hysteresis (VACMPHYST) - added specifications for negative and positive hysteresis at various bias program settings. * VDD SCALED Input Accuracy (VVDDSCALED) - added new specifications (typical). 4.15 Voltage Comparator (VCMP) - Added the following new specifications: * Negative hysteresis (VVCMPHYST_N), replacing VCMP hysteresis. * Positive hysteresis (VVCMPHYST_P), replacing VCMP hysteresis. * Hysteresis Delta (VVCMPHYST_DELTA). * Negative Response Time (tRESPONSE_N). * Positive Response Time (tRESPONSE_P). * Footnote for active current, IVCMP. 4.19 USART SPI - Corrected parameter descriptions for tCS_DIS_MI. 4.20 Digital Peripherals - Added (typical) LE Peripheral Interface Clock Current (ILFCLK) specifications with both the LFXO-LFA and LFXO-LFB clock trees. Removed MSL information (Moisture Sensitivity Level). Instead, MSL information can be found in the Qual report that is available on the Silicon Labs website. New formatting throughout. silabs.com | Building a more connected world. Rev. 2.20 | 457 EFM32LG Data Sheet Revision History 14.4 Revision 1.31 December 16th, 2015 Removed Environmental section from General Operating Conditions. Added max current consumption numbers for energy modes. For devices with an ADC, added clarification on conditions for INLADC and DNLADC parameters. For devices with an EBI, updated EBI ready/wait figure. Updated memory map. Removed DCHFRCO and DCAUXHFRCO parameters. For CSP81 package, updated typical and added min/max values for fHFRCO and fAUXHFRCO. For devices in CSP81 package with a DAC, updated OPAMP table. Fixed typos Added OPAMP, ADC, and ACMP Input Bias Current and Input Offset Current specifications. Added lower limit for GPIO Input Leakage Current and updated the upper limit for this specification. Removed the "by simulation and/or technology characterization" phrase from the Electrical Characteristics Test Conditions section. 14.5 Revision 1.30 June 13th, 2014 This revision applies the following devices: * EFM32LG230 * EFM32LG232 * EFM32LG280 * EFM32LG290 * EFM32LG295 * EFM32LG330 * EFM32LG332 * EFM32LG380 * EFM32LG390 * EFM32LG395 * EFM32LG840 * EFM32LG842 * EFM32LG880 * EFM32LG890 * EFM32LG895 * EFM32LG940 * EFM32LG942 * EFM32LG980 * EFM32LG990 * EFM32LG995 Removed "Preliminary" markings. Updated electrical characteristics and updated/added plots. Updated orderable part numbers. Added AUXHFRCO to block diagram and electrical characteristics. For devices with EBI, added EBI timing chapter. silabs.com | Building a more connected world. Rev. 2.20 | 458 EFM32LG Data Sheet Revision History 14.6 Revision 1.21 November 21st, 2013 This revision applies the following devices: * EFM32LG230 * EFM32LG232 * EFM32LG280 * EFM32LG290 * EFM32LG295 * EFM32LG330 * EFM32LG332 * EFM32LG380 * EFM32LG390 * EFM32LG395 * EFM32LG840 * EFM32LG842 * EFM32LG880 * EFM32LG890 * EFM32LG895 * EFM32LG940 * EFM32LG942 * EFM32LG980 * EFM32LG990 * EFM32LG995 Updated figures. Updated errata-link. Updated chip marking. Added link to Environmental and Quality information. For devices with a DAC, re-added missing DAC-data. silabs.com | Building a more connected world. Rev. 2.20 | 459 EFM32LG Data Sheet Revision History 14.7 Revision 1.20 September 30th, 2013 This revision applies the following devices: * EFM32LG230 * EFM32LG232 * EFM32LG280 * EFM32LG290 * EFM32LG295 * EFM32LG330 * EFM32LG332 * EFM32LG380 * EFM32LG390 * EFM32LG395 * EFM32LG840 * EFM32LG842 * EFM32LG880 * EFM32LG890 * EFM32LG895 * EFM32LG940 * EFM32LG942 * EFM32LG980 * EFM32LG990 * EFM32LG995 Added I2C characterization data. Added SPI characterization data. Corrected the DAC and OPAMP2 pin sharing information in the Alternate Functionality Pinout section. Corrected GPIO operating voltage from 1.8 V to 1.85 V. For devices with USB, added the USB bootloader information. Corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit. For QFN64 packages, removed UART mentioned incorrectly in the QFN64 parts. Updated Environmental information. Updated trademark, disclaimer and contact information. Other minor corrections. This revision applies the following devices: * EFM32LG900 March 16th, 2015 Corrected pad numbers and the order of the pads in the padout table so that it matches the drawing. silabs.com | Building a more connected world. Rev. 2.20 | 460 EFM32LG Data Sheet Revision History 14.8 Revision 1.11 November 17th, 2010 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 Corrected maximum DAC clock speed for continuous mode. Added DAC sample-hold mode voltage drift rate. Added pulse widths detected by the HFXO glitch detector. Added power sequencing information to Power Management section. silabs.com | Building a more connected world. Rev. 2.20 | 461 EFM32LG Data Sheet Revision History 14.9 Revision 1.10 June 28th, 2013 This revision applies the following devices: * EFM32LG230 * EFM32LG232 * EFM32LG280 * EFM32LG290 * EFM32LG295 * EFM32LG330 * EFM32LG332 * EFM32LG380 * EFM32LG390 * EFM32LG395 * EFM32LG840 * EFM32LG842 * EFM32LG880 * EFM32LG890 * EFM32LG895 * EFM32LG940 * EFM32LG942 * EFM32LG980 * EFM32LG990 * EFM32LG995 Updated power requirements in the Power Management section. For BGA packages, updated PCB Land Pattern, PCB Solder Mask and PCB Stencil Design figures. Removed minimum load capacitance figure and table. Added reference to application note. Other minor corrections. This revision applies the following devices: * EFM32LG900 December 12th, 2014 Added recommendation to use gold bond wire. silabs.com | Building a more connected world. Rev. 2.20 | 462 EFM32LG Data Sheet Revision History 14.10 Revision 1.00 This revision applies the following devices: * EFM32LG230 * EFM32LG232 * EFM32LG280 * EFM32LG290 * EFM32LG295 * EFM32LG330 * EFM32LG332 * EFM32LG380 * EFM32LG390 * EFM32LG395 * EFM32LG840 * EFM32LG842 * EFM32LG880 * EFM32LG890 * EFM32LG895 * EFM32LG940 * EFM32LG942 * EFM32LG980 * EFM32LG990 * EFM32LG995 September 11th, 2012 Updated the HFRCO 1 MHz band typical value to 1.2 MHz. Updated the HFRCO 7 MHz band typical value to 6.6 MHz. For BGA112 and BGA120 packages, corrected BGA solder balls material from Sn96.5/Ag3/Cu0.5 to SAC105. This revision applies the following devices: * EFM32LG360 * EFM32LG900 October 15th, 2014 Initial release. 14.11 Revision 0.92 May 25th, 2012 This revision applies the following devices: * EFM32LG290 * EFM32LG295 * EFM32LG390 * EFM32LG395 * EFM32LG890 * EFM32LG895 * EFM32LG990 * EFM32LG995 Corrected BGA solder balls material description. Corrected EM3 current consumption in the Electrical Characteristics section. silabs.com | Building a more connected world. Rev. 2.20 | 463 EFM32LG Data Sheet Revision History 14.12 Revision 0.90 April 27th, 2012 This revision applies the following devices: * EFM32LG230 * EFM32LG232 * EFM32LG280 * EFM32LG290 * EFM32LG295 * EFM32LG330 * EFM32LG332 * EFM32LG380 * EFM32LG390 * EFM32LG395 * EFM32LG840 * EFM32LG842 * EFM32LG880 * EFM32LG890 * EFM32LG895 * EFM32LG940 * EFM32LG942 * EFM32LG980 * EFM32LG990 * EFM32LG995 Initial preliminary release. silabs.com | Building a more connected world. Rev. 2.20 | 464 Simplicity Studio One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! IoT Portfolio www.silabs.com/IoT SW/HW Quality Support and Community www.silabs.com/simplicity www.silabs.com/quality community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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