Nis Se Mu lti-Output, Low-Noise Power-Supply Controllers for Notebook Computers 19-0480; Rev 3; 4/97 y a) ALU ATION a iN General Description Features The MAX1630-MAX1635 are buck-topology, step-down, 96% Efficiency switch-mode, power-supply controllers that generate +4,.2V to +30V Input Range logic-supply voltages in battery-powered systems. These 2.5V to 5.5V Dual Adjustable Outputs high-performance, dualAriple-outout devices include on- Selectable 3.3V and 5V Fixed or Adjustabl board power-up sequencing, power-good signaling with erecta e Ixed or Adjustable - a Outputs (Dual Mode) delay, digital soft-start, secondary winding control, low- . dropout circuitry, internal frequency-compensation net- 12V Linear Regulator works, and automatic bootstrapping. Adjustable Secondary Feedback (MAX1631/MAX1634) Up to 96% efficiency is achieved through synchronous . rectification and Maxim's proprietary Idle Mode control 5V/50mA Linear Regulator Output Precision 2.5V Reference Output scheme. Efficiency is greater than 80% over a 1000:1 load-current range, which extends battery life in system- Programmable Power-Up Sequencing suspend or standby mode. Excellent dynamic response Power-Good (RESET) Output Output Overvoltage Protection corrects output load transients caused by the latest dynamic-clock CPUs within five 300kHz clock cycles. (MAX1630/MAX1631/MAX1632) Output Undervoltage Shutdown Strong 1A on-board gate drivers ensure fast external N-channel MOSFET switching. (MAX1630/MAX1631/MAX1632) These devices feature a logic-controlled and synchroniz- Nol ad. able, fixed-frequency, pulse-width-modulation (PWM) , Operation Low-Noise, Fixed-Frequency operating mode. This reduces noise and RF interference : in sensitive mobile communications and pen-entry appli- Low-Dropout, 99% Duty-Factor Operation cations. Asserting the SKIP pin enables fixed-frequency 2.5mW Typical Quiescent Power (+12V input, both mode, for lowest noise under all load conditions. SMPSs on) The MAX1630-MAX1635 include two PWM regulators, 4A Typical Shutdown Current adjustable from 2.5V to 5.5V with fixed 5.0V and 3.3V = # 28-Pin SSOP Package modes. All these devices include secondary feedback . . regulation, and the MAX1630/MAX1632/MAX1633/ Ordering Information > fet e+ @ of cee Sd Sd MAX1635 each contain 12V/120mA linear regulators. The MAX1631/MAX1634 include a secondary feedback input PART TEMP. RANGE PIN-PACKAGE (SECFB), plus a control pin (STEER) that selects which MAX1630CAI OC to +70C 28 SSOP PWM (3.3V or 5V) receives the secondary feedback sig- MAX1630EAI -40C to +85C 28 SSOP nal. SECFB provides a method for adjusting the sec- Ordering Information continued on last page. ondary winding voltage regulation point with an external resistor divider, and is intended to aid in creating auxiliary voltages other than fixed 12V. Functional Diagram The MAX1630/MAX1631/MAX1632 contain internal out- put overvoltage and undervoltage protection features. INPUT ' Applications 45V (RIC) #12V Tf. 5V 12V Notebook and Subnotebook Computers zr LINEAR | | LINEAR PDAs and Mobile Communicators Desktop CPU Local DC-DC Converters 3.3V BV SMPS SMPS Pin Configurations and Selector Guide appear at end of data sheet. ONOFF POWER-UP} | POWER- RESET SEQUENCE} | GOOD Idle Mode and Dual Mode are trademarks of Maxim Integrated Products. MAXLV Maxim Integrated Products 1 For free samples & the latest literature: http://)www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers ABSOLUTE MAXIMUM RATINGS V+ to GND one enaneeeeeaceeneneel -0.3V to +36V PGND to GND... en neirnneeeeeeeascneeaneninee +0.3V VL to GND ooo nen ne nein eneneer eines -0.3V to +6V BST3, BST5 to GND .... .0.3V to +36V LX3 tO BST3 oie ee erences eeeaicreeaecnee -6V to +0.3V LX5 tO BST5 seen enna eeeeeeeeeascr seein -6V to +0.3V REF, SYNC, SEQ, STEER, SKIP, TIME/ONS, SECFB, RESET to GND 20... eee cece eee eeeeee tee teeeeeees -0.3V to +6V VDD to GND... eee ence enenseeeeeneeeneeeeee -0.3V to +20V RUN/ONS, SHDN to GND... -0.3V to (V+ + 0.3V) 120UT to GND oo. nee reneeeee -0.3V to (VDD + 0.3V) DL3, DLS to PGND... cece eeeneneee -0.3V to (VL + 0.3V) DHS to LX3 we .-0.3V to (BST3 + 0.3V) DH5 to LXS oo iene ene neeereeeeee -0.3V to (BST5 + 0.3V) VL, REF Short to GND .........ccccceecsssessseaeeeeeeeeeeesenseeees Momentary T2OUT Short to GND... eee eee eeeeee tees eeeeeeeeeeeeeeeeeeees Continuous REF Current.....ceeeee w+ 5mA to -imA VL CUIT ON. eee cette tence eeaeeeeeneeeeaneeeeaneeenaeeesaneeeeaneeseneeeenee +50mA 120UT Current .......... .-+200MA VDD Shunt Current,.........ccceccssssssssssessseceeeeceeeeeeeeeeseesssssseeees +15mA Operating Temperature Ranges MAX1 63_CAL.. cece ccee serene neeeeeeeeenseneeeaneas 0C to +70C MAX1 63_EA Lo... nceeeeence ene neeeeee -40C to +85C Storage Temperature Range -65C to + 160C Continuous Power Dissipation (Ta = +70C) SSOP (derate 9.52mW/C above +70C) wo... 762mW Lead Temperature (soldering, 10SC) ....... cee eens +300C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = 15V, both PWMs on, SYNC = VL, VL load = OmA, REF load = OmA, SKIP = OV, Ta = TmIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER | CONDITIONS MIN TYP MAX | UNITS MAIN SMPS CONTROLLERS Input Voltage Range 4.2 30.0 Vv 3V Output Voltage in V+ = 4.2V to 30V, CSH3-CSL3 = OV, Adjustable Mode CSL3 tied to FB3 24g 25 0 288 | 3V Output Voltage in Fixed Mode vee AL to SOV, OmV < CSHS-CSLS < 80mV, 3.20 339 3.47 Vv 5V Output Voltage in V+ = 4.2V to 30V, CSH5-CSL5 = OV, Adjustable Mode CSL5 tied to FB5 2.42 25 2.58 V 5V Output Voltage in Fixed Mode thew to SOV, OmV < CSH-CSLS < 8OmV, 485 513 5.25 Vv Output Voltage Adjust Range Either SMPS REF 5.5 Vv Adjustable-Mode Threshold Voltage Dual Mode comparator 0.5 1.4 Vv Load Regulation Either SMPS, 0V < CSH_-CSL_<< 80mV -2 % Line Regulation Either SMPS, 5.2V < V+ < 30V 0.03 %IV CSH3-CSL3 or CSH5-CSL5 80 100 120 Current-Limit Threshold mV SKIP = VL or Vpp < 13V or SECFB < 2.44V -50 -100 -150 Idle Mode Threshold SKIP = OV, not tested 10 25 40 mV 3 rr Soft-Start Ramp Time From enable to 95% full current limit with respect to 512 clks fosc (Note 1) . SYNC = VL 270 300 330 Oscillator Frequency kHz SYNC = OV 170 200 230 . SYNC = VL 97 98 Maximum Duty Factor % SYNC = OV (Note 2) 98 99 2 MAXUMMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, both PWMs on, SYNC = VL, VL load = OmA, REF load = OmA, SKIP = OV, Ta = TmIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) GEGLXVW-OEILXVWN PARAMETER CONDITIONS MIN TYP MAX | UNITS SYNC Input High Pulse Width Not tested 200 ns SYNC Input Low Pulse Width Not tested 200 ns SYNC Rise/Fall Time Not tested 200 ns SYNC Input Frequency Range 240 350 kHz Current-Sense Input Leakage Current ota oo = CSL5 = CSH5 = 5.5V 0.01 10 pA FLYBACK CONTROLLER Vbpb Regulation Threshold Falling edge (Note 3) 13 14 Vv SECFB Regulation Threshold Falling edge (MAX1631/MAX1634) 2.44 2.60 Vv DL Pulse Width Vpb < 13V or SECFB < 2.44V 1 ys Vbpb Shunt Threshold Rising edge, hysteresis = 1% (Note 3) 18 20 Vv Vpbp Shunt Sink Current Vbb = 20V (Note 3) 10 mA Vpp Leakage Current Vpp = 5V, off mode (Notes 3, 4) 30 pA 12V LINEAR REGULATOR (Note 3) 120UT Output Voltage 13V < VoD < 18V, OmA < ILOAD < 120mA 11.65 12.1 12.50 Vv 120UT Current Limit 120UT forced to 11V, Vpp = 13V 150 mA Quiescent Vpp Current VbbD = 18V, run mode, no 12OUT load 50 100 pA INTERNAL REGULATOR AND REFERENCE VL Output Voltage even SOV. Oma ne som RY 47 54 V Cau Ge Lockout Falling edge, hysteresis = 1% 35 36 37 V VL Switchover Threshold Rising edge of CSL5, hysteresis = 1% 4.2 4.5 4.7 Vv REF Output Voltage No external load (Note 5) 2.45 2.5 2.55 Vv REF Load Regulation OpA < ILOAD < S0HA 12.5 mV OmA < ILOAD < 5mA 100.0 REF Sink Current 10 pA REF Fault Lockout Voltage Falling edge 1.8 2.4 Vv V+ Operating Supply Current VL switched over to CSL5, 5V SMPS on 5 50 pA V+ Standby Supply Current ve a ones off, 30 60 pA V+ Standby Supply Current V+ = 4.2V to 5.5V, both SMPSs off, 50 200 yA in Dropout includes current into SHDN V+ Shutdown Supply Current V+ = 4V to 24V, SHDN = OV 4 10 pA Both SMPSs enabled, FB3 = FBS = ov, |_(Note 3) 2.5 4 Quiescent Power Consumption CSL3 = CSH3 = 3.5V, MAX1631/ mw CSL5 = CSHS5 = 5.3V MAX1634 1.5 4 MAXUM 3MAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, both PWMs on, SYNC = VL, VL load = OmA, REF load = OmA, SKIP = OV, Ta = TmIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER | CONDITIONS MIN TYP MAX | UNITS FAULT DETECTION (MAX1630/MAX1631/MAX1 632) Overvoltage Trip Threshold With respect to unloaded output voltage 4 7 10 % Overvoltage-Fault Propagation Delay | CSL_driven 2% above overvoltage trip threshold 1.5 ys Output Undervoltage Threshold With respect to unloaded output voltage 60 70 80 % Output Undervoltage Lockout Time From each SMPS enabled, with respect to fosc 5000 6144 7000 clks Thermal Shutdown Threshold Typical hysteresis = +10C 150 C RESET FESET Tip Tesol eee ase eee ote0 7 ss 4 | RESET Propagation Delay rang HET tp Trecho oe 1.5 ps RESET Delay Time With respect to fosc 27,000 32,000 37,000) clks INPUTS AND OUTPUTS Feedback Input Leakage Current FB3, FB5; SECFB = 2.6V 1 50 nA . RUN/ONS, SKIP, TIME/ONS5 (SEQ = REF), Logic Input Low Voltage SHDN, STEER, SYNC ( ) 0.6 Vv . . RUN/ONS, SKIP, TIME/ONS5 (SEQ = REF), Logic Input High Voltage SHDN, STEER, SYNC ( ) 2.4 Vv Logic Output Low Voltage RESET, IsiINK = 4mA 0.4 Vv Logic Output High Current RESET = 3.5V 1 mA TIME/ONS Input Trip Level SEQ = OV or VL 2.4 2.6 Vv TIME/ON5 Source Current TIME/ON5 = OV, SEQ = OV or VL 2.5 3 3.5 pA TIME/ON5 On-Resistance TIME/ON5; RUN/ONS = OV, SEQ = OV or VL 15 80 Q Gate Driver Sink/Source Current DL3, DH3, DL5, DH5; forced to 2V 1 A Gate Driver On-Resistance High or low 1.5 7 Q Note 1: Each of the four digital soft-start levels is tested for functionality; the steps are typically in 20mV increments. Note 2: High duty-factor operation supports low input-to-output differential voltages, and is achieved at a lowered operating frequency (see Overload and Dropout Operation section). Note 3: MAX1630/MAX1 632/MAX1 633/MAX1 635 only. Note 4: Off mode for the 12V linear regulator occurs when the SMPS that has flyback feedback (Vpp) steered to it is disabled. In situations where the main outputs are being held up by external keep-alive supplies, turning off the 12OUT regulator pre- vents a leakage path from the output-referred flyback winding, through the rectifier, and into Vpp. Note 5: Since the reference uses VL as its supply, the references V+ line-regulation error is insignificant. 4 MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers (Circuit of Figure 1, 3A Table 1 components, Ta = +25C, unless otherwise noted.) 100 90 80 70 EFFICIENCY (%) 60 50 500 400 300 200 100 MAXIMUM OUTPUT CURRENT (mA) 10,000 1000 INPUT CURRENT (1A) 3 Qa MAXIM 0.001 EFFICIENCY vs. 5V OUTPUT CURRENT V+=6V ON5 = 5V ONS = OV f = 300kHz MAX1631/MAX1634 5V QUTPUT CURRENT (A) MAX1630/MAX1633 MAXIMUM 15V Vpp OUTPUT CURRENT vs. SUPPLY VOLTAGE Vpp > 13V 3.3V REGULATING 1 | 3.3V LOAD = 0A V, lan LOAD = 3A / MAX1630/35-01 0.01 04 1 10 MAX 1630/35-04 SUPPLY VOLTAGE (V) STANDBY INPUT CURRENT vs. INPUT VOLTAGE ONS = OND = OV NO LOAD 0 5 10 15 20 MAX1630/35-07 5 10 15 20 25 30 INPUT VOLTAGE (V) EFFICIENCY (2%) mA) nM 3S INPUT CURRENT (' INPUT CURRENT (1A) 100 90 80 70 60 50 wo S nN on on Qa 0.001 EFFICIENCY vs. 3.3V OUTPUT CURRENT V+=6V ON3 = ONS = 5V f=300kHz | II MAX1631/MAX1 0.01 0.1 1 3,3V OUTPUT CURRENT (A) PWM MODE INPUT CURRENT vs. INPUT VOLTAGE MAX1630/35-02 } } ONS = ONS = BV SKIP = VL MAX1630/35-05 NO LOAD / [ 0 5 10 15 20 25 INPUT VOLTAGE (V) SHUTDOWN INPUT CURRENT vs. INPUT VOLTAGE 30 I SHDN =0V MAX1630/35-08 7 0 5 10 15 20 25 INPUT VOLTAGE (V) 30 MAXIMUM OUTPUT CURRENT (mA) INPUT CURRENT (mA) MIN ViyT0 Vour DIFFERENTIAL (mV) 800 600 400 200 2 1000 100 1 MAX1632/MAX1635 MAXIMUM 15V Vpp OUTPUT CURRENT vs. SUPPLY VOLTAGE Typical Operating Characteristics T Vpp > 13V 5V REGULATING | MAX 1630/35-03 | 5VLOAD = 0A \ J 4 SV LOAD =3A 0.001 0 5 10 15 SUPPLY VOLTAGE (V) IDLE MODE INPUT CURRENT vs. INPUT VOLTAGE ONS = ONS = 5V SKIP =0V NO LOAD 0 5 10 15 20 25 INPUT VOLTAGE (V) 20 MAX1630/35-08 30 MINIMUM Vix TO Vout DIFFERENTIAL vs. 5V OUTPUT CURRENT 5V, 3A CIRCUIT Vout > 4.8V f =300kHz 0.01 0.1 1 5V OUTPUT CURRENT (A) MAX1630/35-09 GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Typical Operating Characteristics (continued) (Circuit of Figure 1, 3A Table 1 components, Ta = +25C, unless otherwise noted.) SWITCHING FREQUENCY VL REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT vs. OUTPUT CURRENT 1000 2 5,00 = = 4.98 SI = 100 = 3 +5V, Vin=15V W IN i 496 -~ oS to 39v, Vw =15V = lm go oa = 5 4.94 = | 3.3V, Vin =6V = @ eH 492 , Vin=6V Vin= 15V ONS = ON5 = 0V o4 4.90 04 1 10 100 1000 0 10 2 30 40 50 60 LOAD CURRENT (mA) OUTPUT CURRENT (mA) REF OUTPUT VOLTAGE vs. OUTPUT CURRENT START-UP WAVEFORMS 2.510 2 2 2.505 g RUN g S 5Vidiv @ 2500 f = * 3.3V OUTPUT : g aVvidiv 2.495 & [amen TIME 3 2.490 5Vidiv aa] 0 a 5V OUTPUT : ? 2.485 | Vy=15V BVIGIV ee eee ON = ONS = OV 2.480 L__ 0 1 2 3 4 5 8 2ms/div OUTPUT CURRENT (mA) SEQ = VL, 0.015F CAPACITOR ON-TIME Pin Description PIN NAME FUNCTION 1 CSH3 Current-Sense Input for the 3.3V SMPS. Current-limit level is 100mV referred to CSL3. 2 CSL3 Current-Sense Input. Also serves as the feedback input in fixed-output mode. Feedback Input for the 3.3V SMPS; regulates at FB3 = REF (approx. 2.5V) in adjustable mode. FB3 is a 3 FB3 Dual Mode input that also selects the 3.3V fixed output voltage setting when tied to GND. Connect FB3 to a resistor divider for adjustable-output mode. 120UT . . (MAX1630/ 12V/1 20mA Linear Regulator Output. Input supply comes from Vpp. Bypass 12OUT to GND with 32/33/35) 1pF minimum. 4 Logic-Control Input for secondary feedback. Selects the PWM that uses a transformer and secondary STEER . (MAX1631/ feedback signal (SECFB): MAX1634) STEER = GND: 3.3V SMPS uses transformer STEER = VL: 5V SMPS uses transformer MAXIMMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers Pin Description (continued) PIN NAME FUNCTION VoD Supply Voltage Input for the 12OUT Linear Regulator. Also connects to an internal resistor divider for (MAX1630/ secondary winding feedback, and to an 18V overvoltage shunt regulator clamp 32/33/35) , . 5 SECFB Secondary Winding Feedback Input. Normally connected to a resistor divider from an auxiliary output. (MAX1631/ SECFB regulates at VSECFB = 2.5V (see Secondary Feedback Regulation Loop section). Tie to VL if not MAX1634) used. 6 SYNC Oscillator Synchronization and Frequency Select. Tie to VL for 300kHz operation; tie to GND for 200kHz operation. Can be driven at 240kHz to 350kHz for external synchronization. 7 TIME/ONS Dual-Purpose Timing Capacitor Pin and ON/OFF Control Input. See Power-Up Sequencing and ON/OFF Controls section. 8 GND Low-Noise Analog Ground and Feedback Reference Point 9 REF 2.5V Reference Voltage Output. Bypass to GND with 1pF minimum. 10 KIP Logic-Control Input that disables Idle Mode when high. Connect to GND for normal use. 14 RESET Active-Low Timed Reset Output. RESET swings GND to VL. Goes high after a fixed 32,000 clock-cycle delay following power-up. Feedback Input for the 5V SMPS; regulates at FB5 = REF (approx. 2.5V) in adjustable mode. FB5 is a 12 FB5 Dual Mode input that also selects the 5V fixed output voltage setting when tied to GND. Connect FBS to a resistor divider for adjustable-output mode. 13 CSL5 Current-Sense Input for the 5V SMPS. Also serves as the feedback input in fixed-output mode, and as the bootstrap supply input when the voltage on CSL5/VL is > 4.5V. 14 CSH5 Current-Sense Input for the 5V SMPS. Current-limit level is 100mV referred to CSL5. Pin-Strap Input that selects the SMPS power-up sequence: 15 SEQ SEQ = GND: 5V before 3.3V, RESET output determined by both outputs SEQ = REF: Separate ON3/ON5 controls, RESET output determined by 3.3V output SEQ = VL: 3.3V before 5V, RESET output determined by both outputs 16 DH5 Gate-Drive Output for the 5V, high-side N-channel switch. DHS is a floating driver output that swings from LX5 to BST5, riding on the LX5 switching node voltage. 17 LX5 Switching Node (inductor) Connection. Can swing 2V below ground without hazard. 18 BST5 Boost capacitor connection for high-side gate drive (0.1p1F) 19 DL5 Gate-Drive Output for the low-side synchronous-rectifier MOSFET. Swings OV to VL. 20 PGND Power Ground 5V Internal Linear-Regulator Output. VL is also the supply voltage rail for the chip. After the 5V SMPS 21 VL output has reached +4.5V (typical), VL automatically switches to the output voltage via CSL5 for boot- strapping. Bypass to GND with 4.7pF. VL supplies up to 25mA for external loads. Battery Voltage Input, +4.2V to +30V. Bypass V+ to PGND close to the IC with a 0.22uF capacitor. 22 V+ . Connects to a linear regulator that powers VL. 23 SHDN Shutdown Control Input, active low. Logic threshold is set at approximately 1V. For automatic start-up, connect SHDN to V+ through a 220kQ resistor and bypass SHDN to GND with a 0.01pF capacitor. 24 DL3 Gate-Drive Output for the low-side synchronous-rectifier MOSFET. Swings OV to VL. 25 BST3 Boost Capacitor Connection for high-side gate drive (0.1 pF) 26 LX3 Switching Node (inductor) Connection. Can swing 2V below ground without hazard. 27 DH3 Gate-Drive Output for the 3.3V, high-side N-channel switch. DH3 is a floating driver output that swings from LX3 to BST, riding on the LX8 switching node voltage. 28 RUN/ON3 ON/OFF Control Input. See Power-Up Sequencing and ON/OFF Controls section. MAXUM GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers INPUT ON OFF +5V ALWAYS ON + 4.7uF 0.1 uF T V+ SHDN SECFB VL SYNC BSTS BsT3 DHS DH3 te @ 0.1 uF 0.1pF +5V OUTPUT LX5 LX3 La Re +3.3V OUTPUT MAXIMA MAX1631 DLS MAX1634 DL3 PGND CSH5 CSH3 CSL CSL3 FB TC | RESET OUTPUT = ESE _-_-___ 5V ON/OFF TIMBON5 | __ SKIP 3.3V ON/OFF RUN/ONS STEER Ile = REF SEQ | +2.5V ALWAYS ON + I 1pF 1A SCHOTTKY DIODE REQUIRED FOR THE MAX1631 (SEE OUTPUT OVERVOLTAGE PROTECTION SECTION). Figure 1. Standard 3.3V/5V Application Circuit (MAX1631/MAX1634) Standard Application Circuit of these circuits without first recalculating component : values (particularly inductance value at maximum bat- The basic MAX1631/MAX1634 dual-output 3.3V/5V tery voltage). Adding a Schottky rectifier across each buck converter (Figure 1) is easily adapted to meet a wide range of applications with inputs up to 28V by synchronous rectifier improves the efficiency of these bstitut is f Table 1. Th ircuit circuits by approximately 1%, but this rectifier is other- substituting components irom rable f. inese Cmculls wise not needed because the MOSFETs required for represent a good set of tradeoffs between cost, size, and efficiency, while staying within the worst-case these circuits typically incorporate a high-speed silicon we diode from drain to source. Use a Schottky rectifier specification limits for stress-related parameters, such : : , rated at a DC current equal to at least one-third of the as capacitor ripple current. Dont change the frequency load current 8 MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers Table 1. Component Selection for Standard 3.3V/5V Application LOAD CURRENT COMPONENT 2A 3A 4A Input Range 4.75V to 18V 4.75V to 28V 4.75V to 24V Application PDA Notebook Workstation Frequency 300kHz 300kHz 200kHz 1/2 IR IRF7301; IR IRF7403 or IRF7401 (18V IR IRF7413 or Q1, Q3 High-Side MOSFETs 1/2 Siliconix Si9925DQ; or 1/2 Motorola MMDF3NO3HD or MMDF4NO1HD (10V max) max); Siliconix Si4412DY; or Motorola MMSF5NO3HD or MMSF5NO2HD (18V max) Siliconix Si4410DY Q2, Q4 Low-Side MOSFETs 1/2 IR IRF7301; 1/2 Siliconix Si9925DQ; or 1/2 Motorola MMDF3NO3HD or MMDF4NO01HD (10V max) IR IRF7403 or IRF7401 (18V max); Siliconix Si4412DY; or Motorola MMSF5NO3HD or MMSF5NO2HD (18V max) IR IRF7413 or Siliconix Si4410DY C3 Input Capacitor 10pF, 30V Sanyo OS-CON; 22uF, 35V AVX TPS; or 2 x 10pF, 30V Sanyo OS-CON; 2 x 22uF, 35V AVX TPS; or 3 x 10pF, 30V Sanyo OS-CON; 4 x 22uF, 35V AVX TPS; or Sprague 594D Sprague 594D Sprague 595D . 220uF, 10V AVX TPS or 2 x 220uF, 10V AVX TPS or 4 x 220pF, 10V AVX TPS or C1, C2 Output Capacitors Sprague 595D Sprague 595D Sprague 595D R1, R2 Resistors 0.033Q IRC LR2010-01-R033 or Dale WSL2010-R033-F 0.02Q IRC LR2010-01-R020 or Dale WSL2010-R020-F 0.012 Dale WSL2512-R012-F L1, L2 Inductors 15pH, 2.4A Ferrite Coilcraft DO3316P-153 or Sumida CDRH125-150 1OpH, 4A Ferrite Coilcraft DO3316P-103 or Sumida CDRH125-100 4.7pH, 5.5A Ferrite Coilcraft DO3316-472 or 5.2uH, 6.5A Ferrite Sumida CDRH127-5R2MC Table 2. Component Suppliers FACTORY FAX FACTORY FAX COMPANY | (couUNTRY CODE) USA PHONE COMPANY | (couUNTRY CODE) USA PHONE AVX (1) 803-626-3123 | (803) 946-0690 Motorola (1) 602-994-6430 | (602) 303-5454 Central Murata-Erie (1) 814-238-0490 | (814) 237-1431 (1) 516-435-1824 | (516) 435-1110 Semiconductor NIEC (81) 3-3494-7414 (805) 867-2555* Coilcraft (1) 847-639-1469 | (847) 639-6400 Sanyo (81) 7-2070-1174 | (619) 661-6835 Coiltronics (1) 561-241-9339 | (561) 241-7876 Siliconix (1) 408-970-3950 | (408) 988-8000 Dale (1) 605-665-1627 | (605) 668-4131 Sprague (1) 603-224-1430 | (603) 224-1961 Sumid 81) 3-3607-5144 847) 956-0666 International (1) 310-322-3332 | (310) 322-3331 ume 67) (84?) Rectifier (IR) TDK (1) 847-390-4428 (847) 390-4373 IRC 1) 512-992-3377 512) 992-7900 ) (912) Transpower (1) 702-831-3521 (702) 831-0140 Matsuo (1) 714-960-6492 | (714) 969-2491 Technologies * Distributor MAXUM GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAMXKIAN MAX1632 ON/OFF 5V LINEAR REG +5V ALWAYS ON RAW +15V T JUL 3.3V PWM LOGIC 200kHz TO 300kHz OSC +5V +3.3V IK At R38 OUTPUTS UP TIME/ONS POWER-ON SEQUENCE LOGIC SEQ RUN/ON3 Figure 2. MAX1632 Block Diagram 10 MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers Detailed Description The MAX1630 is a dual, BICMOS, switch-mode power- supply controller designed primarily for buck-topology regulators in battery-powered applications where high effi- ciency and low quiescent supply current are critical. Light- load efficiency is enhanced by automatic Idle Mode operation, a variable-frequency pulse-skipping mode that reduces transition and gate-charge losses. Each step- down, power-switching circuit consists of two N-channel MOSFETs, a rectifier, and an LC output filter. The output voltage is the average AC voltage at the switching node, which is regulated by changing the duty cycle of the MOSFET switches. The gate-drive signal to the N-channel high-side MOSFET must exceed the battery voltage, and is provided by a flying-capacitor boost circuit that uses a 100nF capacitor connected to BST_. Devices in the MAX1630 family contain ten major circuit blocks (Figure 2). The two pulse-width modulation (PWM) controllers each consist of a Dual Mode feedback network and multi- plexer, a multi-input PWM comparator, high-side and low-side gate drivers, and logic. MAX1630/MAX1631/ MAX1632 contain fault-protection circuits that monitor the main PWM outputs for undervoltage and overvolt- age. A power-on sequence block controls the power- up timing of the main PWMs and determines whether one or both of the outputs are monitored for undervolt- age faults. The MAX1630/MAX1632/MAX1633/ MAX1635 include a secondary feedback network and 12V linear regulator to generate a 12V output from a coupled-inductor flyback winding. The MAX1631/ MAX1634 have a secondary feedback input (SECFB) instead, which allows a quasi-regulated, adjustable- output, coupled-inductor flyback winding to be attached to either the 3.3V or the 5V main inductor. Bias genera- tor blocks include the 5V IC internal rail (VL) linear regu- lator, 2.5V precision reference, and automatic bootstrap switchover circuit. The PWMs share a common 200kHz/300kHz synchronizable oscillator. These internal IC blocks aren't powered directly from the battery. Instead, the 5V VL linear regulator steps down the battery voltage to supply both VL and the gate drivers. The synchronous-switch gate drivers are directly powered from VL, while the high-side switch gate drivers are indirectly powered from VL via an external diode-capacitor boost circuit. An automatic bootstrap circuit turns off the +5V linear regulator and powers the IC from the 5V PWM output voltage if the output is above 4.5V. PWM Controller Block The two PWM controllers are nearly identical. The only differences are fixed output settings (3.3V vs. 5V), the VL/CSL5 bootstrap switch connected to the +5V PWM, and SECFB. The heart of each current-mode PWM con- troller is a multi-input, open-loop comparator that sums three signals: the output voltage error signal with respect to the reference voltage, the current-sense sig- nal, and the slope compensation ramp (Figure 3). The PWM controller is a direct-summing type, lacking a tra- ditional error amplifier and the phase shift associated with it. This direct-summing configuration approaches ideal cycle-by-cycle control over the output voltage. When SKIP = low, Idle Mode circuitry automatically optimizes efficiency throughout the load current range. Idle Mode dramatically improves light-load efficiency by reducing the effective frequency, which reduces switching losses. It keeps the peak inductor current above 25% of the full current limit in an active cycle, allowing subsequent cycles to be skipped. Idle Mode transitions seamlessly to fixed-frequency PWM opera- tion as load current increases. With SKIP = high, the controller always operates in fixed-frequency PWM mode for lowest noise. Each pulse from the oscillator sets the main PWM latch that turns on the high-side switch for a period determined by the duty factor (approximately VoUT/VIN). As the high-side switch turns off, the synchronous rectifier latch sets; 6Ons later, the low-side switch turns on. The low-side switch stays on until the beginning of the next clock cycle. Table 3. SKIP PWM Table Srip LOAD SKIP CURRENT MODE DESCRIPTION Pulse-skipping, supply cur- Low Light Idle | Tent= 250pA at VIN = 12V, discontinuous inductor current Constant-frequency PWM, Low Heavy PWM continuous inductor current Constant-frequency PWM, High Light PWM continuous inductor current Constant-frequency PWM, High Heavy PWM continuous inductor current 11 MAXUM GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAIN PWM COMPARATOR ps P+tl rit MMA SLOPE COMP CK COUNTER SOFT-START SYNCHRONOUS RECTIFIER CONTROL wW R . ips SINGLE-SHOT CSH_ CSL_ FROM FEEDBACK DIVIDER BST_ LX_ VL PGND Figure 3. PWM Controller Detailed Block Diagram 12 MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers In PWM mode, the controller operates as a fixed- frequency current-mode controller where the duty ratio is set by the input/output voltage ratio. The current- mode feedback system regulates the peak inductor current value as a function of the output-voltage error signal. In continuous-conduction mode, the average inductor current is nearly the same as the peak current, so the circuit acts as a switch-mode transconductance amplifier. This pushes the second output LC filter pole, normally found in a duty-factor-controlled (voltage- mode) PWM, to a higher frequency. To preserve inner- loop stability and eliminate regenerative inductor current staircasing, a slope compensation ramp is summed into the main PWM comparator to make the apparent duty factor less than 50%. The MAX1630 family uses a relatively low loop gain, allowing the use of lower-cost output capacitors. The relative gains of the voltage-sense and current-sense inputs are weighted by the values of current sources that bias three differential input stages in the main PWM comparator (Figure 4). The relative gain of the voltage comparator to the current comparator is internally fixed at K = 2:1. The low loop gain results in the 2% typical load-regulation error. The low value of loop gain helps reduce output filter capacitor size and cost by shifting the unity-gain crossover frequency to a lower level. The output filter capacitors (Figure 1, C1 and C2) seta dominant pole in the feedback loop that must roll off the loop gain to unity before encountering the zero intro- duced by the output capacitors parasitic resistance (ESR) (see Design Procedure section). A 60kKHz pole- zero cancellation filter provides additional rolloff above the unity-gain crossover. This internal 60kKHz lowpass compensation filter cancels the zero due to filter capaci- tor ESR. The 60kHz filter is included in the loop in both fixed-output and adjustable-output modes. Synchronous Rectifier Driver (DL) Synchronous rectification reduces conduction losses in the rectifier by shunting the normal Schottky catch diode with a low-resistance MOSFET switch. Also, the synchro- nous rectifier ensures proper start-up of the boost gate- driver circuit. If the synchronous power MOSFETs are omitted for cost or other reasons, replace them with a small-signal MOSFET, such as a 2N7002. If the circuit is operating in continuous-conduction mode, the DL drive waveform is simply the complement of the DH high-side drive waveform (with controlled dead time to prevent cross-conduction or shoot- through). In discontinuous (light-load) mode, the syn- chronous switch is turned off as the inductor current falls through zero. The synchronous rectifier works FB_ REF CSH_ CSL_ LO SLOPE COMPENSATION TO PWM LOGIC. 2 + UNCOMPENSATED HIGH-SPEED LEVEL TRANSLATOR AND BUFFER = OUTPUT DRIVER VBias Figure 4. Main PWM Comparator Block Diagram 13 MAXUM GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers under all operating conditions, including Idle Mode. The SECFB signal further controls the synchronous switch timing in order to improve multiple-output cross- regulation (see Secondary Feedback Regulation Loop section). Internal VL and REF Supplies An internal regulator produces the +5V supply (VL) that powers the PWM controller, logic, reference, and other blocks within the IC. This 5V low-dropout linear regula- tor supplies up to 25mA for external loads, with a reserve of 25mA for supplying gate-drive power. Bypass VL to GND with 4.7pF. Important: Ensure that VL does not exceed 6V. Measure VL with the main output fully loaded. If it is pumped above 5.5V, either excessive boost diode capacitance or excessive ripple at V+ is the probable cause. Use only small-signal diodes for the boost cir- cuit (10mA to 100mA Schottky or 1N4148 are pre- ferred), and bypass V+ to PGND with 4.7pF directly at the package pins. The 2.5V reference (REF) is accurate to +2% over tem- perature, making REF useful as a precision system ref- erence. Bypass REF to GND with 1pF minimum. REF can supply up to 5mA for external loads. (Bypass REF with a minimum 1pF/mA reference load current.) However, if extremely accurate specifications for both the main output voltages and REF are essential, avoid loading REF more than 100HA. Loading REF reduces the main output voltage slightly, because of the refer- ence load-regulation error. When the 5V main output voltage is above 4.5V, an internal P-channel MOSFET switch connects CSL5 to VL, while simultaneously shutting down the VL linear regulator. This action bootstraps the IC, powering the internal circuitry from the output voltage, rather than through a linear regulator from the battery. Bootstrapping reduces power dissipation due to gate charge and quiescent losses by providing that power from a 90%-efficient switch-mode source, rather than from a much less efficient linear regulator. Boost High-Side Gate-Drive Supply (BST3 and BST5) Gate-drive voltage for the high-side N-channel switches is generated by a flying-capacitor boost circuit (Figure 2). The capacitor between BST_ and LX_ is alternately charged from the VL supply and placed par- allel to the high-side MOSFETs gate-source terminals. On start-up, the synchronous rectifier (low-side MOSFET) forces LX_ to OV and charges the boost capacitors to 5V. On the second half-cycle, the SMPS 14 turns on the high-side MOSFET by closing an internal switch between BST_ and DH_. This provides the nec- essary enhancement voltage to turn on the high-side switch, an action that boosts the 5V gate-drive signal above the battery voltage. Ringing at the high-side MOSFET gate (DH3 and DH5) in discontinuous-conduction mode (light loads) is a nat- ural operating condition. It is caused by residual ener- gy in the tank circuit, formed by the inductor and stray capacitance at the switching node, LX. The gate-drive negative rail is referred to LX, so any ringing there is directly coupled to the gate-drive output. Current-Limiting and Current-Sense Inputs (CSH and CSL) The current-limit circuit resets the main PWM latch and turns off the high-side MOSFET switch whenever the voltage difference between CSH and CSL exceeds 100mV. This limiting is effective for both current flow directions, putting the threshold limit at +100mV. The tolerance on the positive current limit is +20%, so the external low-value sense resistor (R1) must be sized for 80mV/IPEAK, where IPEAK is the required peak inductor current to support the full load current, while compo- nents must be designed to withstand continuous cur- rent stresses of 120mV/R1. For breadboarding or for very-high-current applications, it may be useful to wire the current-sense inputs with a twisted pair, rather than PC traces. (This twisted pair needn't be anything special; two pieces of wire-wrap wire twisted together are sufficient.) This reduces the possible noise picked up at CSH_ and CSL_, which can cause unstable switching and reduced output current. The CSL5 input also serves as the ICs bootstrap sup- ply input. Whenever Vcs_s > 4.5V, an internal switch connects CSL5 to VL. Oscillator Frequency and Synchronization (SYNC) The SYNC input controls the oscillator frequency. Low selects 200kHz; high selects 300KHz. SYNC can also be used to synchronize with an external 5V CMOS or TTL clock generator. SYNC has a guaranteed 240kHz to 350kHz capture range. A high-to-low transition on SYNC initiates a new cycle. 300kHz operation optimizes the application circuit for component size and cost. 200kHz operation provides increased efficiency, lower dropout, and improved load-transient response at low input-output voltage dif- ferences (see Low-Voltage Operation section). MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers Shutdown Mode Holding SHDN low puts the IC into its 4uUA shutdown mode. SHDN is logic input with a threshold of about 1V (the VTH of an internal N-channel MOSFET). For auto- matic start-up, bypass SHDN to GND with a 0.01pF capacitor and connect it to V+ through a 220kQ resistor. Power-Up Sequencing and ON/OFF Controls Start-up is controlled by RUN/ON3 and TIME/ONS5 in conjunction with SEQ. With SEQ tied to REF, the two control inputs act as separate ON/OFF controls for each supply. With SEQ tied to VL or GND, RUN/ON3 becomes the master ON/OFF control input and TIME/ON5 becomes a timing pin, with the delay between the two supplies determined by an external capacitor. The delay is approximately 800us/nF. The +3.3V supply powers-up first if SEQ is tied to VL, and the +5V supply is first if SEQ is tied to GND. When driv- ing TIME/ONS as a control input with external logic, always place a resistor (>1kQ) in series with the input. This prevents possible crowbar current due to the inter- nal discharge pull-down transistor, which turns on in standby mode and momentarily at the first power-up or in shutdown mode. RESET Power-Good Voltage Monitor The power-good monitor generates a system RESET sig- nal. At first power-up, RESET is held low until both the 3.3V and 5V SMPS outputs are in regulation. At this point, an internal timer begins counting oscillator pulses, and RESET continues to be held low until 32,000 cycles have elapsed. After this timeout period (107ms at 300kHz or 160ms at 200kHz), RESET is actively pulled up to VL. If SEQ is tied to REF (for separate ON3/ON5 controls), only the 3.3V SMPS is monitoredthe 5V SMPS is ignored. Table 4. Operating Modes Output Undervoltage Shutdown Protection (MAX 1630/MAX1631/MAX 1632) The output undervoltage lockout circuit is similar to foldback current limiting, but employs a timer rather than a variable current limit. Each SMPS has an under- voltage protection circuit that is activated 6144 clock cycles after the SMPS is enabled. If either SMPS output is under 70% of the nominal value, both SMPSs are latched off and their outputs are clamped to ground by the synchronous rectifier MOSFETs (see Output Overvoltage Protection section). They won't restart until SHDN or RUN/ONS is toggled, or until V+ power is cycled below 1V. Note that undervoltage protection can make prototype troubleshooting difficult, since you have only 20ms or 30ms to figure out what might be wrong with the circuit before both SMPSs are latched off. In extreme cases, it may be useful to substitute the MAX1633/MAX1634/MAX1635 into the prototype breadboard until the prototype is working properly. Output Overvoltage Protection (MAX 1630/MAX1631/MAX 1632) Both SMPS outputs are monitored for overvoltage. If either output is more than 7% above the nominal regu- lation point, both low-side gate drivers (DL_) are latched high until SHDN or RUN/ONS is toggled, or until V+ power is cycled below 1V. This action turns on the synchronous rectifiers with 100% duty, in turn rapidly discharging the output capacitors and forcing both SMPS outputs to ground. The DL outputs are also kept high whenever the corresponding SMPS is disabled, and in shutdown if VL is sustained. SHDN SEQ RUN/ON3 TIME/ON5 MODE DESCRIPTION Low x x x Shutdown All circuit blocks turned off. Supply current = 4p/A. High Ref Low Low Standby Both SMPSs off. Supply current = 30p/A. High Ref High Low Run 3.3V SMPS enabled/5V off High Ref Low High Run 5V SMPS enabled/3.3V off High Ref High High Run Both SMPSs enabled High GND Low Timing capacitor Standby Both SMPSs off. Supply current = 30p/A. High GND High Timing capacitor Run Both SMPSs enabled. 5V enabled before 3.3V. High VL Low Timing capacitor Standby Both SMPSs off. Supply current = 30p/A. High VL High Timing capacitor Run Both SMPSs enabled. 3.3V enabled before 5V. X = Dont Care 15 MAXUM GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Discharging the output capacitor through the main inductor causes the output to momentarily go below GND. Clamp this negative pulse with a back-biased 1A Schottky diode across the output capacitor (Figure 1). To ensure overvoltage protection on initial power-up, connect signal diodes from both output voltages to VL (cathodes to VL) to eliminate the VL power-up delay. This circuitry protects the load from accidental overvolt- age caused by a short-circuit across the high-side power MOSFETs. This scheme relies on the presence of a fuse, in series with the battery, which is blown by the resulting crowbar current. Note that the overvoltage circuitry will interfere with external keep-alive supplies that hold up the outputs (such as lithium backup or hot- swap power supplies); in such cases, the MAX1633, MAX1634, or MAX1635 should be used. Low -Noise Operation (PWM Mode) PWM mode (SKIP = high) minimizes RF and audio interference in noise-sensitive applications (such as hi- fi multimedia-equipped systems), cellular phones, RF communicating computers, and electromagnetic pen- entry systems. See the summary of operating modes in Table 2. SKIP can be driven from an external logic signal. Interference due to switching noise is reduced in PWM mode by ensuring a constant switching frequency, thus concentrating the emissions at a known frequency out- side the system audio or IF bands. Choose an oscillator frequency for which switching frequency harmonics don't overlap a sensitive frequency band. If necessary, synchronize the oscillator to a tight-tolerance external clock generator. To extend the output-voltage-regula- tion range, constant operating frequency is not main- tained under overload or dropout conditions (see Overload and Dropout Operation section.) PWM mode (SKIP = high) forces two changes upon the PWM controllers. First, it disables the minimum-current comparator, ensuring fixed-frequency operation. Second, it changes the detection threshold for reverse- current limit from OmvV to -100mV, allowing the inductor current to reverse at light loads. This results in fixed- frequency operation and continuous inductor-current flow. This eliminates discontinuous-mode inductor ring- ing and improves cross regulation of transformer- coupled multiple-output supplies, particularly in circuits that dont use additional secondary regulation via SECFB or VpD. In most applications, tie SKIP to GND to minimize qui- escent supply current. VL supply current with SKIP high is typically 20mA, depending on external MOSFET gate capacitance and switching losses. 16 Internal Digital Soft-Start Circuit Soft-start allows a gradual increase of the internal cur- rent-limit level at start-up to reduce input surge currents. Both SMPSs contain internal digital soft-start circuits, each controlled by a counter, a digital-to-analog con- verter (DAC), and a current-limit comparator. In shut- down or standby mode, the soft-start counter is reset to zero. When an SMPS is enabled, its counter starts counting oscillator pulses, and the DAC begins incre- menting the comparison voltage applied to the current- limit comparator. The DAC output increases from OmvV to 100mvV in five equal steps as the count increases to 512 clocks. As a result, the main output capacitor charges up relatively slowly. The exact time of the output rise depends on output capacitance and load current, and is typically 1ms with a 300kHz oscillator. Dropout Operation Dropout (low input-output differential operation) is enhanced by stretching the clock pulse width to increase the maximum duty factor. The algorithm fol- lows: If the output voltage (VouUT) drops out of regula- tion without the current limit having been reached, the SMPS skips an off-time period (extending the on-time). At the end of the cycle, if the output is still out of regula- tion, the SMPS skips another off-time period. This action can continue until three off-time periods are skipped, effectively dividing the clock frequency by as much as four. The typical PWM minimum off-time is 300ns, regardless of the operating frequency. Lowering the operating fre- quency raises the maximum duty factor above 98%. Adjustable-Output Feedback (Dual Mode FB) Fixed, preset output voltages are selected when FB_ is connected to ground. Adjusting the main output volt- age with external resistors is simple for any of the MAX1630 family ICs, through resistor dividers connect- ed to FB3 and FB5 (Figure 2). Calculate the output volt- age with the following formula: Vout = VREF (1 + R1 / R2) where VREF = 2.5V nominal. The nominal output should be set approximately 1% or 2% high to make up for the MAX1630s -2% typical load-regulation error. For example, if designing for a 3.0V output, use a resistor ratio that results in a nominal output voltage of 3.05V. This slight offsetting gives the best possible accuracy. Recommended normal values for R2 range from 5kQ to 100kQ. To achieve a 2.5V nominal output, simply connect FB_ directly to CSL_. MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers Remote output-voltage sensing, while not possible in fixed-output mode due to the combined nature of the voltage-sense and current-sense inputs (CSL3 and CSL5), is easy to do in adjustable mode by using the top of the external resistor divider as the remote sense point. When using adjustable mode, it is a good idea to always set the 3.3V output to a lower voltage than the SV output. The 3.3V outout must always be less than VL, so that the voltage on CSH3 and CSL3 is within the common-mode range of the current-sense inputs. While VL is nominally 5V, it can be as low as 4.7V when lin- early regulating, and as low as 4.2V when automatically bootstrapped to CSH5. Secondary Feedback Regulation Loop (SECFB or Vpp) A flyback-winding control loop regulates a secondary winding output, improving cross-regulation when the primary output is lightly loaded or when there is a low input-output differential voltage. If VDp or SECFB falls below its regulation threshold, the low-side switch is turned on for an extra ips. This reverses the inductor (primary) current, pulling current from the output filter capacitor and causing the flyback transformer to oper- ate in forward mode. The low impedance presented by the transformer secondary in forward mode dumps cur- rent into the secondary output, charging up the sec- ondary capacitor and bringing Vpp or SECFB back into regulation. The secondary feedback loop does not improve secondary output accuracy in normal flyback mode, where the main (primary) output is heavily loaded. In this condition, secondary output accuracy is determined by the secondary rectifier drop, transformer turns ratio, and accuracy of the main output voltage. A linear post-regulator may still be needed to meet strict output-accuracy specifications. Devices with a 12OUT linear regulator have a Vpp pin that regulates at a fixed 13.5V, set by an internal resis- tor divider. The MAX1631/MAX1634 have an adjustable secondary output voltage set by an external resistor divider on SECFB (Figure 5). Ordinarily, the secondary regulation point is set 5% to 10% below the voltage nor- mally produced by the flyback effect. For example, if the output voltage as determined by turns ratio is 15V, set the feedback resistor ratio to produce 13.5V. Otherwise, the SECFB one-shot might be triggered unintentionally, unnecessarily increasing supply current and output noise. SECFB 4-SHOT tb | 7A POSITIVE 2.5V REE SECONDARY OUTPUT DH. MAAN MAIN MAX1637 OUTPUT MAX1634 DL +Vrap= Var (1+ +) WHERE Veer (NOMINAL) = 2.5V Figure 5. Adjusting the Secondary Output Voltage with SECFB +12V OUTPUT 120UT 200mA 10uF Vpp . MAAXIM MAX1630 Ve MAX1632 MAX1633 MAX1635. DH_ | 0.1uF Vpp OUTPUT 2.2uF MAIN OUTPUT oH Figure 6. Increased 12V Linear Regulator Output Current 12V Linear Regulator Output (MAX 1630/MAX 1632/MAX 1633/MAX 1635) The MAX1630/MAX1632/MAX1633/MAX1635 include a 12V linear regulator output capable of delivering 120mA of output current. Typically, greater current is available at the expense of output accuracy. If an accurate output of more than 120mA is needed, an external pass tran- 17 MAXUM GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers sistor can be added. Figure 6s circuit delivers more than 200mA. Total output current is constrained by the V+ input voltage and the transformer primary load (see Maximum 15V Vpp Output Current vs. Supply Voltage graphs in the Typical Operating Characteristics). Design Procedure The three predesigned 3V/5V standard application cir- cuits (Figure 1 and Table 1) contain ready-to-use solu- tions for common application needs. Also, two standard flyback transformer circuits support the 12OUT linear regulator in the Applications Information section. Use the following design procedure to optimize these basic schematics for different voltage or current require- ments. But before beginning a design, firmly establish the following: Maximum input (battery) voltage, VIN(MAX). This value should include the worst-case conditions, such as no-load operation when a battery charger or AC adapter is connected but no battery is installed. VIN(MAX) must not exceed 30V. Minimum input (battery) voltage, VIN(MIN). This should be taken at full load under the lowest battery conditions. If VIN(MIN) is less than 4.2V, use an external circuit to externally hold VL above the VL undervoltage lockout threshold. If the minimum input-output differ- ence is less than 1.5V, the filter capacitance required to maintain good AC load regulation increases (see Low- Voltage Operation section). Inductor Value The exact inductor value isn't critical and can be freely adjusted to make trade-offs between size, cost, and efficiency. Lower inductor values minimize size and cost, but reduce efficiency due to higher peak-current levels. The smallest inductor is achieved by lowering the inductance until the circuit operates at the border between continuous and discontinuous mode. Further reducing the inductor value below this crossover point results in discontinuous-conduction operation even at full load. This helps lower output filter capacitance requirements, but efficiency suffers due to high |@R losses. On the other hand, higher inductor values mean greater efficiency, but resistive losses due to extra wire turns will eventually exceed the benefit gained from lower peak-current levels. Also, high inductor values can affect load-transient response (see the VsaG equa- tion in the Low-Voltage Operation section). The equa- tions that follow are for continuous-conduction operation, since the MAX1630 family is intended mainly 18 for high-efficiency, battery-powered applications. See Appendix A in Maxims Battery Management and DC- DC Converter Circuit Collection for crossover-point and discontinuous-mode equations. Discontinuous conduc- tion doesnt affect normal Idle Mode operation. Three key inductor parameters must be specified: inductance value (L), peak current (IPEAK), and DC resistance (Rpc). The following equation includes a constant, LIR, which is the ratio of inductor peak-to- peak AC current to DC load current. A higher LIR value allows smaller inductance, but results in higher losses and higher ripple. A good compromise between size and losses is found at a 30% ripple-current to load- current ratio (LIR = 0.3), which corresponds to a peak inductor current 1.15 times higher than the DC load current. VouT(Vin(max) - Vout) VIN(MAX) X #X lout x LIR where: f = switching frequency, normally 200kHz or 300kKHz IOUT = maximum DC load current LIR = ratio of AC to DC inductor current, typi- cally 0.3; should be selected for >0.15 The nominal peak inductor current at full load is 1.15 x lout if the above equation is used; otherwise, the peak current can be calculated by: Vout (Vin(mAX) - Vout) IPEAK = 'LloaD+ST4y1 x VINMAX) The inductors DC resistance should be low enough that Rpc x IPEAK < 100mV, as it is a key parameter for effi- ciency performance. If a standard off-the-shelf inductor is not available, choose a core with an LI@ rating greater than L x IPEAK2 and wind it with the largest-diameter wire that fits the winding area. For 300kHz applications, ferrite core material is strongly preferred; for 200kHz applications, Kool-Mu (aluminum alloy) or even pow- dered iron is acceptable. If light-load efficiency is unim- portant (in desktop PC applications, for example), then low-permeability iron-powder cores, such as the Micrometals type found in Pulse Engineerings 2.1pH PE-53680, may be acceptable even at 300kHz. For high-current applications, shielded-core geometries, such as toroidal or pot core, help keep noise, EMI, and switching-waveform jitter low. Kool-Mu is a registered trademark of Magnetics Div., Soang & Co. MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers Current-Sense Resistor Value The current-sense resistor value is calculated according to the worst-case-low current-limit threshold voltage (from the Electrical Characteristics table) and the peak inductor current: 80mV IPEAK RSENSE = Use IPEAK from the second equation in the Inductor Value section Use the calculated value of RSENSE to size the MOSFET switches and specify inductor saturation-current ratings according to the worst-case high-current-limit threshold voltage: 120mV IPEAK(MAX) = Reense Low-inductance resistors, such as surface-mount metal-film, are recommended. Input Capacitor Value Connect low-ESR bulk capacitors and small ceramic capacitors (0.1pF) directly to the drains on the high- side MOSFETs. The bulk input filter capacitor is usually selected according to input ripple current requirements and voltage rating, rather than capacitor value. Electrolytic capacitors with low enough effective series resistance (ESR) to meet the ripple current requirement invariably have sufficient capacitance values. Aluminum electrolytic capacitors, such as Sanyo OS-CON or Nichicon PL, are superior to tantalum types, which carry the risk of power-up surge-current failure, especially when connecting to robust AC adapters or low-impedance batteries. RMS input ripple current (IRMS) is determined by the input voltage and load current, with the worst case occurring at VIN = 2 x VOUT: Vout (Vin - YouT) IRMS = ILOAD X iN Therefore, when Vin is 2 x VouT: ILOAD | = RMS 9 Bypassing V+ Bypass the V+ input with a 4.7pF tantalum capacitor paralleled with a 0.1pF ceramic capacitor, close to the IC. A 10Q series resistor to VIN is also recommended. Bypassing VL Bypass the VL output with a 4.7yF tantalum capacitor paralleled with a 0.1pF ceramic capacitor, close to the device. Output Filter Capacitor Value The output filter capacitor values are generally deter- mined by the ESR and voltage rating requirements, rather than actual capacitance requirements for loop stability. In other words, the low-ESR electrolytic capacitor that meets the ESR requirement usually has more output capaci- tance than is required for AC stability. Use only special- ized low-ESR capacitors intended for switching-regulator applications, such as AVX TPS, Sprague 595D, Sanyo OS-CON, or Nichicon PL series. To ensure stability, the capacitor must meet both minimum capacitance and maximum ESR values as given in the following equations: Veer (1 + Vout / Vincmin)y) Vout X Rsense * f Rsense Xx Vout VREF Court > ResR < (can be multiplied by 1.5; see text below) These equations are worst case, with 45 degrees of phase margin to ensure jitter-free, fixed-frequency operation and provide a nicely damped output response for zero to full-load step changes. Some cost- conscious designers may wish to bend these rules with less-expensive capacitors, particularly if the load lacks large step changes. This practice is tolerable if some bench testing over temperature is done to verify acceptable noise and transient response. No well-defined boundary exists between stable and unstable operation. As phase margin is reduced, the first symptom is a bit of timing jitter, which shows up as blurred edges in the switching waveforms where the scope won't quite sync up. Technically speaking, this jitter (usually harmless) is unstable operation, since the duty factor varies slightly. As capacitors with higher ESRs are used, the jitter becomes more pronounced, and the load-transient output voltage waveform starts looking ragged at the edges. Eventually, the load-tran- sient waveform has enough ringing on it that the peak noise levels exceed the allowable output voltage toler- ance. Note that even with zero phase margin and gross instability present, the output voltage noise never gets much worse than IPEAK x RESsR (under constant loads). Designers of RF communicators or other noise-sensi- tive analog equipment should be conservative and stay within the guidelines. Designers of notebook computers and similar commercial-temperature-range digital 19 MAXUM GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers systems can multiply the RESR value by a factor of 1.5 without hurting stability or transient response. The output voltage ripple is usually dominated by the filter capacitors ESR, and can be approximated as IRIPPLE X Resr. There is also a capacitive term, so the full equation for ripple in continuous-conduction mode iS VNOISE (p-p) = IRIPPLE X [RESR + 1/(2 x a xt x CouT)]. In Idle Mode, the inductor current becomes discontinuous, with high peaks and widely spaced pulses, so the noise can actually be higher at light load (compared to full load). In Idle Mode, calculate the out- put ripple as follows: 0.02 x Resp + RSENSE 0.0003 x Lx [1 / Vout +1 / (Min - Your) 2 VNOISE(p-p) = (RgENSE) X CouT Transformer Design (for Auxiliary Outputs Only) Buck-plus-flyback applications, sometimes called cou- pled-inductor topologies, need a transformer to gener- ate multiple output voltages. Performing the basic electrical design is a simple task of calculating turns ratios and adding the power delivered to the secondary to calculate the current-sense resistor and primary inductance. However, extremes of low input-output dif- ferentials, widely different output loading levels, and high turns ratios can complicate the design due to par- asitic transformer parameters such as interwinding capacitance, secondary resistance, and leakage inductance. For examples of what is possible with real- world transformers, see the Maximum Secondary Current vs. Input Voltage graph in the Typical Operating Characteristics section. Power from the main and secondary outputs is com- bined to get an equivalent current referred to the main output voltage (see the Inductor Value section for para- meter definitions). Set the current-sense resistor resis- tor value at 80mV / ITOTAL. PTOTAL = The sum of the output power from all outputs ITOTAL = PTOTAL / VoUT = The equivalent output cur- rent referred to VoUT Liprimary) = VouT(Vin(MAX) - Vout) pamenyy = Vin(MAX) Xf X Iota x LIR Vsec_+ VEwp VouT(MIN) + VaecT + VSENSE Turns RatioN = 20 where: VsEc = the minimum required rectified sec- ondary output voltage VFwp = the forward drop across the secondary rectifier VOUT(MIN) = the minimum value of the main output voltage (from the Electrical Characteristics) VRECT = the on-state voltage drop across the synchronous rectifier MOSFET VSENSE = the voltage drop across the sense resistor In positive-output applications, the transformer sec- ondary return is often referred to the main output volt- age, rather than to ground, to reduce the needed turns ratio. In this case, the main output voltage must first be subtracted from the secondary voltage to obtain VSEc. Selecting Other Components MOSFET Switches The high-current N-channel MOSFETs must be logic-level types with guaranteed on-resistance specifications at Vas = 4.5V. Lower gate threshold specifications are bet- ter (i.e., 2V max rather than 3V max). Drain-source break- down voltage ratings must at least equal the maximum input voltage, preferably with a 20% derating factor. The best MOSFETs will have the lowest on-resistance per nanocoulomb of gate charge. Multiplying Ros(On) x Qq provides a good figure for comparing various MOSFETs. Newer MOSFET process technologies with dense cell structures generally perform best. The internal gate drivers tolerate >100nC total gate charge, but 70nC is a more practical upper limit to maintain best switching times. In high-current applications, MOSFET package power dissipation often becomes a dominant design factor. l2R power losses are the greatest heat contributor for both high-side and low-side MOSFETs. I@R losses are distributed between Q1 and @2 according to duty fac- tor (see the following equations). Generally, switching losses affect only the upper MOSFET, since the Schottky rectifier clamps the switching node in most cases before the synchronous rectifier turns on. Gate- charge losses are dissipated by the driver and dont heat the MOSFET. Calculate the temperature rise according to package thermal-resistance specifications to ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature. The worst-case dissipation for the high-side MOSFET occurs at both extremes of input voltage, and the worst-case dissipation for the low-side MOSFET occurs at maximum input voltage. MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers PD(upper FET) = (ILoqp)* x RDS(ON) x DUTY GATE PD(lower FET) = (lLoaD)* x RDS(ON) x (1 - DUTY) DUTY = (VouT+ Va2) / (MN- Vai) + Vin X ILoap x? X [Yn xCAss.. 20ns where: on-state voltage drop Vq_ = ILOAD x RDS(ON) Crss = MOSFET reverse transfer capacitance IGATE = DH driver peak output current capabil- ity (1A typical) 20ns = DH driver inherent rise/fall time Under output short-circuit, the MAX1633/MAX1634/ MAX1635s synchronous rectifier MOSFET suffers extra stress because its duty factor can increase to greater than 0.9. It may need to be oversized to tolerate a con- tinuous DC short circuit. During short circuit, the MAX1630/MAX1631/MAX1632s output undervoltage shutdown protects the synchronous rectifier under out- put short-circuit conditions. To reduce EMI, add a0.1pF ceramic capacitor from the high-side switch drain to the low-side switch source. Rectifier Clamp Diode The rectifier is a clamp across the low-side MOSFET that catches the negative inductor swing during the 60ns dead time between turning one MOSFET off and each low-side MOSFET on. The latest generations of MOSFETs incorporate a high-speed silicon body diode, which serves as an adequate clamp diode if efficiency is not of primary importance. A Schottky diode can be placed in parallel with the body diode to reduce the for- ward voltage drop, typically improving efficiency 1% to 2%. Use a diode with a DC current rating equal to one- third of the load current; for example, use an MBR0530 (500mA-rated) type for loads up to 1.5A, a 1N5819 type for loads up to 3A, or a 1N5822 type for loads up to 10A. The rectifiers rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. Boost-Supply Diode D2 A signal diode such as a 1N4148 works well in most applications. If the input voltage can go below +6V, use a small (20mA) Schottky diode for slightly improved efficiency and dropout characteristics. Dont use large power diodes, such as 1N5817 or 1N4001, since high junction capacitance can pump up VL to excessive voltages. Rectifier Diode D3 (Transformer Secondary Diode) The secondary diode in coupled-inductor applications must withstand flyback voltages greater than 60V, which usually rules out most Schottky rectifiers. Common silicon rectifiers, such as the 1N4001, are also prohibited because they are too slow. This often makes fast silicon rectifiers such as the MURS120 the only choice. The flyback voltage across the rectifier is relat- ed to the Vin - VouT difference, according to the trans- former turns ratio: VeLyBAcK = Vsec + (Vin - Vout) XN where: N = the transformer turns ratio SEC/PRI VsEc = the maximum secondary DC output voltage VouT = the primary (main) output voltage Subtract the main output voltage (VouT) from VFLYBACK in this equation if the secondary winding is returned to VouT and not to ground. The diode reverse breakdown rating must also accommodate any ringing due to leak- age inductance. D3s current rating should be at least twice the DC load current on the secondary output. Low-Voltage Operation Low input voltages and low input-output differential voltages each require extra care in their design. Low absolute input voltages can cause the VL linear regula- tor to enter dropout and eventually shut itself off. Low input voltages relative to the output (low VIN-VouT dif- ferential) can cause bad load regulation in multi-output flyback applications (see the design equations in the Transformer Design section). Also, low VIN-VouT differ- entials can also cause the output voltage to sag when the load current changes abruptly. The amplitude of the sag is a function of inductor value and maximum duty factor (an Electrical Characteristics parameter, 98% guaranteed over temperature at f = 200kHz), as follows: (Istep)* x L 2 X Court X (Vincmax) X Daax - Vout) VsaG = The cure for low-voltage sag is to increase the output capacitors value. For example, at VIN = +5.5V, VOUT = +5V, L = 10UH, f = 200KHz, ISTEP = 3A, a total capaci- tance of 660LF keeps the sag less than 200mV. Note that only the capacitance requirement increases, and the ESR requirements dont change. Therefore, the added capacitance can be supplied by a low-cost bulk capacitor in parallel with the normal low-ESR capacitor. 21 MAXUM GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Table 5. Low-Voltage Troubleshooting Chart step-load change differential, <1.5V slew rate per cycle. SYMPTOM CONDITION ROOT CAUSE SOLUTION Increase bulk output capacitance Sag or droop in VouT under Low VIN-VOUT Limited inductor-current per formula (see Low-Voltage Operation section). Reduce inductor value. Dropout voltage is too high (VouT follows VIN as VIN decreases) Low ViN-VoUT differential, <1V Maximum duty-cycle limits exceeded. Reduce operation to 200kHz. Reduce MOSFET on-resistance and coil DCR. Unstablejitters between different duty factors and frequencies Low ViN-VoUT differential, <0.5V Normal function of internal low-dropout circuitry. Increase the minimum input voltage or ignore. Secondary output won't support a load Low ViN-VoUT differential, VIN < 1.3 x VouT (main) Not enough duty cycle left to initiate forward-mode operation. Small AC current in primary cant store ener- gy for flyback operation. Reduce operation to 200kHz. Reduce secondary impedances; use a Schottky diode, if possible. Stack secondary winding on the main output. Poor efficiency Low input voltage, <5V VL linear regulator is going into dropout and isnt provid- ing good gate-drive levels. Use a small 20mA Schottky diode for boost diode D2. Supply VL from an external source. Won't start under load or quits before battery is completely dead Low input voltage, <4.5V VL output is so low that it hits the VL UVLO threshold. Supply VL from an external source other than Vin, such as the system +5V supply. Applications Information Heavy-Load Efficiency Considerations The major efficiency-loss mechanisms under loads are, in the usual order of importance: e P(IFR) = IPR losses e P(tran) = transition losses e P(gate) = gate-charge losses e P(diode) = diode-conduction losses ( ( U e P(cap) = capacitor ESR losses e P(IC) = losses due to the ICs operating supply supply current Inductor core losses are fairly low at heavy loads because the inductors AC current component is small. Therefore, they aren't accounted for in this analysis. Ferrite cores are preferred, especially at 300kHz, but powdered cores, such as Kool-Mu, can work well. Efficiency = Poyt / Ry x 100% = Pout / (Pout + Protac) x 100% Prota = P(PR) + P(tran) + P(gate) + P(diode) + P(cap) + P(IC) P = (PR) = (Loap)* x (Roc + Ros(on) + Rsense) 22 where Rpc is the DC resistance of the coil, RDS(ON) is the MOSFET on-resistance, and RsensE is the current- sense resistor value. The Rps(ON) term assumes identi- cal MOSFETs for the high-side and low-side switches, because they time-share the inductor current. If the MOSFETs aren't identical, their losses can be estimat- ed by averaging the losses according to duty factor. PD(tran) = transition loss = Vn X lLoap Xf x Xx [(Mn x Crss/ gate) + 20ns| where Crss is the reverse transfer capacitance of the high-side MOSFET (a data-sheet parameter), IGATE is the DH gate-driver peak output current (1.5A typical), and 20ns is the rise/fall time of the DH driver (20ns typical). P(gate) = qGxfx VL where VL is the internal-logic-supply voltage (+5V), and qG is the sum of the gate-charge values for low-side and high- side switches. For matched MOSFETs, qG is twice the data-sheet value of an individual MOSFET. If VouT is set to less than 4.5V, replace VL in this equation with VBATT. In this case, efficiency can be improved by connecting VL to an efficient 5V source, such as the system +5V supply. P(diode)= diode- conduction losses = ILoap X Vewn X tp xf MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers where tp is the diode-conduction time (120ns typical) and Vewp is the forward voltage of the diode. This power is dissipated in the MOSFET body diode if no external Schottky diode is used. 2 P(cap) = input capacitor ESR loss = (Ipys)* x Resa where IRMS is the input ripple current as calculated in the Design Procedure and Input Capacitor Value sections. Light-Load Efficiency Considerations Under light loads, the PWM operates in discontinuous mode, where the inductor current discharges to zero at some point during the switching cycle. This makes the inductor current's AC component high compared to the load current, which increases core losses and |?R loss- es in the output filter capacitors. For best light-load effi- ciency, use MOSFETs with moderate gate-charge levels, and use ferrite, MPP, or other low-loss core material. Avoid powdered-iron cores; even Kool-Mu (aluminum alloy) is not as good as ferrite. PC Board Layout Considerations Good PC board layout is required in order to achieve specified noise, efficiency, and stability performance. The PC board layout artist must be given explicit instructions, preferably a pencil sketch showing the placement of power-switching components and high- current routing. See the PC board layout in the MAX1630 Evaluation Kit manual for examples. A ground plane is essential for optimum performance. In most applications, the circuit will be located on a mullti- layer board, and full use of the four or more copper lay- ers is recommended. Use the top layer for high-current connections, the bottom layer for quiet connections (REF, SS, GND), and the inner layers for an uninterrupt- ed ground plane. Use the following step-by-step guide: 1) Place the high-power components (Figure1, C1, C3, Q1, Q2, D1, L1, and R11) first, with any grounded connections adjacent. Priority 1: Minimize current-sense resistor trace lengths and ensure accurate current sensing with Kelvin connections (Figure 7). Priority 2: Minimize ground trace lengths in the high-current paths (discussed below). Priority 3: Minimize other trace lengths in the high- current paths. Use >5mm-wide traces CIN to high-side MOSFET drain: 10mm max length Rectifier diode cathode to low-side MOSFET: 5mm max length LX node (MOSFETs, rectifier cathode, inductor): 15mm max length Ideally, surface-mount power components are butted up to one another with their ground terminals almost touching. These high-current grounds are then con- nected to each other with a wide filled zone of top-layer copper so they dont go through vias. The resulting top- layer sub-ground-plane is connected to the normal inner-layer ground plane at the output ground termi- nals, which ensures that the ICs analog ground is sensing at the supplys output terminals without interfer- ence from IR drops and ground noise. Other high- current paths should also be minimized, but focusing primarily on short ground and current-sense con- nections eliminates about 90% of all PC board lay- out problems (see the PC board layouts in the MAX1630 Evaluation Kit manual for examples). 2) Place the IC and signal components. Keep the main switching nodes (LX nodes) away from sensitive analog components (current-sense traces and REF capacitor). Place the IC and analog components on the opposite side of the board from the power- switching node. Important: the IC must be no far- ther than 10mm from the current-sense resistors. Keep the gate-drive traces (DH_, DL_, and BST_) shorter than 20mm and route them away from CSH_, CSL_, and REF. 3) Use a single-point star ground where the input ground trace, power ground (sub-ground-plane), and normal ground plane meet at the supplys out- put ground terminal. Connect both IC ground pins and all IC bypass capacitors to the normal ground plane. HIGH CURRENT PATH MAXIM MAX1630 Figure 7. Kelvin Connections for the Current-Sense Resistors 23 MAXUM GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Application Circuits T043.3V OUTPUT ) < TO 45V OUTPUT T1 = 10WH 1:4 TRANSFORMER TRANSPOWRR TECHNOLOGIES TTI-5902 QI-Q4 = Si4410DY or IRF7413 C1 =3x 220uF 10V SPRAGUE 594D227X0010D2T C2 = 2x 220uF 10V SPRAGUE 594D227X0010D2T C3 = C4 =2 x 10LF 30V SANYO OS-CON 308C10M *VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED FOR THE MAX1630 ONLY (SEE OUTPUT OVERVOL TAGE PROTECTION AND OUTPUT UNDERVOL TAGE SHUTDOWN PROTECTION SECTIONS). INPUT _ . 45.2V TO 424V ; aly, aR 102 Tt Fal a= Our ev = aa te ALWAYS ON ONOFF = = 23 | 22 |6 I sp otne 4.7 0F SHDN V+ SYNC VL = = 5 4 . eV Yoo 120UT +r AT120mA + TT 22uF 27uF To 31 gs73 asts 18 | = = Qi| 27 16 |@ 041 pF DH3 DHS Ct aay MAXIMA L2 Re 45V OUTPUT (3A) ar pv e our] 96 7 Jory OUTPUT 7 ee RI m1 OtyRE e241 1x3 MAX1630 =LX Fo 3A 4 (a) <b ke wf, MAXI633 1, Lia af ~ 1NB819 PEND [20 1NBB19 4 gus csHs H4 21 cgi3 csis H3 3 12 FB3 FB5 a L 3V ONOFE 281 puNONS seq P ee 5V ON/OFF TIME/ONS pF Tt" reset H+ POWER-GOOD Ai = Re =20ma SKP__ ond =P? =20m L2 =10,1H SUMIDA CDRHI25- 100 to _[s Figure 8. Triple-Output Application for Low-Voltage Batteries (MAX1630/MAX1633) 24 MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers Application Circuits (continued) 1043.3 OUTPUT ) < TO 45V OUTPUT INPUT _ . +6.5V TO +28V + +] C35 102 To : 4.7 uF 5 0.1HF _ wor 23 |22 16 |21 poe = 4.7HF SHON V+ SYNC VL = = 420UT 4 seen 5 Vpp D1 b2 ed asts 8 4 ale ZI) Dus pHs HE oh 48.3V OUTPUT (3A (3A) was MAXIM | =: Op == elie maxtegg LSPs S| 1 24 MAX1635 DLs 19 - 0.1 MF 1:22 L* pla eH e 20 1N5819 PGND 1N5819 CSHB csHs 4 24 csi3 esis H3 3] rpg rps 2 Lt L 3V ON/OFE 28) eUNVONS seq HP _ REF eo} __ +2.5V REF 5V ON/OFF 1) TIMEONS ap tur reset P- POWER-GOOD RI =R2=20ma SKIP GND L1 = 10H SUMIDA CDRH125-100 _|10 T2 = 10uH 1:2.2 TRANSFORMER TRANSPOWER TECHNOLOGIES TT1-5870 Qi-O4 = Si4410DY or IRF7413 C1 =3 x 220uF 10V SPRAGUE 594D227X001 0D2T C2 = 2 x 220uF 10V SPRAGUE594D227X0010D2T C3 =C4 =2 x 10,1F 30V SANYO OS-CON 30SC10M VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED FOR THE MAX1632 ONLY (SEE OUTPUT OVERVOL TAGE PROTECTION AND OUTPUT UNDERVOL TAGE SHUTDOWN PROTECTION SECTIONS). Nfs +5V ALWAYS ON MAXUM Figure 9. Triple-Output Application for High-Voltage Batteries (MAX1632/MAX1 635) 25 GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Application Circuits (continued) ON/OFF . . INPUT . . 46V TO 424V ; __BVALWAYS ON C3 . T 102 O.4uE 22 _|23 15 |2 ATF = = | V+ SHDN SECFB VL == 4.7uF |+ . ~ 18 4 25 T BSTS STS Ph oye Qt mt LE 18 ous DHS O.1WF = || % 2.5V OUTPUT Rt ut 0.1WF I, I 17H 1x5 LXx3 __43.3V OUTPUT + MAXIM . C1 @ 19] 5 MAKI631 al * MAxi634 DLS Tv ~ 1N5B19 _@ ON enD = ry 8) osHs CSHB 13 ois CSL3 se OPEN 3 12 3 FB5 FBS _ 7 RESET ONOFR ___@@-_ ff TIMEONS __}10 _ >8 SKIP = ONOFF RUN/ON3 4 = STEER 8} enp a =< | A sync_ sa 9 |6 | 15 tue Ri =R2 =15mQ L1 =L2=6,8H SUMIDA CDRH 127-6R8MC Q1 = Q4 = Si441 0DY or 1RF7413 C1 =C2 = 2X SANYO OS-CON 10 SA220M C3 = 4X SANYO OS-CON 308C10M VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED FORTHE MAX1631 ONLY (SEE OUTPUT OVERVOL TAGE PROTECTION AND OUTPUT UNDERVOL TAGE SHUTDOWN PROTECTION SECTIONS). Figure 10. Dual, 4A, Notebook Computer Power Supply 26 MAXIMAMulti-Output, Low-Noise Power-Supply Controllers for Notebook Computers Pin Configurations TOP VIEW e e cses [1 | [28] RUN/ONS cst [1 | 28] PUNONS csi3 [2 | | 27| DH csi3 [2 | |27| DH Fes [3 | j26] LX3 Fes [3 | f26 | LX8 120uT [4 | [25] BST3 steer [4 | [25 | BST Vop [5 | MAXUM 2A DL3 SECFB [5 | MAXLM a | D3 MAX1630 __ MAX1631 sync[e] maxieg2 [23] SHON sync[6] mAx1634 23] SHON MAX1633 TMEONS [7] qyaxyaas feel TIMEON6 [7 | 22] ve eno [8 | fet] ve eno [2 | 21] ve rer [9 | [20] pop rer [9 | [20] Pano SKIP [10 | 19] pis SKP [10 | 9] pis PRESET [11 | 18] ests FESET [11 | 18] ests Fas [12 17] Lxs Fes [12 | 7] Lxs caus [13 | 16] DHS cis [13 | 6] OHS CSH6 [14 15] SEQ CSH6 [14 15] SEQ SSOP SSOP Selector Guide OVER/UNDERVOLTAGE DEVICE AUXILIARY OUTPUT SECONDARY FEEDBACK PROTECTION MAX1630 12V Linear Regulator Feeds into the 3.3V SMPS Yes MAX1631 None (SECEFB input) Selectable (STEER pin) Yes MAX1632 12V Linear Regulator Feeds into the 5V SMPS Yes MAX1633 12V Linear Regulator Feeds into the 3.3V SMPS No MAX1634 None (SECEFB input) Selectable (STEER pin) No MAX1635 12V Linear Regulator Feeds into the 5V SMPS No MAXUM 27 GEGLXVW-OEILXVWNMAX1630-MAX1635 Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers __ Ordering Information (continued) PART TEMP.RANGE _PIN-PACKAGE MAX1631CAI OCto+70C 28. SSOP MAX1631EAl _-40C to +85C 28 SSOP MAX1632CAI OCto+70C 28. SSOP MAX1632EAl --40C to +85C_ 28 SSOP MAX1633CAI OCto+70C 28. SSOP MAX1633EAl -40C to +85C 28 SSOP MAX1634CAI OCto+70C 28. SSOP MAX1634EAl -40C to +85C 28 SSOP MAX1635CAI OCto+70C 28. SSOP MAX1635EAl _--40C to +85C 28 SSOP Package Information on Ta Sane INCHES __|MILLIMETERS a A | 0.068 [0.078 | 1.73 | 1.99 MIN | MAX _| MIN | MAX HL UU ai [0.002 [0.008 | 0.05 | oat _| pees yOe4? | 607 | 6.33 | IAT B Tove tous toes Tose | (pl o2s2 laze | 6.07 | 633 | 16L D/0.278|0.289 | 7.07| 7.33] 20L 4) = 0.004 10.008 10.09 10.20 | /pfo.3t7 [0.328 | 8.07] 8.33 | 24. D | SEE VARIATIONS | || Te Tezes [o20s [5.20 | se | 210.397 10.407 [10.07 [10.33 lee. e [0.0256 BSC [0.65 BSC H [0.301 Jasin | 7.65] 7.90 L_| 0.025 [0.037 | 0.63 | 0.95 alo fle [ole c ny th el a Al NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. VLA Al/VI 2, MOLD FLASH OR PROTRUSIONS NOT TO me EXCEED 15mm 006") PACKAGE QUTLINE, SSOP, 5.3x.65mm 3, CONTROLLING DIMENSION: MILLIMETER ee oose|td|C AL Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 28 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 1997 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products.