FEATURES FUNCTIONAL BLOCK DIAGRAMS SPI interface with error detection Includes CRC, invalid read/write address, and SCLK count error detection Supports burst mode and daisy-chain mode Industry standard SPI Mode 0 and SPI Mode 3 interface compatible Round robin mode allows switching times that are comparable with a parallel interface Four general-purpose digital outputs that can be used to control other devices <1 pC charge injection over full signal range 1 pF off capacitance VSS to VDD analog signal range Fully specified at 15 V and +12 V 1.8 V logic compatibility with 2.7 V VL 3.3 V 24-lead LFCSP package ADGS1208 S1 D S8 SCLK SDI SDO CS RESET/VL Figure 1. ADGS1208 Functional Block Diagram ADGS1209 S1A APPLICATIONS DA S4A Audio and video routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Communication systems S1B DB S4B GPO1 GPO2 GPO3 GPO4 GENERAL DESCRIPTION The ADGS1208/ADGS1209 are analog multiplexers comprising eight single channels and four differential channels, respectively. A serial peripheral interface (SPI) controls the switches. The SPI interface has robust error detection features, such as cyclic redundancy check (CRC) error detection, invalid read/write address detection, and SCLK count error detection. It is possible to daisy-chain multiple ADGS1208/ADGS1209 devices together. Daisy-chain mode enables the configuration of multiple devices with a minimal amount of digital lines. The ADGS1208/ADGS1209 can also operate in burst mode to decrease the time between SPI commands. iCMOS(R) construction ensures ultralow power dissipation, making the devices ideally suited for portable and batterypowered instruments. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Rev. 0 CNV SPI INTERFACE 16724-001 GPO1 GPO2 GPO3 GPO4 SPI INTERFACE SCLK SDI CS RESET/VL CNV SDO 16724-002 Data Sheet SPI Interface, Low CON and QINJ, 15 V/+12 V, 1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches ADGS1208/ADGS1209 Figure 2. ADGS1209 Functional Block Diagram The ultralow on capacitance (CON) and exceptionally low charge injection (QINJ) of these multiplexers make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. PRODUCT HIGHLIGHTS 1. 2. 3. 4. SPI interface removes the need for parallel conversion, logic traces, and reduces GPIO channel count. Daisy-chain mode removes additional logic traces when multiple devices are used. CRC error detection, invalid read/write address detection, and SCLK count error detection ensure a robust digital interface. CRC and error detection capabilities allow the use of the ADGS1208/ADGS1209 in safety critical systems. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADGS1208/ADGS1209 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Software Reset ............................................................................. 23 Applications ....................................................................................... 1 Daisy-Chain Mode ..................................................................... 23 General Description ......................................................................... 1 Power-On Reset .......................................................................... 24 Functional Block Diagrams ............................................................. 1 Round Robin Mode.................................................................... 25 Product Highlights ........................................................................... 1 General-Purpose Outputs ......................................................... 26 Revision History ............................................................................... 2 Applications Information .............................................................. 27 Specifications..................................................................................... 3 Digital Input Buffers .................................................................. 27 15 V Dual Supply ....................................................................... 3 Settling Time ............................................................................... 27 12 V Single Supply ........................................................................ 5 Power Supply Rails ..................................................................... 27 Continuous Current per Channel, Sx or Dx ............................. 8 Power Supply Recommendations............................................. 27 Timing Characteristics ................................................................ 9 Register Summaries ........................................................................ 28 Absolute Maximum Ratings .......................................................... 11 Register Details ............................................................................... 29 Thermal Resistance .................................................................... 11 Switch Data Register .................................................................. 29 ESD Caution ................................................................................ 11 Error Configuration Register.................................................... 30 Pin Configurations and Function Descriptions ......................... 12 Error Flags Register .................................................................... 30 Typical Performance Characteristics ........................................... 14 Burst Enable Register ................................................................. 31 Test Circuits ..................................................................................... 18 Round Robin Enable Register................................................... 31 Terminology .................................................................................... 21 Round Robin Channel Configuration Register...................... 31 Theory of Operation ...................................................................... 22 CNV Edge Select Register ......................................................... 32 Address Mode ............................................................................. 22 Software Reset Register ............................................................. 32 Error Detection Features ........................................................... 22 Outline Dimensions ....................................................................... 33 Clearing the Error Flags Register ............................................. 23 Ordering Guide .......................................................................... 33 Burst Mode .................................................................................. 23 REVISION HISTORY 4/2018--Revision 0: Initial Version Rev. 0 | Page 2 of 33 Data Sheet ADGS1208/ADGS1209 SPECIFICATIONS 15 V DUAL SUPPLY VDD = 15 V 10%, VSS = -15 V 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (ON) +25C -40C to +85C -40C to +125C Unit VDD to VSS V typ 150 240 270 max typ 6 35 64 10 12 VS = 10 V, IS = -1 mA 76 83 max typ max nA typ VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = 10 V, see Figure 36 0.003 0.6 Drain Off Leakage, ID (Off ) 0.1 0.003 0.1 0.02 0.3 0.6 1.0 0.6 1.0 DIGITAL OUTPUTS SDO Output Voltage Low, VOL High Impedance Leakage Current 1.0 0.4 0.2 0.001 0.1 High Impedance Output Capacitance GPOx Output Voltage High, VOH Low, VOL Timing tON tOFF Break-Before-Make Time Delay, tD VS = 10 V, IS = -1 mA, see Figure 39 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -1 mA 200 3.5 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Channel On Leakage, ID (On), IS (On) Test Conditions/Comments 4 VL - 0.2 V 0.2 95 115 15 20 50 115 115 25 25 35 Rev. 0 | Page 3 of 33 nA max nA typ nA max nA typ nA max VS = 10 V, VD = 10 V, see Figure 36 VS = VD = 10 V, see Figure 32 V max V max A typ A max pF typ Sink current (ISINK) = 5 mA ISINK = 1 mA Output voltage (VOUT) = VGND or VL V min V max ISOURCE = 100 A ISINK = 100 A ns typ ns max ns typ ns max ns typ ns min CL = 15 pF, see Figure 44 CL = 15 pF, see Figure 44 CL = 15 pF, see Figure 45 ADGS1208/ADGS1209 Parameter DIGITAL INPUTS/OUTPUTS Input Voltage High, VINH Data Sheet +25C -40C to +85C Low, VINL Input Current, IINL or IINH -40C to +125C Unit Test Conditions/Comments 2 1.35 0.8 0.8 V min V min V max V max A typ A max pF typ 3.3 V < VL 5.5 V 2.7 V VL 3.3 V 3.3 V < VL 5.5 V 2.7 V VL 3.3 V Input voltage (VIN) = VGND or VL RL = 300 , CL = 35 pF VS = 10 V, see Figure 41 RL = 300 , CL = 35 pF VS = 10 V, see Figure 42 RL = 300 , CL = 35 pF VS = 10 V, see Figure 42 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V, see Figure 40 VS = 0 V, RS = 0 , CL = 1 nF, see Figure 43 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 33 RL = 110 , 15 V p-p, f = 20 Hz to 20 kHz, see Figure 38 RL = 50 , CL = 5 pF, see Figure 37 0.001 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION 4 Break-Before-Make Time Delay, tD 90 145 92 110 120 135 32 Charge Injection, QINJ 0.4 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation -85 dB typ Channel to Channel Crosstalk -85 dB typ Total Harmonic Distortion Plus Noise -3 dB Bandwidth ADGS1208 ADGS1209 Insertion Loss 0.15 % typ 550 630 -6 MHz typ MHz typ dB typ CS (Off ) 1 1.6 pF typ pF max RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 37 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 5 5.5 2 3.5 pF typ pF max pF typ pF max VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 5 6.5 3 4.5 pF typ pF max pF typ pF max VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz tON (EN) tOFF (EN) 170 195 140 155 170 190 7 CD (Off ) ADGS1208 ADGS1209 CD (On), CS (On) ADGS1208 ADGS1209 Rev. 0 | Page 4 of 33 Data Sheet Parameter POWER REQUIREMENTS IDD ADGS1208/ADGS1209 +25C -40C to +85C -40C to +125C 0.002 Unit A typ A max A typ A max A typ A max 1.0 220 380 270 440 Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V All switches open All switches closed, VL = 5.5 V All switches closed, VL = 2.7 V IL Inactive 6.3 14 A typ A max A typ 7 A typ 390 A typ 210 A typ 15 7.5 230 120 1.8 A typ A typ A typ A typ mA typ 8.0 Inactive, SCLK = 1 MHz SCLK = 50 MHz Inactive, SDI = 1 MHz SDI = 25 MHz Active at 50 MHz 2.1 mA max mA typ 0.7 1.0 ISS 0.002 1.0 4.5 16.5 VDD/VSS 1 mA max A typ A max V min V max Digital inputs = 0 V or VL CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V Digital inputs toggle between 0 V and VL, VL = 5.5 V E E E E E E E E Digital inputs toggle between 0 V and VL, VL = 2.7 V Digital inputs = 0 V or VL GND = 0 V GND = 0 V Guaranteed by design; not subject to production test. 12 V SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (ON) +25C -40C to +85C -40C to +125C Unit 0 V to VDD V typ 380 Test Conditions/Comments 475 5 570 625 max typ VS = 0 V to 10 V, IS = -1 mA, see Figure 39 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -1 mA 16 200 26 27 max typ VS = 0 V to 10 V, IS = -1 mA Rev. 0 | Page 5 of 33 ADGS1208/ADGS1209 Data Sheet Parameter LEAKAGE CURRENTS Source Off Leakage, IS (Off ) +25C -40C to +85C 0.003 0.1 0.003 0.6 Drain Off Leakage, ID (Off ) 0.1 0.02 0.6 Channel On Leakage, ID (On), IS (On) 0.3 0.6 1.0 1.0 tOFF Break-Before-Make Time Delay, tD V max V max A typ A max pF typ ISINK = 5 mA ISINK = 1 mA VOUT = VGND or VL V min V max ISOURCE = 100 A ISINK = 100 A ns typ ns max ns typ ns max ns typ ns min CL = 15 pF, see Figure 44 VL - 0.2 V 0.2 115 115 25 25 35 2 1.35 0.8 0.8 Low, VINL Input Current, IINL or IINH 0.001 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTIC1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD 4 110 185 120 140 130 145 35 220 245 190 210 195 215 15 Charge Injection, QINJ Off Isolation Channel to Channel Crosstalk VS = VD = 1 V/10 V, see Figure 32 0.4 0.2 4 DIGITAL INPUTS Input Voltage High, VINH nA max nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36 nA max 0.001 95 115 15 20 50 nA max nA typ Test Conditions/Comments VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36 1.0 0.1 High Impedance Output Capacitance GPOx Output Voltage High, VOH Low, VOL Timing tON Unit nA typ DIGITAL OUTPUT Output Voltage Low, VOL High Impedance Leakage Current -40C to +125C -0.2 3.3 V < VL 5.5 V 2.7 V VL 3.3 V 3.3 V < VL 5.5 V 2.7 V VL 3.3 V VIN = VGND or VL ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ RL = 300 , CL = 35 pF VS = 8 V, see Figure 41 RL = 300 , CL = 35 pF VS = 8 V, see Figure 42 RL = 300 , CL = 35 pF VS = 8 V, see Figure 42 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V, see Figure 40 VS = 6 V, RS = 0 , CL = 1 nF, see Figure 43 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 33 dB typ -85 Rev. 0 | Page 6 of 33 CL = 15 pF, see Figure 45 V min V min V max V max A typ A max pF typ dB typ -85 CL = 15 pF, see Figure 44 Data Sheet Parameter -3 dB Bandwidth ADGS1208/ADGS1209 +25C -40C to +85C -40C to +125C Unit Test Conditions/Comments RL = 50 , CL = 5 pF, see Figure 37 ADGS1208 ADGS1209 Insertion Loss 450 550 -12 MHz typ MHz typ dB typ CS (Off ) 1.2 1.8 pF typ pF max RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 37 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 6 6.5 3.2 4 pF typ pF max pF typ pF max VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 6 7 4 4.5 pF typ pF max pF typ pF max VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = 13.2 V All switches open CD (Off ) ADGS1208 ADGS1209 CD (On), CS (On) ADGS1208 ADGS1209 POWER REQUIREMENTS IDD 0.002 1.0 220 380 270 440 A typ A max A typ A max A typ A max All switches closed, VL = 5.5 V All switches closed, VL = 2.7 V IL Inactive 6.3 14 A typ A max A typ 7 A typ 390 A typ 210 A typ 15 A typ 7.5 A typ 230 A typ 120 A typ 1.8 mA typ 8.0 Inactive, SCLK = 1 MHz SCLK = 50 MHz Inactive, SDI = 1 MHz SDI = 25 MHz Active at 50 MHz 2.1 0.7 VDD 1 1.0 5 16.5 Guaranteed by design; not subject to production test. Rev. 0 | Page 7 of 33 mA max mA typ mA max V min V max Digital inputs = 0 V or VL CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V Digital inputs toggle between 0 V and VL, VL = 5.5 V Digital inputs toggle between 0 V and VL, VL = 2.7 V GND = 0 V, VSS = 0 V GND = 0 V, VSS = 0 V ADGS1208/ADGS1209 Data Sheet CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Table 3. ADGS1208, One Channel On Parameter CONTINUOUS CURRENT, Sx OR D1 VDD = +15 V, VSS = -15 V (JA = 63.1C/W) VDD = 12 V, VSS = 0 V (JA = 63.1C/W) 1 25C 85C 125C Unit 29.3 37.7 21.9 27.3 14.1 19 mA max mA max 25C 85C 125C Unit 21.8 28.2 16.1 21.2 9.9 13.4 mA max mA max Sx refers to the S1 to S8 pins. Table 4. ADGS1209, Two Channels On Parameter CONTINUOUS CURRENT, Sx OR Dx1 VDD = +15 V, VSS = -15 V (JA = 63.1C/W) VDD = 12 V, VSS = 0 V (JA = 63.1C/W) 1 Sx refers to the S1A to S4A and S1B to S4B pins, and Dx refers to the DA and DB pins. Rev. 0 | Page 8 of 33 Data Sheet ADGS1208/ADGS1209 TIMING CHARACTERISTICS VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested. Table 5. Parameter TIMING CHARACTERISTICS t1 t2 t3 t4 t5 t6 t7 t8 t91 t10 t11 t12 t13 1 Limit Unit Test Conditions/Comments 20 8 8 10 6 8 10 20 20 20 20 8 8 ns min ns min ns min ns min ns min ns min ns min ns max ns max ns max ns min ns min ns min SCLK or CNV period SCLK or CNV high pulse width SCLK or CNV low pulse width CS falling edge to SCLK or CNV active edge Data setup time Data hold time SCLK or CNV active edge to CS rising edge CS falling edge to SDO data available SCLK falling edge to SDO data available CS rising edge to SDO returns to high impedance CS high time between SPI commands CS falling edge to SCLK or CNV edge rejection CS rising edge to SCLK or CNV edge rejection Measured with the 1 k pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used. Timing Diagrams t1 SCLK t4 t2 t3 t7 CS t5 SDI R/W t6 A6 A5 D2 D1 D0 t10 t9 SDO 0 1 D2 D1 D0 16724-102 0 t8 Figure 3. Address Mode Timing Diagram Rev. 0 | Page 9 of 33 ADGS1208/ADGS1209 Data Sheet t1 SCLK t2 t3 t4 t7 CS t5 SDI D7 t6 D6 D0 D7 INPUT BYTE FOR DEVICE N D6 D1 D0 INPUT BYTE FOR DEVICE N + 1 t9 0 0 0 D7 ZERO BYTE t8 D6 D1 D0 16724-103 SDO t10 INPUT BYTE FOR DEVICE N Figure 4. Daisy Chain Timing Diagram t11 CS t13 16724-004 SCLK OR CNV t12 Figure 5. SCLK or CNV and CS Timing Diagram t4 CS t3 t2 t7 CNV t9 t1 S1 S2 Figure 6. Round Robin Timing Diagram Rev. 0 | Page 10 of 33 S(LAST) 16724-006 SDO MUX CHANNEL t10 RESYNC Data Sheet ADGS1208/ADGS1209 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. THERMAL RESISTANCE Table 6. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Parameter VDD to VSS VDD to GND VSS to GND VL to GND Analog Inputs1 Digital Inputs Peak Current, Sx or Dx Pins2 1 Continuous Current, Sx or Dx2, 3 Operating Temperature Range Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb-Free Rating 35 V -0.3 V to +25 V +0.3 V to -25 V -0.3 V to +6 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first -0.3 V to +6 V 59 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% -40C to +125C -65C to +150C 150C 260(+0/-5)C Table 7. Thermal Resistance Package Type CP-24-152 1 2 JA 63.1 JCB1 27.3 Unit C/W JCB is the junction to the bottom of the case value. Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51. ESD CAUTION Overvoltages at the digital Sx and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins. 3 See Table 4 and Table 5. 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. Rev. 0 | Page 11 of 33 ADGS1208/ADGS1209 Data Sheet 20 RESET/VL 19 SDO 21 CS 22 SCLK 23 SDI 24 GPO4 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS GPO1 1 18 GPO3 GPO2 2 VSS 3 ADGS1208 S1 4 TOP VIEW (Not to Scale) S2 5 17 CNV 16 GND 15 V DD 14 S5 S3 6 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, VSS. 2. NIC = NOT INTERNALLY CONNECTED. 16724-007 S7 12 S8 11 NIC 10 D 9 S4 7 NIC 8 13 S6 Figure 7. ADGS1208 Pin Configuration Table 8. ADGS1208 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8, 10 9 11 12 13 14 15 16 17 18 19 Mnemonic GPO1 GPO2 VSS S1 S2 S3 S4 NIC D S8 S7 S6 S5 VDD GND CNV GPO3 SDO 20 RESET/VL 21 22 23 24 CS SCLK SDI GPO4 EPAD Description General-Purpose Output 1. This pin is a digital output. General-Purpose Output 2. This pin is a digital output. Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground. Source Terminal 1. This pin can be an input or output. Source Terminal 2. This pin can be an input or output. Source Terminal 3. This pin can be an input or output. Source Terminal 4. This pin can be an input or output. Not Internally Connected. These pins are not connected internally. Drain Terminal. This pin can be an input or output. Source Terminal 8. This pin can be an input or output. Source Terminal 7. This pin can be an input or output. Source Terminal 6. This pin can be an input or output. Source Terminal 5. This pin can be an input or output. Most Positive Power Supply Potential. Ground (0 V) Reference. Channel Cycle Input. When in round robin mode, the CNV pin is used to cycle through the selected channels. General-Purpose Output 3. This pin is a digital output. Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of SCLK. Pull this open-drain output to VL with an external resistor. RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply. Pull the RESET/VL pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers are set to their default values. Active Low Control Input. CS is the frame synchronization signal for the input data. Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz. Serial Data Input. Data is captured on the positive edge of the serial clock input. General-Purpose Output 4. This pin is a digital output. Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS. Rev. 0 | Page 12 of 33 20 RESET/VL 19 SDO 21 CS 22 SCLK 23 SDI ADGS1208/ADGS1209 24 GPO4 Data Sheet GPO1 1 18 GPO3 GPO2 2 17 CNV VSS 3 ADGS1209 16 GND S1A 4 TOP VIEW (Not to Scale) 15 V DD 14 S1B S2A 5 S3A 6 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, VSS. 2. NIC = NOT INTERNALLY CONNECTED. 16724-008 S3B 12 S4B 11 DB 10 DA 9 NIC 8 S4A 7 13 S2B Figure 8. ADGS1209 Pin Configuration Table 9. ADGS1209 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Mnemonic GPO1 GPO2 VSS S1A S2A S3A S4A NIC DA DB S4B S3B S2B S1B VDD GND CNV GPO3 SDO 20 RESET/VL 21 22 23 24 CS SCLK SDI GPO4 EPAD Description General-Purpose Output 1. This pin is a digital output. General-Purpose Output 2. This pin is a digital output. Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground. Source Terminal 1A. This pin can be an input or output. Source Terminal 2A. This pin can be an input or output. Source Terminal 3A. This pin can be an input or output. Source Terminal 4A. This pin can be an input or output. Not Internally Connected. This pin is not internally connected. Drain Terminal A. This pin can be an input or output. Drain Terminal B. This pin can be an input or output. Source Terminal 4B. This pin can be an input or output. Source Terminal 3B. This pin can be an input or output. Source Terminal 2B. This pin can be an input or output. Source Terminal 1B. This pin can be an input or output. Most Positive Power Supply Potential. Ground (0 V) Reference. Channel Cycle Input. When in round robin mode, the CNV pin is used to cycle through the selected channels. General-Purpose Output 3. This pin is a digital output. Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of SCLK. Pull this open-drain output to VL with an external resistor. RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply. Pull the RESET/VL pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers are set to their default values. Active Low Control Input. CS is the frame synchronization signal for the input data. Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz. Serial Data Input. Data is captured on the positive edge of the serial clock input. General-Purpose Output 4. This pin is a digital output. Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS. Rev. 0 | Page 13 of 33 ADGS1208/ADGS1209 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 180 500 TA = 25C 160 450 VDD = +13.5V VSS = -13.5V 400 ON RESISTANCE () 120 VDD = +15V VSS = -15V 100 VDD = +16.5V VSS = -16.5V 80 60 40 300 250 200 TA = -40C 150 -5 0 5 SOURCE OR DRAIN VOLTAGE (V) 10 15 0 16724-031 -10 0 Figure 9. On Resistance vs. Source or Drain Voltage for Various Dual Supplies 2 4 6 8 SOURCE OR DRAIN VOLTAGE (V) 10 12 16724-034 50 0 -15 Figure 12. On Resistance vs. Source or Drain Voltage for Various Temperatures, 12 V Single Supply 450 400 TA = 25C 400 VDD = 10.8V VSS = 0V 350 VDD = 12V VSS = 0V 300 250 VDD = 13.2V VSS = 0V 200 VDD = +15V VSS = -15V VBIAS = +10V/-10V 300 LEAKAGE CURRENT (pA) 150 100 ID, IS (ON) + + 200 ID (OFF) + - 100 IS (OFF) + - 0 ID, IS (ON) - - -100 ID (OFF) - + -200 IS (OFF) - + -300 50 0 2 4 6 8 10 SOURCE OR DRAIN VOLTAGE (V) 12 14 -400 16724-032 0 Figure 10. On Resistance vs. Source or Drain Voltage for Various Single Supplies 250 20 30 40 50 60 70 80 TEMPERATURE (C) 90 100 110 120 150 VDD = +15V VSS = -15V VDD = 12V VSS = 0V VBIAS = 1V/10V 100 LEAKAGE CURRENT (pA) TA = +125C TA = +85C 150 10 Figure 13. Leakage Current vs. Temperature, 15 V Dual Supply 200 TA = +25C 100 TA = -40C 50 IS (OFF) + - ID, IS (ON) + + 50 ID (OFF) + - 0 IS (OFF) - + ID, IS (ON) - - -50 ID (OFF) - + -100 -12 -9 -6 -3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 -150 16724-033 0 -15 0 16724-057 ON RESISTANCE () TA = +25C 100 20 ON RESISTANCE () TA = +85C 350 Figure 11. On Resistance vs. Source or Drain Voltage for Various Temperatures, 15 V Dual Supply 0 10 20 30 40 50 60 70 80 TEMPERATURE (C) 90 100 110 120 Figure 14. Leakage Current vs. Temperature, 12 V Single Supply Rev. 0 | Page 14 of 33 16724-058 ON RESISTANCE () 140 VDD = 12V VSS = 0V TA = +125C Data Sheet ADGS1208/ADGS1209 0 MUX (SOURCE TO DRAIN) 0.9 TA = 25C -10 0.8 -20 0.6 VDD = +15V VSS = -15V 0.5 0.4 0.3 -30 OFF ISOLATION (dB) 0.7 VDD = +12V VSS = 0V -40 -50 -60 -70 -80 0.2 -90 -10 -5 -100 0 VS (V) 5 10 15 -110 10k 16724-040 Figure 15. Source to Drain Charge Injection vs. Source Voltage (VS) SOURCE TO DRAIN CHARGE INJECTION (pC) -20 CROSSTALK (dB) 2 VDD = +12V VSS = 0V 0 VDD = +15V VSS = -15V -40 ADJACENT CHANNELS -60 NONADJACENT CHANNELS -80 -4 -100 -5 0 VS (V) 5 10 15 -120 10k 16724-041 -10 Figure 16. Drain to Source Charge Injection vs. Source Voltage (VS) 100k 1M 10M FREQUENCY (Hz) 100M 1G Figure 19. ADGS1208 Crosstalk vs. Frequency, 15 V Dual Supply 0 200 180 -20 12V SS 15V DS 160 120 100 80 VDD = +15V VSS = -15V TA = 25C -40 CROSSTALK (dB) 140 tTRANSITION (ns) 1G VDD = +15V VSS = -15V 0 TA = 25C VDD = +5V VSS = -5V -60 ADJACENT CHANNELS -80 60 40 -100 NONADJACENT CHANNELS 20 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 -120 10k 16724-018 0 -40 100M 20 4 -6 -15 1M 10M FREQUENCY (Hz) Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply DEMUX (DRAIN TO SOURCE) TA = 25C -2 100k 16724-042 0 -15 VDD = +5V VSS = -5V 16724-049 0.1 6 VDD = +15V VSS = -15V TA = 25C Figure 17. Transition Time (tTRANSITION) vs. Temperature for Single Supply (SS) and Dual Supply (DS) 100k 1M 10M FREQUENCY (Hz) 100M 1G Figure 20. ADGS1209 Crosstalk vs. Frequency, 15 V Dual Supply Rev. 0 | Page 15 of 33 16724-053 SOURCE TO DRAIN CHARGE INJECTION (pC) 1.0 ADGS1208/ADGS1209 Data Sheet 10 TA = 25C VDD = +15V VSS = -15V -6 100nF DECOUPLING CAPACITOR 10F + 100nF DECOUPLING CAPACITOR NO DECOUPLING -8 INSERTION LOSS (dB) -10 -50 -70 -90 TA = 25C VDD = +15V VSS = -15V -10 -12 -14 -16 -18 -110 1k 10k 100k 1M 10M FREQUENCY (Hz) -20 100 16724-022 -130 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 16724-125 ACPSRR (dB) -30 Figure 24. ADGS1209 Insertion Loss vs. Frequency, 15 V Dual Supply Figure 21. AC Power Supply Rejection Ratio (ACPSRR) vs. Frequency, 15 V Dual Supply 8 10 LOAD = 10k TA = 25C VDD = +15V VSS = -15V TA = 25C 7 CAPACITANCE (pF) 6 THD + N (%) 1 VDD = +5V, VSS = -5V, VS = +3.5V rms VDD = +15V, VSS = -15V, VS = +5V rms 0.1 5 SOURCE/DRAIN ON 4 DRAIN OFF 3 2 1 1k FREQUENCY (Hz) 10k 100k 0 -15 -10 -5 0 5 SOURCE VOLTAGE (V) 15 10 16724-043 100 16724-036 0.01 10 SOURCE OFF Figure 25. ADG1208 Capacitance vs. Source Voltage, 15 V Dual Supply Figure 22. THD + N vs. Frequency 8 -6 VDD = +12V VSS = 0V TA = 25C 7 6 TA = 25C VDD = +15V VSS = -15V -10 CAPACITANCE (pF) -12 -14 -16 DRAIN OFF 4 3 2 -18 SOURCE OFF 1 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G 0 16724-124 -20 100 SOURCE/DRAIN ON 5 0 1 2 3 4 5 6 7 8 SOURCE VOLTAGE (V) 9 10 11 Figure 26. ADG1208 Capacitance vs. Source Voltage, 12 V Single Supply Figure 23. ADGS1208 Insertion Loss vs. Frequency, 15 V Dual Supply Rev. 0 | Page 16 of 33 12 16724-045 INSERTION LOSS (dB) -8 Data Sheet ADGS1208/ADGS1209 300 5 4 250 15V SOURCE/DRAIN ON 200 IDD (A) 3 DRAIN OFF 12V 150 2 100 SOURCE OFF 50 0 0 1 2 3 4 5 6 7 8 SOURCE VOLTAGE (V) 9 10 11 12 0 2.7 3.0 3.5 4.0 4.5 5.0 5.5 VL (V) 16724-232 1 16724-047 CAPACITANCE (pF) TA = 25C ADGS1208 WITH S8 SLECTED VDD = +12V VSS = 0V TA = 25C Figure 30. IDD vs. VL Figure 27. ADG1209 Capacitance vs. Source Voltage, 12 V Single Supply 450 5 TA = 25C VDD = +15V VSS = -15V TA = 25C 4 350 300 3 IL (A) CAPACITANCE (pF) 400 SOURCE/DRAIN ON 250 VL = 5V 200 2 DRAIN OFF 150 VL = 3V 100 1 SOURCE OFF -12 -9 -6 -3 0 3 6 SOURCE VOLTAGE (V) 9 12 15 0 16724-056 0 -15 1 0.20 SCLK = 2.5MHz SCLK IDLE VOUT (mV) 0.10 0.05 0 -0.05 0 2 4 6 TIME (s) 8 16724-131 -0.10 -0.15 20 30 40 SCLK FREQUENCY (MHz) Figure 28. ADG1209 Capacitance vs. Source Voltage, 15 V Dual Supply 0.15 10 Figure 29. Digital Feedthrough Rev. 0 | Page 17 of 33 Figure 31. IL vs. SCLK Frequency when CS is High 50 16724-126 50 ADGS1208/ADGS1209 Data Sheet TEST CIRCUITS IS (OFF) (ON) VS VD ID (OFF) A VD Figure 36. Off Leakage VDD VSS 0.1F 0.1F VOUT Dx VS Figure 32. On Leakage NETWORK ANALYZER Sx A 16724-028 D Dx 16724-024 Sx VDD VSS VDD 0.1F VSS VDD VSS 0.1F NETWORK ANALYZER S1 RL 50 D S2 Sx RL 50 50 VS Dx GND VOUT VS 16724-026 CHANNEL TO CHANNEL CROSSTALK = 20 log INSERTION LOSS = 20 log Figure 33. Channel to Channel Crosstalk VDD 0.1F V RL OUT 50 GND VOUT WITH SWITCH VS WITHOUT SWITCH Figure 37. Insertion Loss/-3 dB Bandwidth VSS 0.1F NETWORK ANALYZER VSS 50 Sx VDD 0.1F VSS VDD VSS 0.1F AUDIO PRECISION RS Sx VS Dx VS V p-p V RL OUT 50 GND Dx RL 110 OFF ISOLATION = 20 log VOUT VS VOUT 16724-027 GND 16724-029 VDD Figure 34. Off Isolation Figure 38. THD + N VSS NETWORK ANALYZER RL 50 INTERNAL BIAS VDD VSS VS ACPSRR = 20 log GND D1 IDS NC V1 VOUT VS NOTES 1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED FROM THE ACPSRR MEASUREMENT. Sx Figure 35. ACPSRR Dx S RON = V1/IDS Figure 39. On Resistance Rev. 0 | Page 18 of 33 16724-025 S1 RL 50 16724-141 VOUT 16724-130 VS Data Sheet ADGS1208/ADGS1209 VDD VSS VDD VSS SCLK S1 0V VS S2 TO S7 S8 VS1 = VS8 80% 80% ADGS12081 OUTPUT OUTPUT D 300 1SIMILAR 35pF 16724-143 GND tD CONNECTION FOR THE ADGS1209. Figure 40. Break-Before-Make Time Delay, tD VDD VSS VDD VSS SCLK ADGS12081 S1 50% 50% VS1 S2 TO S7 VS8 90% VOUT D RL 300 GND CL 35pF 10% tTRANSITION 1SIMILAR tTRANSITION CONNECTION FOR THE THE ADGS1209. 16724-144 S8 Figure 41. Transition Time, tTRANSITION VDD VSS VDD VSS SCLK ADGS12081 S1 50% 50% VS1 S2 TO S8 90% VOUT GND RL 300 CL 35pF 10% tOFF (EN) 1 SIMILAR tON (ENO) CONNECTION FOR THE ADGS1209. 16724-145 D Figure 42. Switching Times, tON (EN) and tOFF (EN) 3V SCLK RS VDD VSS VDD VSS Sx Dx QINJ = CL x VOUT INPUT LOGIC V OUT SWITCH OFF SWITCH ON Figure 43. Charge Injection, QINJ Rev. 0 | Page 19 of 33 GND 16724-132 VOUT V OUT CL 1nF VS ADGS1208/ADGS1209 Data Sheet VDD VSS VDD VSS SCLK ADGS12081 S1 CL 15pF 50% 50% VGPO 90% GND tOFF (GPO) tON (GPO) 1SIMILAR CONNECTION FOR THE ADGS1209. 16724-146 10% Figure 44. GPOx Timing, tON and tOFF VDD VSS VDD VSS GPO1 CL 15pF 80% 80% ADGS1208 1 CL 15pF VGPO2 GND tD (GPO) TIME DELAY BETWEEN GPO1 TURNING OFF AND GPO2 TURNING ON GPO2 VGPO2 1SIMILAR CONNECTION FOR THE ADGS1209. Figure 45. GPOx Break-Before-Make Time Delay, tD Rev. 0 | Page 20 of 33 16724-147 VGPO1 VGPO1 Data Sheet ADGS1208/ADGS1209 TERMINOLOGY IDD IDD is the positive supply current. CS (On), CD (On) CS (On) and CD (On) are the on switch capacitances, which are measured with reference the ground. ISS ISS is the negative supply current. VD, VS VD and VS are the analog voltage on Terminal Dx and Terminal Sx, respectively. RON RON is the ohmic resistance between Terminal Dx and Terminal Sx. RON RON is the difference between the RON of any two channels. RFLAT (ON) RFLAT (ON) is flatness that is the difference between maximum and minimum on resistance values measured over the specified analog signal range. IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. IS (On), ID (On) IS (On) and ID (On) are the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. CIN CIN is the digital input capacitance. tON tON is the delay between applying the digital control input and the output switching on. tOFF tOFF is the delay between applying the digital control input and the output switching off. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. -3 dB Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH are the low and high input currents of the digital inputs, respectively. CS (Off) CS (Off) is the off switch source capacitance, which is measured with reference to ground. CD (Off) CD (Off) is the off switch drain capacitance, which is measured with reference to ground. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) THD + N is the ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is the ratio of the amplitude of signal on the output to the amplitude of the modulation. ACPSRR is a measure of the ability of the devices to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. Rev. 0 | Page 21 of 33 ADGS1208/ADGS1209 Data Sheet THEORY OF OPERATION The target register address of an SPI command is determined on the eighth SCLK rising edge. Data from this register propagates out on SDO from the ninth to the 16th SCLK falling edge during SPI reads. A register write occurs on the 16th SCLK rising edge during SPI writes. The ADGS1208/ADGS1209 are a set of serially controlled analog multiplexers comprising eight single channels and four differential channels, respectively, with error detection features. SPI Mode 0 and SPI Mode 3 can be used with the devices, and they operate with SCLK frequencies up to 50 MHz. The default mode for the ADGS1208/ADGS1209 is address mode, in which the registers of the device are accessed by a 16-bit SPI command bounded by CS. The SPI command becomes 24-bit if the user enables CRC error detection. Other error detection features include SCLK count error and invalid read/write error. If any of these SPI interface errors occur, they are detectable by reading the error flags register. The ADGS1208/ADGS1209 can also operate in two other modes, namely burst mode and daisy-chain mode. During any SPI command, SDO sends out eight alignment bits on the first eight SCLK falling edges. The alignment bits observed at SDO are 0x25. ERROR DETECTION FEATURES Protocol and communication errors on the SPI interface are detectable. The three detectable errors are incorrect SCLK error detection, invalid read and write address error detection, and CRC error detection. Each error has a corresponding enable bit in the error configuration register. In addition, there is an error flag bit for each error in the error flags register. The interface pins of the ADGS1208/ADGS1209 are CS, SCLK, SDI, and SDO. Hold CS low when using the SPI interface. Data is captured on SDI on the rising edge of SCLK, and data is propagated out on SDO on the falling edge of SCLK. SDO has an open-drain output; thus, connect a pull-up to this output. When not pulled low by the ADGS1208/ADGS1209, SDO is in a high impedance state. Cyclic Redundancy Check (CRC) Error Detection The CRC error detection feature extends a valid SPI frame by eight SCLK cycles. These eight extra cycles are needed to send the CRC byte for that SPI frame. The CRC byte is calculated by the SPI block using the 16-bit payload: the R/W bit, Register Address Bits[6:0], and Register Data Bits[7:0]. The CRC polynomial used in the SPI block is x8 + x2 + x1 + 1 with a seed value of 0. For a timing diagram with CRC enabled, see Figure 47. Register writes occur at the 24th SCLK rising edge with CRC error checking enabled. ADDRESS MODE Address mode is the default mode for the ADGS1208/ADGS1209 on power-up. A single SPI frame in address mode is bounded by a CS falling edge and the succeeding CS rising edge. An SPI frame is comprised of 16 SCLK cycles. The timing diagram for address mode is shown in Figure 46. The first SDI bit indicates if the SPI command is a read or write command. When the first bit is set to 0, a write command is issued, and if the first bit is set to 1, a read command is issued. The next seven bits determine the target register address. The remaining eight bits provide the data to the addressed register. The last eight bits are ignored during a read command, because during these clock cycles, SDO propagates out the data contained in the addressed register. During an SPI write, the microcontroller/CPU provides the CRC byte through SDI. The SPI block checks the CRC byte just before the 24th SCLK rising edge. On this same edge, the register write is prevented if an incorrect CRC byte is received by the SPI interface. In the case that an incorrect CRC byte is detected, the CRC error flag is asserted in the error flags register. During an SPI read, the CRC byte is provided to the microcontroller through SDO. The CRC error detection feature is disabled by default and can be configured by the user through the error configuration register. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CS SDI SDO 0 0 1 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 16724-133 SCLK Figure 46. Address Mode Timing Diagram 1 2 8 9 10 16 17 18 19 20 21 22 23 24 R/W A6 A0 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0 CS SDI SDO 0 0 1 D7 D6 D0 C7 C6 C5 Figure 47. Timing Diagram with CRC Enabled Rev. 0 | Page 22 of 33 C4 C3 C2 C1 C0 16724-134 SCLK Data Sheet ADGS1208/ADGS1209 SCLK Count Error Detection BURST MODE SCLK count error detection allows the user to detect if an incorrect number of SCLK cycles are sent by the microcontroller/ CPU. When in address mode, with CRC disabled, 16 SCLK cycles are expected. If 16 SCLK cycles are not detected, the SCLK count error flag asserts in the error flags register. When less than 16 SCLK cycles are received by the device, a write to the register map never occurs. When the ADGS1208/ADGS1209 receive more than 16 SCLK cycles, a write to the memory map still occurs at the 16th SCLK rising edge, and the flag asserts in the error flags register. With CRC enabled, the expected number of SCLK cycles is 24. SCLK count error detection is enabled by default and can be configured by the user through the error configuration register. The SPI interface can accept consecutive SPI commands without the need to de-assert the CS line, which is called burst mode. Burst mode is enabled through the burst enable register. This mode uses the same 16-bit command to communicate with the device. In addition, the response of the device at SDO is still aligned with the corresponding SPI command. Figure 48 shows an example of SDI and SDO during burst mode. The invalid read/write address and CRC error checking functions operate similarly during burst mode as they do during address mode. However, SCLK count error detection operates in a slightly different manner. The total number of SCLK cycles within a given CS frame are counted, and if the total is not a multiple of 16, or a multiple of 24 when CRC is enabled, the SCLK count error flag asserts. Invalid Read/Write Address Error Detection An invalid read/write address error detects when a nonexistent register address is a target for a read or write. In addition, this error asserts when a write to a read only register is attempted. The invalid read/write address error flag asserts in the error flags register when an invalid read/write address error occurs. The invalid read/write address error is detected on the ninth SCLK rising edge, which means a write to the register never occurs when an invalid address is targeted. Invalid read/write address error detection is enabled by default and can be disabled by the user through the error configuration register. SDI COMMAND0[15:0] COMMAND1[15:0] COMMAND2[15:0] COMMAND3[15:0] SDO RESPONSE0[15:0] RESPONSE1[15:0] RESPONSE2[15:0] RESPONSE3[15:0] Figure 48. Burst Mode Frame SOFTWARE RESET When in address mode, the user can initiate a software reset. To do so, write two consecutive SPI commands, 0xA3 followed by 0x05, targeting Register 0x0B. After a software reset, all register values are set to default. CLEARING THE ERROR FLAGS REGISTER DAISY-CHAIN MODE To clear the error flags register, write the special 16-bit SPI frame, 0x6CA9, to the device. This SPI command does not trigger the invalid read/write address error. When CRC is enabled, the user must also send the correct CRC byte for a successful error clear command. At the 16th or 24th SCLK rising edge, the error flags register resets to 0. The connection of several ADGS1208/ADGS1209 devices in a daisy chain configuration is possible, and Figure 49 shows this setup. All devices share the same CS and SCLK line, whereas the SDO of a device forms a connection to the SDI of the next device, creating a shift register. In daisy-chain mode, SDO is an eight cycle delayed version of SDI. When in daisy-chain mode, all commands target the switch data register. Therefore, it is not possible to make configuration changes while in daisy-chain mode. ADGS1208 ADGS1208 DEVICE 1 DEVICE 2 S1 S1 D D VL S8 SPI INTERFACE 16724-135 CS S8 SDO SPI INTERFACE SDO 16724-050 SDI SCLK CS RESET/VL Figure 49. Two ADGS1208/ADGS1209 Devices Connected in a Daisy-Chain Configuration Rev. 0 | Page 23 of 33 ADGS1208/ADGS1209 Data Sheet The ADGS1208/ADGS1209 can only enter daisy-chain mode when in address mode by sending the 16-bit SPI command, 0x2500 (see Figure 50). When the ADGS1208/ADGS1209 receive this command, the SDO of the device sends out the same command because the alignment bits at SDO are 0x25, which allows multiple daisy-connected devices to enter daisychain mode in a single SPI frame. A hardware reset is required to exit daisy-chain mode. An SCLK rising edge reads in data on SDI while data is propagated out of SDO on an SCLK falling edge. The expected number of SCLK cycles must be a multiple of eight before CS goes high. When this is not the case, the SPI interface sends the last eight bits received to the switch data register. POWER-ON RESET The digital section of the ADGS1208/ADGS1209 goes through an initialization phase during VL power up. This initialization also occurs after a hardware or software reset. After VL power-up or a reset, ensure that a minimum of 120 s from the time of power-up or reset before any SPI command is issued. Ensure that VL does not drop out during the 120 s initialization phase, because it may result in incorrect operation of the ADGS1208/ADGS1209. For the timing diagram of a typical daisy-chain SPI frame, see Figure 51. When CS goes high, Device 1 writes Command 0, Bits[7:0] to its switch data register, Device 2 writes Command 1, Bits[7:0] to its switches, and so on. The SPI block uses the last eight bits it received through SDI to update the switches. After entering daisy chain mode, the first eight bits sent out by SDO on each device in the chain are 0x00. When CS goes high, the internal shift register value does not reset back to 0. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 CS SDI 0 SDO 0 1 0 0 1 0 1 0 0 0 0 0 0 0 16724-037 SCLK 0 Figure 50. SPI Command to Enter Daisy-Chain Mode SDI COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] COMMAND0[7:0] DEVICE 1 SDO 8'h00 COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] DEVICE 2 SDO2 8'h00 8'h00 COMMAND3[7:0] COMMAND2[7:0] DEVICE 3 8'h00 8'h00 8'h00 COMMAND3[7:0] DEVICE 4 SDO3 NOTES 1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY. 16724-038 CS Figure 51. Example of an SPI Frame Where Four ADGS1208/ADGS1209 Devices Connect in Daisy-Chain Mode Rev. 0 | Page 24 of 33 Data Sheet ADGS1208/ADGS1209 ROUND ROBIN MODE Round robin mode allows the ADGS1208/ADGS1209 to cycle through the channels faster by reducing the overhead needed from the digital interface to switch from one channel to the next. The round robin configuration register selects which channels are to be included in a cycle, while the CNV edge select register selects on which edge of CNV the ADGS1208/ ADGS1209 switch to the next channel in the sequence. At the end of the channel cycle, a resync pulse appears on SDO to inform the user that the current cycle ended and then it loops back to the start of the sequence of channels. Figure 52 shows an example of the round robin mode interface and Figure 53 shows the CNV signal of the analog-to-digital converter (ADC) being used in conjunction with the ADGS1208 in round robin mode. After configuration completes, the round robin enable register allows the ADGS1208/ADGS1209 to enter round robin mode. When in round robin mode, the SPI is no longer used to switch between channels. Instead, to switch from one channel to another, ensure that a digital signal is present on the CNV pin while CS is pulled low. To exit round robin mode, either perform a hardware reset or send the 16-bit addressable mode SPI frames: 0xA318 followed by 0xE3B4. These are the only SPI commands recognized by the SPI interface while in round robin mode. Round robin mode is significantly faster than addressable mode to cycle through channels because it removes the 16-bit overhead required to change input channel. In addition, round robin mode removes the need for SCLK to be running, which reduces the digital current consumption (IL). The maximum CNV frequency is bound by the transition time of the device, along with the required settling time for the application. ROUND ROBIN CYCLE CS CNV MUX CHANNEL X S1 S2 S(LAST) 16724-154 RESYNC SDO Figure 52. Round Robin Mode Interface Example tCYC VIO S1 S2 S3 SDI CNV D ADGS1208 IN7 IN AD7980 SDO CNV SCK S8 AQUISITION CNV tCONV tACQ CONVERSION AQUISITION CS SDI SCK CONVERT CLK 1 SCK 2 3 14 15 16 GPO GPO DATA IN DIGITAL HOST tDIS tEN SDO MUX CHANNEL D15 N D14 D13 N+1 Figure 53. Example of CNV Signal of an ADC Cycling Through Channels in the ADGS1208 Rev. 0 | Page 25 of 33 D1 D0 N+2 16724-155 IN0 IN1 IN2 ADGS1208/ADGS1209 Data Sheet GENERAL-PURPOSE OUTPUTS or low. When the device is in round robin mode, the GPOs are driven low. The logic low level is GND and VL sets the logic high level. Figure 54 shows how the ADGS1208 can be used to control another device, which in this example is the ADG758. The ADGS1208/ADGS1209 have four general-purpose outputs (GPOs). These digital outputs allow the control of other devices using the ADGS1208/ADGS1209. The GPOs are controlled from the SW_DATA register, where they can be either set high ADGS1208 ADG758 S1 S1 D D S8 S8 SDO CNV SPI INTERFACE GPO1 GPO2 GPO3 GPO4 1 OF 8 DECODER A0 A1 A2 EN 16724-156 SDI SCLK CS RESET/VL Figure 54. ADGS1208 Device Controlling the ADG758 Rev. 0 | Page 26 of 33 Data Sheet ADGS1208/ADGS1209 APPLICATIONS INFORMATION DIGITAL INPUT BUFFERS POWER SUPPLY RECOMMENDATIONS There are input buffers present on the digital input pins (CS, SCLK, and SDI). These buffers are active at all times; as result, there is current draw from the VL supply if SCLK or SDI are toggling, regardless of whether CS is active. For typical values of this current draw, refer to the Specifications section and Figure 31. Analog Devices, Inc., has a wide range of power management products to meet the requirements of most high performance signal chains. Disturbances are apparent on the source/drain when switching between channels, as is typical with complementary metaloxide semiconductor (CMOS) switches and multiplexers. A sufficient wait time is necessary for these disturbances to settle before taking a measurement to ensure an accurate reading. The settling time for a data acquisition system is dependent on the load on the output of the multiplexer. The ADM7160 can be used to generate the VL voltage required to power digital circuitry within the ADGS1208/ADGS1209. POWER SUPPLY RAILS ADM7160 LDO To guarantee correct operation of the ADGS1208/ADGS1209, 0.1 F decoupling capacitors are required. The ADGS1208/ADGS1209 can operate with bipolar supplies between 4.5 V and 16.5 V. The supplies on VDD and VSS do not need to be symmetrical. However, the VDD to VSS range must not exceed 33 V. The ADGS1208/ADGS1209 can also operate with single supplies between 5 V and 20 V with VSS connected to GND. The voltage range that can be supplied to VL is from 2.7 V to 5.5 V. The device is fully specified at 15 V and +12 V analog supply voltage ranges. +16.5V +5V INPUT ADP7118 LDO ADP5070 -16.5V ADP7182 LDO +3.3V +15V -15V 16724-142 SETTLING TIME An example of a bipolar power solution is shown in Figure 55. The ADP5070 dual switching regulator generates a positive and negative supply rail for the ADGS1208/ADGS1209, amplifier, and/or a precision converter in a typical signal chain. Also shown in Figure 55 are two optional low dropout (LDO) regulators, ADP7118 and ADP7182 (positive and negative, respectively), that can be used to reduce the output ripple of the ADP5070 in ultralow noise sensitive applications. . Figure 55. Bipolar Power Solution Table 10. Recommended Power Management Devices Product ADP5070 ADM7160 ADP7118 ADP7182 Rev. 0 | Page 27 of 33 Description 1 A/0.6 A, dc-to-dc switching regulator with independent positive and negative outputs 5.5 V, 200 mA, ultralow noise LDO linear regulator 20 V, 200 mA, low noise CMOS LDO linear regulator -28 V, -200 mA, low noise LDO linear regulator ADGS1208/ADGS1209 Data Sheet REGISTER SUMMARIES Table 11. ADGS1208 Register Summary Reg. 0x01 0x02 0x03 0x05 0x06 0x07 0x09 0x0B Name SW_DATA ERR_CONFIG ERR_FLAGS BURST_EN ROUND_ROBIN_EN RROBIN_CHANNEL_CONFIG CNV_EDGE_SEL SOFT_RESETB Bit 7 Bit 6 GPO4 GPO3 S8_EN S7_EN Bit 5 Bit 4 GPO2 GPO1 Reserved Reserved S6_EN Bit 3 A2 Bit 2 A1 RW_ERR_EN RW_ERR_FLAG Reserved Reserved S5_EN S4_EN S3_EN RESERVED SOFT_RESETB Bit 1 A0 SCLK_ERR_EN SCLK_ERR_FLAG S2_EN Bit 0 EN CRC_ERR_EN CRC_ERR_FLAG BURST_MODE_EN ROUND_ROBIN_EN S1_EN CNV_EDGE_SEL Default 0x00 0x06 0x00 0x00 0x00 0xFF 0x00 0x00 RW R/W R/W R R/W R/W R/W R/W R/W Bit 0 EN CRC_ERR_EN CRC_ERR_FLAG BURST_MODE_EN ROUND_ROBIN_EN S1_EN CNV_EDGE_SEL Default 0x00 0x06 0x00 0x00 0x00 0x0F 0x00 0x00 RW R/W R/W R R/W R/W R/W R/W R/W Table 12. ADGS1209 Register Summary Reg. 0x01 0x02 0x03 0x05 0x06 0x07 0x09 0x0B Name SW_DATA ERR_CONFIG ERR_FLAGS BURST_EN ROUND_ROBIN_EN RROBIN_CHANNEL_CONFIG CNV_EDGE_SEL SOFT_RESETB Bit 7 Bit 6 GPO4 GPO3 Bit 5 Bit 4 GPO2 GPO1 Reserved Reserved Reserved Bit 3 Reserved Bit 2 A1 RW_ERR_EN RW_ERR_FLAG Reserved Reserved S4_EN S3_EN Reserved SOFT_RESETB Rev. 0 | Page 28 of 33 Bit 1 A0 SCLK_ERR_EN SCLK_ERR_FLAG S2_EN Data Sheet ADGS1208/ADGS1209 REGISTER DETAILS SWITCH DATA REGISTER Address: 0x01, Reset: 0x00, Name: SW_DATA The switch data register controls the status of the eight switches of the ADGS1208/ADGS1209 as well as the general-purpose digital outputs. Use the ADGS1208/ADGS1209 truth tables in conjunction with the bit descriptions. Table 13. Bit Descriptions for SW_DATA in the ADGS1208 Bits 7 6 5 4 3 2 1 0 Bit Name GPO4 GPO3 GPO2 GPO1 A2 A1 A0 EN Settings 0 1 Description Enable bit for GPO4. Enable bit for GPO3. Enable bit for GPO2. Enable bit for GPO1. Enable bit for A2. Enable bit for A1. Enable bit for A0. Enable bit for the ADGS1208. ADGS1208 disabled. ADGS1208 enabled. Default 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W Default 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R R/W R/W R/W Table 14. Bit Descriptions for SW_DATA ADGS1209 Bits 7 6 5 4 3 2 1 0 Bit Name GPO4 GPO3 GPO2 GPO1 Reserved A1 A0 EN Settings 0 1 Description Enable bit for GPO4. Enable bit for GPO3. Enable bit for GPO2. Enable bit for GPO1. This bit is reserved. Set this bit to 0. Enable bit for A1. Enable bit for A0. Enable bit for ADGS1209. ADGS1209 disabled. ADGS1209 enabled. Table 15. ADGS1208 Truth Table A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 Rev. 0 | Page 29 of 33 On Switch None S1 S2 S3 S4 S5 S6 S7 S8 ADGS1208/ADGS1209 Data Sheet Table 16. ADGS1209 Truth Table A1 X 0 0 1 1 A0 X 0 1 0 1 EN 0 1 1 1 1 On Switch Pair None S1 S2 S3 S4 ERROR CONFIGURATION REGISTER Address: 0x02, Reset: 0x06, Name: ERR_CONFIG The error configuration register allows the user to enable and disable the relevant error features as required. Table 17. Bit Descriptions for ERR_CONFIG Bits [7:3] 2 Bit Name Reserved RW_ERR_EN Settings 0 1 1 SCLK_ERR_EN 0 1 0 CRC_ERR_EN 0 1 Description These bits are reserved. Set these bits to 0. Enable bit for detecting an invalid read/write address. Disabled. Enabled. Enable bit for detecting the correct number of SCLK cycles in an SPI frame. 16 SCLK cycles are expected when CRC is disabled and burst mode is disabled. 24 SCLK cycles are expected when CRC is enabled and burst mode is disabled. A multiple of 16 SCLK cycles is expected when CRC is disabled and burst mode is enabled. A multiple of 24 SCLK cycles is expected when CRC is enabled and burst mode is enabled. Disabled. Enabled. Enable bit for CRC error detection. SPI frames are 24 bits wide when enabled. Disabled. Enabled. Default 0x0 0x1 Access R R/W 0x1 R/W 0x0 R/W ERROR FLAGS REGISTER Address: 0x03, Reset: 0x00, Name: ERR_FLAGS The error flags register allows the user to determine if an error occurred. To clear the error flags register, write the special 16-bit SPI command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user must include the correct CRC byte during the SPI write for the clear error flags register command to succeed. Table 18. Bit Descriptions for ERR_FLAGS Bits [7:3] 2 Bit Name Reserved RW_ERR_FLAG Settings 0 1 1 SCLK_ERR_FLAG 0 1 0 CRC_ERR_FLAG 0 1 Description These bits are reserved. Set these bits to 0. Error flag for invalid read/write address. The error flag asserts during an SPI read if the target address does not exist. The error flag also asserts when the target address of an SPI write does not exist or is read only. No error. Error. Error flag for the detection of the correct number of SCLK cycles in an SPI frame. No error. Error. Error flag that determines if a CRC error occurred during a register write. No error. Error. Rev. 0 | Page 30 of 33 Default 0x0 0x0 Access R R 0x0 R 0x0 R Data Sheet ADGS1208/ADGS1209 BURST ENABLE REGISTER Address: 0x05, Reset: 0x00, Name: BURST_EN The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI commands without deasserting CS. Table 19. Bit Descriptions for BURST_EN Bits [7:1] 0 Bit Name Reserved BURST_MODE_EN Settings 0 1 Description These bits are reserved. Set these bits to 0. Burst mode enable bit. Disabled. Enabled. Default 0x0 0x0 Access R R/W ROUND ROBIN ENABLE REGISTER Address: 0x06, Reset: 0x00, Name: ROUND_ROBIN_EN The round robin register allows the user to enable or disable round robin mode. When enabled, the user can cycle through the channels enabled in the round robin configuration register by presenting the relevant edge on the CNV pin. Table 20. Bit Descriptions for ROUND_ROBIN_EN Bits [7:1] 0 Bit Name Reserved ROUND_ROBIN_EN Settings 0 1 Description These bits are reserved. Set these bits to 0. Round robin mode enable bit. Disabled. Enabled. Default 0x0 0x0 Access R R/W ROUND ROBIN CHANNEL CONFIGURATION REGISTER Address: 0x07, Reset: 0xFF (ADGS1208), 0x0F (ADGS1209), Name: RROBIN_CHANNEL_CONFIG The round robin channel configuration register controls which channels are included a cycle during round robin mode. During round robin mode, the channels are cycled through in ascending order. Table 21. Bit Descriptions for RROBIN_CHANNEL_CONFIG (ADGS1208) Bits 7 Bit Name S8_EN Settings 0 1 6 S7_EN 0 1 5 S6_EN 0 1 4 S5_EN 0 1 3 S4_EN 0 1 2 S3_EN 0 1 Description Enable bit for S8. S8 disabled during round robin mode. S8 enabled during round robin mode. Enable bit for S7. S7 disabled during round robin mode. S7 enabled during round robin mode. Enable bit for S6. S6 disabled during round robin mode. S6 enabled during round robin mode. Enable bit for S5. S5 disabled during round robin mode. S5 enabled during round robin mode. Enable bit for S4. S4 disabled during round robin mode. S4 enabled during round robin mode. Enable bit for S3. S3 disabled during round robin mode. S3 enabled during round robin mode. Rev. 0 | Page 31 of 33 Default 0x1 Access R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W ADGS1208/ADGS1209 Bits 1 Bit Name S2_EN Data Sheet Settings 0 1 0 S1_EN 0 1 Description Enable bit for S2. S2 disabled during round robin mode. S2 enabled during round robin mode. Enable bit for S1. S1 disabled during round robin mode. S1 enabled during round robin mode. Default 0x1 Access R/W 0x1 R/W Default 0x0 0x1 Access R R/W 0x1 R/W 0x1 R/W 0x1 R/W Table 22. Bit Descriptions for RROBIN_CHANNEL_CONFIG (ADGS1209) Bits [7:4] 3 Bit Name Reserved S4_EN Settings 0 1 2 S3_EN 0 1 1 S2_EN 0 1 0 S1_EN 0 1 Description These bits are reserved. Set these bits to 0. Enable bit for S4. S4 disabled during round robin mode. S4 enabled during round robin mode. Enable bit for S3. S3 disabled during round robin mode. S3 enabled during round robin mode. Enable bit for S2. S2 disabled during round robin mode. S2 enabled during round robin mode. Enable bit for S1. S1 disabled during round robin mode. S1 enabled during round robin mode. CNV EDGE SELECT REGISTER Address: 0x09, Reset: 0x00, Name: CNV_EDGE_SEL The CNV edge select register allows the user to select the active edge of the CNV pin when the device is in round robin mode. Table 23. Bit Descriptions for CNV_EDGE_SEL Bits [7:1] 0 Bit Name Reserved CNV_EDGE_SEL Settings 0 1 Description These bits are reserved. Set these bits to 0. CNV active edge select bit. Falling edge of CNV is the active edge. Rising edge of CNV is the active edge. Default 0x0 0x0 Access R R/W SOFTWARE RESET REGISTER Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB Use the software reset register to perform a software reset. Consecutively, write 0xA3 followed by 0x05 to this register, and the registers of the device reset to their default state. Table 24. Bit Descriptions for SOFT_RESETB Bits [7:0] Bit Name SOFT_RESETB Settings Description To perform a software reset, consecutively write 0xA3 followed by 0x05 to this register. Rev. 0 | Page 32 of 33 Default 0x0 Access R Data Sheet ADGS1208/ADGS1209 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 1 0.50 BSC 2.70 2.60 SQ 2.50 EXPOSED PAD 13 TOP VIEW 0.80 0.75 0.70 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PKG-004273/5069 0.50 0.40 0.30 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 18 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8 03-02-2017-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.75 mm Package Height (CP-24-15) Dimensions shown in millimeters ORDERING GUIDE Model1 ADGS1208BCPZ ADGS1208BCPZ-RL7 ADGS1209BCPZ ADGS1209BCPZ-RL7 EVAL-ADGS1208SDZ EVAL-ADGS1209SDZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] ADGS1208 Evaluation Board ADGS1209 Evaluation Board Z = RoHS Compliant Part. (c)2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16724-0-4/18(0) Rev. 0 | Page 33 of 33 Package Option CP-24-15 CP-24-15 CP-24-15 CP-24-15