ISL54502IRUZ-T - Intersil Corporation

ISL54501, ISL54502

+1.8V to +5.5V, 5Ω, Single SPST Analog Switches

ISL54501, ISL54502

The Intersil ISL54501 and ISL54502 devices are low

ON-resistance, low voltage, bi-directional, single

pole/single throw (SPST) analog switches designed to

operate from a single +1.8V to +5.5V supply . Targeted

applications include battery powered equipment that

benefit from low rON resistance (5Ω), excellent rON

flatness, and fast switching speeds (tON = 22ns, tOFF

= 15ns). The digital logic input is 1.8V CMOS

compatible when using a single +3V supply.

Cell phones, for example, often face ASIC functionality

limitations. The number of analog input or GPIO pins

may be limited and digital geometries are not well

suited to analog switch performance. This family of

parts may be used to switch in additional functionalit y

while reducing ASIC design risk. The ISL54501,

ISL54502 are offered in a 6 Ld 1.2mmx1.0mmx0.4mm

pitch µTDFN package, alleviating board space

limitations.

The ISL54501 has one normally open (NO) switch and

ISL54502 has one normally closed (NC) switch.

Features

• ON-resistance (rON)

-V

CC = +5.0V . . . . . . . . . . . . . . . . . . . . . 5.0Ω

-V

CC = +3.0V . . . . . . . . . . . . . . . . . . . . . 7.0Ω

-V

CC = +1.8V . . . . . . . . . . . . . . . . . . . . . 13Ω

•r

ON Flatness (+4.5V Supply) . . . . . . . . . . . . . 1.1Ω

• Single Supply Operation . . . . . . . . +1.8V to +5.5V

• Fast Switching Action (+4.5V Supply)

-t

ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22ns

-t

OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns

• ESD HBM Ra ting . . . . . . . . . . . . . . . . . . . . . . . 6kV

• 1.8V CMOS Logic Compatible (+3V supply)

• Available in 6 Ld µTDFN and 6 Ld SOT-23 Packages

• Pb-free Available (RoHS compliant)

Applications

• Battery powered, handheld, and portable

equipment

- Cellular/mobile phones

-Pagers

- Laptops, notebooks, palmtops

• Portable Test and Measurement

•Medical Equipment

• Audio and video switching

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount

Devices (SMDs)”

TABLE 1. FEATU R ES AT A GLANCE

ISL54501 ISL54502

NUMBER OF

SWITCHES 11

SW NO NC

1.8V rON 12Ω12Ω

1.8V tON/tOFF 70ns/52ns 70ns/52ns

3V rON 6.0Ω6.0Ω

3V tON/tOFF 30ns/20ns 30ns/20ns

5V rON 5.0Ω5.0Ω

5V tON/tOFF 22ns/15ns 22ns/15ns

Packages 6 Ld µTDFN, 6 Ld SOT-23

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a regi s tered trademark of Inters il Amer ic as Inc .

All other trademarks mentioned are the property of their respective owners.

October 26, 2009

FN6550.2

2FN6550.2

October 26, 2009

Ordering Information

PART NUMBER

(Notes 1, 4) PART

MARKING TEMP. RANGE

(°C)

PACKAGE

(Tape and Reel)

(Pb-Free) PKG.

DWG. #

ISL54501IRUZ-T (Note 2) 1 -40 to +85 6 Ld µTDFN L6.1.2x1.0A

ISL54501IHZ-T (Note 3) 4501 -40 to +85 6 Ld SOT-23 MDP0038

ISL54502IRUZ-T (Note 2) 2 -40 to +85 6 Ld µTDFN L6.1.2x1.0A

ISL54502IHZ-T (Note 3) 4502 -40 to +85 6 Ld SOT-23 MDP0038

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb -free plast ic packaged produ cts emplo y special Pb-free material sets; molding compounds/die attach

materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

3. These Intersil Pb -free plast ic packaged produ cts emplo y special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temper atures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD -020.

4. For Moisture Sensitivity Level (MSL), please see device information page for ISL54501, ISL54502. F or more i nformation on

MSL please see tech brie f TB363.

ISL54501, ISL54502

3FN6550.2

October 26, 2009

Pin Configurations (Note 5)

ISL54501

(6 LD µTDFN)

TOP VIEW

ISL54502

(6 LD µTDFN)

TOP VIEW

ISL54501

(6 LD SOT-23)

TOP VIEW

ISL54502

(6 LD SOT-23)

TOP VIEW

NOTE:

5. Switches Shown for Logic “0” Input.

V+

GND

N.C. COM 3

V+

GND

N.C.

COM

N.C.

GND

V+

COM

N.C.

GND

V+

COM

Pin Descriptions

PIN FUNCTION

V+ System Power Supply Input (+1.8V to +5.5V)

GND Ground Connection

IN Digital Control Input

COM Analog Switch Common Pin

NO Analog Switch Normally Open Pin

NC Analog Switch Normally Closed Pin

N.C. No Connect

Truth Table

LOGIC ISL54501 ISL54502

0OffOn

1OnOff

NO T E: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

ISL54501, ISL54502

4FN6550.2

October 26, 2009

Absolute Maximum Ratings Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.5V

Input Voltages

NO, NC, IN (Note 6) . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)

Output Voltages

COM (Note 6) . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)

Continuous Current NO, NC, or COM. . . . . . . . . . . .±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10 % Duty Cycle, Max) . . . . . . . . . . . . . . . . . ±600mA

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >6k V

Machine Mo del . . . . . . . . . . . . . . . . . . . . . . . . . . >200V

Charged Device Model . . . . . . . . . . . . . . . . . . . . .>2.2kV

Thermal Resistance (Typical) θJA (°C/W) θJC(°C/W)

6 Ld µTDFN Pkg. (Notes 7, 9) . . . . 239.2 111.6

6 Ld SOT-23 Pkg. (Note 8, 9). . . . . 260 120

Maximum Junction Temperature (Plastic Package). . +150°C

Maximum Storage Temperature Range. . . . . -65°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

V+ (Positive DC Supply Voltage). . . . . . . . . . . 1.8V to 5.5V

Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . 0V to V+

VIN (Digital Logic Input Voltage (IN) . . . . . . . . . . . 0V to V+

Temperature Range. . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warrant y.

NOTES:

6. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum

current ratings.

7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”

features. See Tech Brief TB379.

8. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief

TB379 for details.

9. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V

(Note 10), Unless Otherwise Specified. Boldface limits apply over the operat-

ing temperature range, -40°C to +85°C.

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 11, 12) TYP MAX

(Notes 11, 12) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

VANALOG Full 0-V+ V

ON-Resistance, rON V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V

to V+, (Note 14, see Figure 4) 25 -4.2 5Ω

Full --6Ω

rON Flatness, rFLAT(ON) V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V

to V+, (Not es 1 3 , 14) 25 -1.1 1.3 Ω

Full --1.5 Ω

NO or NC OFF Leakage

Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 0.3V, 5V, VNO or

VNC =5V, 0.3V 25 -25 1.2 25 nA

Full -150 -150 nA

COM ON Leakage Current,

ICOM(ON) V+ = 5.5V, VCOM = 0.3V, 5V, or VNO or

VNC = 0.3V, 5V, or Floating 25 -30 1.7 30 nA

Full -300 -300 nA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω,

CL= 35pF (see Figure 1, Note 14) 25 -22 -ns

Full -23 -ns

Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω,

CL= 35pF (see Figure 1, Note 14) 25 -15 -ns

Full -15 -ns

Break-Before-Make Time

Delay, tDV+ = 5.5V, VNO or VNC = 3.0V, RL = 50Ω,

CL= 35pF (see Figure 3, Note 14) Full -18 -ns

Charge Injection, Q VG = 0V, RG = 0Ω, CL = 1.0nF (see Figure 2) 25 -16 -pC

OFF-Isolation L = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VP-P

(see Figure 3) 25 -75 -dB

Total Harmonic Distortion f = 20Hz to 20kHz, V COM = 2VP-P, RL = 32Ω25 -0.12 -%

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω25 -0.01 -%

-3dB Bandwidth Signal = 0dBm, RL = 50Ω25 -350 -MHz

ISL54501, ISL54502

5FN6550.2

October 26, 2009

NO or NC OFF Capaci tance,

COFF V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM

=0V (see Figure 5) 25 -6-pF

COM ON Capacitance,

CCOM(ON) V+ = 4.5V, f = 1MHz, VNO or

VNC =V

COM = 0V (see Figure 5) 25 -12 -pF

POWER SUPPLY CHARACTERISTICS

Power Supply Range Full 1.8 -5.5 V

Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+ 25 -0.02 0.1 µA

Full -0.5 2.5 µA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL Full --0.8 V

Input Voltage High, VINH Full 2.4 --V

Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Full -0.1 0.04

40.1 µA

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V

(Note 10), Unless Otherwise Specified. Boldface limits apply over the operat-

ing temperature range, -40°C to +85°C.

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 11, 12) TYP MAX

(Notes 11, 12) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

VANALOG Full 0-V+ V

ON-Resistance, rON V+ = 2.7V, ICOM = 100mA, VNO or

VNC = 0V to V+,

(Note 14, see Figure 4)

25 -6.3 7Ω

Full --8Ω

rON Flatness, rFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or

VNC = 0V to V+, (Notes 13, 14) 25 -1.8 2.3 Ω

Full --2.5 Ω

DYNAMIC CHAR AC TERISTICS

Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω,

CL = 35pF (see Figure 1, Note 8) 25 -28 -ns

Full -30 -ns

Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω,

CL = 35pF (see Figure 1, Note 14) 25 -20 -ns

Full -30 -ns

Charge Injection, Q VG = 0V, RG = 0Ω,CL = 1.0nF

(see Figure 2) 25 -12 -pC

OFF-Isolation RL = 50Ω, CL = 5pF, f = 1MHz,

VCOM =1V

P-P (see Figure 3) 25 -75 -dB

T otal Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω25 -0.4 -%

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P,

RL= 600Ω

25 -0.053 -%

-3dB Bandwidth Signal = 0dBm, RL = 50Ω25 -350 -MHz

NO or NC OFF Capacitance,

COFF f = 1MHz, VNO or VNC = VCOM = 0V

(see Figure 5) 25 -6-pF

COM OFF Capacitance,

CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V

(see Figure 5) 25 -10 -pF

COM ON Capacitance,

CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V

(see Figure 5) 25 -12 -pF

Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V

(Note 10), Unless Otherwise Specified. Boldface limits apply over the operat-

ing temperature range, -40°C to +85°C. (Continue d)

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 11, 12) TYP MAX

(Notes 11, 12) UNITS

ISL54501, ISL54502

6FN6550.2

October 26, 2009

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ 25 -0.02 -µA

Full -0.11 -µA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL Full --0.5 V

Input Voltage High, VINH Full 1.4 --V

Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Full -0.1 0.049 0.1 µA

Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 10),

Unless Otherwise Specified. Boldface limits apply over the operating tem-

perature range, -40°C to +85°C.

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 11, 12) TYP MAX

(Notes 11, 12) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

VANALOG Full 0-V+ V

ON-Resistance, rON V+ = 1.8V, ICOM = 10mA, VNO or

VNC = 0V to V+(Note 14 , s ee Figure 4) 25 -11.9 12.8 Ω

Full --13.8 Ω

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 1.8V, VNO or VNC = 1.5V, RL =50Ω,

CL = 35pF (see Figure 1, Note 14) 25 -70 -ns

Full -130 -ns

Turn-OFF Time, tOFF V+ = 1.8V, VNO or VNC = 1.5V, RL =50Ω,

CL = 35pF (see Figure 1, Note 14) 25 -52 -ns

Full -100 -ns

Charge Injection, Q VG = V+/2, RG = 0Ω, CL = 1.0nF

(see Figure 2) 25 -5.8 -pC

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL Full --0.4V

Input Voltage High, VINH Full 1--V

NOTES:

10. VIN = input voltage to perform proper function.

11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, i s used in this data

sheet.

12. P arameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established

by characterization and are not production tested.

13. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal

range.

14. Limits established by characterization and are not production tested.

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V

(Note 10), Unless Otherwise Specified. Boldface limits apply over the operat-

ing temperature range, -40°C to +85°C. (Continued)

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 11, 12) TYP MAX

(Notes 11, 12) UNITS

ISL54501, ISL54502

7FN6550.2

October 26, 2009

Test Circuits and Waveforms

Logic input waveform is inverted for switches that have the

opposite logic sense.

FIGURE 1A. MEASUREMENT POINTS

Repeat test for all switches. CL includes fixture and stray

capacitance.

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

FIGURE 3. OFF ISOLATION TEST CIRCUIT FIGURE 4. rON TEST CIRCUIT

50%

tr < 20ns

tf < 20ns

tOFF

90%

V+

VNO

tON

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

90%

VOUT

VOUT V(NO or NC) RL

RLrON()

----------------------------

SWITCH

INPUT

LOGIC

INPUT

VOUT

RL CL

COM

NO or NC

50Ω35pF

GND

V+ C

VOUT

ΔVOUT

ON OFF ON

Q = ΔVOUT x CL

SWITCH

OUTPUT

LOGIC

INPUT

VINH

VINL

VOUT

VGGND

COM

NO OR NC

V+ C

LOGIC

INPUT

ANALYZER

SIGNAL

GENERATOR

V+ C

0V OR V+

NO OR NC

COM

GND

V+

VINL OR VINH

NO OR NC

COM

GND

VNX

100mA

rON = V1/I1 *

* I1 = 10mA AT V+ = 1.8V

ISL54501, ISL54502

8FN6550.2

October 26, 2009

Detailed Description

The ISL54501 and ISL54502 are bi-directional, single

pole/single throw (SPST) analog switches. They offer

precise switching capability from a single 1.8V to 5.5V

supply with low ON-resistance and high speed

operation. With a single supply of 5V the typical

ON-resistance is only 5Ω, with a typical turn-on and

turn-off time of: tON = 22ns, tOFF = 15ns. The

devices are especially well suited for portable battery

powered equipment due to their low operating supply

voltage (1.8V), low power consumption (0.11µW), low

leakage curren ts (30 0nA max) , and ti n y µ T D F N

package.

The ISL54501 is a single normally open (NO) SPST

analog switch. The ISL54502 is a single normally

closed (NC) SPST analog switch.

External V+ Series Resistor

For impro ved ESD and latch-up immunity, Intersil

recommends adding a 100Ω resistor in series with the

V+ power supply pin of the ISL54501, ISL54502 IC

(see Figure 6).

During an overvoltage tr ansient ev ent (such as occurs

during system level IEC 61000 ESD testing), substrate

currents can be generated in the IC that can trigger

parasitic SCR structures to turn ON, creating a low

impedance path from the V+ power supply to ground.

This will result in a significant amount of current flow in

the IC, which can potentially create a latch-up state or

permanently damage the IC. The external V+ resistor

limits the current during this over -stress situation and

has been found to prevent latch-up or destructive

damage for many over voltage transient events.

Under normal operation the sub-microamp IDD current

of the IC produces an insignificant voltage drop across

the 100Ω series resistor resulting in no impact to

switch operation or performance.

Supply Sequencing And Overvoltage

Protection

With any CM OS device, proper powe r supply

sequencing is required to protect the device from

excessive input currents, which might permanently

damage the IC. All I/O pins contain ESD protection

diodes from the pin to V+ and to GND (see Figure 7).

To prevent forward biasing these diodes, V+ must be

applied before any input signals, and the input signal

voltages must remain between V+ and GND .

If these conditions cannot be guaranteed then

precautions must be implemented to prohibit the

current and voltage at the logic pin and signal pins

from exceeding the maximum ratings of the switch.

The following two methods can be used to pro vided

additional protection to limit the current in the ev ent

that the voltage at a signal pin or logic pin goes below

ground or above the V+ r ail.

Logic inputs can easily be protected by adding a 1kΩ

resistor in series with the input (see Figure 7). The

resistor limits the input current below the threshold

FIGURE 5. CAPACITANCE TEST CIRCUIT

Test Circuits and Waveforms (Continued)

V+ C

GND

NO OR NC

COM

IMPEDANCE

ANALYZER

VINL OR VINH

FIGURE 6. V+ SERIES RESISTOR FOR ENHANCED

ESD AND LATCH-UP IMMUNITY

COM

100Ω

V+

GND

OPTIONAL

PROTECTION

RESISTOR

ISL54501, ISL54502

9FN6550.2

October 26, 2009

that produces permanent damage, and the

sub-microamp input current produces an insignificant

voltage drop during normal oper ation.

This method is not acceptable for the signal path

inputs. Adding a series resistor to the switch input

defeats the purpose of using a low rON switch.

Connecting Schottky diodes to the signal pins (as

shown in Figure 9) will shunt the fault current to the

supply or to ground, thereby protecting the switch.

These Schottky diodes must be sized to handle the

expected fault current.

Power-Supply Considerations

The ISL54501, ISL54502 construction is typical of

most single supply CMOS analog switches in that they

have two supply pins: V+ and GND. V+ and GND drive

the internal CMOS switches and set their analog

voltage limits. Unlike switches with a 4V maximum

supply voltage, the ISL54501, ISL54502 5.5V

maximum supply voltage provides plenty of room for

the 10% tolerance of 3.6V supplies, as well as room for

overshoot and noise spikes.

The minimum recommended supply voltage is 1.8V but

the part will operate with a supply below 1.8V. It is

important to note that the input signal range, switching

times, and ON-resistance degrade at lower supply

voltages. Re fer to the “Electrical Specifications” tables

starting on page 4 the and “Typical Perform ance

Curves” starting on page 10 for details.

V+ and GND also power the internal logic and level

shiftier. The level shiftier converts the input logic levels

to switched V+ and GND signals to drive the an alog

switch gate terminals.

This family of switches cannot be operated with bipolar

supplies, because the input switching point becomes

negative in this configuration.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and

1.4V) over a supply range of 2V to 3.6V

(see Figure 14). At 3.6V the VIH level is about 0.98V.

This is still below the 1.8V CMOS guaranteed high

output minimum level of 1.4V, but noise margin is

reduced.

The digital input stages draw supply current whenever

the digital input voltage is not at one of the supply

rails. Driving the digital input signals from GND to V+

with a fast transition time minimizes power dissipation.

High-Frequency Performance

In 50Ω systems, the ISL54501, ISL54502 has a -3dB

bandwidth of 350MHz (see Figure 15). The frequency

response is very consistent over a wide V+ range, and

for varying an alog signal levels.

An OFF switch behaves like a capacitor and passes

higher frequencies with less attenuation, resulting in

signal feedthrough from a switch’s input to output. Off

isolation is the resistance of this signal feedthrough.

Figure 16 details the high off isolation provided by the

ISL54501, ISL54502. At 1MHz, off isolation is about

75dB in 50Ω systems, decreasing approximately 20dB

per decade as frequency increases. Higher load

impedances decrease off isolation due to the voltage

divider action of the switch OFF impedance and the

load impedance.

Leakage Considerations

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND.

One of these diodes conducts if any analog signal

exceeds V+ or GND.

Virtually all the analog leakage current comes from the

ESD diodes to V+ or GND. Although the ESD diodes on

a given signal pin are identical and therefore fairly well

balanced, they are reverse biased differently. Each is

biased by either V+ or GND and the analog signal. This

means their leakages will v ary as the signal v aries. The

difference in the two diode leakages to the V+ and

GND pins constitutes the analog-signal-path leakage

current. All analog leakage current flows between each

pin and one of the supply terminals, not to the other

switch terminal. This is why both sides of a given

switch can show leakage currents of the same or

opposite polarity. There is no connection between the

analog signal paths and V+ or GND .

FIGURE 7. OVERVOLTAGE PROTECTION

GND

VCOM

VNX

V+

INX

OPTIONAL

PROTECTION

RESISTOR

OPTIONAL

SCHOTTKY

DIODE

OPTIONAL

SCHOTTKY

DIODE

ISL54501, ISL54502

10 FN6550.2

October 26, 2009

Typical Performance Curves TA = +25°C, Unless Otherwise Specified

FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLT AGE FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE

FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 11. ON-RESISTANC E vs SWITCH VOLTAGE

FIGURE 12. TURN-ON TIME vs SUPPLY VOLTAGE FIGURE 13. TURN-OFF TIME vs SUPPLY VOLTAGE

rON (Ω)

VCOM (V)

012345

8ICOM = 100mA

V+ = 2.7V

V+ = 3V

V+ = 4.5V

V+ = 5V

rON (Ω)

VCOM (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

ICOM = 100mA

+25°C

+85°C

-40°C

V+ = 4.5V

rON (Ω)

VCOM (V)

0 0.5 1.0 1.5 2.0 2.5

+25°C

+85°C

-40°C

V+ = 2.7V

ICOM = 100mA

rON (Ω)

VCOM (V)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

V+ = 1.8V

ICOM = 10mA

+85°C

-40°C

+25°C

tON (ns)

V+ (V)

100

110

120

130

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

+25°C

-40°C

+85°C

tOFF (ns)

V+ (V)

100

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

+25°C

-40°C

+85°C

ISL54501, ISL54502

11 FN6550.2

October 26, 2009

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

PROCESS:

Submicron CMOS

FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY

VOLTAGE FIGURE 15. FREQUENCY RESPONSE

FIGURE 16. OFF ISOLATION F IGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE

Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)

V+ (V)

VINH AND VINL (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VINH

VINL

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

100k 1M 10M 100M 1G

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

V+ = 1.8V TO 5.5V

VCOM = 1VP-P

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

(dB)

V+ = 1.8V T O 5. 5V

VCOM (V)

-6

-1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

V+ = 3V

V+ = 1.8V

V+ = 5V

Q (pC)

ISL54501, ISL54502

12 FN6550.2

October 26, 2009

ISL54501, ISL54502

Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)

0.10 C

PIN 1

TOP VI EW

0.10 C

REFERENCE

DETAIL A

0.10 C

0.08 C

A3A1

SEATING

PLANE

BOTTOM VIEW

SIDE VIEW

0.10 CAB

0.05 C

b6X

NOTE 3

DETAIL A DETAIL B PIN 1 LEAD

0.1x45°

CHAMFER

DETAIL B

1.40

LAND PA TTERN

1.00

0.30

0.35

0.20

0.45

0.40

0.20

L6.1.2x1.0A

6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

0.45 0.50 0.55

- - 0.05

0.127 REF

0.15 0.20 0.25

0.95 1.00 1.05

1.15 1.20 1.25

0.40 BSC

0.30 0.35 0.40

0.40 0.45 0.50

0-12

Rev. 2 8/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Ne refers to the number of terminals on E side.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located wi thin the zone indicated. The pin #1 identif ier may be

either a mold or mark feature.

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil produc ts are sol d by desc rip tio n o nly . Intersil Corporation reserves the rig ht to make ch ange s in c irc uit design, software and/or specifications

at any time without n oti ce. Acco rdin gly, the reader is cautioned to verify that data sheets are current before placing orders. Informatio n furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of t hird parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil o r i ts s ub si di arie s .

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6550.2

October 26, 2009

For additional products, see www.intersil.com/product_tree

ISL54501, ISL54502

SOT-23 Package Family

321

0.15 DC

2X 0.20 C

B0.20 MDC A-B

2 3

SEATING

PLANE

0.10 C

1 3

0.15 A-BC

(L1)

0.25

0° +3°

-0°

GAUGE

PLANE

MDP0038

SOT-23 PACKAGE FAMILY

SYMBOL

MILLIMETERS

TOLERANCESOT23-5 SOT23-6

A 1.45 1.45 MAX

A1 0.10 0.10 ±0.05

A2 1.14 1.14 ±0.15

b 0.40 0.40 ±0.05

c 0.14 0.14 ±0.06

D 2.90 2.90 Basic

E 2.80 2.80 Basic

E1 1.60 1.60 Basic

e 0.95 0.95 Basic

e1 1.90 1.90 Basic

L 0.45 0.45 ±0.10

L1 0.60 0.60 Reference

N 5 6 Reference

Rev. F 2/07

NOTES:

1. Plastic or metal protrusions of 0.25mm maximum per side are not

included.

2. Plastic interlead protrusions of 0.25mm maximum per side are not

included.

3. This dimension is measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Index area - Pin #1 I.D. will be located within the indicated zone

(SOT23-6 only).

6. SOT23-5 version has no center lead (shown as a dashed line).