GS8182R08/09/18/36BD-400/375/333/300/250/200/167
18Mb SigmaDDR-II™
Burst of 4 SRAM
400 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.04c 11/2011 1/37 © 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• Simultaneous Read and Write SigmaDDR-II™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDR-II™ Family Overview
The GS8182R08/09/18/36BD are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. The GS8182R08/09/18/36BD SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8182R08/09/18/36BD SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaDDR-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 and A1 are used to initialize the pointers that control
the data multiplexer / de-multiplexer so the RAM can perform
"critical word first" operations. From an external address point
of view, regardless of the starting point, the data transfers
always follow the same linear sequence {00, 01, 10, 11} or
{01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where
the digits shown represent A1, A0).
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B4 RAMs are two address pins less than the advertised index
depth (e.g., the 2M x 8 has a 512K addressable index, and A0
and A1 are not accessible address pins).
Parameter Synopsis
-400 -375 -333 -300 -250 -200 -167
tKHKH 2.5 ns 2.67 ns 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns
tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.5 ns
512K x 36 SigmaDDR-II SRAM—Top View
12345678910 11
A CQ NC/SA
(144Mb)
NC/SA
(36Mb) R/WBW2 KBW1 LD SA NC/SA
(72Mb) CQ
B NC DQ27 DQ18 SA BW3 KBW0 SA NC/SA
(288Mb) NC DQ8
C NC NC DQ28 VSS SA SA0 SA1 VSS NC DQ17 DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6
F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5
G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4
K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3
L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2
M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1
N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10
P NC NC DQ26 SA SA CSA SA NC DQ9 DQ0
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35.
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 2/37 © 2007, GSI Technology
1M x 18 SigmaDDR-II SRAM—Top View
12345678910 11
A CQ NC/SA
(72Mb) SA R/WBW1 KNC/SA
(144Mb) LD SA NC/SA
(36Mb) CQ
B NC DQ9 NC SA NC/SA
(288Mb) KBW0 SA NC NC DQ8
C NC NC NC VSS SA SA0 SA1 VSS NC DQ7 NC
D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6
F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5
G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC
K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3
L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2
M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC
N NC NC DQ16 VSS SA SA SA VSS NC NC NC
P NC NC DQ17 SA SA CSA SA NC NC DQ0
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 3/37 © 2007, GSI Technology
2M x 9 SigmaDDR-II SRAM—Top View
12345678910 11
A CQ NC/SA
(72Mb) SA R/WNC KNC/SA
(144Mb) LD SA NC/SA
(36Mb) CQ
B NC NC NC SA NC/SA
(288Mb) KBW SA NC NC DQ4
C NC NC NC VSS SA NC SA VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ5 VDDQ VSS VSS VSS VDDQ NC NC DQ3
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC NC DQ6 VDDQ VDD VSS VDD VDDQ NC NC NC
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ2 NC
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC DQ7 NC VDDQ VSS VSS VSS VDDQ NC NC DQ1
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS SA SA SA VSS NC NC NC
P NC NC DQ8 SA SA CSA SA NC NC DQ0
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0.
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 4/37 © 2007, GSI Technology
2M x 8 SigmaDDR-II SRAM—Top View
12345678910 11
A CQ NC/SA
(72Mb) SA R/WNW1 KNC/SA
(144Mb) LD SA NC/SA
(36Mb) CQ
B NC NC NC SA NC/SA
(288Mb) KNW0 SA NC NC DQ3
C NC NC NC VSS SA NC SA VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC DQ6 NC VDDQ VSS VSS VSS VDDQ NC NC DQ0
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS SA SA SA VSS NC NC NC
P NC NC DQ7 SA SA CSA SA NC NC NC
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to
0 at the beginning of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7.
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 5/37 © 2007, GSI Technology
Pin Description Table
Symbol Description Type Comments
SA Synchronous Address Inputs Input —
R/WRead/Write Control Pin Input Write Active Low; Read Active High
BW0–BW3 Synchronous Byte Writes Input Active Low
x18/x36 only
NW0–NW1 Nybble Write Control Pin Input Active Low
x8 only
BW Byte Write Control Pin Input Active Low
x9 only
LD Synchronous Load Pin Input Active Low
KInput Clock Input Active High
KInput Clock Input Active Low
COutput Clock Input Active High
COutput Clock Input Active Low
TMS Test Mode Select Input —
TDI Test Data Input Input —
TCK Test Clock Input Input —
TDO Test Data Output Output —
VREF HSTL Input Reference Voltage Input —
ZQ Output Impedance Matching Input Input —
DQ Data I/O Input/Output Three State
Doff Disable DLL when low Input Active Low
CQ Output Echo Clock Output —
CQ Output Echo Clock Output —
VDD Power Supply Supply 1.8 V Nominal
VDDQ Isolated Output Buffer Supply Supply 1.5 V or 1.8 V Nominal
VSS Power Supply: Ground Supply —
NC No Connect — —
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 6/37 © 2007, GSI Technology
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. C, C, K, K cannot be set to VREF voltage.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 7/37 © 2007, GSI Technology
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are
unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in
the timing diagrams. This means that it is possible to load new addresses every other K clock cycle. Addresses can be loaded less
often, if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z.A high on the LD pin prevents the RAM from
loading read or write command
inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.
SigmaDDR-II B4 SRAM Read Cycles
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. Because the device executes a four beat burst
transfer in response to a read command, if the previous command captured was a read or write command, the Address, LD and R/
W pins are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes
pipelined reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM
produces data out in response to the next rising edge of C (or the next rising edge of K, if C and C are tied high). The second beat
of data is transferred on the next rising edge of C, then on the next rising edge of C and finally on the next rising edge of C, for a
total of four transfers per address load.
SigmaDDR-II B4 SRAM Write Cycles
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. Because the device executes a four beat burst
transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD and R/
W pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is
checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the
rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst
of four write transfer the SRAM captures data in on the next rising edge of K, the following rising edge of K and finally on the next
rising edge of K, for a total of four transfers per address load.
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Rev: 1.04c 11/2011 8/37 © 2007, GSI Technology
Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. Apply VDD.
1b. Apply VDDQ.
1c. Apply VREF (may also be applied at the same time as VDDQ).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note:
If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 ns to reset the DLL after
the clocks become stablized.
DLL Constraints
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter . The DLL cannot operate at a
frequency lower than that specified by the tKHKH maximum specification for the desired operating clock frequency.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause
undefined errors or failures during the initial stage.
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 9/37 © 2007, GSI Technology
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device,
“Nybble Write Enable” and “NBx” may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time BW0 BW1 D0–D8 D9–D17
Beat 1 0 1 Data In Don’t Care
Beat 2 1 0 Don’t Care Data In
Beat 3 0 0 Data In Data In
Beat 4 1 0 Don’t Care Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Written Unchanged Unchanged Written Written Written Unchanged Written
Beat 1 Beat 2 Beat 3 Beat 4
Output Register Control
SigmaDDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
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Rev: 1.04c 11/2011 10/37 © 2007, GSI Technology
Example Four Bank Depth Expansion Schematic
A
K
LD
R/W
A0–An
K
R0/W0
Bank 0 Bank 1 Bank 2 Bank 3
LD0
A
K
R/W
A
K
R/W
A
K
R/W
LD LD LD
DQ DQ DQ DQ
R1/W1
LD1
R2/W2
LD2
R3/W3
LD3
Note:
For simplicity BWn not shown.
CQ CQ CQ CQ
CQ0
CQ1
CQ2
CQ3
DQ1-DQn
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Rev: 1.04c 11/2011 11/37 © 2007, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaDDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and tempera-
ture. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may
move the output driver impedance level one step at a time towards the optimum level.
Common I/O SigmaDDR-II B4 SRAM Truth Table
KnLD R/W
DQ
Operation
A + 0 A + 1 A + 2 A + 3
↑1 X Hi-Z Hi-Z Hi-Z Hi-Z Deselect
↑0 0 D@Kn+1 D@Kn+1 D@Kn+2 D@Kn+2 Write
↑0 1
Q@Kn+1
or
Cn+1
Q@Kn+2
or
Cn+2
Q@Kn+2
or
Cn+2
Q@Kn+3
or
Cn+3
Read
Note:
Q is controlled by K clocks if C clocks are not used.
B4 Byte Write Clock Truth Table
BW BW BW BW Current Operation D D D D
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
K ↑
(tn)
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
T T T T Write
Dx stored if BWn = 0 in all four data transfers D0 D2 D3 D4
T F F F Write
Dx stored if BWn = 0 in 1st data transfer only D0 X X X
F T F F Write
Dx stored if BWn = 0 in 2nd data transfer only XD1 X X
F F T F Write
Dx stored if BWn = 0 in 3rd data transfer only X X D2 X
F F F T Write
Dx stored if BWn = 0 in 4th data transfer only X X X D3
F F F F Write Abort
No Dx stored in any of the four data transfers X X X X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
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Rev: 1.04c 11/2011 12/37 © 2007, GSI Technology
B4 Nybble Write Clock Truth Table
NW NW NW NW Current Operation D D D D
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
K ↑
(tn)
K ↑
(tn+1)
K ↑
(tn+1½)
K ↑
(tn+2)
K ↑
(tn+2½)
T T T T Write
Dx stored if NWn = 0 in all four data transfers D0 D2 D3 D4
T F F F Write
Dx stored if NWn = 0 in 1st data transfer only D0 X X X
F T F F Write
Dx stored if NWn = 0 in 2nd data transfer only XD1 X X
F F T F Write
Dx stored if NWn = 0 in 3rd data transfer only X X D2 X
F F F T Write
Dx stored if NWn = 0 in 4th data transfer only X X X D3
F F F F Write Abort
No Dx stored in any of the four data transfers X X X X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
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Rev: 1.04c 11/2011 13/37 © 2007, GSI Technology
x36 Byte Write Enable (BWn) Truth Table
BW0 BW1 BW2 BW3 D0–D8 D9–D17 D18–D26 D27–D35
1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care
0 1 1 1 Data In Don’t Care Don’t Care Don’t Care
1 0 1 1 Don’t Care Data In Don’t Care Don’t Care
0 0 1 1 Data In Data In Don’t Care Don’t Care
1 1 0 1 Don’t Care Don’t Care Data In Don’t Care
0 1 0 1 Data In Don’t Care Data In Don’t Care
1 0 0 1 Don’t Care Data In Data In Don’t Care
0 0 0 1 Data In Data In Data In Don’t Care
1 1 1 0 Don’t Care Don’t Care Don’t Care Data In
0 1 1 0 Data In Don’t Care Don’t Care Data In
1 0 1 0 Don’t Care Data In Don’t Care Data In
0 0 1 0 Data In Data In Don’t Care Data In
1 1 0 0 Don’t Care Don’t Care Data In Data In
0 1 0 0 Data In Don’t Care Data In Data In
1 0 0 0 Don’t Care Data In Data In Data In
0 0 0 0 Data In Data In Data In Data In
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1 D0–D8 D9–D17
1 1 Don’t Care Don’t Care
0 1 Data In Don’t Care
1 0 Don’t Care Data In
0 0 Data In Data In
x8 Nybble Write Enable (NWn) Truth Table
NW0 NW1 D0–D3 D4–D7
1 1 Don’t Care Don’t Care
0 1 Data In Don’t Care
1 0 Don’t Care Data In
0 0 Data In Data In
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Rev: 1.04c 11/2011 14/37 © 2007, GSI Technology
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 2.9 V
VDDQ Voltage in VDDQ Pins –0.5 to VDD V
VREF Voltage in VREF Pins –0.5 to VDDQ V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V
IIN Input Current on Any Pin +/–100 mA dc
IOUT Output Current on Any I/O Pin +/–100 mA dc
TJMaximum Junction Temperature 125 oC
TSTG Storage Temperature –55 to 125 oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
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Rev: 1.04c 11/2011 15/37 © 2007, GSI Technology
Recommended Operating Conditions
Power Supplies
Parameter Symbol Min. Typ. Max. Unit
Supply Voltage VDD 1.7 1.8 1.9 V
I/O Supply Voltage VDDQ 1.4 —1.9 V
Reference Voltage VREF 0.68 —0.95 V
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ VDDQ ≤ 1.6 V (i.e., 1.5 V I/O)
and 1.7 V ≤ VDDQ ≤ 1.9 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The
power down sequence must be the reverse. VDDQ must not exceed VDD.
Operating Temperature
Parameter Symbol Min. Typ. Max. Unit
Ambient Temperature
(Commercial Range Versions) TA025 70 °C
Ambient Temperature
(Industrial Range Versions) TA–40 25 85 °C
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HSTL I/O DC Input Characteristics
Parameter Symbol Min Max Units Notes
DC Input Logic High VIH (dc) VREF + 0.10 VDDQ + 0.3 V V1, 4
DC Input Logic Low VIL (dc) –0.3 V VREF – 0.10 V1, 3
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers.
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
3. VIL (Min) DC = –0.3 V, VIL(Min) AC = –1.5 V (pulse width ≤ 3 ns).
4. VIH (Max) DC = VDDQ + 0.3 V, VIH(Max) AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
HSTL I/O AC Input Characteristics
Parameter Symbol Min Max Units Notes
AC Input Logic High VIH (ac) VREF + 0.20 — V 2, 3
AC Input Logic Low VIL (ac) —VREF – 0.20 V2, 3
VREF Peak-to-Peak AC Voltage VREF (ac) —5% VREF (DC) V 1
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
20% tKHKH
VSS – 1.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKHKH
VDD + 1.0 V
50%
VDD
VIL
Capacitance
oC, f = 1 MHZ, VDD = 3.3 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 4 5 pF
Output Capacitance COUT VOUT = 0 V 6 7 pF
Clock Capacitance CCLK — 5 6 pF
Note:
This parameter is sample tested.
(TA = 25
AC Test Conditions
Parameter Conditions
Input high level VDDQ
Input low level 0 V
Max. input slew rate 2 V/ns
Input reference level VDDQ/2
Output reference level VDDQ/2
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
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DQ
VT = VDDQ/2
50Ω
RQ = 250 Ω (HSTL I/O)
VREF = 0.75 V
AC Test Load Diagram
Input and Output Leakage Characteristics
Parameter Symbol Test Conditions Min. Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA
Doff IINDOFF
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–2 uA
2 uA
2 uA
Output Leakage Current IOL
Output Disable,
VOUT = 0 to VDDQ –2 uA 2 uA
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Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter Symbol Min. Max. Units Notes
Output High Voltage VOH1 VDDQ/2 VDDQ V 1, 3
Output Low Voltage VOL1 Vss VDDQ/2 V 2, 3
Output High Voltage VOH2 VDDQ – 0.2 VDDQ V 4, 5
Output Low Voltage VOL2 Vss 0.2 V 4, 6
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V
4. 0Ω ≤ RQ ≤ ∞Ω
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Operating Currents
Parameter Symbol Test Conditions
-400 -375 -333 -300 -250 -200 -167
Notes
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating Current
(x36): DDR IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
765
mA
775
mA
725
mA
735
mA
550
mA
560
mA
505
mA
515
mA
440
mA
450
mA
370
mA
380
mA
330
mA
340
mA 2, 3
Operating Current
(x18): DDR IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
605
mA
615
mA
570
mA
580
mA
435
mA
445
mA
405
mA
415
mA
350
mA
360
mA
300
mA
310
mA
265
mA
275
mA 2, 3
Operating Current
(x9): DDR IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
605
mA
615
mA
570
mA
580
mA
435
mA
445
mA
405
mA
415
mA
350
mA
360
mA
300
mA
310
mA
265
mA
275
mA 2, 3
Operating Current
(x8): DDR IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
605
mA
615
mA
570
mA
580
mA
435
mA
445
mA
405
mA
415
mA
350
mA
360
mA
300
mA
310
mA
265
mA
275
mA 2, 3
Standby Current
(NOP): DDR ISB1
Device deselected,
IOUT = 0 mA, f = Max,
All Inputs ≤ 0.2 V or
≥ VDD – 0.2 V
200
mA
210
mA
195
mA
205
mA
170
mA
180
mA
165
mA
175
mA
155
mA
165
mA
140
mA
150
mA
135
mA
145
mA 2, 4
Notes:
1. Power measured with output pins floating.
2. Minimum cycle, IOUT = 0 mA
3. Operating current is calculated with 50% read cycles and 50% write cycles.
4. Standby Current is only after all pending read and write burst operations are completed.
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AC Electrical Characteristics
Parameter Symbol -400 -375 -333 -300 -250 -200 -167
Units
Notes
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time
tKHKH
tCHCH
2.5 8.4 2.67 8.4 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns
tTKC Variable tKCVar —0.2 —0.2 —0.2 —0.2 —0.2 —0.2 —0.2 ns 6
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.0 —1.13 —1.2 —1.32 —1.6 —2.0 —2.4 —ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.0 —1.13 —1.2 —1.32 —1.6 —2.0 —2.4 —ns
K to K High
C to C High
tKHKH
tCHCH
1.0 —1.13 —1.35 —1.49 —1.8 —2.2 —2.7 —ns
K to K High
C to C High
tKHKH
tCHCH
1.0 —1.13 —1.35 —1.49 —1.8 —2.2 —2.7 —ns
K, K Clock High to C, C Clock High tKHCH 01.1 01.2 01.3 01.45 01.8 0 2.3 02.8 ns
DLL Lock Time tKCLock 1024 —1024 —1024 —1024 —1024 —1024 —1024 —cy
cle 6
K Static to DLL reset tKCReset 30 —30 —30 —30 —30 —30 —30 —ns
Output Times
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
—0.45 —0.45 —0.45 —0.45 —0.45 —0.45 —0.5 ns 4
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
tKHQX
tCHQX
–0.45 —–0.45 —–0.45 —–0.45 —–0.45 —–0.45 —–0.5 —ns 4
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
tKHCQV
tCHCQV
—0.45 —0.45 —0.45 —0.45 —0.45 —0.45 —0.5 ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
tKHCQX
tCHCQX
–0.45 —–0.45 —–0.45 —–0.45 —–0.45 —–0.45 —–0.5 —ns
CQ, CQ High Output Valid tCQHQV —0.25 —0.25 —0.25 —0.27 —0.30 —0.35 —0.40 ns 8
CQ, CQ High Output Hold tCQHQX –0.25 —–0.25 —–0.25 —–0.27 —–0.30 —–0.35 —–0.40 —ns 8
CQ Phase Distortion tCQHCQH
tCQHCQH
0.9 —1.0 —1.10 —1.24 —1.55 —1.95 —2.45 —ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
tKHQZ
tCHQZ
—0.45 —0.45 —0.45 —0.45 —0.45 —0.45 —0.5 ns 4
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
tKHQX1
tCHQX1
–0.45 —–0.45 —–0.45 —–0.45 —–0.45 —–0.45 —–0.5 —ns 4
Setup Times
Address Input Setup Time tAVKH 0.4 —0.4 —0.4 —0.4 —0.5 —0.6 —0.7 —ns 1
Control Input Setup Time (R/W, LD)tIVKH 0.4 —0.4 —0.4 —0.4 —0.5 —0.6 —0.7 —ns 2
Control Input Setup Time (BWX,
NWX) tIVKH 0.28 —0.28 —0.28 —0.3 —0.35 —0.4 —0.5 —ns 3
Data Input Setup Time tDVKH 0.28 —0.28 —0.28 —0.3 —0.35 —0.4 —0.5 —ns
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Hold Times
Address Input Hold Time tKHAX 0.4 —0.4 —0.4 —0.4 —0.5 —0.6 —0.7 —ns 1
Control Input Hold Time (R/W, LD)tKHIX 0.4 —0.4 —0.4 —0.4 —0.5 —0.6 —0.7 —ns 2
Control Input Hold Time (BWX,
NWX) tIVKH 0.28 —0.28 —0.28 —0.3 —0.35 —0.4 —0.5 —ns 3
Data Input Hold Time tKHDX 0.28 —0.28 —0.28 —0.3 —0.35 —0.4 —0.5 —ns
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are RW, LD.
3. Control singles BW0, BW1, (NW0, NW1 for x8) and BW2, BW3 for x36.
4. If C, C are tied high, K, K become the references for C, C timing parameters.
5. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter
that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same
board to be at such different voltages and temperatures.
6. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
7. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
8. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands
and test setup variations.
AC Electrical Characteristics (Continued)
Parameter Symbol -400 -375 -333 -300 -250 -200 -167
Units
Notes
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
C and C Controlled Read First Timing Diagram
Read A Cont Read A NOP Write B Cont Write B Read C
A B C
BB+1 B+2 B+3
AA+1 A+2 A+3 BB+1 B+2 B+3
CQHQXCQHQVCHCQV
CHCQX
CHCQV
CHCQX
KHDX
DVKH
CHQZ
CHQV
CHQXCHQX1
KHnKH
KLKHKLKH
KHKLKHKL
KHKHKHKH
KHIX
IVKH
KHIX
IVKH
KHIX
IVKH
KHAX
AVKH
KHnKH
KLKHKLKH
KHKLKHKL
KHKHKHKH
K
K
Address
LD
R/W
BWx
C
C
DQ
CQ
CQ
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K and K Controlled Read First Timing Diagram
Read A Cont Read A NOP Write B Cont Write B Read C
A B C
BB+1 B+2 B+3
AA+1 A+2 A+3 BB+1 B+2 B+3
CQHQXCQHQVCHCQV
CHCQX
CHCQV
CHCQX
KHDX
DVKH
KHQZ
KHQV
KHQX
KHQX1
KHIX
IVKH
KHIX
IVKH
KHIX
IVKH
KHAX
AVKH
KH#KH
KLKHKLKH
KHKLKHKL
KHKHKHKH
K
K
Address
LD
R/W
BWx
DQ
CQ
CQ
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C and C Controlled Write First Timing Diagram
Write A Cont Write A Read B Cont Read B NOP Write C Cont Write C
A B C
AA+1 A+2 A+3 CC+1 C+2
AA+1 A+2 A+3 BB+1 B+2 B+3 CC+1
CQHQX
CQHQVCHCQV
CHCQX
CHQZ
CHQX
CHQVCHQX1
KHDX
DVKH
KHnKH
KLKHKLKH
KHKLKHKL
KHKHKHKH
KHIX
IVKH
KHIX
IVKH
KHIX
IVKH
KHAX
AVKH
KHnKH
KLKHKLKH
KHKLKHKL
KHKHKHKH
K
K
Address
LD
R/W
C
C
DQ
CQ
CQ
BWx
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K and K Controlled Write First Timing Diagram
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JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDD.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin Pin Name I/O Description
TCK Tes t C lock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.
TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state
machine. An undriven TMS input will produce the same result as a logic one input level.
TDI Test Data In In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.
TDO Test Data Out Out Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
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Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Instruction Register
ID Code Register
Boundary Scan Register
012
0
····
31 30 29 12
0
Bypass Register
TDI TDO
TMS
TCK Test Access Port (TAP) Controller
108
·
10
·
·· ······
Control Signals
·
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
See BSDL Model
GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X X X X X X X X X 0 0 0 1 1 0 1 1 0 0 1 1
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Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
00
0
1
1
0 0
110
0
0
1
111
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
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SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
JTAG TAP Instruction Set Summary
Instruction Code Description Notes
EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2
SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z. 1
GSI 011 GSI private instruction. 1
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 30/37 © 2007, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter Symbol Min. Max. Unit Notes
Test Port Input Low Voltage VILJ –0.3 0.3 * VDD V 1
Test Port Input High Voltage VIHJ 0.7 * VDD VDD +0.3 V 1
TMS, TCK and TDI Input Leakage Current IINHJ –300 1uA 2
TMS, TCK and TDI Input Leakage Current IINLJ –1100 uA 3
TDO Output Leakage Current IOLJ –1 1 uA 4
Test Port Output High Voltage VOHJ VDD – 0.2 —V5, 6
Test Port Output Low Voltage VOLJ —0.2 V5, 7
Test Port Output CMOS High VOHJC VDD – 0.1 —V5, 8
Test Port Output CMOS Low VOLJC —0.1 V5, 9
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDD supply.
6. IOHJ = –2 mA
7. IOLJ = + 2 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1
GSI 101 GSI private instruction. 1
GSI 110 GSI private instruction. 1
BYPASS 111 Places Bypass Register between TDI and TDO. 1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG TAP Instruction Set Summary
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDD/2
Output reference level VDD/2
TDO
VDD/2
50Ω30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 31/37 © 2007, GSI Technology
JTAG Port Timing Diagram
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKLtTKLtTKHtTKHtTKCtTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter Symbol Min Max Unit
TCK Cycle Time tTKC 50 —ns
TCK Low to TDO Valid tTKQ —20 ns
TCK High Pulse Width tTKH 20 —ns
TCK Low Pulse Width tTKL 20 —ns
TDI & TMS Set Up Time tTS 10 —ns
TDI & TMS Hold Time tTH 10 —ns
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 32/37 © 2007, GSI Technology
Package Dimensions—165-Bump FPBGA (Package D)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
A1 CORNER TOP VIEW A1 CORNER
BOTTOM VIEW
1.0 1.0
10.0
1.01.0
14.0
13±0.05
15±0.05
A
B
0.20(4x)
Ø0.10
Ø0.25
C
C A B
M
M
Ø0.40~0.60 (165x)
C
SEATING PLANE
0.15 C
0.36~0.46
1.40 MAX.
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 33/37 © 2007, GSI Technology
Ordering Information—GSI SigmaDDR-II SRAM
Org Part Number1 Type Package Speed (MHz) TA2
2M x 8 GS8182R08BD-400 SigmaDDR-II B4 SRAM 165-bump BGA 400 C
2M x 8 GS8182R08BD-375 SigmaDDR-II B4 SRAM 165-bump BGA 375 C
2M x 8 GS8182R08BD-333 SigmaDDR-II B4 SRAM 165-bump BGA 333 C
2M x 8 GS8182R08BD-300 SigmaDDR-II B4 SRAM 165-bump BGA 300 C
2M x 8 GS8182R08BD-250 SigmaDDR-II B4 SRAM 165-bump BGA 250 C
2M x 8 GS8182R08BD-200 SigmaDDR-II B4 SRAM 165-bump BGA 200 C
2M x 8 GS8182R08BD-167 SigmaDDR-II B4 SRAM 165-bump BGA 167 C
2M x 8 GS8182R08BD-400I SigmaDDR-II B4 SRAM 165-bump BGA 400 I
2M x 8 GS8182R08BD-375I SigmaDDR-II B4 SRAM 165-bump BGA 375 I
2M x 8 GS8182R08BD-333I SigmaDDR-II B4 SRAM 165-bump BGA 333 I
2M x 8 GS8182R08BD-300I SigmaDDR-II B4 SRAM 165-bump BGA 300 I
2M x 8 GS8182R08BD-250I SigmaDDR-II B4 SRAM 165-bump BGA 250 I
2M x 8 GS8182R08BD-200I SigmaDDR-II B4 SRAM 165-bump BGA 200 I
2M x 8 GS8182R08BD-167I SigmaDDR-II B4 SRAM 165-bump BGA 167 I
2M x 9 GS8182R09BD-400 SigmaDDR-II B4 SRAM 165-bump BGA 400 C
2M x 9 GS8182R09BD-375 SigmaDDR-II B4 SRAM 165-bump BGA 375 C
2M x 9 GS8182R09BD-333 SigmaDDR-II B4 SRAM 165-bump BGA 333 C
2M x 9 GS8182R09BD-300 SigmaDDR-II B4 SRAM 165-bump BGA 300 C
2M x 9 GS8182R09BD-250 SigmaDDR-II B4 SRAM 165-bump BGA 250 C
2M x 9 GS8182R09BD-200 SigmaDDR-II B4 SRAM 165-bump BGA 200 C
2M x 9 GS8182R09BD-167 SigmaDDR-II B4 SRAM 165-bump BGA 167 C
2M x 9 GS8182R09BD-400I SigmaDDR-II B4 SRAM 165-bump BGA 400 I
2M x 9 GS8182R09BD-375I SigmaDDR-II B4 SRAM 165-bump BGA 375 I
2M x 9 GS8182R09BD-333I SigmaDDR-II B4 SRAM 165-bump BGA 333 I
2M x 9 GS8182R09BD-300I SigmaDDR-II B4 SRAM 165-bump BGA 300 I
2M x 9 GS8182R09BD-250I SigmaDDR-II B4 SRAM 165-bump BGA 250 I
2M x 9 GS8182R09BD-200I SigmaDDR-II B4 SRAM 165-bump BGA 200 I
2M x 9 GS8182R09BD-167I SigmaDDR-II B4 SRAM 165-bump BGA 167 I
1M x 18 GS8182R18BD-400 SigmaDDR-II B4 SRAM 165-bump BGA 400 C
1M x 18 GS8182R18BD-375 SigmaDDR-II B4 SRAM 165-bump BGA 375 C
1M x 18 GS8182R18BD-333 SigmaDDR-II B4 SRAM 165-bump BGA 333 C
1M x 18 GS8182R18BD-300 SigmaDDR-II B4 SRAM 165-bump BGA 300 C
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS818R36BD-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 34/37 © 2007, GSI Technology
1M x 18 GS8182R18BD-250 SigmaDDR-II B4 SRAM 165-bump BGA 250 C
1M x 18 GS8182R18BD-200 SigmaDDR-II B4 SRAM 165-bump BGA 200 C
1M x 18 GS8182R18BD-167 SigmaDDR-II B4 SRAM 165-bump BGA 167 C
1M x 18 GS8182R18BD-400I SigmaDDR-II B4 SRAM 165-bump BGA 400 I
1M x 18 GS8182R18BD-375I SigmaDDR-II B4 SRAM 165-bump BGA 375 I
1M x 18 GS8182R18BD-333I SigmaDDR-II B4 SRAM 165-bump BGA 333 I
1M x 18 GS8182R18BD-300I SigmaDDR-II B4 SRAM 165-bump BGA 300 I
1M x 18 GS8182R18BD-250I SigmaDDR-II B4 SRAM 165-bump BGA 250 I
1M x 18 GS8182R18BD-200I SigmaDDR-II B4 SRAM 165-bump BGA 200 I
1M x 18 GS8182R18BD-167I SigmaDDR-II B4 SRAM 165-bump BGA 167 I
512K x 36 GS8182R36BD-400 SigmaDDR-II B4 SRAM 165-bump BGA 400 C
512K x 36 GS8182R36BD-375 SigmaDDR-II B4 SRAM 165-bump BGA 375 C
512K x 36 GS8182R36BD-333 SigmaDDR-II B4 SRAM 165-bump BGA 333 C
512K x 36 GS8182R36BD-300 SigmaDDR-II B4 SRAM 165-bump BGA 300 C
512K x 36 GS8182R36BD-250 SigmaDDR-II B4 SRAM 165-bump BGA 250 C
512K x 36 GS8182R36BD-200 SigmaDDR-II B4 SRAM 165-bump BGA 200 C
512K x 36 GS8182R36BD-167 SigmaDDR-II B4 SRAM 165-bump BGA 167 C
512K x 36 GS8182R36BD-400I SigmaDDR-II B4 SRAM 165-bump BGA 400 I
512K x 36 GS8182R36BD-375I SigmaDDR-II B4 SRAM 165-bump BGA 375 I
512K x 36 GS8182R36BD-333I SigmaDDR-II B4 SRAM 165-bump BGA 333 I
512K x 36 GS8182R36BD-300I SigmaDDR-II B4 SRAM 165-bump BGA 300 I
512K x 36 GS8182R36BD-250I SigmaDDR-II B4 SRAM 165-bump BGA 250 I
512K x 36 GS8182R36BD-200I SigmaDDR-II B4 SRAM 165-bump BGA 200 I
512K x 36 GS8182R36BD-167I SigmaDDR-II B4 SRAM 165-bump BGA 167 I
2M x 8 GS8182R08BGD-400 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 C
2M x 8 GS8182R08BGD-375 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 375 C
2M x 8 GS8182R08BGD-333 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 C
2M x 8 GS8182R08BGD-300 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 C
2M x 8 GS8182R08BGD-250 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 C
2M x 8 GS8182R08BGD-200 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 200 C
2M x 8 GS8182R08BGD-167 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 167 C
2M x 8 GS8182R08BGD-400I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 I
2M x 8 GS8182R08BGD-375I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 375 I
Ordering Information—GSI SigmaDDR-II SRAM
Org Part Number1 Type Package Speed (MHz) TA2
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS818R36BD-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 35/37 © 2007, GSI Technology
2M x 8 GS8182R08BGD-333I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 I
2M x 8 GS8182R08BGD-300I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 I
2M x 8 GS8182R08BGD-250I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 I
2M x 8 GS8182R08BGD-200I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 200 I
2M x 8 GS8182R08BGD-167I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 167 I
2M x 9 GS8182R09BGD-400 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 C
2M x 9 GS8182R09BGD-375 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 375 C
2M x 9 GS8182R09BGD-333 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 C
2M x 9 GS8182R09BGD-300 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 C
2M x 9 GS8182R09BGD-250 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 C
2M x 9 GS8182R09BGD-200 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 200 C
2M x 9 GS8182R09BGD-167 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 167 C
2M x 9 GS8182R09BGD-400I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 I
2M x 9 GS8182R09BGD-375I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 375 I
2M x 9 GS8182R09BGD-333I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 I
2M x 9 GS8182R09BGD-300I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 I
2M x 9 GS8182R09BGD-250I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 I
2M x 9 GS8182R09BGD-200I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 200 I
2M x 9 GS8182R09BGD-167I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 167 I
1M x 18 GS8182R18BGD-400 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 C
1M x 18 GS8182R18BGD-375 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 375 C
1M x 18 GS8182R18BGD-333 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 C
1M x 18 GS8182R18BGD-300 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 C
1M x 18 GS8182R18BGD-250 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 C
1M x 18 GS8182R18BGD-200 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 200 C
1M x 18 GS8182R18BGD-167 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 167 C
1M x 18 GS8182R18BGD-400I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 I
1M x 18 GS8182R18BGD-375I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 375 I
1M x 18 GS8182R18BGD-333I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 I
1M x 18 GS8182R18BGD-300I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 I
1M x 18 GS8182R18BGD-250I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 I
1M x 18 GS8182R18BGD-200I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 200 I
1M x 18 GS8182R18BGD-167I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 167 I
Ordering Information—GSI SigmaDDR-II SRAM
Org Part Number1 Type Package Speed (MHz) TA2
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS818R36BD-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 36/37 © 2007, GSI Technology
512K x 36 GS8182R36BGD-400 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 C
512K x 36 GS8182R36BGD-375 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 375 C
512K x 36 GS8182R36BGD-333 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 C
512K x 36 GS8182R36BGD-300 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 C
512K x 36 GS8182R36BGD-250 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 C
512K x 36 GS8182R36BGD-200 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 200 C
512K x 36 GS8182R36BGD-167 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 167 C
512K x 36 GS8182R36BGD-400I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 I
512K x 36 GS8182R36BGD-375I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 375 I
512K x 36 GS8182R36BGD-333I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 I
512K x 36 GS8182R36BGD-300I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 I
512K x 36 GS8182R36BGD-250I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 I
512K x 36 GS8182R36BGD-200I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 200 I
512K x 36 GS8182R36BGD-167I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 167 I
Ordering Information—GSI SigmaDDR-II SRAM
Org Part Number1 Type Package Speed (MHz) TA2
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS818R36BD-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Revision History
Rev. Code: Old; New Types of Changes
Format or Content Revisions
GS8182RxxB_r1 Format • Creation of new datasheet
(Rev1.00b: erroneous green part numbers corrected)
GS8182RxxB_r1_01 Format • Updated AC Electrical Characteristics table
GS8182RxxB_r1_02 Content
• Revised Example Four Bank Depth Expansion Schematic
• Updated JTAG Port AC Test Conditions
• Updated 165 BGA Package Drawing
• (Rev1.02a: Added Operating Currents numbers)
GS8182RxxB_r1_03 Content • Added 400 & 375 MHz speed bins
• Added x9 configuration
GS8182RxxB_r1_04 Content
• Removed “Preliminary” banner to indicate MP status
• (Rev1.04a: Updated power up)
• (Rev1.04b: removed CQ reference from SAMPLE-Z section in
JTAG Tap Instruction Set Summary)
• (Rev1.04c: Editorial updates)
GS8182R08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04c 11/2011 37/37 © 2007, GSI Technology