SS = CYPRESS Sa FS SE Features e 0.8-micron CMOS for optimum speed/power Automatic power-down e TTL compatible CY7C130/CY7C131 CY7C140/CY7C141 MICONDUCTOR Functional Description The CY7C130/CY7C13 1/CY7C140/ CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are pro- vided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM oras a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual- port device in systems requiring 16-bit or Capable of withstanding greater than 2001V electrostatic discharge e Fully asynchronous operation @ Master CY7C130/CY7C131 easily ex- pands data bus width to 16 or more 1K x 8 Dual-Port Static RAM Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OB). Two flags are provided oneach port, BUSY and INT. BUSY signals that the port is trying to access the same lo- cation currently being accessed by the other port. INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. bits using SLAVE CY7C140/ greater word widths. It is the solution to . . CY7Ci41 applications requiring shared or buffered The CY7C130and CY7C140 are available in BUSY output flag on CY7C130/ data, such as cache memory for DSP, bit- both 48-pin DIP and 48-pin LCC, The CY7C131; BUSY input on slice, or multiprocessor designs. CY7C131 and CY7C141 are available in CY7C140/CY7C141 both 52-pin LCC and PLCC. e INT flag for port-to-port communication Logic Block Diagram Pin Configurations RAM, RW; CEL CER EL OER Ag Agr An A "Oo. COLUMN COLUMN VOer VOr, vO vo Ore BUSY. BUSYAt Pot MEMORY Aer ARRAY Ao. Aor ARBITRATION : LoGic (7C130/7C131 ONLY) AND INTERRUPT LOGIC INT (2) INT, 130-1 Notes: 1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor. CY7C140/CY7C141 (Slave): BUSY is input. 2. Open drain outputs: pull-up resistor required. Ma SRAMsCY7C130/CY7C131 Bins CY7C140/CY7C141 # SEMICONDUCTOR Pin Configurations (continued) $2-Pin LCC/PLCC 48-Pin LCC/QFP Top View Top View =! oc a x = (2 a 2 =\e ag & eee Begsde Ble egegewsde Beg 6 VO7R Oger C120-3 c1304 Selection Guide 7C130-2517] 7C13030 7C130-35 7C130-45 7C13055 7C13125 7131-30 7131-35 7C131-45 7C13155 7C14025 7C140-30 7C140-35 70140-45 7C14055 7C141-25 7C141-30 7C141-35 7C141-45 7141-55 Maximum Access Time (ns) 25 30 35 45 55 Maximum Operating Coml/Ind 170 170 120 90 90 Current (mA, Military 170 120 120 Maximum Standby ComI/Ind 65 65 45 35 35 Current (mA) Military 65 45 45 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Static Discharge Voltage ................00.000 >2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................ 65C to +150 C Latch-Up Current 2.2.20... 0... e cee cece eee e es >200 mA Ambient Temperature with . Power Applied ..........c0cc0s.0e0e- ~55Cto +125C Operating Range i Ambient Supply Voltage to Ground Potential (Pin 48 to Pin 24) .. 0... .c.ccceeeeeeees - 05V to +7.0V Range Temperature Vee DC Voltage Applied to Outputs Commercial 0C to +70C 5V + 10% in High Z State ..............00. 00.000. 0.5V to +7.0V Industrial 40C to +85C SV + 10% DC Input Voltage ...................04. 3.5V to +7.0V Miantl 5 = SV 2 10% Output Current into Outputs (LOW) .............. 20 mA my ~ 55C to + 125C *_ Notes: 3. 25-ns version available only in PLCC/LCC packages. 4. Tz is the instant on case temperatureFi CYPRESS = SEMICONDUCTOR CY7C130/CY7C131 CY7C140/CY7C141 Electrical Characteristics Over the Operating Rangel! 7C130-25, 301] | 7130-35 | 7C130-45,55 7C13125,30 7C131-35 | 7C131-45,55 7C14025,30 7140-35 | 7C140~-45,55 7C14125,30 7C141-35 | 7014145,55 Parameter Description Test Conditions Min. Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH Voltage | Vcc = Min., lon = 4.0mA 24 2.4 2.4 Vv VoL Output LOW Voltage | Io, = 4.0 mA 0.4 0.4 0.4 Vv Io = 16.0 mall 0.5 0.5 0.5 Vin Input HIGH Voltage 2.2 2.2 2.2 Vv Vin Input LOW Voltage 0.8 0.8 0.8 Vv lix InputLeakageCurrent | GND < V] < Vcc ~5 +5 -5 +5 5 +5 pA Ioz Output Leakage GND < Vo < Vcc, - +5 -5 +5 -5 +5 pA Current Output Disabled los Output Short Vcc = Max., ~ 350 350 350 | mA Circuit Current!?8] | Vgur = GND Icc Vcc Operating CE = Vy, Com'l 170 120 90 mA Supply Current Outputs Open, f = fyaxl Mil 170 120 Ispi Standby Current CE, and CER> > Vin, Coml 65 45 35 mA Both Ports, f = fyaxl?l . TTL Inputs Mil 65 45 Isp2 Standby Current CE, or CEp > Vin, Com! 115 90 75 mA One Port, Active Port OutputsOpen, L TTL Inputs f= fyaxl*l Mil 115 90 Isp3 Standby Current Both Ports ts CEy al and Com! 15 15 15 mA Both Ports, CER > Vec - 0.2V, CMOS Inputs Vin > Vec 0.2V or - Vin < 0.2V, f = 0 Mil 15 is Ispq Standby Current One Port CE. or Com! 105 85 70 mA One Port, CEe > Vcc - 0.2V, CMOS Inputs Vin = Vec ~ 0.2V or Vin < 0.2V, * Active Port Outputs Open, Mil 105 85 f = fyax!l Capacitancell Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 15 pF Cout Output Capacitance Voc = 5.0V 10 pF Notes: 5. See the last page of this specification for Group A subgroup testing 12, AC Test Conditions use Voy = 1.6V and Voy = 1.4V. information. 13. 6. BUSY and INT pins only. 7. Duration of the short circuit should not exceed 30 seconds. 14, 8. Tested initially and after any design or process changes that may affect these parameters. 9, Atf=fyax, address and data inputs are cycling at the maximum fre- 15. quency of read cycle of 1/tac and using AC Test Waveforms input lev- els of GND to 3V. 10. AC Test conditions use Voy = 1.6V and Voy = 1.4V. 11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified Io, /Iox, and 30-pF load capacitance. At any given temperature and voltage condition for any given device, tuzck is less than thzcg and tyzog is less than thzog. tLzce, tLzwe, tz, tLZOE, tuzce and tyzwe are tested with C,, = 5pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady state voltage. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input set-up and hold timing should be referencd to the rising edge of the signal that terminates the write. SRAMs |j CYPRESS = SEMICONDUCTOR CY7C130/CY7C131 AC Test Loads and Waveforms R41 5V By R1893Q 5v 893Q OUTPUT P OUTPUT P 281 BUSY 30 pF R2 5 pF 3 R2 OF pF 3472 p L 3472 nr INCLUDING LL INCLUDING L k _[ F JIGAND = = JIGAND - = C130 SCOPE (a) SCOPE (b) Wor8 BUSY Output Load (CY7C130/CY7C131 ONLY) ALL INPUT PULSES 130-6 Equivalent to: THEVENIN EQUIVALENT 2502. QUT PUT mnt 1 40 Switching Characteristics Over the Operating Range!:!!] 70130-2515! | 7130-30 | 7C130-35 | 7C130-45 | 7C130-55 7C131-25 | 7C131-30 | 7131-35 | 7C131-45 | 7C131-55 7C140-25 | 7C140-30 | 7C140-35 | 7C14045 | 7C140-55 7C141-25 | 70141-30 | 7C141-35 | 7C141-45 | 7C141-55 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit READ CYCLE tre Read Cycle Time 25 30 35 45 55 ns taa Address to Data Validlt2] 25 30 35 45 55 ns toHA Data Hold from 0 0 0 0 0 ns Address Change tack CE LOW to Data Validl!2] 25 30 35 45 55 ns tpog OE LOW to Data Validl!21 15 20 20 25 25 ns tLZOE OE LOW to Low 2/13] 3 3 3 3 3 ns tyZz0B OE HIGH to High Zl 14] 15 15 20 20 25 ns tLZcE CE LOW to Low ZI13, 14] 5 5 5 5 5 ns tHZcR CE HIGH to High ZI13. 14] 15 15 20 20 25 ns tpy CE LOW to Power-Up 0 0 0 0 0 ns tpp CE HIGH to Power-Down 25 25 35 35 35 ns WRITE CYCLEI'5} twe Write Cycle Time 25 30 35 45 55 ns tsce CE LOW to Write End 20 25 30 35 40 ns taw Address Set-Up to Write End 20 25 30 35 40 ns tHa Address Hold from Write End 2 2 2 ns tsa Address Set-Up to Write Start 0 0 0 ns tpwe R/W Pulse Width 15 25 25 30 30 ns tsp Data Set-Up to Write End 15 15 15 20 20 ns typ Data Hold from Write End 0 0 0 0 0 ns tHzwE R/W LOW to High Z 15 15 20 20 25 ns tLZwE R/W HIGH to Low Z 0 0 0 0 0 ns; CYPRESS = SEMICONDUCTOR CY7C130/CY7C131 CY7C140/CY7C141 Switching Characteristics Over the Operating Rangel>-!"] (continued) 7C130251! | 7C130-30 | 7C130-35 | 7C130-45 | 7C130-55 7C13125 7C131-30 | 7C131-35 713145 70131-55 7C14025 7C140-30 | 7C140-35 7C14045 70140-55 7141-25 7C141-30 | 7C141-35 7C141-45 7C141-55 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit BUSY/INTERRUPT TIMING tBLA BUSY LOW from Address Match 20 20 20 25 30 ns tBHA BUSY HIGH from 20 20 20 25 30 ns Address Mismatch!!6] tic BUSY LOW from CE LOW 20 20 20 25 30 ns tpHc BUSY HIGH from CE HIGHL!6] 20 20 20 25 30 ns tps Port Set Up for Priority 5 5 5 5 5 ns twa R/W LOW after BUSY LOW 0 0 ns twH R/W HIGH after BUSY HIGH 20 30 30 35 35 ns tapp BUSY HIGH to Valid Data 25 30 35 45 45 ns tppp Write Data Valid to Note Note Note Note Note | ns Read Data Valid 18 18 18 18 18 twop Write Pulse to Data Delay Note Note Note Note Note | ns 18 18 18 18 18 INTERRUPT TIMING twins R/W to INTERRUPT Set Time 25 25 25 35 45 ns tEINS CE to INTERRUPT Set Time 25 25 25 35 45 ns tins Address to INTERRUPT 25 25 25 35 45 ns Set Time toInR OE to INTERRUPT 25 25 25 35 45 ns Reset Timel!6] tEINR CE to INTERRUPT 25 25 25 35 45 ns Reset Timel!6] tiInR Address to INTERRUPT 25 25 25 35 45 ns Reset Timel!6] Notes: _ 16. These parameters are measured from the input signal changing, until 19. R/W is HIGH for read cycle. the output pin goes to a high-impedance state. 20. Device is continuously selected, CE = Vi, and OF = Viz. 17, CYTCI40/CY7C141 only. 21. Address valid prior to or coincident with CE transition LOW. 18. Awrite operation on Port A, where Port A has priority, leavesthedata 22. If OE is LOW during a R/W controlled write cycle, the write pulse on Port Bs outputs undisturbed until one access time after one of the width must be the larger of tpwe or tuzwe + tsp to allow the data I/O following: pins to enter high impedance and for data to be placed on the bus for A. BUSY on Port B goes HIGH. the required tsp. & Pare ncaress towed 23. If the CE LOW transition occurs simultaneously with or after the R/ DR AW for Port Bis toggled during valid read. W LOW transition, the outputs remain in the high-impedance state. Switching Waveforms Read Cycle No. 1119. 20] Either Port Address Access | tac ADDRESS DATA OUT toua >} aa PREVIOUS DATA VALID KXKKKK DATA VALID C130~-7 SRAMs aCY7C130/CY7C131 =, CYPRESS CY7C140/CY7C141 4 SEMICONDUCTOR Switching Waveforms (continued) Read Cycle No. 2[19.21] Either Port CE/OE Access ce y fe tHzce oe tace X t bor ; HZOE tLz0E tizce BLikhL LA hl ~*~ DATA OUT SRE DATA VALID > * teu _ /+* tpp 130-8 Read Cycle No. 3120] Read with BUSY, Master: CY7C130 and CY7C131 tac ADDRESS, ADDRESS MATCH RWp, tpwe Dinr VALID ADDRESS, ADDRESS MATCH BUSY, DOUT, Write Cycle No.1 (OE Tri-States Data I/Os ~ Either Port)!15.22] Either Port twe ADDRESS CE tpwe RW tsp DATA\n DATA VALID OE tyz0E noe HIGH IMPEDANCE Dout A AA A C130-10CY7C130/CY7C131 =p, CYPRESS CY7C140/CY7C141 SEMICONDUCTOR Switching Waveforms (continued) Write Cycle No. 2 (R/W Tri-States Data I/Os Either Port)[15.23] Either Port two ADDRESS CE R/W tsp tub DATAin DATA VALID tLawe TVS ASN NNN NN NS HIGH IMPEDANCE _ DATAguT 7 SS LLL LL LOL LLL. MAOAASSN C130-11 Busy Timing Diagram No. 1 (CE Arbitration) CE, Valid First: ADDRESS, p x ADDRESS MATCH x CEL tps cc eefF iN taic tBHc BUSY, C130-12 CER Valid First: ADDRESS, p x ADDRESS MATCH x CER tpg CEL taic i tac BUSY, C130-13ay CY7C130/CY7C131 CY7C140/CY7C141 CYPRESS SEMICONDUCTOR Switching Waveforms (continued) Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tac oF two ADDRESS MATCH ADDRESS MISMATCH x ADDRESS, < tps ADDRESS, Xx {BLA h* teHa BUSY, c130-14 Right Address Valid First: trac or two ADDRESS MATCH ADDRESS MISMATCH x ADDRESS, tes ADDRESS, xX tBLa * teHa BUSY, 6130-15 Busy Timing Diagram No. 3 Write with BUSY (Slave: CY7C140/CY7C141) CE \ | t PWE RW a twe twH | BUSY C130~16CY7C130/CY7C131 re CYPRESS CY7C140/CY7C141 SEMICONDUCTOR Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR \ ' WC ADDR, WRITE 3FF xKxKx x tins ta " CEL teins RW, K t SA | twins INTR Ss Right Side Clears INTg tac wom KX XXX KKK KKK KKK moe OK }#H tua tnt > CER \ ter ate DI ZILLI ILL o CXR / 0130-17 __ ae tonr * _ Tr A 130-18 Right Side Sets INT, | twe or ADDRR KY WRITE 3FE Kx x x *__ tng tHA CER teins > RW, a tsa t INT, T WINS \ 130-19 Left Side Clears INT], wom KXX KKK KKK KKK RIO aoe OK tya tnR ] CE, K teInR an DIDI LLL LOR o, SSSA / toinR INTL / C130~20CY7C130/CY7C131 CY7C140/CY7C141 CYPRESS SEMICONDUCTOR =i Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT ys. AMBIENT TEMPERATURE ys. SUPPLY VOLTAGE 1.4 12 B12 8 1.0 Ico = loc _ 8 1.0 8 08 2 08 6 N N os Van= 50v Zz 06 z oc = 5: = = 04 Vin = 5.0V & . oO 0.4 5 z = op 0.2 Isp3 6. Ispa 0.0 0.6 4.0 45 5.0 65.5 6.0 -55 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE ys. AMBIENT TEMPERATURE 1.6 a 3 1.4 Q a Ni N 12 A al < Z z a foal gE 1.0 8 z Veco = 5.0V 0.8 L 0.8 0.6 4.0 45 5.0 5.5 6.0 55 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) TYPICAL POWER -ON CURRENT TYPICAL ACCESS TIME CHANGE vs. SUPPLY VOLTAGE vs. OUTPUT LOADING 3.0 30.0 9 28 250 < @ 20 =20.0 N Z Z 150 = 15 < Wi 8 10 @ 10.0 Voc = 4.5V 06 5.0 Th = 25C 0.0 0 0 10 20 30 40 50 0 200 400 600 800 1000 SUPPLY VOLTAGE (V) CAPACITANCE (PF) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE _ nN Qo vt o oa oO oO OUTPUT SOURCE CURRENT (mA) fs>] oQ 40 20 0 o 10 #20 30 40 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT ys. QUTPUT VOLTAGE ~~ = 120 G @ 100 5 a 80 x Z 60 wo 5 40 5 Voc = 5.0V cc. 3 Ta = 25C 0 00 10 #20 30 40 OUTPUT VOLTAGE (V) NORMALIZED Icc vs. CYCLE TIME 1.25 T Voc = 4.5V Oo Ta = 26C 2 Vin = 0.5V 8 1.0 N | =< = | x 90.75 7 50 10 20 30 40 CYCLE FREQUENCY (MHZ)CY7C130/CY7C131 =7 CYPRESS CY7C140/CY7C141 SEMICONDUCTOR Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 30 CY7C13030PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C13030PI P25 48-Lead (600-Mil) Molded DIP Industrial 35 CY7C13035PC P25 48-Lead (600-Mil) Molded DIP CY7C130-35PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C130~35DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C13035FMB F78 48-Lead Quad Flatpack CY7C13035LMB L68 48-Square Leadless Chip Carrier 45 CY7C13045PC P25 48-Lead (600-Mil) Molded DIP CY7C13045PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C13045DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C130-45FMB F78 48-Lead Quad Flatpack CY7C13045LMB L68 48-Square Leadless Chip Carrier 55 CY7C13055PC P25 48-Lead (600-Mil) Molded DIP CY7C13055PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C130-55DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C130S5FMB F78 48-Lead Quad Flatpack CY7C13055LMB L68 48-Square Leadless Chip Carrier Speed Package Operating (ns) Ordering Code Name Package Type Range 25 CY7C13125JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial 30 CY7C131-303C J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C13130H1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial 35 CY7C131-353C J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C13135H1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial CY7C13135FMB F78 48-Lead Quad Flatpack Military CY7C13135LMB L69 52-Square Leadless Chip Carrier 45 CY7C13145JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C13145J1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial CY7C13145FMB F78 48-Lead Quad Flatpack Military CY7C13145LMB L69 52-Square Leadless Chip Carrier 55 CY7C13155JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C131-S55JI J69 52-Lead Plastic Leaded Chip Carrier | Industrial CY7C13155FMB F78 48-Lead Quad Flatpack Military CY7C131-5SMB L69 52-Square Leadless Chip CarrierBric ! SEMICONDUCTOR CY7C130/CY7C131 CY7C140/CY7C141 Ordering Information (continued) Speed Package Operating (ns) Ordering Code Name Package Type Range 30 CY7C14030PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C14030PI P25 48-Lead (600-Mil) Molded DIP Industrial 35 CY7C14035PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C14035PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C140-35DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C14035FMB F78 48-Lead Quad Flatpack CY7C14035LMB L68 48-Square Leadless Chip Carrier 45 CY7C14045PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C14045PI1 P25 48-Lead (600-Mil) Molded DIP Industrial CY7C140-45DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C14045FMB F78 48-Lead Quad Flatpack CY7C14045LMB L68 48-Square Leadless Chip Carrier 55 CY7C14055PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C14055PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C14055DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C14055FMB F78 48-Lead Quad Flatpack CY7C14055LMB L68 48-Square Leadless Chip Carrier Speed Package Operating (ns) Ordering Code Name Package Type Range 25 CY7C14125JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial 30 CY7C141-30IC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C1413051 J69 52-Lead Plastic Leaded Chip Carrier | Industrial 35 CY7C14135JC 569 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C141-35]1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial CY7C141-35FMB F78 48-Lead Quad Flatpack Military CY7C14135LMB L69 52-Square Leadless Chip Carrier 45 CY7C14145JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C14145JI J69 52-Lead Plastic Leaded Chip Carrier | Industrial CY7C14145FMB F78 48-Lead Quad Flatpack Military CY7C14145LMB L69 52-Square Leadless Chip Carrier 55 CY7C14155JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C141-S5J1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial CY7C14155FMB F78 48-Lead Quad Flatpack Military CY7C14155LMB L69 52-Square Leadless Chip Carrier= CYPRESS B SEMICONDUCTOR CY7C130/CY7C131 CY7C140/CY7C141 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Vou 1,2,3 VoL 1, 2,3 Vin 1, 2,3 Vir Max. 1, 2,3 Ix 1, 2,3 Toz 1, 2,3 Tec 1,2,3 Ispi 1,2,3 Isp2 1,2,3 Igp3 1,2,3 Isp4 1,2,3 Switching Characteristics Parameter Subgroups Parameter Subgroups READ CYCLE BUSY/INTERRUPT TIMING tre 7, 8, 9, 10, 11 tBLa 7, 8, 9, 10, 11 tad 7, 8, 9, 10, 11 tpHaA 7, 8,9, 10, 11 tACE 7, 8, 9, 10, 11 tBic 7, 8, 9, 10, 11 tpoE 7, 8,9, 10, 11 tBHc 7, 8,9, 10, 11 WRITE CYCLE tps 7, 8,9, 10, 11 twc 7, 8,9, 10, 11 twins 7, 8, 9, 10, 11 tscE 7, 8, 9, 10, 11 tEINS 7, 8, 9, 10, 11 taw 7, 8, 9, 10, 11 tins 7, 8, 9, 10, 11 tHa 7, 8,9, 10, 11 toINR 7, 8, 9, 10, 11 tsa 7, 8, 9, 10, 11 tEINR 7, 8,9, 10, 11 tpwe 7, 8, 9, 10, 11 tinr 7, 8,9, 10, 11 tsp 7, 8, 9, 10, 11 BUSY TIMING typ 7, 8, 9, 10, 11 twpl24] 7, 8, 9, 10, 11 twH 7, 8, 9, 10, 11 tBpp 7, 8, 9, 10, 11 Note: 24, CY7C140/CY7C141 only. Document #: 38-00027-I