AM29F016B-120EIB - Advanced Micro Devices

PRELIMINARY

Publicati on# 21444 Rev: BAmendment/+2

Issue Date: April 1998

Am29F016B

16 Megabit (2 M x 8-Bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■5.0 V ± 10%, single power supply oper ation

— Minimizes system level power requirements

■Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29F016 device

■High performan c e

— Access times as fast as 70 ns

■Low power consumptio n

— 25 mA typical active read current

— 30 mA typical program/erase current

— 1 µA typical standby current (standard access

time to active mode)

■Flexible sector architecture

— 32 unifor m sectors of 64 Kbytes each

— Any combination of sectors can be erased

— Supports full chip erase

— Group sector protection:

A hardware method of locking sector groups to

prevent any program or erase operations within

that sector group

Temporary Sector Group Unprotect allo ws code

changes in prev iously locked sectors

■Embe dded Algorithms

— Embedded Erase algorithm automatically

preprogr ams and erases the ent ire chip or any

combination of designated sectors

— Embedded Program algor ithm automatically

writes and verifies bytes at specified addresses

■Minimum 1,000,000 program/erase c ycles per

sector guaranteed

■Package options

— 48-pin and 40-pin TSOP

— 44-pin SO

■Compatible with JEDEC standar ds

— Pinout and software compatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■Data# Polling and toggle bits

— Provides a software method of detecting

program or erase cycle completion

■Ready/Busy# output (RY/BY#)

— Provides a hardware method for detecting

program or erase cycle completion

■Erase Suspend/Erase Resume

— Suspends a sector erase operation to read data

from, or progr am data to, a non-erasing sector,

then resumes the erase operation

■Hardware reset pin (RESET#)

— Resets internal state machine to the read mode

2 Am29F016B

PRELIMINARY

GENERAL DESCRIPTION

The Am29F016B is a 1 6 Mbit, 5.0 v olt-only Flash mem-

ory organized as 2,097,152 bytes. The 8 bits of data

appear on DQ0–DQ7. The Am29F016B is offered in

48-pin and 40-pin TSOP, and 44-pin SO packages.

This device is designed to be programmed in-system

with the standard system 5.0 volt VCC supply. A 12.0

volt VPP is not required for program or erase

operations. The device can also be programmed in

standard EPROM programmers.

This device is manufactured using AMD’s 0.35 µm

process technolog y, and offers all the f eatures and ben-

efits of the Am29F016, which was manufactured using

0.5 µm proces s technology.

The standard de vice off ers access times o f 70, 90, 120,

and 150 ns, allowing high-speed microprocessors to

operate without wait states. To eliminate bus conten-

tion, the device has separate chip enable (C E#), write

enable (WE#), and output enable (OE#) controls .

The dev ice requires only a single 5.0 volt po wer sup-

ply for both read and write functions. Inter nally gener-

ated and regulated voltages are provided for the

program and erase operations.

The de vice is entirely command set compatib le with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input to an internal state-machine that con-

trols the erase and programming circuitry. Write cycles

also internally latch addresses an d data needed f or t he

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM devices.

Devic e programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the arra y (if it is not already prog rammed)

bef ore ex ecuting the erase operation. During er ase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready t o read arra y data

or accept another command.

The sector erase ar chitecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when s hipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achiev ed via prog ramming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure . True background er ase can thus be achie ved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading arra y data. The RESET# pin ma y be tied to t he

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The system can place the device into the standby

mode. Power consumption is greatly reduced in

this mode.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost

effectiveness. The device electrically erases all

bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is

program med using hot electron injection.

Am29F016B 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

Note: See the AC Characteristics section for more information.

BLOCK DIAGRAM

Family Part Number Am29F016B

Speed Options (VCC = 5.0 V ± 10% ) -70 -90 -120 -150

Max Access Time (ns) 70 90 120 150

CE# Access (ns) 70 90 120 150

OE# Access (ns) 40 40 50 75

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

CE#

OE#

STB

DQ0

–

DQ7

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A20

21444B-1

4 Am29F016B

PRELIMINARY

CONNECTION DIAGRAMS

A19

A18

A17

A16

A15

A14

A13

A12

CE#

VCC

RESET#

A11

A10

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

VCC

VSS

DQ3

DQ2

DQ1

DQ0

40-Pin Standard TSOP

21444B-2

A19

A18

A17

A16

A15

A14

A13

A12

CE#

VCC

RESET#

A11

A10

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

VCC

VSS

DQ3

DQ2

DQ1

DQ0

40-Pin Reverse TSOP

21444B 3

Am29F016B 5

PRELIMINARY

CONNECTION DIAGRAMS (continued)

A19

A18

A17

A16

A15

A14

A13

A12

CE#

VCC

RESET#

A11

A10

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

VCC

VSS

DQ3

DQ2

DQ1

DQ0

48-Pin Standard TSOP

21444B-4

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

VCC

VSS

DQ3

DQ2

DQ1

DQ0

A19

A18

A17

A16

A15

A14

A13

A12

CE#

VCC

RESET#

A11

A10

48-Pin Reverse TSOP

21444B-5

6 Am29F016B

PRELIMINARY

CONNECTION DIAGRAMS

PIN CONFIGURATION

A0–A20 = 21 Addresses

DQ0–DQ7 = 8 Data Inputs/Outputs

CE# = Chip Enable

WE# = Write Enable

OE# = Output Enable

RESET# = Hardware Reset Pin, Active Low

RY/BY# = Ready/Busy Output

VCC = +5.0 V single power supply

(see Product Selec tor Guide for

device speed ratings and voltage

supply tolerances)

VSS = Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

RESET#

A11

A10

DQ0

DQ1

DQ2

DQ3

VSS

VCC

CE#

A12

A13

A14

A15

A16

A17

A18

A19

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

VCC

21444B-6

DQ0–DQ7

A0–A20

CE#

OE#

WE#

RESET# RY/BY#

21444B-7

Am29F016B 7

PRELIMINARY

ORDERING INFORMATION

Standard Prod ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be support-

ed in volum e for thi s dev ice. Cons ult the loc al AM D sale s of-

fice to con firm availability o f specific valid com binations and

to check on newly released combinations.

DEVICE NU MB ER/ DE SCR IP TIO N

Am29F016B

16 Megabit (2 M x 8-Bit) CMO S 5.0 Volt-on ly Sec tor Era se Fla sh Mem or y

5.0 V Read, Program, and Erase

Am29F016B -70 E I

OPTION AL PROCES SI NG

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPER ATURE RAN GE

C=Commercial (0°C to +70°C)

I = Industr ial (–40 °C to +85 °C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package

(TSOP) Rever se Pin out (TS R0 48)

E4 = 40-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 040)

F4 = 40-Pin Thin Small Outline Package

(TSOP) Rever se Pin out (TS R0 40)

S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

Am29F016B-70 EC, EI, FC, FI,

E4C, E4I, F4C, F4I, SC, SI

Am29F016B-90 EC, EI, EE, FC, FI, FE

E4C, E4I, E4E, F4C, F4I,

F4E, SC, SI, SE

Am29F016B-120

Am29F016B-150

8 Am29F016B

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The regi st er is composed of latc hes that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control le vels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29F016B Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0

0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In

Note:

See the sections on Sector Protection and Temporary Sector Unprotect for more information.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device . OE# is the output control

and gates arra y dat a to the output pins . WE# should re-

main at VIH.

The internal state machine is set for reading array

data upon device power-up , or after a hardware reset.

This ensures that no spur ious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs

produce valid data on the device data outputs. The

device remains enabled for read access until the

command reg ister contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

the timing waveforms. ICC1 in the DC Characteristics

table represents the active current specification for

reading array data.

Writing Commands/Command Sequences

To wr ite a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and O E # to V IH.

An erase oper at ion can er ase one sect or, mult iple sec-

tors, or the entire de vice. The Sector Address Tables in-

dicate the address space that each sector occupies. A

“sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the en-

tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autos elect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections f or more information.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tabl es and timing diagrams for write operations.

Operation CE# OE# WE# RESET# A0–A20 DQ0–DQ7

Read L L H H AIN DOUT

Write L H L H AIN DIN

CMOS Sta ndby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z

TTL Standby H X X H X High-Z

Output Disable L H H H X High-Z

Hardware Reset X X X L X High-Z

Temporary Sector Unprotect

(See Note) XXX V

ID AIN DIN

Am29F016B 9

PRELIMINARY

Program and Erase Operation Status

During an erase or prog ram oper ation, th e system ma y

check the status of the operation by reading the status

bits on DQ7–DQ0. St andard read cycle timings and I CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to t he device ,

it can place the device in the standby mode. In this

mode, current co nsumption is g reat ly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The de vice enters the CMOS standby mode when CE#

and RESET# pins are both held at VCC ± 0.5 V. (Note

that this is a more restricted voltage range than VIH.)

The device enters the TTL standby mode when CE#

and RESET# pins are both held at VIH. The device re-

quires standard access time (tCE) f or read access when

the de vice is in either of these standb y modes, bef ore it

is ready to read data.

The device also enters the standby mode when the RE-

SET# pin is dr iven low. Refer to the next section, “RE-

SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics tables, ICC3 represents the

standby current specification .

RESET#: Hardware Reset Pin

The RESET# pin pro vides a har dware method of reset-

ting the device to reading arr ay data. When the s yst em

drives the RESET# pin low for at leas t a period of tRP,

the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the de vice is ready

to accept another comm and sequence, to ensure data

integrity.

Current is reduced for the duration of the RESET#

pulse. W hen RESET# is held at VIL, the device enters

the TTL standby mode; if RESET# is held at VSS ±

0.5 V, the device enters the CMOS standby mode .

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up f i rm-

ware from the Flash memory.

If RESET# is ass erted during a progr am or er ase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor R Y/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the RE-

SET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the de vice is

disabled. The output pins are plac ed in the h igh imped-

ance state.

10 Am29F016B

PRELIMINARY

Table 2. Sector Address Table

Note: All sectors are 64 Kbytes in size.

Sector A20 A19 A18 A17 A16 Address Range

SA0 0 0 0 0 0 000000h-00FFFFh

SA1 0 0 0 0 1 010000h-01FFFFh

SA2 0 0 0 1 0 020000h-02FFFFh

SA3 0 0 0 1 1 030000h-03FFFFh

SA4 0 0 1 0 0 040000h-04FFFFh

SA5 0 0 1 0 1 050000h-05FFFFh

SA6 0 0 1 1 0 060000h-06FFFFh

SA7 0 0 1 1 1 070000h-07FFFFh

SA8 0 1 0 0 0 080000h-08FFFFh

SA9 0 1 0 0 1 090000h-09FFFFh

SA10 0 1 0 1 0 0A0000h-0AFFFFh

SA11 0 1 0 1 1 0B0000h-0BFFFFh

SA12 0 1 1 0 0 0C0000h-0CFFFFh

SA13 0 1 1 0 1 0D0000h-0DFFFFh

SA14 0 1 1 1 0 0E0000h-0EFFFFh

SA15 0 1 1 1 1 0F0000h-0FFFFFh

SA16 1 0 0 0 0 100000h-10FFFFh

SA17 1 0 0 0 1 110000h-11FFFFh

SA18 1 0 0 1 0 120000h-12FFFFh

SA19 1 0 0 1 1 130000h-13FFFFh

SA20 1 0 1 0 0 140000h-14FFFFh

SA21 1 0 1 0 1 150000h-15FFFFh

SA22 1 0 1 1 0 160000h-16FFFFh

SA23 1 0 1 1 1 170000h-17FFFFh

SA24 1 1 0 0 0 180000h-18FFFFh

SA25 1 1 0 0 1 190000h-19FFFFh

SA26 1 1 0 1 0 1A0000h-1AFFFFh

SA27 1 1 0 1 1 1B0000h-1BFFFFh

SA28 1 1 1 0 0 1C0000h-1CFFFFh

SA29 1 1 1 0 1 1D0000h-1DFFFFh

SA30 1 1 1 1 0 1E0000h-1EFFFFh

SA31 1 1 1 1 1 1F0000h-1FFFFFh

Am29F016B 11

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended f or programming equipment

to automatically match a de vice to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the c ommand register.

When using programming equipment, the autoselect

mode requires VID (11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Aut oselect Codes (High Voltage Method) tab le. I n addi-

tion, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order

address bits. Refer to the corresponding Sector Ad-

dress Tables. The Command Definitions table shows

the remaining address bits that are don’t care . When all

necessary b its hav e been set as required, the progr am-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

tions table. This method does not require VID. See

“Command Definitions” for details on using the autose-

lect mode.

Table 3. Am29F016B Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Group Protection/Unprotection

The hardware sector group protection feature dis-

ables both program and erase operations in any sec-

to r gr o u p. Each sector group consists of four adjacent

sectors. Table 4 shows how the sectors are grouped,

and the address range that each sector group con-

tains. The hardware sector group unprotection fea-

ture re-enables both program and erase operations in

previously protected sector groups.

Sector group protection/unprotection must be imple-

mented using programming equipment. The procedure

requires a high v oltage (V ID) on address pin A9 and the

control pins. Details on this method are provided in a

supplement, publication number 19613. Contact an

AMD representativ e to obtain a copy of the ap propriate

document.

The device is shipped with all sector groups unpro-

tected. AMD offers the option of prog r amming a nd pro-

tecting sector groups at its factory prior to shipp ing t he

device through AMD’s ExpressFlash™ Service. Con-

tact an AMD representative for details.

It is possible to determine whether a sector group is

protected or unprotected. See “Autoselect Mode” for

details.

Table 4. Sector Group Addresses

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ-

ously protected sector groups to change data in-sys-

tem. The Sector Group Unprotect mode is activated

by setting the RESET# pin to VID. During this mode,

formerly protected sector g roups can be programmed

or erased by selecting the sector group addresses.

Once VID is removed from the RESET# pin, all the

previously protected sector groups are

protected again. Figure 1 shows the algorithm, and

the Temporar y Sector Group Unprotect diagram (Fig-

ure 16) shows the timing wavefor ms, for this feature.

Description CE# OE# WE# A20-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0 DQ7-DQ0

Manufacturer ID:

AMD LLH X X V

ID XV

IL XV

IL VIL 01h

Device ID:

Am29F016B LLH X X V

ID XV

IL XV

IL VIH ADh

Sector Group

Protection

Verification LLH

Sector

Group

Address XV

ID XV

IL XV

IH VIL

01h (protected)

00h (unprotected)

Sector

Group A20 A19 A18 Sectors

SGA0 0 0 0 SA0

–

SA3

SGA1 0 0 1 SA4

–

SA7

SGA2 0 1 0 SA8

–

SA11

SGA3 0 1 1 SA12

–

SA15

SGA4 1 0 0 SA16

–

SA19

SGA5 1 0 1 SA20

–

SA23

SGA6 1 1 0 SA24

–

SA27

SGA7 1 1 1 SA28

–

SA31

12 Am29F016B

PRELIMINARY

Figure 1. Temporary Sector Group Unprotect

Operation

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection meas ures pre vent a ccidental eras ure or pro-

gramming, which might otherwise be caused by spuri-

ous system level signals during VCC power-up and

power-down transitions, or from system noise.

Low V CC Write Inhibit

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-do wn. The command register and

all internal program/er ase circuits are disabled, and the

dev ice resets . Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical In hibit

Write c ycles are inhibi ted by holding any one of OE#

= VIL, CE# = VIH or WE# = VIH. To initiate a write c y-

cle, CE# and WE# must be a logical zero while OE#

is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power

up, the device does not accept commands on the

rising edge of WE#. The inter nal state machine is

automatically reset to reading array data on

power-up.

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary

Sector Gro up Un prot ect

Completed (Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected

once again.

21444B-8

Am29F016B 13

PRELIMINARY

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates de vice op-

erations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Charac teristics” section.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a progr amming operation in the Erase

Suspend mode, th e system ma y once again read array

data with the same exception. See “Erase Suspend/

Erase Resume Commands” for more infor mation on

this mode.

The system

must

issue the reset command to re-en-

abl e the de vice f or reading arr ay data if DQ5 goes high,

or while in the autoselect mode. See the “Res et Com-

mand” se ctio n , next.

See also “Requirements for Reading Arr ay Data” in the

“Device Bus Operations” section for more infor mation.

The Read Operations table provides the read param e-

ters, and Read Operation Timings diagram shows the

timing diagram.

Reset Command

Writing the reset command to the device reset s the de-

vice to reading array data. Addres s bits are don’t c are

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the aut oselect mode , the re set command

must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command retur ns the device to read-

ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the man uf acturer and devices codes ,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements . This method is an alternativ e to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

mers and requires VID on address bit A9.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

A read cycle at address XX00h retrie v es the manuf ac-

turer code. A read cycle at address XX01h returns the

device code . A read cycle containing a sector address

(SA) and the address 02h in returns 01h if that sector

is protected, or 00h if it is unprotected. Refer to the

Sec tor Addr e s s ta bles for valid s ector ad dr esses.

The system must write the reset command to exit the

autoselect mode and return to reading arra y data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated b y writing two un-

lock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is

not

required to provide fur ther

controls or timings. The device autom atically provides

internally generated progr am pulses and v erify the pro-

grammed cell margin. The Command Definitions take

shows the address and data requirements for the byte

progr am command sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using DQ7,

14 Am29F016B

PRELIMINARY

DQ6, or RY/BY#. See “Write Operation Status” for in-

formation on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinitiated once the de vice has res et to read-

ing array data, to ensure data integr ity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempt ing to do so ma y halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. Howe ver , a succeeding read will show that the

data is still “0”. Only erase operations can con vert a “0”

to a “1”.

Note: See the appropriate Command Definitions table for

program comma nd seq ue nce.

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase is a six-b us-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Eras e

algorithm. The device does

not

require the system to

preprogr am prior to erase. The Embedded Erase algo-

rithm automatically preprogr ams and verifies the entire

memor y for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Not e that a hardware

reset during the chip erase operation imm ediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure data int eg rity.

The system can determine the status of the erase

operation b y using DQ7, DQ6, DQ2, or R Y/BY#. See

“Write Operation Status” for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data

and address es are no long er latched.

Figure 3 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for par ameters, and to the Chip/Sector

Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated b y writing two un-

lock cycles, followed by a set-up command. Two addi-

tional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the sec-

tor erase command sequence.

The device does

not

require the system to preprogram

the memory prior to er ase. The Embedded Erase algo-

rithm automatically progr ams and verifies the s ector f or

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

ma y be done in any sequence , and the number of sec-

tors ma y be from one sector to al l sectors. The time be-

tween these additional cycles mus t be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disab led during this time to

ensure all commands are accepted. The inte rrupts can

be re-enabled after the last Sector Erase command is

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

21444B-9

Am29F016B 15

PRELIMINARY

written. If the time between additional sector erase

commands can be assumed to be les s than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Er ase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence .

Once the sector erase operation has begun, only the

Erase Suspend command is v alid. All oth er commands

are ignored. Note that a hardware reset during the

sector erase operation im mediately terminates the op-

eration. The Sector Eras e command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

When the Embedded Eras e algorithm is complete, the

dev ice returns to reading arra y data and addresses are

no longer latched. The system can determine the sta-

tus of the erase opera tion b y using DQ7, DQ6, DQ2, or

RY/BY#. Refer to “Write Operation Status” for informa-

tion on these status bits.

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “A C Char acteristics ” section f or par amet ers , and to

the Sector Er ase Oper ations Timing dia gr am for timing

waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend c ommand allo ws the s ystem to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and s uspends t he er ase oper at ion. Ad-

dresses are “don’t-cares” when writing the Erase Sus -

pend command.

When the Erase Suspend command is written during a

sector erase oper ation, the devi ce requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not select ed for er asure . (The devic e “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for infor mation on these

status bits.

After an erase-suspended program operation is com-

plete, the system c an once again r ead arra y d ata within

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See “Write Operation Status” for more informa-

tion.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device rever ts to

the Erase Suspend mode, and is ready for another

valid operation. See “ Autoselect Command Sequence”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the s ector erase oper ati on. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be wr itten after the de-

vice has resumed erasing.

16 Am29F016B

PRELIMINARY

Notes:

1. See the appropriate Command Definitions table for erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

21444B-10

Am29F016B 17

PRELIMINARY

Table 5. Am29F016B Command Definitions

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on

the rising edge of WE# or CE# pulse, whichever happens

first.

SA = Address of the sector to be verified (in autoselect mode)

or erased. Address bits A20–A16 select a unique sector.

SGA = Address of the sector group to be verified. Address

bits A20–A 18 select a uniq ue sec tor group.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus

cycles are write operations.

4. Address bits A20–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading

array data.

6. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5

goes high (while the device is providing status data).

7. The f ourth cycle of the autoselect command sequence is

a read cycle.

8. The data is 00h f or an unprotected sector group and 01h

for a protected sector group. See “Autoselect Command

Sequence” for more information.

9. The system may read and program in non-erasing

sectors, or enter the autoselect mode, when in the Erase

Suspend mode. The Erase Suspend command is valid

only during a sector erase operation.

10. The Erase Resume command is valid only during the

Erase Suspend mode.

Command

Sequence

(Note 1)

Bus Cycles (Notes 2–4)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 5) 1 RA RD

Reset (Note 6) 1 XXX F0

Autoselect

(Note 7)

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01

Device ID 4 555 AA 2AA 55 555 90 X01 AD

Sector Grou p Protect

Verify (Note 8) 4 555 AA 2AA 55 555 90 SGA

X02 XX00

XX01

Program 4 555 AA 2AA 55 555 A0 PA PD

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Erase Suspen d (Note 9) 1 XXX B0

Erase Resume (N ote 10) 1 XXX 30

Cycles

18 Am29F016B

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to deter mine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and R Y/BY# . Table 6 and t he f ollowing s ubsections de-

scribe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# P olling is v alid after the rising

edge of the final WE# pulse in the program or erase

command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# P olling on DQ7 is activ e for ap-

proximately 2 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When t he Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous t o the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

After an er ase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active f or approximately 100 µs, then t he de-

vice returns to reading array data. If not all selected

sectors are protec ted, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the system detects DQ7 has changed from the

complement to true data, it can read valid dat a at DQ7–

DQ0 on the

following

read cycles . This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asser ted low. The D ata# Poll-

ing Timings (During Embedded Algorithms) figure in

the “AC Characteristics” section il lustrates this.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21444B-11

Figure 4. Data# Polling Algorithm

Am29F016B 19
PRELIMINARY
RY/BY#: Ready/Busy# 
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open- drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the outpu t is low (Busy ), the de vice is activ ely er asing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array  data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. The timing dia-
grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address,  and is
valid  after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read c ycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles f or app roximately 100 µ s , t hen returns to read ing
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the de vice is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status tab le shows the outp uts for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle  bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on D Q2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the  Embedded Er ase algo rithm is in progr ess),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pu lse in
the command sequence. 
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode info rmation. Ref er t o Tabl e 6 to compare output s
for DQ2 and DQ6. 
Figure 5 shows the toggle bit algorithm in flowchart
for m, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subse ction.
Refer  to the Toggle Bit Timings figure for the toggle bit
timing diagr am. The DQ2 vs. DQ6 figure sho ws the dif-
ferences between DQ2 and DQ6 in gr aphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle  bi t is togg ling. Typically, a
system w ould note and  store the v alue  of the toggle  bit
after the first read. After t he second read, the syst em
would co mpare the ne w v alue of the  toggle bit  with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can r ead arra y data on  DQ7–DQ0 on  the f ollowing
read cycle.
However, if after the initial two read c ycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as  DQ5 went high. If  the toggle bit is  no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
dev ice did not complete the operat ion successfully, and

20 Am29F016B

PRELIMINARY

the system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is togglin g and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successiv e read cycles , de-

termining the stat us as described in the previous par a-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it re turns to determine

the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exc eeded a specified inter nal pulse count limit. U nder

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the prog ram or er ase cycle w as

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system ma y read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tiona l sector s are selected f or erasure, th e enti re time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the s ystem can gua rant ee that t he ti me betw een ad-

ditional sector erase commands will always be less

than 50 µ s . See also the “ Secto r Era se Command Se-

quence” sect ion.

After the sector erase command sequence is written,

the system should re ad the s tatus on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence , and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other th an Er ase Su spend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the s ystem softw are should chec k the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 6 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it ma y stop toggling as DQ5

changes to “1”. See text.

21444B-12

Figure 5. Toggle Bit Algorithm

(Notes

1, 2)

(Note 1)

Am29F016B 21

PRELIMINARY

Table 6. Write Operation Status

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Operation DQ7

(Note 1) DQ6 DQ5

(Note 2) DQ3 DQ2

(Note 1) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

22 Am29F016B

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

A9, OE#, RESET# (Note 2). . . . .–2.0 V to 12.5 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, inputs may overshoot VSS to –2.0 V

for periods of up to 20 ns. See Figure 6. Maximum DC

voltage on output and I/O pins is VCC + 0.5 V. During

voltage transitions, outputs ma y overshoot to VCC + 2.0 V

for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on A9, OE#, RESET# pins is

–0.5V. During v oltage transitions, A9, OE#, RESET# pins

may overshoot VSS to –2.0 V for periods of up to 20 ns.

See Figure 6. Maximum DC input voltage on A9, OE#,

and RESET# is 12.5 V which ma y overshoot to 13.5 V for

periods up to 20 ns.

3. No more than one output shorted at a time. Duration of

the short circuit should not be greater than one second.

Stresses greater than those listed in this section may cause

permanent damage to the device. This is a stress rating

only; functional operation of the device at these or any other

conditions above those indicated in the operational sections

of this specification is not implied. Exposure of the device to

absolute maximum rating conditions for extended periods

may affect device reliability.

Figure 6. Maximu m Negative Overshoot

Waveform

Figure 7. Maximum Positive Over shoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Case Temperature (TC) . . . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Case Temperature (TC) . . . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for± 10% de vices . . . . . . . . . . . .+4.5 V to +5.5 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

21444B-13

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

21444B-14

Am29F016B 23

PRELIMINARY

DC CHARACTERISTICS

TTL/NMOS Compatible

CMOS Compatible

Notes for DC Characteristics (both tables):

1. The ICC current is typically less than 1 mA/MHz, with OE# at VIH.

2. ICC active while Embedded Program or Embedded Erase algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH 25 40 mA

ICC2 VCC Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 40 60 mA

ICC3 VCC Standby Current

(CE# Controlled) VCC = VCC Max, CE# = VIH,

RESET# = VIH 0.4 1.0 mA

ICC4 VCC Standby Current

(RESET# Controlled) VCC = VCC Max, RESET# = VIL 0.4 1.0 mA

VIL Input Low Level –0.5 0.8 V

VIH Input High Level 2.0 VCC + 0.5 V

VID Voltage for Autoselect and Sector

Protect VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V

VOH Output High Level IOH = –2.5 mA VCC = VCC Min 2.4 V

VLKO L ow VCC Lock-out Voltage 3.2 4.2 V

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH 25 40 mA

ICC2 VCC Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 30 40 mA

ICC3 VCC Standby Current

(CE# Controlled) VCC = VCC Max, CE# = VCC ± 0.5 V,

RESET# = VCC ± 0.5 V 15µA

CC4 VCC Standby Current

(RESET# Controlled) VCC = VCC Max,

RESET# = VSS ± 0.5 V 15µA

IL Input Low Level –0.5 0.8 V

VIH Input High Level 0.7x VCC VCC + 0.3 V

VID Voltage for Autoselect

and Sector Protect VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC – 0.4 V

VLKO L ow VCC Lock-out Voltage 3.2 4.2 V

24 Am29F016B

PRELIMINARY

TEST CONDITIONS

Table 7. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

5.0 V

Device

Under

Test

21444B-15

Figure 8. Test Setup

Note: Diodes are IN3064 or equivalent

Test Condition All speed

options Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 100 pF

Input Rise and Fall Times 20 ns

Input Pulse Levels 0.45–2.4 V

Input timing measurement

reference levels 0.8 V

Output timing measurement

reference levels 2.0 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Am29F016B 25

PRELIMINARY

AC CHARACTERISTICS

Read-only Operations

Notes:

1. Not 100% tested.

2. Refer to Figure 1 and Table 6 for test specifications.

Parameter Symbol

Parameter Description Test

Setup

Speed Options

UnitJEDEC Standard -70 -90 -120 -150

tAVAV tRC Read Cycle Time (Note 1) Min 70 90 120 150 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 70 90 120 150 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 40 40 50 55 ns

tOEH Output Enable Hold

Time (Note 1)

Read Min0000ns

Toggle and

Data# Polling Min10101010ns

EHQZ tDF Chip Enable to Output High Z (Note 1) Max 20 20 30 35 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 20 20 30 35 ns

tAXQX tOH Output Hold Time From Addresses CE#

or OE# Whichever Occurs First Min0000ns

Ready RESET# Pin Low to Read Mode

(Note 1) Max20202020µs

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

21444B-16

Figure 9. Read O peration Ti mi ng s

26 Am29F016B

PRELIMINARY

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (See Note) Min 50 ns

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

21444B-17

Figure 10. RESET# Timings

Am29F016B 27

PRELIMINARY

AC CHARACTERISTICS

Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter

Parameter Description

Speed Options

UnitJEDEC Std -70 -90 -120 -150

tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 150 ns

tAVWL tAS Address Set up Tim e Min 0 ns

tWLAX tAH Address Hold Time Min 40 45 50 50 ns

tDVWH tDS Data Setup Tim e Min 40 45 50 5 0 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL Read Recover Time Before Write

(OE# high to WE# low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 40 45 50 50 ns

tWHWL tWPH Write Pulse Wid th High Min 20 ns

tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

Max 8 sec

tVCS VCC Set Up Time (Note 1) Min 50 µs

tBUSY WE# to RY/BY# Valid Min 40 40 50 60 ns

28 Am29F016B

PRELIMINARY

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tGHWL

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

Note: PA = program address, PD = program data, DOUT is the true data at the program address.

21444B-18

Figure 11. Program Operation Timings

Am29F016B 29

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tGHWL

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

RY/BY#

tRB

tBUSY

Note:

SA = Sector Address. VA = Valid Address for reading status data.

21444B-19

Figure 12. Chip/Sector Erase Operation Timings

30 Am29F016B

PRELIMINARY

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note:

V A = V alid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

21444B-20

Figure 13. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

tOE

DQ6/DQ2

RY/BY#

tBUSY

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

tACC

tRC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note:

V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,

and array data read cycle.

21444B-21

Figure 14. Toggle Bit Timings (During Embedded Algorithms)

Am29F016B 31

PRELIMINARY

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std. Description Unit

tVIDR VID Rise and Fall Tim e (S ee Note) Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

Enter

Erase

Enter Erase

Suspend Pro gra m

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the

erase-suspe nd ed sec tor.

21444B-22

Figure 15. DQ2 vs. DQ6

RESET#

tVIDR

12 V

0 or 5 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 5 V

21444B-23

Figure 16. Temporary Sector Group Unprotect Timings

32 Am29F016B

PRELIMINARY

AC CHARACTERISTICS

Erase and Program Operations

Alternate CE# Controlled Writes

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Symbol

Parameter Description

Speed Options

UnitJEDEC Standard -70 -90 -120 -150

tAVAV tWC Write Cyc le Time (N ote 1) Min 7 0 90 120 1 50 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 40 45 50 50 ns

tDVEH tDS Data Setup Time Min 40 45 50 50 ns

tEHDX tDH Address Hold Time Min 0 ns

tGHEL tGHEL Read Recover Time Before Write Min 0 ns

tWLEL tWS CE# Setup Time Min 0 ns

tEHWH tWH CE# Hold Time Min 0 ns

tELEH tCP Write Puls e Width Min 4 0 45 50 50 ns

tEHEL tCPH Write Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

Max 8 sec

Am29F016B 33

PRELIMINARY

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.

2. Figure indicates the last two bus cycles of the command sequence.

21444B-24

Figure 17. Alternate CE# Controlled Write Operation Timing s

34 Am29F016B

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 5.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then

does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-lev el overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further

information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTIC

Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25

C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 8 se c Excludes 00h programming prior to

erasure (Note 4)

Chip Erase Time 32 256 sec

Byte Programming Time 7 300 µs Excludes system-level overhead

(Note 5)

Chip Programming Time (Note 3) 14.4 43.2 sec

Min Max

Input Voltage with respect to VSS on I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

Am29F016B 35

PRELIMINARY

PH YS ICAL DIMENSIONS

TS 040—40-Pin Standard Thin Small Outline Package (measured in millimeters)

TSR040—40-Pin Reverse Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

Pin 1 I.D.

0.50 BSC

9.90

10.10

0.95

1.05

0.05

0.15

1.20

MAX

0.50

0.70

0°

5°

16-038-TSOP-1_AE

TS 040

2-27-97 lv

0.10

0.21

0.08

0.20

18.30

18.50

19.80

20.20

Pin 1 I.D.

0.50 BSC

9.90

10.10

0.95

1.05

0.05

0.15

1.20

MAX

0.50

0.70

0°

5°

16-038-TSOP-1_AE

TSR040

2-27-97 lv

0.10

0.21

0.08

0.20

36 Am29F016B

PRELIMINARY

PH YSICAL DIMENSI ONS (continued)

TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)

TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

11.90

12.10

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48-2

TS 048

DT95

8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

18.30

18.50

19.80

20.20

11.90

12.10

SEATING PLANE

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48

TSR048

DT95

8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

Am29F016B 37

PRELIMINARY

PH YSICAL DIMENSI ONS (continued)

SO 044—44-Pin Small Outline Package (measured in millimeters)

44 23

122

13.10

13.50 15.70

16.30

1.27 NOM.

28.00

28.40

2.17

2.45

0.35

0.50 0.10

0.35

2.80

MAX. SEATING

PLANE

16-038-SO44-2

SO 044

DF83

8-8-96 lv

0.10

0.21

0.60

1.00

0°

8°

END VIEW

SIDE VIEW

TOP VIEW

38 Am29F016B

PRELIMINARY

REVISION SUMMARY FOR AM29F016B

Revision B

Global

Made for matting and layout consistent with other data

sheets. Used updated common tab l es and diagrams.

Revision B+1

AC Characteristi cs—Read-only Operations

Deleted note referring to output driver dis able time.

Figure 16—Tempor ar y Sector Group Unprotect

Timings

Corrected title to indicate “sector group.”

Revision B+2

Global

Added -70 speed option, deleted -75 speed option.

Distinctive Characteri stics

Changed minimum 100K write/erase cycles guaran-

teed to 1,000,000.

Ordering Information

Added extended temperature availability to -90, -120,

and -150 speed options.

Operating Ranges

Added extended temperature range.

DC Characteristics, CMOS Compatible

Corrected the CE# and RESET# test conditions for

ICC3 and ICC4 to VCC ±0.5 V.

AC Characteristics

Erase/Program Operations; Erase and Program Oper-

ations Alternate CE# Controlled Wr ites:

Corrected the

notes ref erence f or tWHWH1 and tWHWH2. These param-

eters are 100% tested. Corrected the note ref erence for

tVCS. This parameter is not 100% tested.

Temporary Sector Unprotect Table

Added note reference for tVIDR. This parameter is not

100% tested.

Erase and Programming Performance

Changed minimum 100K program and erase cycles

guaranteed to 1,000,000.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.