THIS SPEC IS OBSOLETE Spec No: 001-51592 Spec Title: STK14CA8 128KX8 AUTOSTORE NVSRAM Sunset Owner: Girija Chougala (GVCH) Replaced by: None STK14CA8 128Kx8 AutoStore nvSRAM Features Description [1] 25 , 35, 45 ns Read Access and Read/Write Cycle Time Unlimited Read/Write Endurance Automatic Nonvolatile STORE on Power Loss Nonvolatile STORE Under Hardware or Software Control Automatic RECALL to SRAM on Power Up Unlimited RECALL Cycles 200K STORE Cycles 20-Year Nonvolatile Data Retention Single 3.0V + 20%, -10% Operation Commercial and Industrial Temperatures Small Footprint SOIC and SSOP Packages (RoHS Compliant) The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvolatile QuantumTrap storage element included with each memory cell. This SRAM provides fast access and cycle times, ease of use, and unlimited read and write endurance of a normal SRAM. Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The Cypress nvSRAM is the first monolithic nonvolatile memory to offer unlimited writes and reads. It is the highest performing and most reliable nonvolatile memory available. Logic Block Diagram VCC Quantum Trap 1024 X 1024 ROW DECODER A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 VCAP POWER CONTROL STORE STATIC RAM ARRAY 1024 X 1024 RECALL STORE/ RECALL CONTROL HSB SOFTWARE DETECT INPUT BUFFERS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A15 - A0 COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 A11 G E W Note 1. 25 ns speed in Industrial temperature range is over the operating voltage range of 3.3V+ 0.3V only. Cypress Semiconductor Corporation Document Number: 001-51592 Rev. *D * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised March 02, 2011 STK14CA8 Contents Features............................................................................... 1 Description.......................................................................... 1 Logic Block Diagram.......................................................... 1 Contents .............................................................................. 2 Pinouts ................................................................................ 3 Pin Descriptions ................................................................. 3 Absolute Maximum Ratings .............................................. 4 DC Characteristics ............................................................. 4 Capacitance ........................................................................ 6 SRAM READ Cycles #1 and #2 .................................... 7 SRAM WRITE Cycles #1 and #2................................... 8 AutoStore/POWER UP RECALL ........................................ 9 Software Controlled STORE/RECALL Cycle .................. 10 Hardware STORE Cycle ................................................... 11 Soft Sequence Commands ............................................... 11 Mode Selection ................................................................. 12 nvSRAM Operation........................................................... 13 nvSRAM ...................................................................... 13 Document Number: 001-51592 Rev. *D SRAM READ ............................................................... 13 SRAM WRITE ............................................................. 13 AutoStore Operation.................................................... 13 Hardware STORE (HSB) Operation............................ 13 Hardware RECALL (Power Up)................................... 13 Software STORE......................................................... 14 Software RECALL ....................................................... 14 Data Protection............................................................ 14 Noise Considerations .................................................. 14 Best Practices ............................................................. 14 Low Average Active Power ......................................... 15 Preventing AutoStore....................................................... 15 Package Diagrams............................................................ 17 Document History Page .................................................... 18 Sales, Solutions, and Legal Information ........................ 18 Worldwide Sales and Design Support......................... 18 Products ...................................................................... 18 Page 2 of 17 STK14CA8 Pinouts Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC VCAP 1 48 VCC VCAP 1 32 VCC A16 A14 2 47 A15 A16 2 31 A15 3 46 HSB 30 4 5 6 43 A5 6 27 42 HSB W A13 A8 7 NC A7 A6 A5 A4 29 28 A6 W A13 A8 4 5 45 44 A14 A12 3 A12 A7 7 26 8 25 A3 A2 9 24 10 23 A9 NC 8 41 A4 9 40 A11 NC 10 39 NC NC 11 38 NC A9 A11 G A10 NC 12 37 NC 22 13 36 VSS A1 A0 11 VSS 12 21 NC NC 14 35 NC DQ0 13 20 15 34 14 DQ6 DQ5 16 33 DQ4 17 32 G 15 18 A3 A2 DQ1 DQ2 VSS 19 DQ0 NC DQ6 31 A10 17 18 16 DQ3 A1 19 30 E A0 DQ1 DQ2 20 29 DQ7 21 28 DQ5 22 23 27 DQ4 NC 26 DQ3 NC 24 25 VCC E DQ7 Figure 3. Relative PCB Area Usage[2] Pin Descriptions Pin Name I/O Description A16-A0 Input DQ7-DQ0 I/O E Input Chip Enable: The active low E input selects the device. W Input Write Enable: The active low W allows to write the data on the DQ pins to the address location latched by the falling edge of E. G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins to tri-state. VCC Power Supply HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection is optional). VCAP Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. VSS Power Supply Ground. NC No Connect Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array. Data: Bi-directional 8-bit data bus for accessing the nvSRAM. Power: 3.0V, +20%, -10%. Unlabeled pins have no internal connections. Note 2. See Package Diagrams on page 16 for detailed package size specifications. Document Number: 001-51592 Rev. *D Page 3 of 17 STK14CA8 Absolute Maximum Ratings NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS Voltage on Input Relative to Ground.................-0.5V to 4.1V Voltage on Input Relative to VSS ...........-0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB ......................-0.5V to (VCC + 0.5V) Temperature under Bias ............................... -55C to 125C Junction Temperature ................................... -55C to 140C Storage Temperature .................................... -65C to 150C Power Dissipation............................................................. 1W DC Output Current (1 output at a time, 1s duration).... 15 mA jc 5.4 C/W; ja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm]. RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS jc 6.2 C/W; ja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm]. Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Characteristics (VCC = 2.7V to 3.6V) Symbol Parameter Commercial Min Max Industrial Min Max Units Notes ICC1 Average VCC Current 65 55 50 70 60 55 mA mA mA tAVAV = 25 ns tAVAV = 35 ns tAVAV = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. ICC2 Average VCC Current during STORE 3 3 mA All Inputs Don't Care, VCC = max Average current for duration of STORE cycle (tSTORE) ICC3 Average VCC Current at tAVAV = 200 ns 3V, 25C, Typical 10 10 mA ICC4 Average VCAP Current during AutoStore Cycle 3 3 mA ISB VCC Standby Current (Standby, Stable CMOS Levels) 3 3 mA IILK Input Leakage Current 1 1 A VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current 1 1 A VCC = max VIN = VSS to VCC, E or G VIH VIH Input Logic "1" Voltage 2.0 VCC+0.3 2.0 VCC+0.3 V All Inputs VIL Input Logic "0" Voltage VSS-0.5 0.8 VSS-0.5 0.8 V All Inputs VOH Output Logic "1" Voltage VOL Output Logic "0" Voltage TA Operating Temperature 0 70 VCC Operating Voltage 2.7 3.6 120 2.4 2.4 All Inputs Don't Care Average current for duration of STORE cycle (tSTORE) E VCC -0.2V) All Others VIN0.2V or (VCC-0.2V) Standby current level after nonvolatile cycle complete V IOUT = - 2 mA 0.4 V IOUT = 4 mA -40 85 C 2.7 3.6 V 3.0V +20%, -10% 17 120 F Between VCAP pin and VSS, 5V rated. 0.4 VCAP Storage Capacitance 17 NVC Nonvolatile STORE operations 200 200 DATAR Data Retention 20 20 Note W (V CC - 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads. K Years At 55 C The HSB pin has IOUT=-10 uA for VOH of 2.4 V, this parameter is characterized but not tested. Document Number: 001-51592 Rev. *D Page 4 of 17 STK14CA8 AC Test Conditions Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times 5 ns Input and Output Timing Reference Levels .................... 1.5V Output Load..................................See Figure 4 and Figure 5 Capacitance (TA = 25C, f = 1.0 MHz) Symbol Parameter[3] Max Units CIN Input Capacitance 7 pF COUT Output Capacitance 7 pF Conditions V = 0 to 3V V = 0 to 3V Figure 4. AC Output Loading 3.0V 577 Ohms OUTPUT 30 pF INCLUDING SCOPE AND FIXTURE 789 Ohms Figure 5. AC Output Loading for Tristate Specifications (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ) 3.0V 577 Ohms OUTPUT 789 Ohms 5 pF INCLUDING SCOPE AND FIXTURE Note 3. These parameters are guaranteed but not tested. Document Number: 001-51592 Rev. *D Page 5 of 17 STK14CA8 SRAM READ Cycles #1 and #2 Symbols NO. STK14CA8-25[1] STK14CA8-35 Parameter #1 #2 Alt. Min Max Min Max Min tELQV tACS Chip Enable Access Time 2 tELEH[4] tRC Read Cycle Time 3 tAVQV[5] tAVQV[5] tAA Address Access Time 25 35 45 ns tGLQV tOE Output Enable to Data Valid 12 15 20 ns tAXQX[5] tOH Output Hold after Address Change 3 3 3 ns 6 tELQX tLZ Address Change or Chip Enable to Output Active 3 3 3 ns 7 tEHQZ[6] tHZ Address Change or Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active tGHQZ[6] tELICCH[3] tEHICCL[3] tOHZ Output Disable to Output Inactive tPA Chip Enable to Power Active tPS Chip Disable to Power Standby 4 5 9 10 11 tAXQX[5] 35 Units Max tAVAV[4] 1 25 STK14CA8-45 25 35 45 45 10 13 0 0 15 0 10 13 0 0 35 ns ns 15 0 25 ns ns ns ns 45 ns Figure 6. SRAM READ Cycle #1: Address Controlled[4, 5, 7] 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID Figure 7. SRAM READ Cycle #2: E and G Controlled[4, 7] 2 29 1 11 6 7 3 9 4 8 10 Notes 4. W must be high during SRAM READ cycles. 5. Device is continuously selected with E and G both low 6. Measured 200mV from steady state output voltage. 7. HSB must remain high during READ and WRITE cycles Document Number: 001-51592 Rev. *D Page 6 of 17 STK14CA8 SRAM WRITE Cycles #1 and #2 NO. Symbols #1 #2 Alt. STK14CA8-25[1] Parameter Min Max STK14CA8-35 Min Max STK14CA8-45 Min Max Units 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns 15 tDVWH tDVEH tDW Data Setup to End of Write 10 12 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Setup to End of Write 20 25 30 ns 18 tAVWL tAVEL tAS Address Setup to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 ns 20 tWLQZ[6,8] tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write 10 3 13 3 15 3 ns ns Figure 8. SRAM WRITE Cycle #1: W Controlled[8,9] 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN 16 tWHDX DATA VALID 20 tWLQZ DATA OUT HIGH IMPEDANCE PREVIOUS DATA 21 tWHQX Figure 9. SRAM WRITE Cycle #2: E Controlled[8,9] 12 tAVAV ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH 13 tWLEH W 15 tDVEH DATA IN DATA OUT 16 tEHDX DATA VALID HIGH IMPEDANCE Notes 8. If W is low when E goes low, the outputs remain in the high impedance state. 9. E or W must be VIH during address transitions. Document Number: 001-51592 Rev. *D Page 7 of 17 STK14CA8 AutoStore/POWER UP RECALL NO. Symbols STK14CA8 Parameter Standard Alternate Min Power up RECALL Duration Units Notes 20 ms 10 11, 12 Max 22 tHRECALL 23 tSTORE STORE Cycle Duration 12.5 ms 24 VSWITCH Low Voltage Trigger Level 2.65 V 25 VCCRISE VCC Rise Time tHLHZ 150 s t Figure 10. AutoStore/POWER UP RECALL 25 23 22 23 22 Note Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. Notes 10. tHRECALL starts from the time VCC rises above VSWITCH 11. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place 12. Industrial Grade devices require maximum 15 ms. Document Number: 001-51592 Rev. *D Page 8 of 17 STK14CA8 Software Controlled STORE/RECALL Cycle NO. Symbols E Cont G Cont Parameter[13,14] Alt STK14CA8-25[1] Min Max STK14CA8-35 Min Max STK14CA8-45 Min Max Units Notes 26 tAVAV tAVAV tRC STORE/RECALL Initiation Cycle Time 25 35 45 ns 27 tAVEL tAVGL tAS Address Setup Time 0 0 0 ns 28 tELEH tGLGH tCW Clock Pulse Width 20 25 30 ns 29 tEHAX tGHAX Address Hold Time 1 1 1 ns 30 tRECALL tRECALL RECALL Duration 50 50 50 14 s Figure 11. Software STORE/RECALL CYCLE: E Controlled[14] 26 26 27 28 29 23 30 Figure 12. Software STORE/RECALL CYCLE: G Controlled[14] 26 27 26 28 23 30 29 Notes 13. The software sequence is clocked on the falling edge of E controlled READs or G controlled READs 14. The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles. Document Number: 001-51592 Rev. *D Page 9 of 17 STK14CA8 Hardware STORE Cycle NO. Symbols Standard 31 tDELAY 32 tHLHX Parameter Alternate tHLQZ STK14CA8 Min Max Hardware STORE to SRAM Disabled 1 70 Hardware STORE Pulse Width 15 Units Notes s 15 ns Figure 13. Hardware STORE Cycle 32 23 31 Soft Sequence Commands Symbols NO. 33 Parameter Standard tSS STK14CA8 Min Soft Sequence Processing Time Units Notes s 16, 17 Max 70 Figure 14. Software Sequence Commands 33 33 Notes 15. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete. 16. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. 17. Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command. Document Number: 001-51592 Rev. *D Page 10 of 17 STK14CA8 Mode Selection E W G A16-A0 Mode I/O Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output Data Output Data Output Data Output Data Output Data Output Data Active 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output Data Output Data Output Data Output Data Output Data Output Data Active 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Output Data Output Data Output Data Output Data Output Data Active 0x08FC0 Nonvolatile Store Output High Z ICC2 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output Data Output Data Output Data Output High Z Active L L L H H H L L L Notes 18, 19, 20 18, 19, 20 18, 19, 20 18, 19, 20 Notes 18. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. 19. While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes 20. I/O state depends on the state of G. The I/O table shown assumes G low Document Number: 001-51592 Rev. *D Page 11 of 17 STK14CA8 SRAM READ The STK14CA8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-16 determine which of the 131,072 data bytes are accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs are valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs repeatedly responds to address changes within the tAVQV access time without the need for transitions on any control input pins, and remains valid until another address change or until E or G is brought high, or W and HSB is brought low. To reduce unneeded nonvolatile stores, AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress. Figure 15. AutoStore Mode VCC VCAP VCC W 0.1F The STK14CA8 nvSRAM has two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates similar to a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The STK14CA8 supports unlimited read and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations. 10k Ohm nvSRAM on page 4 for the size of the capacitor. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. VCAP nvSRAM Operation SRAM WRITE Hardware STORE (HSB) Operation A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 are written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. The STK14CA8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14CA8 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pull up and is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry turns off the output buffers tWLQZ after W goes low. AutoStore Operation The STK14CA8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). AutoStore operation is a unique feature of Cypress Quantum Trap technology is enabled by default on the STK14CA8. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 15 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to DC Characteristics Document Number: 001-51592 Rev. *D SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14CA8 continues to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low, it is allowed a time tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes low are inhibited until HSB returns high. If HSB is not used, it should be left unconnected. Hardware RECALL (Power Up) During power up or after any low power condition (VCC<VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. Page 12 of 17 STK14CA8 Software STORE Data Protection Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initiated by executing sequential E controlled or G controlled READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. After a STORE cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed. The STK14CA8 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC<VSWITCH. To initiate the software STORE cycle, the following READ sequence must be performed: Read Address 0x4E38 Valid READ Read Address 0xB1C7 Valid READ Read Address 0x83E0 Valid READ Read Address 0x7C1F Valid READ Read Address 0x703F Valid READ Read Address 0x8FC0 Initiate STORE Cycle When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles be used in the sequence and that G is active. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation. If the STK14CA8 is in a WRITE mode (both E and W low) at power up, after a RECALL, or after a STORE, the WRITE is inhibited until a negative transition on E or W is detected. This protects against inadvertent writes during power up or brown out conditions. Noise Considerations The STK14CA8 is a high speed memory and so must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are a short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise. Best Practices nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprograms these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on. should always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. Power up boot firmware routines should rewrite the nvSRAM into the desired state such as AutoStore enabled. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on.) If AutoStore is firmware disabled, it does not reset to "AutoStore enabled" on every power down event captured by the nvSRAM. The application firmware should re-enable or re-disable AutoStore on each reset sequence based on the behavior desired. The Vcap value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max Vcap value because the nvSRAM internal algorithm calculates Vcap charge time based on this max Vcap value. Customers that want to use a larger Vcap value to make sure there is extra store charge and store time should discuss their Vcap size selection with Cypress to understand any impact on the Vcap voltage level at the end of a tRECALL period. Software RECALL Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled or G controlled READ operations must be performed: Read Address 0x4E38 Valid READ Read Address 0xB1C7 Valid READ Read Address 0x83E0 Valid READ Read Address 0x7C1F Valid READ Read Address 0x703F Valid READ Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for READ or WRITE operations. The RECALL operation in no way alters the data in the nonvolatile storage elements. Document Number: 001-51592 Rev. *D Page 13 of 17 STK14CA8 Low Average Active Power CMOS technology provides the STK14CA8 with the benefit of power supply current that scales with cycle time. Less current is drawn as the memory cycle time becomes longer than 50 ns. Figure 16 shows the relationship between ICC and READ/WRITE cycle time. Worst case current consumption is shown for commercial temperature range, VCC=3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14CA8 depends on the following items: 1. The duty cycle of chip enable 2. The overall cycle rate for operations 3. The ratio of READs to WRITEs 4. The operating temperature 5. The VCC Level 6. I/O Loading Figure 16. Current vs Cycle Time Preventing AutoStore The AutoStore function can be disabled by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled or G controlled READ operations must be performed: Read Address 0x4E38 Valid READ Read Address 0xB1C7 Valid READ Read Address 0x83E0 Valid READ Read Address 0x7C1F Valid READ Read Address 0x703F Valid READ Read Address 0x8B45 AutoStore Disable The AutoStore can be re-enabled by initiating an AutoStore Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled or G controlled READ operations must be performed: Read Address 0x4E38 Valid READ Read Address 0xB1C7 Valid READ Read Address 0x83E0 Valid READ Read Address 0x7C1F Valid READ Read Address 0x703F Valid READ Read Address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled. Document Number: 001-51592 Rev. *D Page 14 of 17 STK14CA8 Ordering Information STK14CA8-R F 45 ITR Packing Option Blank=Tube TR=Tape and Reel Temperature Range Blank=Commercial (0 to +70 C) I= Industrial (-45 to +85 C) Access Time 25=25 ns 35=35 ns 45=45 ns Lead Finish F=100% Sn (Matte Tin) RoHS Compliant Package N=Plastic 32-pin 300 mil SOIC (50 mil pitch) R=Plastic 48-pin 300 mil SSOP (25 mil pitch) Ordering Codes These parts are not recommended for new designs. Part Number STK14CA8-NF25 STK14CA8-NF35 STK14CA8-NF45 STK14CA8-NF25TR STK14CA8-NF35TR STK14CA8-NF45TR STK14CA8-RF25 STK14CA8-RF35 STK14CA8-RF45 STK14CA8-RF25TR STK14CA8-RF35TR STK14CA8-RF45TR STK14CA8-NF25I STK14CA8-NF35I STK14CA8-NF45I STK14CA8-NF25ITR STK14CA8-NF35ITR STK14CA8-NF45ITR STK14CA8-RF25I STK14CA8-RF35I STK14CA8-RF45I STK14CA8-RF25ITR STK14CA8-RF35ITR STK14CA8-RF45ITR Description 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3.3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3.3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3V 128Kx8 AutoStore nvSRAM SOP32-300 3.3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3.3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 3V 128Kx8 AutoStore nvSRAM SSOP48-300 Document Number: 001-51592 Rev. *D Access Times 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns Temperature Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Page 15 of 17 STK14CA8 Package Diagrams Figure 17. 32-Pin 300 mil SOIC (51-85127) PIN 1 ID 16 1 DIMENSIONS IN INCHES[MM] 0.292[7.416] 0.299[7.594] REFERENCE JEDEC MO-119 0.405[10.287] 0.419[10.642] 17 MIN. MAX. PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. 32 SEATING PLANE 0.810[20.574] 0.822[20.878] 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.050[1.270] TYP. 0.026[0.660] 0.032[0.812] 0.014[0.355] 0.020[0.508] 0.004[0.101] 0.0100[0.254] 0.006[0.152] 0.012[0.304] 0.021[0.533] 0.041[1.041] 51-85127 *B Figure 18. 48-Pin 300 mil SSOP (51-85061) 51-85061 *D Document Number: 001-51592 Rev. *D Page 16 of 17 STK14CA8 Document History Page Document Title: STK14CA8 128Kx8 AutoStore nvSRAM Document Number: 001-51592 Revision ECN Orig. of Change Submission Date ** 2665610 GVCH/PYRS 02/04/09 New data sheet *A 2821358 GVCH 12/04/09 Added Note in Ordering Information mentioning that these parts are not recommended for new designs. Added "Not recommended for New Designs" watermark in the PDF. Added Contents on page 2. *B 2895330 GVCH 03/18/10 Added foot note 1 for 25ns access speed, Updated Package Diagram 48-Pin 300 mil SSOP. Updated Ordering Codes Description *C 2902517 GVCH 03/31/2010 Added watermark "Not Recommended for New Designs" in pdf version. Move to external web. *D 3185985 GVCH 03/02/2011 Obsolete datasheet Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2009-2011. 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Document Number: 001-51592 Rev. *D Revised March 02, 2011 All other products and company names mentioned in this document may be the trademarks of their respective holders. Page 17 of 17