THIS SPEC IS OBSOLETE
Spec No: 001-51592
Spec Title: STK14CA8 128KX8 AUTOSTORE NVSRAM
Sunset Owner: Girija Chougala (GVCH)
Replaced by
:
None
STK14CA8
128Kx8 AutoStore nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-51592 Rev. *D Revised March 02, 2011
Features
■25[1], 35, 45 ns Read Access and Read/Write Cycle Time
■Unlimited Read/Write Endurance
■Automatic Nonvolatile STORE on Power Loss
■Nonvolatile STORE Under Hardware or Software Control
■Automatic RECALL to SRAM on Power Up
■Unlimited RECALL Cycles
■200K STORE Cycles
■20-Year Nonvolatile Data Retention
■Single 3.0V + 20 % , -10% Opera ti o n
■Commercial and Industrial Temperatures
■Small Footprint SOIC and SSOP Packages (RoHS Compliant)
Description
The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol-
atile QuantumTrap storage element included with each memory
cell. This SRAM provides fast access and cycle times, ease of
use, and unlimited read and write endurance of a normal SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is de tected (th e STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performing
and most reliable nonvolatile memory available.
ROW DECODER
INPUT BUFFERS
COLUM N D EC
G
E
W
COLUM N I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT A15 – A0
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
Quantum Trap
1024 X 1024
STATIC RAM
ARRAY
1024 X 1024
STORE
RECALL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0 A1 A2 A3 A4 A 10 A11
VCC VCAP
Logic Block Diagram
Note
1. 25 ns speed in Industrial temper ature range is over the operating voltage range of 3.3V+ 0.3V only.
STK14CA8
Document Number: 001-51592 Rev. *D Page 2 of 17
Contents
Features ............................................................................... 1
Description.......................................................................... 1
Logic Block Diagram.......................................................... 1
Contents.............................................................................. 2
Pinouts ................................................................................ 3
Pin Descriptions................................................................. 3
Absolute Maximum Ratings .............................................. 4
DC Characteristics ....................... ............................ ... ... .... 4
Capacitance ........................................................................ 6
SRAM READ Cycles #1 and #2.................................... 7
SRAM WRITE Cycles #1 and #2................................... 8
AutoStore/POWER UP RECALL........................................ 9
Software Controlled STORE/RECALL Cycle. ................. 10
Hardware STORE Cycle ................................................... 11
Soft Sequence Commands...............................................11
Mode Selection................................................................. 12
nvSRAM Operation........................................................... 13
nvSRAM...................................................................... 13
SRAM READ............................................................... 13
SRAM WRITE............................................................. 13
AutoStore Operation... ... ... ........................................... 13
Hardware STORE (HSB) Operation............................ 13
Hardware RECALL (Power Up)................................... 13
Software STORE................. ........................................ 14
Software RECALL....................... ... ... .......................... 14
Data Protection.................................. ... ... .................... 14
Noise Considerations.................................................. 14
Best Practices ............................................................. 14
Low Average Active Power ......................................... 15
Preventing AutoStore...... ... ... ........................................... 15
Package Diagrams............................................................ 17
Document History Page.............. .. ............................. .. ... ..18
Sales, Solutions, and Legal Information........................ 18
Worldwide Sales and Design Supp ort......................... 18
Products...................................................................... 18
STK14CA8
Document Number: 001-51592 Rev. *D Page 3 of 17
Pinouts
Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC
Figure 3. Relative PCB Area Usage[2]
Pin Descriptions
Note
2. See Package Diagrams on page 16 for detailed package size specifications.
A16
A14
A12
A7
DQ0
DQ1
DQ2
A4
A2
A1
VCAP
A13
A8
A9
A11
A10
DQ7
DQ6
VSS
A0
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A6
A3
A5
32
31
30
29
VCC
HSB
W
DQ5
DQ3
DQ4
G
E
A15
Pin Name I/O Description
A16-A0Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.
DQ7-DQ0I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
EInput Chip Enable: The active low E input selects the device.
WInput Write Enable: The active low W allows to write the data on the DQ pins to the address location
latched by the falling edge of E.
GInput Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high causes the DQ pins to tri-state.
VCC Power Supply Power: 3.0V, +20%, -10%.
HSB I/O Hardware Store Busy: When low this output indicates a S t ore is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection is optional).
VCAP Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
VSS Power Supply Ground.
NC No Connect Unlabeled pins have no internal connections.
STK14CA8
Document Number: 001-51592 Rev. *D Page 4 of 17
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to VSS...........–0.5V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB.................... ..–0.5V to (VCC + 0.5V)
Temperature under Bias............................... –55C to 125C
Junction Temperature................................... –55C to 140C
Storage Temperature........ ... ......................... –65C to 150C
Power Dissipation................ ... ..........................................1W
DC Output Current (1 output at a time, 1s duration)....15 mA
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
jc 5.4 C/W; ja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
jc 6.2 C/W; ja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].
Note: Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to the device.
This is a stress rating only , and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
DC Characteristics
(VCC = 2.7V to 3.6V)
Note The HSB pin has IOUT=-10 uA for VOH of 2.4 V, this parameter is characterized but not tested.
Symbol Parameter Commercial Industrial Units Notes
Min Max Min Max
ICC1Average VCC Curre nt 65
55
50
70
60
55
mA
mA
mA
tAVAV = 25 ns
tAVAV = 35 ns
tAVAV = 45 ns
Dependent on output loading and cycle
rate. Values obtained without outp ut
loads.
ICC2Average VCC Curre nt during
STORE 3 3 mA All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (tSTORE)
ICC3Average VCC Current at tAVAV =
200 ns
3V, 25°C, Typical
10 10 mA W (VCC – 0.2V)
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without outp ut
loads.
ICC4Average VCAP Current during
AutoStore Cy cle 3 3 mA All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE)
ISB VCC Standby Current
(Standby, Stable CMOS Levels) 33mAE VCC -0.2V)
All Others VIN0.2V or (VCC-0.2V)
Standby current level after nonvolatile
cycle complete
IILK Input Leakage Current 11AV
CC = max
VIN = VSS to VCC
IOLK Off-State Output Leakage
Current 11AV
CC = max
VIN = VSS to VCC, E or G VIH
VIH Input Logic “1” Voltage 2.0 VCC+0.3 2.0 VCC+0.3 V All Inputs
VIL Input Logic “0” Voltage VSS–0.5 0.8 VSS–0.5 0.8 V All Inputs
VOH Output Logic “1” Voltage 2.4 2.4 V IOUT = –2 mA
VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 4 mA
TAOperating Temperature 0 70 –40 85 C
VCC Operating Voltage 2.7 3.6 2.7 3.6 V 3.0V +20%, -10%
VCAP Storage Capacitance 17 120 17 120 FBetween V
CAP pin and VSS, 5V rated.
NVCNonvolatile STORE operations 200 200 K
DATARData Retention 20 20 Years At 55 C
STK14CA8
Document Number: 001-51592 Rev. *D Page 5 of 17
AC Test Conditions
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times 5 ns
Input and Output Timing Reference Levels....................1.5V
Output Load..................................See Figure 4 and Figure 5
Capacitance
(TA = 25C, f = 1.0 MHz)
Figure 4. AC Output Loading
Figure 5. AC Output Loading for Tristate Specifications
(tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ)
Symbol Parameter[3] Max Units Conditions
CIN Input Capacitance 7 pF V = 0 to 3V
COUT Output Capacita nce 7 pF V = 0 to 3V
577 Ohms
30 pF
789 Ohms
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
577 Ohms
5 pF
789 Ohms
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
Note
3. These parameters are guaranteed but not tested.
STK14CA8
Document Number: 001-51592 Rev. *D Page 6 of 17
SRAM READ Cycles #1 and #2
Figure 6. SRAM READ Cycle #1: Address Cont rolled[4, 5, 7]
Figure 7. SRAM READ Cycle #2: E and G Controlled[4 , 7]
NO. Symbols Parameter STK14CA8-25[1] STK14CA8-35 STK14CA8-45 Units
#1 #2 Alt. Min Max Min Max Min Max
1tELQV tACS Chip Enable Access Time 25 35 45 ns
2tAVAV[4] tELEH[4] tRC Read Cycle Time 25 35 45 ns
3tAVQV[5] tAVQV[5] tAA Address Access T ime 25 35 45 ns
4tGLQV tOE Output Enable to Data Valid 12 15 20 ns
5tAXQX[5] tAXQX[5] tOH Output Hold after Address
Change 333ns
6tELQX tLZ Address Change or Chip Enable
to Output Active 333ns
7tEHQZ[6] tHZ Address Change or Chip Disable
to Output Inactive 10 13 15 ns
8tGLQX tOLZ Output Enable to Output Active 0 0 0 ns
9tGHQZ[6] tOHZ Output Disable to Output Inactive 10 13 15 ns
10 tELICCH[3] tPA Chip Enable to Power Active 0 0 0 ns
11 tEHICCL[3] tPS Chip Disable to Power Standby 25 35 45 ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
Notes
4. W must be high during SRAM READ cycles.
5. Device is continuously selected with E and G both low
6. Measured 200mV from steady state output voltage.
7. HSB must remain high during READ and WRITE cycles
229
11
7
9
10
84
3
61
STK14CA8
Document Number: 001-51592 Rev. *D Page 7 of 17
SRAM WRITE Cycles #1 and #2
Figure 8. SRAM WRITE Cycle #1: W Controlled[8,9]
Figure 9. SRAM WRITE Cycle #2: E Controlled[8,9]
NO. Symbols Parameter STK14CA8-25[1] STK14CA8-35 STK14CA8-45 Units
#1 #2 Alt. Min Max Min Max Min Max
12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns
13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 ns
14 tELWH tELEH tCW Chip Enable to End of Wr ite 20 25 30 ns
15 tDVWH tDVEH tDW Data Setu p to End of Write 10 12 15 ns
16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns
17 tAVWH tAVEH tAW Address Setup to End of Write 20 25 30 ns
18 tAVWL tAVEL tAS Address Setup to Start of Write 0 0 0 ns
19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 ns
20 tWLQZ[6,8] tWZ Write Enable to Output Disable 10 13 15 ns
21 tWHQX tOW Output Active after End of Write 3 3 3 ns
Notes
8. If W is low when E goes low, the outputs remain in the high impedan ce state.
9. E or W must be VIH during address transitions.
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
tAVAV
W
16
tWHDX
DATA IN
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
DATA IN
12
tAVAV
16
tEHDX
13
tWLEH
19
tEHAX
18
tAVEL
17
tAVEH
DATA VALID
15
tDVEH
HIGH IMPEDANCE
14
tELEH
DATA OUT
E
ADDRESS
W
DATA IN
STK14CA8
Document Number: 001-51592 Rev. *D Page 8 of 17
AutoS tore/POWER UP RECALL
t
Figure 10. AutoStore/POWER UP RECALL
Note Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
NO. Symbols Parameter STK14CA8 Units Notes
Standard Alternate Min Max
22 tHRECALL Power up RECALL Duration 20 ms 10
23 tSTORE tHLHZ STORE Cycle Duration 12.5 ms 11, 12
24 VSWITCH Low Voltage Trigger Level 2.65 V
25 VCCRISE VCC Rise Time 150 s
Notes
10.tHRECALL starts from the time VCC rises above VSWITCH
11. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE take s place
12.Industrial Grade devices require maximum 15 ms.
25
23 23
22 22
STK14CA8
Document Number: 001-51592 Rev. *D Page 9 of 17
Software Controlled STORE/RECA LL Cycle
Figure 11. Software STORE/RECALL CYCLE: E Controlled[14]
Figure 12. Software STORE/RECALL CYCLE: G Controlled[14]
NO. Symbols Parameter[13,14] STK14CA8-25[1] STK14CA8-35 STK14CA8-45 Units Notes
E Cont G Cont Alt Min Max Min Max Min Max
26 tAVAV tAVAV tRC STORE/RECALL Initiation
Cycle Time 25 35 45 ns 14
27 tAVEL tAVGL tAS Address Setup Time 0 0 0 ns
28 tELEH tGLGH tCW Clock Pulse Width 20 25 30 ns
29 tEHAX tGHAX Address Hold T i me 1 1 1 ns
30 tRECALL tRECALL RECALL Duration 50 50 50 s
26 26
27 28
29
23 30
26 26
27 28
29 23 30
Notes
13.The software sequen ce is clocked on the falling edge of E controlled READs or G controlled READs
14.The six consecutive addresses must be read in the order listed in the Sof tware STORE/RECALL Mode Selection T able. W must be high during all six consecutive cycles.
STK14CA8
Document Number: 001-51592 Rev. *D Page 10 of 17
Hardware STORE Cycle
Figure 13. Hardware STORE Cycle
Soft Sequence Commands
Figure 14. Software Sequence Commands
NO. Symbols Parameter STK14CA8 Units Notes
Standard Alternate Min Max
31 tDELAY tHLQZ Hardware STORE to SRAM Disabled 1 70 s 15
32 tHLHX Hardware STORE Pulse Width 15 ns
32
23
31
NO. Symbols Parameter STK14CA8 Units Notes
Standard Min Max
33 tSS Soft Sequence Processing Time 70 s16, 17
33 33
Notes
15.On a hardware ST ORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete.
16.This is the amount of time that it takes to take acti on on a soft sequence command. Vcc power must remain high to effectively register command.
17.Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
STK14CA8
Document Number: 001-51592 Rev. *D Page 11 of 17
Mode Selection
E W G A16-A0Mode I/O Power Notes
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x08B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
18, 19, 20
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
18, 19, 20
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active 18, 19, 20
0x08FC0 Nonvolatile Store Output High Z ICC2
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
18, 19, 20
Notes
18.The six consecutive addresses must be in the order listed. W mus t be high during all six consecutive cycles to enable a nonvolat ile cycle.
19.While there are 17 addresses on the STK14CA8, only the lower 16 are used to control softwar e modes
20.I/O state depends on the state of G. The I/O tabl e shown assumes G low
STK14CA8
Document Number: 001-51592 Rev. *D Page 12 of 17
nvSRAM Operation
nvSRAM
The STK14CA8 nvSRAM has two functional components paired
in the same physical cell. These are the SRAM memory cell and
a nonvolatile QuantumTrap cell. The SRAM memory cell
operates similar to a standard fast static RAM. Dat a in the SRAM
can be transferred to the nonvolatile cell (the STORE operation),
or from the nonvolatile cell to SRAM (the RECALL operation).
This unique architecture allows all cells to be stored and recalled
in parallel. During the STORE and RECALL operations, SRAM
READ and WRITE operations are inhibited. The STK14CA8
supports unlimited read and writes similar to a typical SRAM. In
addition, it provides unlimited RECALL operations from the
nonvolatile cells and up to 200K STORE operations.
SRAM READ
The STK14CA8 performs a READ cycl e whenever E and G are
low while W and HSB are high. The address specified on pins
A0-16 determine which of the 131,072 d ata bytes are accessed.
When the READ is initiated by an address transition, the outputs
are valid after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E and G, the outputs are valid at tELQV or at tGLQV,
whichever is later (READ cycle #2). The data outputs repeatedly
responds to address changes within the tAVQV access time
without the need for transitions on any control input pins, and
remains valid until another address change or until E or G is
brought high, or W and HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB
is high. The address inputs must be stable prior to entering the
WRITE cycle and must remain stable until either E or W goes
high at the end of the cycle. The data on the common I/O pins
DQ0-7 are written into memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an E
controlled WR I TE.
It is recommended that G be kept high during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If G is
left low, internal circuitry turns off the output buffers tWLQZ after
W goes low.
AutoStore Operation
The STK14CA8 stores data to nvSRAM using one of three
storage operations. These three operations are Hardware Store
(activated by HSB), Software Store (activated by an address
sequence), and AutoStore (on power down).
AutoStore operation is a unique feature of Cypress Quantum
Trap technology is enabled by default on the STK14CA8.
During normal operation, the device draws current from V CC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 15 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Characteristics
on page 4 for the size of the capacitor. The voltage on the VCAP
pin is driven to 5V by a charge pu mp internal to the chip. A pull
up should be placed on W to hold it inactive during power up.
To reduce unneeded nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whe ther a WRITE o peration has taken
place. The HSB signal can be monitored by the system to detect
an AutoStore cycle is in progress.
Figure 15. AutoStore Mode
Hardware STORE (HSB) Operation
The STK14CA8 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
low, the STK14CA8 conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM took place since the last STORE or RECALL cycle.
The HSB pin has a very resistive pull up and is internally driven
low to indicate a busy condition while the STORE (initiated by
any means) is in progress. This pin should be externally pu lled
up if it is used to drive other inputs.
SRAM READ and WRITE operati ons that are in prog ress when
HSB is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB goes low , the
STK14CA8 continues to allow SRAM operations for tDELAY.
During tDELAY, multiple SRAM READ operations may take place.
If a WRITE is in progress when HSB is pulled low , it is allowed a
time tDELAY to complete. However, any SRAM WRITE cycles
requested after HSB goes low are inhibited until HSB returns
high.
If HSB is not used, it should be left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition
(VCC<VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
VCC
VCAP
10k Ohm
0.1µF
VCC
VCAP
W
STK14CA8
Document Number: 001-51592 Rev. *D Page 13 of 17
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The STK14CA8
software STORE cycle is initiated by executing sequential E
controlled or G controlled READ cycles from six specific address
locations in exact order. During the STORE cycle, previous dat a
is erased and then the new data is programmed into the nonvol-
atile elements. After a STORE cycle is initiated, further memory
inputs and outputs are disabled until the cycle is completed.
To initiate the software STORE cycle, the following READ
sequence must be performed:
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence
and that G is active. After the tSTORE cycle time is fulfilled, the
SRAM is again activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled or G
controlled READ operations must be performed:
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is trans-
ferred into the SRAM cells. After the tRECALL cycle time, the
SRAM is again ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the nonvolatile
storage elements.
Data Protection
The STK14CA8 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The lo w voltage condition is detected when
VCC<VSWITCH.
If the STK14CA8 is in a WRITE mode (both E and W low) at
power up, after a RECALL, or after a STORE, the WRITE is
inhibited until a negative transition on E or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Noise Considerations
The STK14CA8 is a high speed memory and so must have a high
frequency bypass capacitor of approximately 0.1 µF co nnected
between VCC and VSS, using l eads and traces that are a short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Best Practice s
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and qua lity assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume an NV array is in a
set programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on. should always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■Power up boot firmware routines should rewrite the nvSRAM
into the desired state such as AutoStore enabled. While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, and so on.)
■If AutoStore is firmware disabled, it does not reset to “AutoStore
enabled” on every power down event captured by the nvSRAM.
The application firmware should re-enable or re-disable
AutoStore on each reset sequence based on the behavior
desired.
■The Vcap value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the max Vcap value because the
nvSRAM internal algorithm calculates Vcap charge time based
on this max Vcap value. Customers that want to use a larger
Vcap value to make sure there is extra store charge and store
time should discuss their Vcap size selection with Cypress to
understand any impact on the Vcap voltage level at the end of
a tRECALL period.
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Address 0x8FC0 Initiate STORE Cycle
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Address 0x4C63 Initiate RECALL Cycle
STK14CA8
Document Number: 001-51592 Rev. *D Page 14 of 17
Low Average Active Power
CMOS technology provides the STK14CA8 with the benefit of
power supply current that scales with cycle time. Less current is
drawn as the memory cycle time becomes longer than 50 ns.
Figure 16 shows the relationship between ICC and
READ/WRITE cycle time. Worst case current consumption is
shown for commercial temperature range, VCC=3.6V, and chip
enable at maximum frequency. Only standby current is drawn
when the chip is disabled. The overall average current drawn by
the STK14CA8 depends on the following items:
1. The duty cycle of chip enable
2. The overall cycle rate for operations
3. The ratio of READs to WRITEs
4. The operating temperature
5. The VCC Level
6. I/O Loading
Figure 16. Current vs Cycle Time
Preventing AutoStore
The AutoStore function can be disabled by initiating an
AutoStore Disable sequence. A sequence of READ operations
is performed in a manner similar to the software STORE initi-
ation. To initiate the AutoStore Di sable sequence, the following
sequence of E controlled or G controlled READ operations must
be performed:
The AutoStore can be re-enabled by initiating an AutoStore
Enable sequence. A sequence of READ operations is performed
in a manner similar to the software RECALL initiation. To initiate
the AutoStore Enable sequence, the following sequence of E
controlled or G controlled READ operations must be performed:
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Addres s 0x8 B45 AutoStore Disabl e
Read Address 0x4E38 Valid READ
Read Address 0xB1C7 Valid READ
Read Address 0x83E0 Valid READ
Read Address 0x7C1F Valid READ
Read Address 0x703F Valid READ
Read Address 0x4B46 AutoStore Enable
STK14CA8
Document Number: 001-51592 Rev. *D Page 15 of 17
Ordering Information
Ordering Codes
These parts are not recommended for new designs.
Packing Option
Blank=Tube
TR=Tape and Reel
Temperature Range
Blank=Commercial (0 to +70 C)
I= Industrial (-45 to +85 C)
Access Time
25=25 ns
35=35 ns
45=45 ns
Lead Finish
F=100% Sn (Matte Tin) RoHS Compliant
Package
N=Plastic 32-pin 300 mil SOIC (50 mil pitch)
R=Plastic 48-pin 300 mil SSOP (25 mil pitch)
STK14CA8-R F 45 ITR
Part Number Description Access Times Temperature
STK14CA8-NF25 3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Commercial
STK14CA8-NF35 3V 128Kx8 AutoStore nvSRAM SOP32-300 35 ns Commercial
STK14CA8-NF45 3V 128Kx8 AutoStore nvSRAM SOP32-300 45 ns Commercial
STK14CA8-NF25TR 3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Commercial
STK14CA8-NF35TR 3V 128Kx8 AutoStore nvSRAM SOP32-300 35 ns Commercial
STK14CA8-NF45TR 3V 128Kx8 AutoStore nvSRAM SOP32-300 45 ns Commercial
STK14CA8-RF25 3V 128Kx8 AutoStore nvSRAM SSOP48-300 25 ns Commercial
STK14CA8-RF35 3V 128Kx8 AutoStore nvSRAM SSOP48-300 35 ns Commercial
STK14CA8-RF45 3V 128Kx8 AutoStore nvSRAM SSOP48-300 45 ns Commercial
STK14CA8-RF25TR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 25 ns Commercial
STK14CA8-RF35TR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 35 ns Commercial
STK14CA8-RF45TR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 45 ns Commercial
STK14CA8-NF25I 3.3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Industrial
STK14CA8-NF35I 3V 128Kx8 AutoStore nvSRAM SOP32-300 35 ns Industrial
STK14CA8-NF45I 3V 128Kx8 AutoStore nvSRAM SOP32-300 45 ns Industrial
STK14CA8-NF25ITR 3.3V 128Kx8 AutoStore nvSRAM SOP32-300 25 ns Industrial
STK14CA8-NF35ITR 3V 128Kx8 AutoStore nvSRAM SOP32-300 35 ns Industrial
STK14CA8-NF45ITR 3V 128Kx8 AutoStore nvSRAM SOP32-300 45 ns Industrial
STK14CA8-RF25I 3.3V 128Kx8 AutoStore nvSRAM SSOP48-300 25 ns Industrial
STK14CA8-RF35I 3V 128Kx8 AutoStore nvSRAM SSOP48-300 35 ns Industrial
STK14CA8-RF45I 3V 128Kx8 AutoStore nvSRAM SSOP48-300 45 ns Industrial
STK14CA8-RF25ITR 3.3V 128Kx8 AutoStore nvSRAM SSOP48-300 25 ns Industrial
STK14CA8-RF35ITR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 35 ns Industrial
STK14CA8-RF45ITR 3V 128Kx8 AutoStore nvSRAM SSOP48-300 45 ns Industrial
STK14CA8
Document Number: 001-51592 Rev. *D Page 16 of 17
Package Diagrams
Figure 17. 32-Pin 300 mil SOIC (51-85127)
Figure 18. 48-Pin 300 mil SSOP (51-85061)
PIN 1 ID
SEATING PLANE
116
17 32
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.292[7.416]
0.299[7.594]
0.405[10.287]
0.419[10.642]
0.050[1.270]
TYP.
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.0100[0.254]
0.006[0.152]
0.012[0.304]
0.021[0.533]
0.041[1.041]
0.026[0.660]
0.032[0.812]
0.004[0.101]
REFERENCE JEDEC MO-119
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
0.014[0.355]
0.020[0.508]
0.810[20.574]
0.822[20.878]
51-85127 *B
51-85061 *D
Document Number: 001-51592 Rev. *D Revised March 02, 2011 Page 17 of 17
All other products and company names mentioned in this document may be the trademarks of their respective holders.
STK14CA8
© Cypress Semico nducto r Co rpora tion , 2009 -2011. The information cont ained her ein is subje ct to chang e with out no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products a re n ot war r ant ed nor int e nded to be used fo r
medical, life supp or t, lif e savi n g, critical control or safety applicatio ns, unless pursuan t to a n express writte n ag re em en t with Cypress. Furthermore, Cypress does not author iz e it s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product s in life-support syst ems
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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Document Title: STK14CA8 128Kx8 AutoStore nvSRAM
Document Number: 001-51592
Revision ECN Orig. o f
Change Submission
Date Description of Change
** 2665610 GVC H/PYRS 02/04/09 New data sheet
*A 2821358 GVCH 12/04/09 Added Note in Ordering Information mentioning that these parts are not
recommended for new design s.
Added “Not recommended for New Designs” watermark in the PDF.
Added Contents on page 2.
*B 2895330 GVCH 03/18/10 Added foot note 1 for 25ns access speed, Updated Package Diagram 48-Pin
300 mil SSOP. Updated Ordering Codes De scription
*C 2902517 GVCH 03/31/2010 Added watermark "Not Recommended for New Designs" in pdf version.
Move to external web.
*D 3185985 GVCH 03/02/2011 Obsolete datasheet