M45PE20-VMN6P - MICRON TECHNOLOGY

May 2008 Rev 6 1/47

M45PE20

2-Mbit, page-erasable serial flash memory

with byte alterability and a 75 MHz SPI bus interface

Features

■SPI bus compatible serial interface

■75 MHz cloc k rate (maximum)

■2.7 V to 3.6 V single supply voltage

■2-Mbit, page-erasable flash memory

■Page size: 256 bytes

– Page write in 11 ms (typical)

– Page program in 0.8 ms (typical)

– Page erase in 10 ms (typical)

■Sector erase (512 Kbits )

■Hardware write protection of the bottom sector

(64 Kbytes)

■Electronic signature

– JEDEC standard two-byte signature

(4012h)

– Unique ID code (UID) with 16 bytes read-

only, available upon customer request only

in the T9HX process

■Deep power-down mode 1 µA (typical)

■More than 10 0 00 0 writ e cyc le s

■More than 20 years data retention

■Packages

– ECOPACK® (RoHS compliant)

SO8 (MN)

150 mil width

VFQFPN8 (MP)

(MLP8)

www.numonyx.com

Contents M45PE20

2/47

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13

4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.6 Active power, standby power and deep power-down modes . . . . . . . . . . 13

4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3 Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

M45PE20 Contents

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6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.5 Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.6 Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 23

6.7 Page write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.8 Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.9 Page erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.10 Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.11 Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.12 Release from deep power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

List of tables M45PE20

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List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 8. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 12. AC characteristics (25 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 13. AC characteristics (33 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 14. AC characteristics (50 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 15. AC characteristics (75 MHz operation, T9HX (0.11 µm) process) . . . . . . . . . . . . . . . . . . . 40

Table 16. SO8N – 8 lead plastic small outline, 150 mils body width, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 17. MLP8, 8-lead very thin dual flat package no lead, 6 × 5 mm, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

M45PE20 List of figures

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List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. SO and VFQFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20

Figure 9. Read status register (RDSR) instruction sequ ence and data-out sequence . . . . . . . . . . . 21

Figure 10. Read data bytes (READ) inst ruction sequence and data-out sequence . . . . . . . . . . . . . . 22

Figure 11. Read data bytes at higher speed (FAST_READ) instruction sequence

and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. Page write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 13. Page program (PP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 14. Page erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 15. Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 16. Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17. Release from deep power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 31

Figure 18. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 21. Write protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 22. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 23. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 24. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 43

Figure 25. MLP8, 8-lead very thin dual flat package no lead, 6 × 5 mm, package outline. . . . . . . . . . 44

Description M45PE20

6/47

1 Description

The M45PE20 is a 2-Mbit (25 6 Kbits ×8) serial paged flash memory accessed by a high

speed SPI-compatible bus.

The memory can be written or programmed 1 to 256 b ytes at a time , using the page write or

page prog ram instruction. The page write instruction consist s of an integr ated page erase

cycle followed by a page program cycle.

The memory is organized as 4 sectors, each containing 256 pages. Each page is 256 bytes

wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144

bytes.

The memory can be erased a page at a time, using the page er ase instruction, or a sect or at

a time, using the sector erase instruction.

Important note

This datasheet deta ils the functionalit y of the M45PE20 devices, based on the pre vious T7X

process or based on the curr ent T9HX process (available since August 2007). Delivery of

parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008 .

Figure 1. Logic diagram

Figure 2. SO and VFQFPN connections

1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to

VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

2. See Package mechanical section for package dimensions, and how to identify pin-1.

Reset

AI07400

VCC

M45PE20

VSS

AI07401

5WS VCC

VSS

Reset

M45PE20

M45PE20 Description

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Table 1. Signal names

Signal name Function Direction

C Serial Clo ck Input

D Serial data in put Input

Q Serial data ou tput Output

SChip Select Input

WWrite Protect Input

Reset Reset Input

VCC Supply voltage

VSS Ground

Signal descriptions M45PE20

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2 Signal descriptions

2.1 Serial data output (Q)

This output signal is used to tr ansf er data serially out of the de vice . Data is shifted out on the

falling edge of Serial Clock (C).

2.2 Serial data input (D)

This input signal is used to transfer data serially into the de vice. It receives instructions,

addresses, and the data to be programmed. Values are lat ched on the rising edge of Serial

Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at serial data input (D) are latched on the rising edge of Serial Clock (C). Data on

serial data output (Q) changes after the falling edge of Serial Cloc k (C).

2.4 Chip Select (S)

When this input signal is High, th e device is deselected and serial data output (Q) is at high

impedance. Unless an internal read, prog ram, e rase or write cycle is in prog ress , the device

will be in the standby power mode (this is not the deep power-do wn mode). Driving Chip

Select (S) Low selects the device, placing it in the active power mode.

After power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5 Reset (Reset)

The Reset (Reset) input pr ovides a hardw are reset f or the memory. In this mode, the outpu ts

are high impedance.

When Reset (Reset) is driven High, the memory is in the normal operating mode. When

Reset (Reset) is driven Lo w, the memory will enter the reset mode, pro vided that no internal

operat ion is currently in prog ress. Driving Reset (Reset) Low while an internal operation is in

progress has no effect on that internal operation (a write cycle, program cycle, or erase

cycle).

2.6 Write Protect (W)

This input signal pu ts the device in the hardw are protect ed mode , when Write Protect (W) is

connected to VSS, causing the first 256 p ages of memory to become read- only by pr otecting

them from write, program and erase operations. When Write Protect (W) is connected to

VCC, the first 256 page s of mem o ry be h ave like the ot he r pa g es of mem o ry.

M45PE20 Signal descriptions

9/47

2.7 VCC supply voltage

VCC is the supply voltage.

2.8 VSS ground

VSS is the reference for the VCC supply voltage.

SPI modes M45PE20

10/47

3 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two follo wing modes:

●CPOL=0, CPHA=0

●CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference betw een t he two modes , as shown in Figure 4, is the clock polarity when the

bus mast er is in standby mode and not transferring data:

●C remains at 0 for (CPOL=0, CPHA=0)

●C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. Bus master and memory devices on the SPI bus

1. The Write Protect (W) signal should be driven, High or Low as appropriate.

Figure 3 shows a n examp le of three de vices connected t o an MCU , on an SPI bus . Only one

device is selected at a time, so only one device drives the serial data output (Q) line at a

time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure

that the M45PE20 is not selected if the bus master leaves the S line in the high impedance

state . As the bus master ma y enter a state wher e all inputs/outputs are in high impedance at

the same time (for ex ample, when the bus master is reset), the clock line (C) must be

connected to an external pull-down resistor so that, when all inputs/outputs become high

impedance, the S line is pulled High while the C line is pulled Lo w ( thus ensuring that S a nd

C do not become High at the same time, and so, that the tSHCH requirement is met). The

typical v alue of R is 100 kΩ, ass um i ng th at the tim e co nst an t R*Cp (Cp = parasitic

capacitance of the bus line) is shorter than the time during which the bus master leaves the

SPI bus in high impe dance.

AI12836c

SPI bus master

SPI memory

device

SDO

SDI

SCK

CQD

SPI memory

device

CQD

SPI memory

device

CQD

CS3 CS2 CS1

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WReset WWReset

RR R

VCC

VCC VCC VCC

VSS

VSS VSS VSS

Reset

M45PE20 SPI modes

11/47

Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the bus

master never leaves the SPI bus in the high impedance state for a time period shorter than

5µs.

Figure 4. SPI modes supported

AI01438B

MSB

CPHA

CPOL

MSB

Operating features M45PE20

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4 Operating features

4.1 Sharing the overhead of modifying data

To write or program one (or more) data bytes, two instructions are required: write enable

(WREN), which is one byte, and a page write (PW) or page program (PP) sequence, which

consists of f our by tes plus data. This is f ollo w ed b y the internal cycle (of duration t PW or tPP).

To share this overhead, the page write (PW) or page prog ram (PP) instruction allows up to

256 bytes to be programmed (changing bits from ‘1’ to ‘0’) or written (changing bits to ‘0’ or

‘1’) at a time, provided that they lie in consecutive addresses on the same page of memory.

4.2 An easy way to modify data

The page write (PW) instruction provides a convenient way of modifying data (up to 256

contiguous bytes at a time), and simply requires the start address, and the new data in the

instruction sequence.

The page write (PW) instruction is entered by driving Chip Select (S) Low, an d then

transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte,

and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data

bytes are written to the data buffer, starting at the address given in the third address byte

(A7-A0). When Chip Select (S) is driven High, the write cycle starts. The remaining,

unchanged, bytes of the data buffer are automatically loaded with the values of the

correspond in g bytes of the add re sse d mem o ry pa g e. The addressed memory page the n

automatically put into an erase cycle. Finally, the addressed memory page is programmed

with the contents of the data buffer.

All of this buffer management is handled internally, and is transparent to the user. The user

is given the facility of being ab le to alter the contents of the memory on a byte-by-byte basis.

For optimized timings, it is recommended to use the page write (PW) instruction to write all

consecutive targeted bytes in a single sequence versus using several page write (PW)

sequences with each containing only a few bytes (see Section 6 .7: Page write (PW),

Table 14: AC characteristics (50 MHz operation), and Table 15: AC ch aracteristics (75 MHz

operation, T9HX (0.11 µm) process)).

M45PE20 Operating features

13/47

4.3 A fast wa y to modify data

The page program (PP) instruction provides a fast way of modifying data (up to 256

contiguous bytes at a time), provided that it only involves resetting bits to 0 that had

previously been set to ‘1’.

This might be:

●when the designer is programming the device for the first time

●when the designer knows that the page has already been erased by an earlier page

erase (PE) or sector erase (SE) instruction. This is useful, for example , when storing a

fast stream of data, having first performed the erase cycle when time was availab le

●when the designer knows that the only changes involve resetting bits to ‘0’ that are still

set to ‘1’. When this method is possible, it has the additional advantage of minimizing

the number of unnecessary erase operations, and the extra stress incurred by each

page.

F or optimized timings, it is recommended to use the page program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several page

program (PP) sequences with each containing only a few bytes (see Section 6.8: Page

program (PP), Tab le 14: AC characteristics (50 MHz operation), and Table 15: AC

characteristics (75 MHz operation, T9HX (0.11 µm) process)).

4.4 Polling during a write, program or erase cycle

A further improv e ment in the write, prog ram or er ase time can be achie v ed b y not waiting f or

the worst case dela y (tPW, tPP

, tPE, or tSE). The write in progress (WIP) bit is provided in the

status register so that the application program can monitor its va lue, polling it to establish

when the previous cycle is complete.

4.5 Reset

An internal power on reset circuit helps protect against inadvertent data writes. Addition

protection is provided by driving Reset (Reset) Low during the power-on process, and only

driving it High when VCC has reached the correct voltage level, VCC(min).

4.6 Active power, standby power and deep power-down modes

When Chip Select (S) is Low, the device is selected, and in the active power mode.

When Chip Select (S) is High, the d e vice is deselecte d, b ut could remain in the act iv e powe r

mode until all in ternal cycles have completed (pro gram, erase, write). The device then goes

in to the standby power mode. The device consumption drops to ICC1.

The deep power-down mo de is ente red whe n the spe cific inst ruction (the de ep po w er -do w n

(DP) instruction) is executed. The device consumption drops further to ICC2. The device

remains in this mode until another specific instruction (the release from deep power-down

and read electronic signature (RES) instruction) is executed.

All other instructions are ignored while the de vice is in the deep po wer-do wn mode. This can

be used as an e xtr a sof twa re protectio n mechanism, when the device is not in active use, to

protect the device from inadvertent write, program or erase instructions.

Operating features M45PE20

14/47

4.7 Status register

The status register contains two status bits that can be read by the read status register

(RDSR) instruction. See Section 6.4: Read status regist er (RDSR) f or a detailed description

of the status register bits.

4.8 Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can oper ate correctly in the presence of excessive noise . To help combat this, the

M45PE20 features the following data protection mechanisms:

●Power on reset and an internal timer (tPUW) can pr ovide protection against inadvertent

changes while the power supply is outside the operating specification

●Progr am, erase and write instructions are checked that they consist of a number of

clock pulses that is a multiple of eight, before they are accepted for execution

●All instructions that modify data m ust be preceded by a Write Enable (WREN)

instruction to set the Write Enab le Latch (WEL) bit. This bit is retu rned to its rese t st ate

by the following events:

–Power-up

– Reset (Reset) driven Low

– Write disable (WRDI) instruction completion

– Page write (PW) instruction completion

– Page program (PP) instruction completion

– Page erase (PE) instruction completion

– Sector erase (SE) instruction completion

●The hardware protected mode is entered when Write Protect (W) is driven Low,

causing the first 25 6 pages of mem ory to become re ad-only. When Write Protect ( W) is

driven High, the first 256 pa ges of memory behave like the other pages of memory

●The Reset (Reset) signal can be driven Low to protect the contents of the memory

during any critical time, not just during power-up and power-down

●In addition to the low power consumption feature, the deep power-down mode offers

extra software protection from inadvertent write, program and erase instructions while

the device is not in active use.

M45PE20 Memory organization

15/47

5 Memory organization

The memory is organized as:

●1024 pages (256 bytes each).

●262,144 bytes (8 bits each)

●4 sectors (512 Kbits, 65536 bytes each)

Each page can be individually:

●programmed (bits are programmed from ‘1’ to ‘0’)

●erased (bits are erased from ‘0’ to ‘1’)

●written (bits are changed to either ‘0’ or ‘1’)

The device is page or sector erasable (bit s are erased from ‘0’ to ‘1’).

Table 2. Memory organization

Sector Address range

3 30000h 3FFFFh

2 20000h 2FFFFh

1 10000h 1FFFFh

0 00000h 0FFFFh

Memory organization M45PE20

16/47

Figure 5. Block diagram

AI07402

WControl logic High voltage

generator

I/O shift register

Address register

and counter 256-byte

data buffer

256 bytes (page size)

X decoder

Y decoder

Status

00000h

3FFFFh

000FFh

Reset

10000h

First 256 pages can

be made read-only

M45PE20 Instructions

17/47

6 Instructions

All instruct ion s, addresses and dat a are shifted in and out of the device, most significant bit

first.

Serial data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select

(S) is drive n L ow. Then, t he on e- byte instruction code must be shifte d in to the device, most

significant bit first , on serial data input (D), each bit being latched on the rising edges of

Serial Clock (C).

The instruction set is listed in Table 3.

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or b y data bytes, or by both or none.

In the case of a read data bytes (READ), read data by tes at hig her speed (FAST_READ) or

read status register ( RDSR) instruction, the shifted-in instruction sequence is followed by a

data-out sequence. Chip Select (S) can be driven High after any bit of the data-out

sequence is being shifted out.

In the case of a page write (PW), page program (PP), page erase (PE), sector erase (SE),

write enable (WREN), write disable (WRDI), deep power-down (DP) or release from deep

power-down (RDP) instr uction, Chip Select (S) must be driven High exactly at a byte

boundary, otherwise the instruction is rejected, and is no t ex ecut ed. That is, Chip Select (S)

must driven High when the number of clock pulses after Chip Select (S) being driv en Low is

an exact multiple of eight.

All attempts to acce ss the memory array during a write cycle, program cycle or erase cycle

are ignored, and the internal write cycle, program cycle or erase cycle contin ues unaffected.

Table 3. Instruction set

Instruction Description One-byte

instruction code Address

bytes Dummy

bytes Data

bytes

WREN Write enable 0000 0110 06h 0 0 0

WRDI Write disable 0000 0100 04h 0 0 0

RDID Read identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read status register 0000 0101 05h 0 0 1 to ∞

READ Read data bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read data bytes at higher

speed 0000 1011 0Bh 3 1 1 to ∞

PW Page write 0000 1010 0Ah 3 0 1 to 256

PP Page program 0000 0010 02h 3 0 1 to 256

PE Page erase 1101 1011 DBh 3 0 0

SE Sector erase 1101 1000 D8h 3 0 0

DP Deep power-down 1011 1001 B9h 0 0 0

RDP Release from deep power-

down 1010 1011 ABh 0 0 0

Instructions M45PE20

18/47

6.1 Write enable (WREN)

The write enable (WREN) instru ction (Figure 6) sets the write enab le latch (WEL) bit.

The write enable latch (WEL) bit must be set prior to every page write (PW), page program

(PP), page era se (PE), and sector er ase (SE) instruction.

The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending th e

instruction code, an d then driving Chip Select (S) High.

Figure 6. Write enable (WREN) instruction sequence

6.2 Write disable (WRDI)

The write disable (WRDI) instruction (Figure 7) resets the write enable latch (WEL) bit.

The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, an d then driving Chip Select (S) High.

The write enable latch (WEL) bit is reset under the following conditions:

●Power-up

●Write disable (WRDI) instruction completion

●Page write (PW) instruction completion

●Page progr am (PP) instruction completion

●Page erase (PE) instruction completion

●Sector erase (SE) instruction completion

Figure 7. Write disable (WRDI) instruction sequence

AI02281E

21 34567

High Impedance

Instruction

AI03750D

21 34567

High Impedance

Instruction

M45PE20 Instructions

19/47

6.3 Read identification (RDID)

The read identification (RDID) instruction allows to read the device identification data:

●Manufacturer identification (1 byte)

●De vice identification (2 bytes)

●A unique ID code (UID) (17 bytes, of which 16 available upon customer request)(a).

The manu facturer identificat ion is assigned by JEDEC, and has t he value 20h f or Numonyx.

The device identification is assigned by the device manufacturer, and indicates the memory

type in the first byte (40h), and the memory capacity of the device in the second byte (12h).

The UID contains the length of the following data in the first byte (set to 10h), and 16 bytes

of the optiona l customized factory data (CFD) content. The CFD bytes are read-only and

can be programmed with customers data upon their demand. If the customers do not make

requests, the devices are shipped with all the CFD bytes programmed to zero (00h).

Any read identification (RDID) instruction while an erase or program cycle is in progress, is

not decoded, and has no effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in. After this, the 24-bit device identification, stored in the

memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on

serial data output (Q). Each bit is shifted out during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 8.

The read identification (RDID) instruction is terminated b y driving Chip Select (S) High at

any time during data output.

When Chip Select (S) is driven High, the device is put in the standby power mode. Once in

the standb y po w er mode , the device waits to be selected, so that it can receive, decode and

execute instructions.

a. The 17 bytes of unique ID code are available only in the T9HX process (see Important note on

page 6).

Table 4. Read identification (RDID) data-out sequence

Manufacturer identification Device Identification UID(1)

Memory type Memory capacity CFD length CFD content

20h 40h 12h 10h 16 bytes

1. The unique ID code is available only in the T9HX process (see Important note on page 6).

Instructions M45PE20

20/47

Figure 8. Read identification (RDID) instruction sequence and data-out sequence

1. The unique ID code is available only in the T9HX process (see Important note on page 6).

213456789101112131415

Instruction

AI06809c

Manufacturer identification

High Impedance

MSB

Device identification

MSB

15 14 13 3 2 1 0

16 17 18 28 29 30 31

MSB

UID

M45PE20 Instructions

21/47

6.4 Read status register (RDSR)

The read status register (RDSR) instruction allows the status register to be read. The status

When one of these cycles is in progress, it is recommended to check the write in progress

(WIP) bit before sending a ne w instruction to the device. It is al so possible to read the stat us

The status bits of the status register are as follows:

6.4.1 WIP bit

The write in progress (WIP) bit indicates whether the memory is busy with a write, program

or erase cycle . When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is

in progress.

6.4.2 WEL bit

The write enable la tch (WEL) bit indicates t he status of the internal write enable latc h. When

set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is

reset and no write, program or erase instruction is accepted.

Figure 9. Read status re gister (RDSR) instruc tion sequence and da ta-out seque nce

Table 5. Status register format

b7 b0

0 0 0 0 0 0 WEL(1)

1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is

automatically set and reset by the internal logic of the device).

WIP(1)

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status register out

High Impedance

MSB

76543210

Status register out

MSB

Instructions M45PE20

22/47

6.5 Read data bytes (READ)

The de vice is first selected by driving Chip Select (S) Low. Th e in st ructi on co de for the read

data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that

address, is shifted out on se rial data output (Q), each bit being shifted out, at a maximum

frequency fR, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 10.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single read data bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during data output. Any read data bytes (READ)

instruction, while an erase, program or write cycle is in progress, is rejected without having

any effects on the cycle that is in progress.

Figure 10. Read data bytes (READ) instruction sequence and data-out sequence

1. Address bits A23 to A18 are don’t care.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data out 1

Instruction 24-bit address

MSB

Data out 2

M45PE20 Instructions

23/47

6.6 Read data bytes at higher speed (FAST_READ)

The de vice is first selected by driving Chip Select (S) Low. Th e in st ructi on co de for the read

data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).

Then the memory contents , at that ad dress , is shift ed out on serial data ou tput (Q), ea ch bit

being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 11.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.

When the highest add ress is reached, the address counter rolls over to 000000h, allowing

the read sequence to be continued indefinitely.

The read data b ytes at higher speed (FAST_READ) instruction is terminated by driving Chip

Select (S) High. Chip Select (S) can be driven High at an y time du ring data output. An y read

data bytes at higher speed (FAST_READ) instruction, while an erase, prog ram or write cycle

is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 11. Read data bytes at higher speed (FAST_READ) instruction sequence

and data-out sequence

1. Address bits A23 to A18 are don’t care.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24-bit address

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

Instructions M45PE20

24/47

6.7 Page write (PW)

The page write (PW) instruction allows by tes to be written in the memory. Before it can be

accepted, a write enable (WREN) instruction must previously hav e bee n e xecuted. After the

write enable (WREN) instruction has been decoded, the device sets the write enabl e latch

(WEL).

The page write (PW) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code , three addres s bytes a nd at least one data b yte on serial data input (D). The

rest of the page remains unchanged if no power failure occurs during this write cycle.

The page write (PW) instruction performs a page erase cycle even if only one byte is

updated.

If the 8 least significant addre s s bits (A7 -A0) are no t all zero, all transmitted data exceeding

the addressed page boundary wrap round, and are written from the start address of the

same page (the one whose 8 least significant a ddress bits (A7-A0) are all z ero). Chip Select

(S) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 12.

If more tha n 256 bytes are sent to the device, p reviously latched data ar e disca rded an d th e

last 256 data b yt es are guar antee d to be written correctly with in the sa me page . If less than

256 Data bytes are sent to device, they are correctly written at the requested addresses

without having any e ffects on the other bytes of the same page.

For optimized timings, it is recommended to use the page write (PW) instruction to write all

consecutive targeted bytes in a single sequence versus using several page write (PW)

sequences with each containing only a few b ytes (see Table 14: A C char acteristics (50 MHz

operation) and Table 15: AC characteristics (75 MHz operation, T9HX (0.11 µm) process)).

Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise the page write (PW) instruction is not executed.

As soon as Chip Select (S) is driv en High, the self- timed page write cycle (whose duration is

tPW) is initiated. Whil e the p age write cycle is in prog ress , the st atus regi ster may be read to

chec k the v a lue of the write in prog ress (WIP ) bit. The write in prog ress (WIP) bit is 1 during

the self-timed page write cycle, and is 0 when it is completed. At some unspecified time

before the cycle is complete, the write enable latch (WEL) bit is reset.

A page write (PW) instruction applied to a page that is hard ware protected is not executed.

Any page write (PW) instruction, while an erase, program or write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

M45PE20 Instructions

25/47

Figure 12. Page write (PW) instruction sequence

1. Address bits A23 to A18 are don’t care.

2. 1 ≤ n ≤ 256.

AI04045

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-bit address

765432 0

Data byte 1

765432 0

Data byte 2

765432 0

Data byte 3 Data byte n

765432 0

MSB MSB

MSB MSB MSB

Instructions M45PE20

26/47

6.8 Page program (PP)

The page prog ram (PP) instruction allo ws bytes to be pr ogrammed in the m emory (changing

bits from ‘1’ to ‘0’, only). Before it can be accepted , a write enable (WREN) instruction must

previously have been executed. After the write enable (WREN) instruction has been

decoded, the device sets the write enable latc h (WEL).

The page prog ram (PP) instruction is entered b y driving Chip Select (S) Low, f ollowed b y the

instruction code, three address bytes and at least one data byte on serial data input (D). If

the 8 least significant address bits ( A7-A0) are not all ze ro, all transmitted data exceeding

the addressed page boundary wrap round, and are programmed from the start address of

the same page (the one whose 8 least significant addres s bits (A7-A0) are all zero). Chip

Select (S) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 13.

If more tha n 256 bytes are sent to the device, p reviously latched data ar e disca rded an d th e

last 256 dat a bytes ar e guaranteed to be progr ammed corr ectly within the same pag e. If less

than 256 data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same page.

F or optimized timings, it is recommended to use the page program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several page

program (PP) sequences with each containing only a few bytes (see Table 14: AC

characteristics (50 MHz operation) and Table 15: AC characteristics (75 MHz operation,

T9HX (0.11 µm) process)).

Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise the page program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose

duration is tPP) is initiated. While the page program cycle is in progress, the status register

may be read to check the value of the write in progress (WIP) bit. The write in progress

(WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At

some unspecified time bef ore the cycle is co mplete, the write enab le latch (WEL) bit is reset.

A page program (PP) instruction applied to a page that is hardware protected is not

executed.

Any page pr ogram (PP) instruction, while an erase, program or write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

M45PE20 Instructions

27/47

Figure 13. Page program (PP) instruction sequence

1. Address bits A23 to A18 are don’t care.

2. 1 ≤ n ≤ 256.

AI04044

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-bit address

765432 0

Data byte 1

765432 0

Data byte 2

765432 0

Data byte 3 Data byte n

765432 0

MSB MSB

MSB MSB MSB

Instructions M45PE20

28/47

6.9 Page erase (PE)

The page erase (PE) instruction sets to ‘1’ (FFh) all bits inside the chosen page. Before it

can be accepted, a write enable (WREN) instruction must previously have been executed.

After the write enable (WREN) instruction has been decoded, the device sets the write

enable latch (WEL).

The page erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on serial data input (D). Any address inside the

page is a valid address for the page erase (PE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the page erase (PE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self -timed page er ase cycle (wh ose duratio n is tPE) is initiated.

While the page er ase cycle is in progress , the status register may be read to check th e value

of the write in progress (WIP) bi t. The write in progress (WIP) bit is 1 during the self-timed

page erase cycle, and is 0 when it is completed. At some unspecified time before the cycle

is complete, the write enable latch (WEL) bit is reset.

A page erase (PE) instruction applied to a page that is hardware protected is not ex ecuted.

Any page erase (PE) instruction, while an erase, program or write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

Figure 14. Page erase (PE) instruction sequence

1. Address bits A23 to A18 are don’t care.

24-bit address

AI04046

21 3456789 293031

Instruction

23 22 2 0

MSB

M45PE20 Instructions

29/47

6.10 Sector erase (SE)

The sector er a se (SE) instruction sets to ‘1’ (FF h) all bits inside th e chosen sector. Before it

can be accepted, a write enable (WREN) instruction must previously have been executed.

After the write enable (WREN) instruction has been decoded, the device sets the write

enable latch (WEL).

The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on serial data input (D). Any address inside the

sector (see Table 2) is a valid address for the sector erase (SE) instruction. Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed sector erase cycle (whose duration is tSE) is

initiated. While the sector erase cycle is in progress, the status register may be read to

chec k the v a lue of the write in prog ress (WIP ) bit. The write in prog ress (WIP) bit is 1 during

the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time

before the cycle is complete, the write enable latch (WEL) bit is reset.

A sector erase (SE) instruction applied to a sector th at contains a page that is hardware

protected is not executed.

Any sector erase (SE) instruction, while an erase, program or write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

Figure 15. Sector erase (SE) instruction sequence

1. Address bits A23 to A18 are don’t care.

24-bit address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

Instructions M45PE20

30/47

6.11 Deep power-down (DP)

Executing the deep power-down (DP) instruction is the only way to put the device in the

lowest consumption mode (the deep power-down mode). It can also be used as an extra

softwar e protecti on mechanism, wh ile the device is not in active use, since in this mode, the

device ignores all write, program and erase instructions.

Driving Chip Select (S) High deselects the device, and puts the device in the standby po wer

mode (if there is no internal cycle currently in progress). But this mode is not the deep

pow er-do wn mode . The deep po we r-do wn mode can only be ente red by e x ecutin g the deep

power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified

in Table 11: DC characteristics).

Once the device has entered the deep power-down mode, all instructions are ignored

except the release from deep power-down (RDP) instruction. This releases th e device from

this mode.

The deep power-down mode automatically sto ps at power -down, and the device always

powers-up in the standby power mode.

The deep power-down (DP) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code on serial data input (D). Chip Select (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as

Chip Select (S) is driven High, it requires a delay of tDP bef or e the su pply cu rrent is r educe d

to ICC2 and the deep power-down mode is entered.

Any deep power-down (DP) instruction, while an erase, program or write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 16. Deep power-down (DP) instruction sequence

AI03753D

21 345670tDP

Deep power-down mode

Standby mode

Instruction

M45PE20 Instructions

31/47

6.12 Release from deep power-down (RDP)

Once the device has entered the deep power-down mode, all instructions are ignored

except the release from deep power-down (RDP) instruction. Executing this instruction

takes the device out of the deep power-down mode .

The release from deep power-down (RDP) instruction is entered by driving Chip Select (S)

Low, f ollo wed by the instruction code on serial data input (D). Chip Select (S) must be driv en

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 17.

The release from de ep power-down (RDP) instruction is terminated by driving Chip Select

(S) High. Sending additional clock cycles on Serial Cloc k (C), while Chip Select (S) is driven

Low, cause the instruction to be rejected, and not executed.

After Chip Select (S) has been driv en High, followed b y a de la y, tRDP

, the de vice is put in the

standb y pow er mode . Chip Select (S) must remain High at least until this period is o v er. The

device waits to be selected, so that it can receive, decode and execute instructions.

Any release from deep power-down (RDP) instruction, while an erase, program or write

cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Release from deep power-down (RDP) instruction sequence

AI06807

21 345670tRDP

Standby mode

Deep power-down mode

QHigh Impedance

Instruction

Power-up and power-down M45PE20

32/47

7 Power-up and power-down

At power-up and power-down, the device must not be se lecte d (t hat is Chip Select ( S ) m ust

follow the voltage applied on VCC) until VCC reaches the correct value:

●VCC(min) at power-up, and then for a further delay of tVSL

●VSS at power-down

A safe configuration is provided in Section 3: SPI modes.

To a void data corruption and inadvertent write operations during power-up , a power on reset

(POR) circuit is includ ed. T he logic in side th e d evice is held reset while VCC is less than the

power on reset (POR) threshold value, VWI – all operations are disabled, and the device

does not respond to any instruction.

Moreo ver , the device ig nores all write enable (WREN), page write (PW), page prog ram (PP),

page erase (PE) and sector erase (SE) instructions until a time delay of tPUW has elapsed

after the moment that VCC rises abov e the VWI threshold. However, the correct operation of

the device is not guaranteed if, b y this time, VCC is still below VCC(min). No write, program or

erase instructions should be sent until the later of:

●tPUW after VCC passed the VWI threshold

●tVSL after VCC passed the VCC(min) level

These values are specified in Table 6.

If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be

selected for read instructions even if the tPUW delay is not yet fully elapsed.

As an extra protection, the Reset (R eset ) signal can be driv en Low for the whol e d uration of

the power-up and power-down phases.

At power-up, the device is in the following state:

●The device is in the standby power mode (not the deep power-down mode).

●The write enab le latch (WEL) bit is reset.

●The write in progress (WIP) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.

Each de vice in a system should ha v e the V CC rail decoupled b y a suitab le capacitor close to

the package pins (generally, this capacitor is of the order of 100 nF).

At power-down, when VCC drops from the operating voltage, to below the power on reset

(POR) threshold value, VWI, all operations are disabled and the device does not respond to

any instruction (the designer needs to be aware that if a power-down occurs while a write,

program or erase cycle is in progress , some data corruption can result).

M45PE20 Power -up and power-down

33/47

Figure 18. Power-up timing

Table 6. Power-up timing and VWI threshold

Symbol Parameter Min Max Unit

tVSL(1)

1. These parameters are characterized only, over the temperature range –40 °C to +85 °C.

VCC(min) to S low 30 µs

tPUW(1) Time delay before the first wr ite, program or erase instruction 1 10 ms

VWI(1) Write inhibit voltage 1.5 2.5 V

VCC

AI04009C

VCC(min)

VWI

Reset state

of the

device

Chip selection not allowed

Program, erase and write commands are rejected by the device

tVSL

tPUW

time

Read access allowed Device fully

accessible

VCC(max)

Initial delivery state M45PE20

34/47

8 Initial delivery state

The device is delivered with the memory array erased: all bits are set to ‘1’ ( each byte

contains FFh). All usable status register bits are ‘0’.

9 Maximum ratings

Stressing the device outside the ratings listed in Table 7: Absolute max imum ratings may

cause permanent damage to the device. The se ar e stre ss ratings only, and ope r at ion of the

device at these, or any other conditions outside those indicated in the operating sections of

this specification, is not implied. Exposure to absolute maximum rating con ditions for

extended periods may affect device reliability (r efer to quality documents f or further details).

Table 7. Absolute maximum ratings

Symbol Parameter Min Max Unit

TSTG Storage temperature –65 150 °C

TLEAD Lead temperature during solde ring See note (1)

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ECOPACK®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)

2002/95/EU.

°C

VIO Input and output voltage (with respect to ground) –0.6 VCC + 0.6 V

VCC Supply voltage –0.6 4.0 V

VESD Electrostatic discharge voltage (human body model)(2)

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

–2000 2000 V

M45PE20 DC and AC parameters

35/47

10 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristic tables that

follow are derived from tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurem ent conditions when relying on the quoted parameters.

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 19. AC measurement I/O waveform

1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 33 MHz.

Table 8. Operating conditions

Symbol Parameter Min Max Unit

VCC Supply voltage 2.7 3.6 V

TAAmbient operating temperature –40 85 °C

Table 9. AC measurement conditions

Symbol Parameter Min Max Unit

CLLoad capacitance 30 pF

Input rise and fall times 5 ns

Input pulse voltages 0.2VCC to 0.8VCC V

Input and output timing reference voltages 0.3VCC to 0.7VCC V

Table 10. Capacitance

Symbol Parameter Test condition Min Max Unit

COUT Output capacitance (Q) VOUT = 0 V 8 pF

CIN Input capacitance (other pins) VIN = 0 V 6 pF

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and output

timing reference levels

Input Levels

DC and AC parameters M45PE20

36/47

Table 11. DC characteristics

Symbol Parameter Test condition

(in addition to those in Table 8)Min Max Unit

ILI Input leakage current ± 2 µA

ILO Output leakage current ± 2 µA

ICC1

Standby current

(standby and reset

modes) S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep power-down

current S = VCC, VIN = VSS or VCC 10 µA

ICC3 Operating current

(FAST_READ)

C=0.1V

CC / 0.9.VCC at 33 MHz,

Q = open 4mA

C=0.1V

CC / 0.9.VCC at 75 MHz,

Q = open 12

ICC4 Operating current (PW) S = VCC 15 mA

ICC5 Operating current (SE) S = VCC 15 mA

VIL Input low voltage – 0.5 0.3VCC V

VIH Input high voltage 0.7VCC VCC+0.4 V

VOL Output low voltage IOL = 1.6 mA 0.4 V

VOH Output high v oltage IOH = –100 µA VCC–0.2 V

M45PE20 DC and AC parameters

37/47

Table 12. AC characte ristics (25 MHz operat ion)

Test conditions specified in Table 8 and Table 9

Symbol Alt. Parameter Min Typ Max Unit

fCfC

Clock frequency for th e following

instructions: FAST_READ, PW, PP, PE,

SE, DP, RDP, WREN, WRDI, RDSR D.C. 25 MHz

fRClock frequency for read instructions D.C. 20 MHz

tCH(1)

1. tCH + tCL must be greater than or equal to 1/ fC(max).

tCLH Clock High time 18 ns

tCL(1) tCLL Cloc k Low time 18 ns

Clock slew rate(2) (peak to peak)

2. Value guaranteed by characterization, not 100% tested in production.

0.03 V/ns

tSLCH tCSS S active setup time (relative to C) 10 ns

tCHSL S not active hold time (relative to C) 10 ns

tDVCH tDSU Data in setup time 5 ns

tCHDX tDH Data in hold time 5 ns

tCHSH S active hold time (relati ve to C) 10 ns

tSHCH S not active setup time (relative to C) 10 ns

tSHSL tCSH S deselect time 200 ns

tSHQZ(2) tDIS Output disable time 15 ns

tCLQV tVClock Low to Output Valid 15 ns

tCLQX tHO Output hold time 0 n s

tRLRH(2) tRST Reset pulse width 10 µs

tRHSL tREC Reset recovery time 3 µs

tSHRH Chip should have been deselected

before reset is de-asserted 10 ns

tWHSL Write protect setup time 50 ns

tSHWL Write protect hold time 100 ns

tDP(2) S to deep power-down 3 µs

tRDP(2) S High to standby power mode 30 µs

tPW(3)

3. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one

sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).

Page write cycle time (256 bytes) 11 25 ms

Page write cycle time (n by tes) 10.2+

n*0.8/256

tPP(3) Page program cycle time (256 bytes) 1.2 5ms

Page program cycle time (n bytes) 0.4+

n*0.8/256

tPE Page erase cycle time 10 20 ms

tSE Sector erase cycle time 1 5 s

DC and AC parameters M45PE20

38/47

Table 13. AC characte ristics (33 MHz operat ion)

33 MHz only av ailable for pr oducts marked since week 40 of 2005(1)

Test conditions specified in Table 8 and Table 9

1. Details of how to find the date of marking are given in application note, AN1995.

Symbol Alt. Parameter Min Typ Max Unit

fCfC

Clock frequency for th e following

instructions: FAST_READ, PW, PP, PE,

SE, DP, RDP, WREN, WRDI, RDSR D.C. 33 MHz

fRClock frequency for read instructions D.C. 20 MHz

tCH(2)

2. tCH + tCL must be greater than or equal to 1/ fC.

tCLH Clock High time 13 ns

tCL(2) tCLL Clock Low time 13 ns

Clock slew rate(3) (peak to peak)

3. Value guaranteed by characterization, not 100% tested in production.

0.03 V/ns

tSLCH tCSS S active setup time (relative to C) 10 ns

tCHSL S not active hold time (relative to C) 10 ns

tDVCH tDSU Data in setup time 3 ns

tCHDX tDH Data in hold time 5 ns

tCHSH S active hold time (relative to C) 5 ns

tSHCH S not active setup time (relative to C) 5 ns

tSHSL tCSH S deselect time 200 ns

tSHQZ(3) tDIS Output disable time 12 ns

tCLQV tVClock Low to Output Valid 12 ns

tCLQX tHO Output hold time 0 ns

tTHSL Top sector lock setup time 50 ns

tSHTL Top sector lock hold time 100 ns

tDP(3) S to deep power-down 3 µs

tRDP(3) S High to standby power mode 30 µs

tPW(4)

4. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one

sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).

Page write cycle time (256 bytes) 11 25 ms

Page write cycle time (n by tes) 10.2+

n*0.8/256

tPP(4) Page program cycle time (256 bytes) 1.2 5ms

Page program cycle time (n bytes) 0.4+

n*0.8/256

tPE Page erase cycle time 10 20 ms

tSE Sector erase cycle time 1 5 s

M45PE20 DC and AC parameters

39/47

Table 14. AC characteris tics (50 MHz operation)(1)

50 MHz preliminary data for T9HX technology(2)

Test conditions specified in Table 8 and Table 9

Symbol Alt. Parameter Min Typ Max Unit

fCfC

Clock frequency for the following instructions:

FAST_READ, PW, PP, PE, SE, DP, RDP,

WREN, WRDI, RDSR, RDID D.C. 50 MHz

fRClock frequency for READ instructions D.C. 33 MHz

tCH(3) tCLH Clock High time 9 ns

tCL(3) tCLL Clock Lo w time 9 ns

Clock slew rate(4) (peak to peak) 0.1 V/ns

tSLCH tCSS S active setup time (relative to C) 5 ns

tCHSL S not active hold time (relative to C) 5 ns

tDVCH tDSU Data in setup time 2 ns

tCHDX tDH Data in hold time 5 ns

tCHSH S active hold time (relative to C) 5 ns

tSHCH S not active setup time (relative to C) 5 ns

tSHSL tCSH S deselect time 100 ns

tSHQZ(4) tDIS Output disable time 8 ns

tCLQV tVClock Low to Output Valid 8 ns

tCLQX tHO Output hold time 0 ns

tWHSL Write protect setup time 50 ns

tSHWL Write protect hold time 100 ns

tDP(4) S to deep power-down 3 µs

tRDP(4) S High to standby mode 30 µs

tRLRH(4) tRST Reset pulse width 10 µs

tRHSL tREC Reset recovery time 3 µs

tSHRH Chip should have been deselected before

reset is de-asserted 10 ns

tPW(5) Page write cycle time (256 bytes) 11 23 ms

tPP(5) Page program cycle time (256 bytes) 0.8 3ms

Page program cycle time (n bytes) int(n/8) × 0.025

tPE Page erase cycle time 10 20 ms

tSE Sector erase cycle time 1 5 s

1. Preliminary data.

2. Delivery of parts in T9HX process to start from August 2007.

3. tCH + tCL must be greater than or equal to 1/ fC.

4. Value guaranteed by characterization, not 100% tested in production.

5. n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2,

int(17/8) = 3.

DC and AC parameters M45PE20

40/47

Table 15. AC characteris tics (75 MHz operation, T9HX (0.11 µm) process(1))(2)

Test conditions specified in Table 8 and Table 9

Symbol Alt. Parameter Min Typ Max Unit

fCfC

Clock frequency fo r the following instructions:

FAST_READ, PW, PP, PE, SE, DP, RDP,

WREN, WRDI, RDSR, RDID D.C. 75 MHz

fRClock frequency for read instructions D.C. 33 MHz

tCH(3) tCLH Clock High time 6 ns

tCL(3) tCLL Clock Low time 6 n s

Clock slew rate(4) (peak to peak) 0.1 V/ns

tSLCH tCSS S active setup time (relative to C) 5 ns

tCHSL S not activ e hold time (relative to C) 5 ns

tDVCH tDSU Data in setup time 2 n s

tCHDX tDH Data in hold time 5 ns

tCHSH S active hold time (relative to C) 5 ns

tSHCH S not active setup time (relative to C) 5 ns

tSHSL tCSH S deselect time 100 ns

tSHQZ(4) tDIS Output disable time 8 n s

tCLQV tVClock Low to Output valid 8 ns

tCLQX tHO Output hold time 0 ns

tWHSL(5) Write protect setup time 20 ns

tSHWL(5) Write protect hold time 100 ns

tDP(4) S to deep power-down 3 µs

tRDP(4) S High to standby mode 30 µs

tWWrite status register cycle time 3 15 ms

tPW(6) Page write cycle time (256 bytes) 11 23 ms

tPP(6) Page program cycle time (256 bytes) 0.8 3ms

Page program cycl e ti me (n bytes) int(n/ 8) × 0. 0 25 (7)

tPE Page erase cycle time 10 20 ms

tSE Sector erase cycle time 1.5 5 s

1. See Important note on page 6.

2. Details of how to find the technology process in the marking are given in AN1995, see also Section 12: Ordering

information.

3. tCH + tCL must be greater than or equal to 1/ fC.

4. Value guaranteed by characterization, not 100% tested in production.

5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.

6. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence

including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).

7. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.

M45PE20 DC and AC parameters

41/47

Figure 20. Serial input timing

Figure 21. Write protect setup and hold timing

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

DC and AC parameters M45PE20

42/47

Figure 22. Output timing

Figure 23. Reset AC waveforms

AI01449e

LSB OUT

DADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

AI06808

Reset tRLRH

tRHSLtSHRH

M45PE20 Package mechanical

43/47

11 Package mechanical

To meet environmental requirements, Numonyx offers these devices in ECOPACK®

packages. ECOPACK® packages are lead-free. The category of second level interconnect

is marked on the package and on the inner box label, in compliance with JEDEC Standard

JESD97. The maximum r atings related t o soldering conditions are also marked on the inner

box label.

Figure 24. SO8N – 8 lead plastic small outline, 150 mils body width, package outline

1. Drawing is not to scale.

Table 16. SO8N – 8 lead plastic small outline, 150 mils body width, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A1.750.069

A1 0.10 0.25 0.004 0.010

A2 1.25 0.049

b 0.28 0.48 0.011 0.019

c 0.17 0.23 0.007 0.009

ccc 0.10 0.004

D 4.90 4.80 5.00 0.193 0.189 0.197

E 6.00 5.80 6.20 0.236 0.228 0.244

E1 3.90 3.80 4.00 0.154 0.150 0.157

e1.27– –0.050– –

h 0.25 0.50 0.010 0.020

k0°8°0°8°

L 0.40 1.27 0.016 0.050

L1 1.04 0.041

SO-A

ccc

h x 45˚

0.25 mm

GAUGE PLANE

Package mechanical M45PE20

44/47

Figure 25. MLP8, 8-lead very thin dual flat package no lead, 6 × 5 mm, package

outline

1. Drawing is not to scale.

Table 17. MLP8, 8-l ead very thin dual fl at package no lead, 6 × 5 mm, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 0.85 0.80 1.00 0.033 0.031 0.039

A1 0.00 0.05 0.000 0.002

A2 0.65 0.026

A3 0.20 0.008

b 0.40 0.35 0.48 0.016 0.014 0.019

D6.00 0.236

D1 5.75 0.226

D2 3.40 3.20 3.60 0.134 0.126 0.142

E5.00 0.197

E1 4.75 0.187

E2 4.00 3.80 4.30 0.157 0.150 0.169

e1.27– –0.050– –

R1 0.10 0.00 0.004 0.000

L 0.60 0.50 0.75 0.024 0.020 0.029

Θ12° 12°

aaa 0.15 0.006

bbb 0.10 0.004

ddd 0.05 0.002

70-ME

AA3

eE2

ddd

bbb

CAB

aaa CAA

aaa CB

0.10 CA

0.10 CB

M45PE20 Ordering information

45/47

12 Ordering information

Note: For a list of a vailable optio ns (speed, pac ka ge, e tc.), for further inf ormation on any aspect of

this device or when ordering parts operating at 75 MHz (0.11 µm technology, process digit

‘4’), please contact yo ur nearest Numonyx sales office .

Table 18. Ordering informat ion scheme

Example: M45PE20 – V MP 6 T G

Device type

M45PE = serial flash memory for data storage

Device function

20 = 2-Mbit (256 Kbits ×8)

Operatin g voltage

V = VCC = 2.7 V to 3.6 V

Package

MN = SO8 (150 mil width)

MP = VDFPN8 6 x 5 mm (MLP8)

Device grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

Option

blank = standard packing

T = tape and reel packing

Plating technology

P or G = ECOPACK® (RoHS compliant)

Revision history M45PE20

46/47

13 Revision history

Table 19. Document revision history

Date Version Changes

30-Apr-2003 1.0 Initial release.

04-Jun-2003 1.1 Description corrected of entering hardware protected mode (W must be

driven, and cannot be left unconnected).

04-Dec-2003 1.2 VIO(min) extended to –0.6 V, tPW(typ) and tPP(typ) improved. Table of

contents, warning about e xposed paddle on MLP8, and Pb-free options

added. Change of naming for VDFPN8 package

21-Apr-2004 1.3 Soldering temperature information clarified for RoHS compliant devices.

Device grade clarified.

22-Sep-2004 2 Document promoted to preliminary data. Minor wording changes. Devi ce

grade further clarified.

08-Oct-2004 3 Document promoted to full datasheet. No other changes.

4-Oct-2005 4

Added Table 13: AC characteristics (33 MHz operation). An easy way to

modify data, A fast way to modify data, Page write (PW) and Page

program (PP) sections updated to explain optimal use of page write and

page program instructi ons. Updated ICC3 values in Table 11: DC

characteristics. Updated Table 18. ECOPACK® inf ormation added.

02-Feb-2007 5

Document reformatted. Small text changes.

50 MHz frequency added (Table 14 added). VCC supply voltage and VSS

ground descriptions added.

Figure 3: Bus master an d memory devices on the SPI bus modified and

explanatory text added.

VIO max modified in Table 7: Absolute maximum ratings.

At power-up, The write in progress (WIP) bit is reset.

tSHQZ end timing line modified in Figure 22: Output timing.

Blank option removed belo w Plating technology in Table 18: Ordering

information scheme. Small text changes.

Package specifications updated (see Section 11: Package mechanical).

22-May-2008 6

Applied Numonyx branding.

Removed ‘low voltage’ from the title.

Updated the value for the maximum clock frequency (from 50 to 75 MHz)

throughout the document.

Added: Table 15: AC characteristics (75 MHz operation, T9HX (0.11 µm)

process) and ECOPACK® text in Section 11: Package mechanical.

Modified: Table 11: DC characteristics, Figure 3: Bus master and memory

de vices on the SPI bus, Section 3: SPI modes, and Section 6.3: Read

identification (RDID).

M45PE20

47/47

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Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

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Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

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these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and befo re placing your p roduct order.

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*Other names and brands may be clai med as the propert y of others.