Vishay Siliconix
Si9168
Document Number: 70899
S11-0975-Rev. B, 16-May-11
www.vishay.com
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Product is End of Life 3/2014
Synchronous Buck or Boost Controller for 2-Cell Li+ Battery
Operated Portable Communication Devices
FEATURES
• Voltage Mode Control
• 5 V to 10 V Input Voltage Range for VDD
• 5 V to 12.6 V Input Voltage Range for VS - Boost
• Programmable PWM/PSM Control
- Up to 2 MHz Switching Frequency in PWM
- Synchronous Rectification in PWM
- Less than 350 µA IDD in PSM
• Very High Efficiencies In Buck or Boost Modes
• Low Dropout Operation at 100 % Duty Cycle In Buck
Mode
• Integrated UVLO and POR
• Integrated Soft-Start
• Synchronization
• Logic Controlled Micropower Shutdown Current < 2 µA
• Fast Line and Load Transient Response
• Available in 16-Lead TSSOP Package
APPLICATIONS
• Cellular Telephones
• Wireless Modems
• Portable Instruments
• Notebook and Palmtop Computers
• PDA’s
• Battery Operated Devices
DESCRIPTION
The Si9168 is a synchronous buck or boost controller for
2-cell Li+ battery operated portable communication devices.
Designed for use with external high-frequency MOSFETs,
the Si9168 is ideal for providing power to various power
amplifiers such as TDMA, CDMA, GSM, or PCS. For ultra-
high efficiency, converters are designed to operate in
synchronous rectified PWM mode under full load, while
transforming into externally controlled pulse skipping mode
(PSM) under light load conditions. All these features are
provided by Si9168 without sacrificing system integration
requirements of fitting these circuits into ever demanding
smaller space. The Si9168 is capable of switching up to
2 MHz to minimize the size of the output inductor and
capacitor, in order to decrease the overall converter
footprint. The programmability to design a buck or boost
converter with this IC makes it convenient to power either the
high voltage (7.2 V) or low voltage (4 V) PAs.
The Si9168 is available in TSSOP-16 pin package and
specified to operate over the industrial temperature range of
- 25 °C to 85 °C.
FUNCTIONAL BLOCK DIAGRAM
Buck Mode
1.3 V ~ 10 V
SMPS
1.3 V
Voltage Reference
Shutdown
Control
SD
VOUT
(1.3 ~ 10 V)
VREF
(1.3 V)
VIN
(5 - 10 V)
Boost Mode
5 V ~ 12.6 V
SMPS
1.3 V
Voltage Reference
Shutdown
Control
SD
VOUT
(5 ~ 12.6 V)
VREF
(1.3 V)
VIN
(5 - 10 V)
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Document Number: 70899
S11-0975-Rev. B, 16-May-11
Vishay Siliconix
Si9168
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Product is End of Life 3/2014
Notes:
a. Device Mounted with all leads soldered or welded to PC board.
b. Derate 7.4 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
Voltages Referenced to AGND
VDD 13.2
V
VSS - VDD 2
PWM/PSM, SYNC, SD, VREF
, ROSC, COMP, FB, Mode - 0.3 to VDD + 0.3
VO- 0.3 to VS + 0.3
PGND ± 0.3
Voltages Referenced to PGND
VS13.2 V
DH, DL- 0.3 to VS + 0.3
Peak Output Current (DH, DL)1A
Storage Temperature - 65 to 150 °C
Operating Junction Temperature 150
Power Dissipation (Package)a16-Pin TSSOP (Q Suffix)b925 mW
Thermal Impedance (ΘJA) 16-Pin TSSOP 135 °C/W
RECOMMENDED OPERATING RANGE
Parameter Limit Unit
Voltages Referenced to AGND
VDD 5 to 10 V
FOSC 200 kHz to 2 MHz
ROSC 25 to 300 kΩ
PWM/PSM, SYNC, SD, Mode 0 to VDD V
VREF 0.1 µF
Voltages Referenced to PGND
VS
Buck 5.0 to 10 V
Boost 5.0 to 12.6
SPECIFICATIONS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
5 V ≤ VDD, VS ≤ 10 V
Limits
- 25 °C to 85 °C
Unit Min.aTyp.bMax.a
Reference
Output Voltage VREF
IREF = 0 A 1.268 1.3 1.332 V
VDD = 7.2, 25 °C 1.280 1.3 1.320
VREF Current IREF - 500 µA
Power Supply Rejection PSRR 60 dB
UVLO
Under Voltage Lockout (Turn-On) VUVLO/LH 4.3 4.5 4.7 V
Hysteresis VHYS 0.2
Soft-Start Time
SS Time tSS 3ms
Document Number: 70899
S11-0975-Rev. B, 16-May-11
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Vishay Siliconix
Si9168
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Product is End of Life 3/2014
Notes:
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
c. Guaranteed by design and characterization, not subject to production testing.
SPECIFICATIONS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
5 V ≤ VDD, VS ≤ 10 V
Limits
- 25 °C to 85 °C
Unit Min.aTyp.bMax.a
SD, SYNC, PWM/PSM
Logic High VIH 2.4 V
Logic Low VIL 0.8
Input Current IL- 1.0 1.0 µA
Mode
Logic High VIH 70 % VDD V
Logic Low VIL 70 % VDD
Input Current IL- 1.0 1.0 µA
Oscillator
Maximum Frequency FMAX 2MHz
Accuracy 1 External Resistor - 20 20
%
Maximum Duty Cycle
(Buck, Non LDO Mode) DMAX
FSW = 2 MHz 75 80
Maximum Duty Cycle (Boost) ROSC = 130 kΩ, VDD = 5 V, VS = 12.6 V 65 71
SYNC Range FSYNC/FOSC 1.2 1.5
SYNC Low Pulse Width 50
ns
SYNC High Pulse Width 50
SYNC tr, tftr, tf50
Error Amplifier
Input Bias Current IBIAS VFB = 1.4 V - 1 1 µA
Open Loop Voltage Gain AVOL 50 60 dB
Offset Voltage VOS - 10 10 mV
Unity Gain BW BW 2 MHz
Output Current (Source) IEA
VFB = 1.05 V - 2 - 1 mA
Output Current (Sink) VFB = 1.55 V 13
Power Supply Rejection PSRR 60 dB
PSM Modulator
Switch On Time tON VDD = 7.2 V, VOUT = 3.3 V, Buck Mode 180 ns
Switch Off Blanking Time tOFF 330
Output Drive (DH and DL)
Output High Voltage VOH VS = 7.2, IOUT = - 20 mA 7.08 7.14 V
Output Low Voltage VOL VS = 7.2, IOUT = 20 mA 0.06 0.12
Peak Output Source ISOURCE VS = 7.2 V, DH = DL = VS/2 - 1000 - 500 mA
Peak Output Sink ISINK 500 1000
Break-Before-Make tBBM VS = VDD = 10 V 40 ns
Supply
Normal Mode
IDD
VDD = 7.2 V, fOSC = 2 MHz 1100
µAPSM Mode VDD = 7.2 V 350
Shutdown Mode VDD = 7.2 V, SD = 0 V 2.0
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Document Number: 70899
S11-0975-Rev. B, 16-May-11
Vishay Siliconix
Si9168
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Product is End of Life 3/2014
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
VREF vs. VDD
Frequency vs. Temperature
Max Duty Cycle vs. Frequency (Buck Mode)
1.29
1.292
1.294
1.296
1.298
1.300
1.302
1.304
1.306
1.308
1.310
4 6 8 10 12 14
VDD - (V)
)V(V FER
1.7
1.8
1.9
2.0
2.1
2.2
- 50 0 50 100
Temperature (°C)
)zHM( ycneuqe
r
F
VDD = 7.2 V
ROSC = 25 kΩ
70
74
78
82
86
90
94
98
400 600 800 1000 1200 1400 1600 1800 2000 2200
e
lcy
C
ytu
D
x
a
M
%
Frequency (kHz)
VIN = 7.2 V
VREF vs. Temperature
Frequency vs. ROSC
Max Duty Cycle vs. Frequency (Boost Mode)
1.28
1.284
1.288
1.292
1.296
1.300
1.304
1.308
1.312
1.316
1.320
- 50 - 25 0 25 50 75 100
Temperature (°C)
)V(V FER
VDD = 7.2 V
100
1000
10000
10 100 1000
ROSC (kΩ)
)zHk( yc
ne
u
qerF
42
46
50
54
58
62
66
70
74
400 600 800 1000 1200 1400 1600 1800 2000 2200
e
lcy
C
y
t
u
D
x
a
M
%
Frequency (kHz)
VIN = 7.2 V
Document Number: 70899
S11-0975-Rev. B, 16-May-11
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Vishay Siliconix
Si9168
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Product is End of Life 3/2014
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
PWM Supply Current vs. VDD (Buck Mode)
PSM Supply Current vs. VDD (Buck Mode)
Efficiency - Buck, VOUT = 3.6 V
200
400
600
800
1000
1200
1400
4 6 8 10 12 14
VDD - (V)
(µA)I
DD
FOSC = 1.6 MHz
50
100
150
200
250
300
468101214
VDD - (V)
(µA)I
DD
50
60
70
80
90
100
10 100 1000 10000
Load Current (mA)
)%( ycneiciffE
PSM = 5 VIN
PWM = 5 VIN
PWM = 7.2 VIN
PSM = 7.2 VIN
PSM = 8.4 VIN
PWM = 8.4 VIN
PWM Supply Current vs. VDD (Boost Mode)
PSM Supply Current vs. VDD (Boost Mode)
Efficiency - Boost, VOUT = 7.2 V
200
400
600
800
1000
1200
1400
4 6 8 10 12 14
VDD - (V)
(µA)I
DD
FOSC = 1.6 MHz
50
100
150
200
250
300
4 6 8 10 12 14
VDD - (V)
(µA)I
DD
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Document Number: 70899
S11-0975-Rev. B, 16-May-11
Vishay Siliconix
Si9168
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Product is End of Life 3/2014
PIN CONFIGURATION
16
15
14
13
1
2
3
4
12
11
10
9
5
6
7
8
MODE VS
DLN/C
PGND DH
SD PWM/PSM
VOSYNC
VDD GND
ROSC VREF
COMP FB
TSSOP-16
Top View
Si9168BQ
ORDERING INFORMATION
Part Number Temperature Range Package
Si9168BQ-T1 - 25 °C to 85 °C Tape and Reel
Eval Kit Temperature Range Board Type
Si9168DB - 25 °C to 85 °C Surface Mount
PIN DESCRIPTION
Pin Number Name Function
1MODE
Determines the converter topology. Connect to AGND for buck or VDD for boost.
2DL The gate drive output for the low-side N-Channel MOSFET for buck and boost converter
3 PGND Power ground for output drive stage
4SD
Logic low shuts down the IC completely and decreases the current consumption of IC to < 2 µA.
5VO Direct output voltage sense
6VDD
Input supply voltage for the analog circuit. VDD voltage should be the ac filtered voltage of VSS. Input voltage range
is 5 V to 10 V.
7ROSC External resistor to determine the switching frequency.
8 COMP Error amplifier output for external compensation network.
9 FB Output voltage feedback connected to the inverting input of an error amplifier.
10 VREF 1.3 V reference voltage. Connected internally to non-inverting error amplifier input. Decouple with 0.1 µF ceramic
capacitor.
11 GND Low power controller ground
12 SYNC Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not
used, the pin must be connected to VDD, or logic high.
13 PWM/PSM Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification drive is disabled.
14 DH The gate drive output for the high-side P-Channel MOSFET for buck and boost converter
15 N/C Not used.
16 VS Supply voltage for the output driver section. Voltage range is 5 V to 10 V (Buck), 5 V to 12.6 V (Boost).
Document Number: 70899
S11-0975-Rev. B, 16-May-11
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Vishay Siliconix
Si9168
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Product is End of Life 3/2014
BLOCK DIAGRAM
DETAIL OPERATIONAL DESCRIPTION
Start-Up
The UVLO circuit prevents the controller output driver and
oscillator circuit from turning on, if the voltage on VDD pin is
less than 4.5 V. With typical UVLO hysteresis of 0.2 V, the
controller is continuously powered on until the VDD voltage
drops below 4.3 V. This hysteresis prevents the converter
from oscillating during the start-up phase and unintentionally
locking up the system. Once the VDD voltage exceeds the
UVLO threshold, and with no other shutdown condition
detected, an internal power-on-reset timer is activated while
most circuitry, except the output driver, are turned on. After
the POR time-out of about 1 ms, the internal soft-start capac-
itor is allowed to charge. When the soft-start capacitor volt-
age reaches 0.5 V, the PWM circuit is enabled. Thereafter,
the constant current charging of the soft-start capacitor will
force the converter output voltage to rise gradually without
overshooting. To prevent negative undershoot, the synchro-
nous switch is tri-stated until the duty cycle reaches about
10 %. See start-up timing diagram. In tri-state, the high-side
P-Channel MOSFET is turned off by pulling up the gate volt-
age (DH) to VS potential. The low-side N-Channel MOSFET
is turned off by pulling down the gate voltage (DL) to PGND
potential. Note that Si9168 will always soft starts in the PWM
mode regardless of the voltage level on the PWM/PSM pin.
Shutdown
Si9168 is designed to conserve as much battery life as pos-
sible by decreasing current consumption of IC during normal
operation as well as the shutdown mode. With logic low level
on the SD pin, current consumption of the Si9168 decreases
to less than 2 µA by shutting off most of the circuits. The logic
high enables the controller and starts up as described in
"Start-Up" section above.
Figure 1.
Reference
Threshold
Generator
Soft-Start
Timer
Oscillator
COSC
UVLO POR Bias
Generator
System Monitor
Drivers
PWMIN
PSMIN
PWM/PFM
Select
PWMIN
PSMIN
PWM
Modulator
PSM
Modulator
0.5 V
1.0 V
Ramp
VREF
VO
FB
COMP
SYNC
ROSC
MODE
PWM/PSM
GND
VDD SD
DL
Negative Return
and
Substrate
Positive Supply
1.3 V
PGND
DH
VS
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Document Number: 70899
S11-0975-Rev. B, 16-May-11
Vishay Siliconix
Si9168
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Product is End of Life 3/2014
DETAIL OPERATIONAL DESCRIPTION
PWM Mode
With PWM/PSM mode pin in logic high condition, Si9168
operates in constant frequency (PWM) mode. As the load
and input voltage vary, switching frequency remain constant.
The switching frequency is programmed by the ROSC value
as shown by the oscillator curve. In the PWM mode, the
synchronous drive is always enabled, even when the output
current reaches 0 A. In continuous current mode, the transfer
function of the converter remain constant providing fast
transient response. If the converter operates in
discontinuous current mode, overall loop gain decreases and
transient response time can be 10 times longer than if the
converter remain in continuous current mode. This transient
response time advantage can significantly decrease the
hold-up capacitors needed on the output of dc-dc converter
to meet the transient voltage regulation. Therefore, the
PWM/PSM pin is available to dynamically program the
controller. If the synchronous rectifier switch is not used, the
converter may not operate in PWM mode if the load current
is low enough to force the converter into pulse skipping
mode.
The maximum duty cycle of the Si9168 can reach 100 % in
buck mode. The duty cycle will continue to increase as the
input voltage decreases until it reaches 100 %. This allows
the system designers to extract out the maximum stored
energy from the battery. Once the controller delivers 100 %
duty cycle, the converter operates like a saturated linear
regulator. At 100 % duty cycle, synchronous rectification is
completely turned off. At up to 80 % duty cycle at 2 MHz
switching frequency, the controller maintains perfect output
voltage regulation. If the input voltage drops below the level
where the converter requires greater than 80 % duty cycle,
the controller will deliver 100 % duty cycle. This
instantaneous jump in duty cycle is due to fixed BBM time
and the internal propagation delays. In order to maintain
regulation, the controller might fluctuate its duty cycle back
and forth from 100 % to something lower than 80 % during
this input voltage range. If the input voltage drops further, the
controller will remain on for 100 % duty cycle. If the input
voltage increases to a point where it’s requiring less than 80
% duty cycle, synchronous rectification is once again
activated.
The maximum duty cycle under boost mode is internally
limited to 75 % to prevent inductor saturation. If the converter
is turned on for 100 % duty cycle, the inductor never gets a
chance to discharge its energy and eventually saturate. In
boost mode, the synchronous rectifier is always turned on for
minimum or greater duration as long as the switch has been
turned on. The controller will deliver 0 % duty cycle, if the
input voltage is greater than the programmed output voltage.
Because of fixed BBM time, the controller will not transition
smoothly from minimum controllable duty cycle to 0 % duty
cycle. For example, controller may decrease its duty cycle
from 5 % to 0 % abruptly, instead of the gradual decrease
seen from 75 % to 5 %.
Pulse Skipping Mode
The gate charge losses produced from the Miller
capacitance of MOSFETs are the dominant power
dissipation parameter during light load (i.e. < 200 mA).
Therefore, less gate switching will improve overall converter
efficiency. This is exactly why the Si9168 is designed with
pulse skipping mode. If the PWM/PSM pin is connected to
logic low level, converter operates in pulse skipping
modulation (PSM) mode. During the pulse skipping mode,
quiescent current of the controller is decreased to
approximately 350 µA, instead of 900 µA during the PWM
mode. This is accomplished by turning off most of the internal
control circuitry and utilizing a simple constant on-time
control with the feedback comparator. The controller is
designed to have a constant on-time and a minimum off-time
acting as the feedback comparator blanking time. If the
output voltage drops below the desired level, the main switch
is first turned on and then off. If the applied on-time is
insufficient to provide the desired voltage, the controller will
force another on and off sequence, until the desired voltage
is accomplished. If the applied on-time forces the output to
exceed the desired level, as typically found in the light load
condition, the converter stays off. The excess energy is
delivered to the output slowly, forcing the converter to skip
pulses as needed to maintain regulation. The on-time and
off-time are set internally based on the inductor used
(2 µH typical) and the maximum load current. Therefore, with
this control method, duty cycles ranging from 0 to 100 % are
possible depending on whether the boost or buck mode is
chosen.
Reference
The reference voltage for the Si9168 is set at 1.3 V. The
reference voltage is internally connected to the non-inverting
inputs of the error amplifier. The REF pin requires a 0.1 µF
decoupling capacitor.
Error Amplifier
The error amplifier gain-bandwidth product and slew rate are
critical parameters which determines the transient response
of converter. The transient response is function of both small
and large signal responses. The small signal response is
determined by the feedback compensation network while the
large signal is determined by the error amplifier dv/dt and the
inductor di/dt slew rate. Besides the inductance value, the
error amplifier determines the converter response time. In
order to minimize the response time, Si9168 is designed with
a 2 MHz error amplifier gain-bandwidth product to generate
the widest converter bandwidth and a 3.5 V/µs slew rate for
ultra-fast large signal response.
Document Number: 70899
S11-0975-Rev. B, 16-May-11
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Si9168
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Product is End of Life 3/2014
DETAIL OPERATIONAL DESCRIPTION
Oscillator
The oscillator is designed to operate up to 2 MHz minimum.
The 2 MHz operating frequency allows the converter to
minimize the inductor and capacitor size, improving the
power density of the converter. Even with a 2 MHz switching
frequency, quiescent current is only 1100 µA (max) with the
unique power saving circuit design. The switching frequency
is easily programmed by attaching a resistor to the ROSC pin.
See oscillator frequency versus Rosc curve to select the
proper timing values for the desired operating frequency.
The tolerance on the operating frequency is ± 20 % with a
1 % tolerance resistor.
Synchronization
The synchronization to external clock is easily accomplished
by connecting the external clock into the SYNC pin. The logic
high to low transition synchronizes the clock. The external
clock frequency must be within 1.2 to 1.5 times the internal
clock frequency.
Break-Before-Make Timing
A proper BBM time is essential in order to prevent shoot-
through current and to maintain high efficiency. The break-
before-make time is set internally at 20 to 60 ns at VS = 7.2 V.
The high- and low-side gate drive voltages are monitored
and when the gate-to-source voltage reaches 3.5 V above or
below the initial starting voltage, 20 to 60 ns BBM time is set
before the other gate drive transitions to its proper state. The
maximum and minimum duty cycle is limited by the BBM
time. Since the BBM time is fixed, controllable maximum duty
cycle will vary depending on the switching frequency.
Output Driver Stage
The DH pin is designed to drive the main switch MOSFET
and DL pin is designed to drive the synchronous rectifier
MOSFET. The driver stage is sized to sink and source peak
currents up to 1000 mA with VS = 7.2 V. The ringing from the
gate drive output trace inductance can produce negative
voltage on the DH and DL respect to PGND. The gate drive
circuit is capable of withstanding these negative voltages
without any functional defects.
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Document Number: 70899
S11-0975-Rev. B, 16-May-11
Vishay Siliconix
Si9168
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Product is End of Life 3/2014
APPLICATIONS
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70899.
Figure 2. 1.5 A Buck Regulator Using the Si9168BQ
R1*
51 Ω
C3
0.1 µ F
C2
10 µ F
10 V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Si9168BQ
U1
2, 3
V
IN
5-10 V
V
OUT
3.6 V
1.5 A
C4
330 pF
C8
0.1 µ F
C6
1 nF
C7
56 pF
C5
0.1 µ F
6, 7
8
1
4
C1
22 µ F
16 V
R5
75 kΩ
R8*
5.6 Ω
R9*
5.6 Ω
5
R6
8.2 k
Q1B
Si6803DQ
Q1A
Si6803DQ
R2
200 Ω
R3
22 kΩ
R4
12.4 kΩ
L1, 4.7 µ H
IHLP2525
1 D
1 T 0 2 5 0 R B M
C9
0.1 µ F
MODE
D
L
PGND
SD
V
OUT
V
DD
R
OSC
COMP
V
S
NC
D
H
PWM/PSM
GND
V
REF
FB
SYNC
COM
COM
PWM/PSM to V
IN
for PWM mode;
PWM/PSM
to GND for PSM mode.
SD
to V
IN
for converter enable mode;
SD
to GND for shutdown mode.
* = Optional
Ω
Figure 3. Si9168BQ Boost Regulator Application
C1
10 µF
16 V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U1
VIN
5-7.2 V
C2
47 µF
16 V
C3
0.1 µF
Q1
SI9803DY
C4
560 pF
C8
0.1 µF
C6
5.6 nF
C7
220 pF
C5
0.1 µF
4
R1*
51 Ω
R5
75 kΩ
1, 2, 3
R6
4.7 kΩ
R3
56.2 kΩ
R2
1 kΩ
R4
12.4 kΩ
5, 6, 7, 8
3
4
1, 2, 5, 6
Q2
Si3442DV
D1
B130LB
L1, 4.7 µH
IHLP2525
Si9168
VOUT
7.2 V
2.5 A
MODE
DL
PGND
SD
VOUT
VDD
ROSC
COMP
VS
NC
DH
PWM/PSM
GND
VREF
FB
SYNC
COM
COM
PWM/PSM to VIN for PWM mode;
PWM/PSM to GND for PSM mode.
SD to VIN for converter enable mode;
SD to GND for shutdown mode.
* = Optional
Vishay Siliconix
Package Information
Document Number: 74417
23-Oct-06
www.vishay.com
1
Symbols
DIMENSIONS IN MILLIMETERS
Min Nom Max
A - 1.10 1.20
A1 0.05 0.10 0.15
A2 - 1.00 1.05
B 0.22 0.28 0.38
C - 0.127 -
D 4.90 5.00 5.10
E 6.10 6.40 6.70
E1 4.30 4.40 4.50
e-0.65-
L 0.50 0.60 0.70
L1 0.90 1.00 1.10
y--0.10
θ10°3°6°
ECN: S-61920-Rev. D, 23-Oct-06
DWG: 5624
TSSOP: 16-LEAD
PAD Pattern
www.vishay.com Vishay Siliconix
Revision: 02-Sep-11 1Document Number: 63550
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
RECOMMENDED MINIMUM PAD FOR TSSOP-16
0.281
(7.15)
Recommended Minimum Pads
Dimensions in inches (mm)
0.171
(4.35)
0.055
(1.40)
0.012
(0.30)
0.026
(0.65)
0.014
(0.35)
0.193
(4.90)
Legal Disclaimer Notice
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Revision: 08-Feb-17 1Document Number: 91000
Disclaimer
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