Supertex inc.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV5530
Functional Block Diagram
32-Channel Serial to Parallel Converter
With Open Drain Outputs
POL
BL
LE
DATA
INPUT
CLK
DATA
OUTPUT
HV
OUT
1
(Outputs 3 to 30 not shown)
Latch
Latch
HV
OUT
2
HV
OUT
31
HV
OUT
32
Latch
Latch
32-Bit
Shift
Register
General Description
The HV5530 is a low-voltage serial to high-voltage parallel
converter with open drain outputs. This device has been designed
for use as a driver for AC-electroluminescent displays. It can also
be used in any application requiring multiple output high voltage
current sinking capabilities such as driving inkjet and electrostatic
print heads, plasma panels, vacuum uorescent, or large matrix
LCD displays.
This device consists of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. Data is shifted through the shift register on the high to low
transition of the clock. The HV5530 shifts in the counter clockwise
direction when viewed from the top of the package. A data output
buffer is provided for cascading devices. This output reects the
current status of the last bit of the shift register. Operation of the
shift register is not affected by the LE (latch enable), BL (blanking),
or the POL (polarity) inputs. Transfer of data from the shift register
to the latch occurs when the LE (latch enable) input is high. The
data in the latch is stored when LE is low.
Features
►Processed with HVCMOS® technology
►Sink current minimum 100mA
►Shift register speed 8.0MHz
►Polarity and Blanking inputs
►CMOS compatible inputs
►Forward and reverse shifting options
►Diode to VPP allows efcient power recovery
2
HV5530
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Pin Congurations
1
44
1 44
6 40
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
HV5530PG
LLLLLLLLL
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
A = Assembler ID
C = Country of Origin*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW AAA
HV5530PJ
LLLLLLLLLL
CCCCCCCCCCC
44-Lead PQFP (PG)
(top view)
44-Lead PLCC (PJ)
(top view)
Product Marking
44-Lead PQFP (PG)
44-Lead PLCC (PJ)
Ordering Information
Device
Package Options
44-Lead Quad
Plastic Gullwing
10.00x10.00mm body
2.45mm height (max)
0.80mm pitch
44-Lead Quad
Plastic Chip Carrier
.653x.653in body
.180in height (max)
.050in pitch
HV5530 HV5530PG-G HV5530PJ-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter Value
Supply voltage, VDD
1-0.5V to +15V
Output voltage, VPP
1-0.5V to +315V
Logic input levels1-0.5V to VDD +0.5V
Ground current21.5A
Continuous total power dissipation31200mW
Operating temperature range -40OC to +85OC
Storage temperature range -65OC to +150OC
Sym Parameter Min Max Units
Recommended Operating Conditions
VDD Logic voltage supply 10.8 13.2 V
HVOUT High voltage output -0.3 +300 V
VIH Input high voltage VDD -2.0 VDD V
VIL Input low voltage 0 2.0 V
fCLK Clock frequency - 8.0 MHz
TAOperating free-air temperature -40 +85 OC
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
Notes:
1. All voltages are referenced to VSS
2. Duty cycle is limited by the total power dissipated in the package
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C.
Power-Up Sequence
Power-up sequence should be the following:
1. Connect ground
2. Apply VDD
3. Set all inputs to a known state
Power-down sequence should be the reverse of the above.
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
3
HV5530
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Input and Output Equivalent Circuits
VDD
DATA
INPUT
HVOUT
Lo
g
ic Inputs
DATA
OUTPUT
Logic Data Output High Voltage Outputs
VDD
HVIN
VSS VSS
VSS
Sym Parameter Min Max Units Conditions
Electrical Characteristics (over recommended operating conditions unless otherwise noted)
DC Characteristics
AC Characteristics (VDD = 12V, TC = 25OC)
Sym Parameter Min Max Units Conditions
fCLK Clock frequency - 8.0 MHz ---
tWClock width, high or low 62 - ns ---
tSU Data set-up time before CLK falls 25 - ns ---
tHData hold time after CLK falls 10 - ns ---
tON Turn-on time, HVOUT from enable - 500 ns RL = 2.0KΩ to VPP max.
tDHL Delay time clock to data high to low - 100 ns CL = 15pF
tDLH Delay time clock to data low to high - 100 ns CL = 15pF
tDLE Delay time clock to LE low to high 50 - ns ---
tWLE Width of LE pulse 50 - ns ---
tSLE LE setup time before clock falls 50 - ns ---
IDD VDD supply current - 15 mA fCLK = 8.0MHz, FDATA = 4.0MHz
IDDQ VDD supply current (quiescent) - 100 µA VIN = 0V
IO(OFF) Off state output current - 10 µA All outputs high, all SWS parallel
IIH High-level logic input current - 1.0 µA VIH = VDD
IIL Low-level logic input current - -1.0 µA VIL = 0V
VOH High-level output data out VDD -1.0V - V IDOUT = -100µA
VOL Low-level output voltage HVOUT - 15 V IHVOUT = +100mA
DATA OUT - 1.0 V IDOUT = +100µA
VOC HVOUT clamp voltage - -1.5 V IOL = -100mA
4
HV5530
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Switching Waveforms
LE
HV
OUT
w/ S/R HIGH
Data Valid 50% 50%
DATA
INPUT
CLK
DATA
OUTPUT
50% 50% 50%
t
SU
t
H
t
WH
t
WL
50%
50%
t
DLH
t
DHL
50%
t
WLE
t
DLE
t
SLE
50% 50%
10%
t
ON
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
OH
V
OL
Functional Table
Function
Inputs Outputs
Data CLK LE BL POL Shift Reg HV Outputs Data Out
*
1 2...32 1 2...32
All on X X X L L * *...* On On...On *
All off X X X L H * *...* Off Off...Off *
Invert mode X X L H L * *...* * *...* *
Load S/R H or L ↓L H H H or L *...* * *...* *
Load latches X H or L ↑H H * *...* * *...* *
X H or L ↑H L * *...* * *...* *
Transparent latch
mode
L↓H H H L *...* Off *...* *
H↓H H H H *...* On *...* *
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion.
* dependent on previous stage’s state before the last CLK ↓ or last LE high.
5
HV5530
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
44-Lead PQFP Pin Assignment (PG)
Pin # Function Description
1 HVOUT11
High voltage outputs.
2 HVOUT12
3 HVOUT13
4 HVOUT14
5 HVOUT15
6 HVOUT16
7 HVOUT17
8 HVOUT18
9 HVOUT19
10 HVOUT20
11 HVOUT21
12 HVOUT22
13 HVOUT23
14 HVOUT24
15 HVOUT25
16 HVOUT26
17 HVOUT27
18 HVOUT28
19 HVOUT29
20 HVOUT30
21 HVOUT31
22 HVOUT32
23 DATA OUTPUT Data output pin.
24 N/C
No connect.25 N/C
26 N/C
27 POL Inverts the polarity of the HVOUT pins
28 CLK Clock pin, shift registers shifts data on falling edge of input clock.
29 VSS Reference voltage, usually ground.
30 VDD Logic supply voltage.
31 LE Latch enable pin, data is shifted from shift register to latches on logic input high.
32 DATA INPUT Data input pin.
33 BL Blanking pin sets all HVOUT pins low or high depending upon state of polarity.
See function table.
34 N/C No connect.
35 HVOUT1
High voltage outputs.
36 HVOUT2
37 HVOUT3
38 HVOUT4
39 HVOUT5
40 HVOUT6
41 HVOUT7
42 HVOUT8
43 HVOUT9
44 HVOUT10
6
HV5530
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
44-Lead PLCC Pin Assignment (PJ)
Pin # Function Description
1 HVOUT16
High voltage outputs.
2 HVOUT17
3 HVOUT18
4 HVOUT19
5 HVOUT20
6 HVOUT21
7 HVOUT22
8 HVOUT23
9 HVOUT24
10 HVOUT25
11 HVOUT26
12 HVOUT27
13 HVOUT28
14 HVOUT29
15 HVOUT30
16 HVOUT31
17 HVOUT32
18 DATA OUTPUT Data output pin.
19 N/C
No connect.20 N/C
21 N/C
22 POL Inverts the polarity of the HVOUT pins
23 CLK Clock pin, shift registers shifts data on falling edge of input clock.
24 VSS Reference voltage, usually ground.
25 VDD Logic supply voltage.
26 LE Latch enable pin, data is shifted from shift register to latches on logic input high.
27 DATA INPUT Data input pin.
28 BL Blanking pin sets all HVOUT pins low or high depending upon state of polarity.
See function table.
29 N/C No connect.
30 HVOUT1
High voltage outputs.
31 HVOUT2
32 HVOUT3
33 HVOUT4
34 HVOUT5
35 HVOUT6
36 HVOUT7
37 HVOUT8
38 HVOUT9
39 HVOUT10
40 HVOUT11
41 HVOUT12
42 HVOUT13
43 HVOUT14
44 HVOUT15
7
HV5530
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
44-Lead PQFP Package Outline (PG)
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch
Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ
Dimension
(mm)
MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80*
0.80
BSC
0.73
1.95
REF
0.25
BSC
0O
NOM - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5O
MAX 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7O
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.
* This dimension is not specied in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PQFPPG, Version C041309.
1
44
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
Seating
Plane
Top View
D
D1
E
E1
be
Side View
A2
A
A1
Note 1
(Index Area
D1/4 x E1/4)
Note:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8
HV5530
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline information go to http://www.
supertex.com/packaging.html.)
Doc.# DSFP-HV5530
B080411
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
Symbol A A1 A2 b b1 D D1 E E1 e R
Dimension
(inches)
MIN .165 .090 .062 .013 .026 .685 .650 .685 .650
.050
BSC
.025
NOM .172 .105 - - - .690 .653 .690 .653 .035
MAX .180 .120 .083 .021 .036†.695 .656 .695 .656 .045
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PLCCPJ, Version F031111.
.150 MAX
.048/.042 x 45O
1
.075 MAX
6 40
D
D1
E1 E
Top View
Horizontal Side View
View B
A A2
A1
Seating
Plane
e
b
Note 1
(Index Area)
.056/.042 x 45O
.020max
(3 Places)
.020 MIN
Vertical Side View
View B
Note 2
44
b1
Base
Plane
R
Notes:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
2. Actual shape of this feature may vary.