TPA2012D2 YZH RTJ www.ti.com .................................................................................................................................................. SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 2.1 W/CH STEREO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER FEATURES APPLICATIONS * Output Power By Package: - QFN: - 2.1 W/Ch Into 4 at 5 V - 1.4 W/Ch Into 8 at 5 V - 720 mW/Ch Into 8 at 3.6 V - WCSP: - 1.2 W/Ch Into 4 at 5 V(1) - 1.3 W/Ch Into 8 at 5 V - 720 mW/Ch Into 8 at 3.6 V * Only Two External Components Required * Power Supply Range: 2.5 V to 5.5 V * Independent Shutdown Control for Each Channel * Selectable Gain of 6, 12, 18, and 24 dB * Internal Pulldown Resistor On Shutdown Pins * High PSRR: 77 dB at 217 Hz * Fast Startup Time (3.5 ms) * Low Supply Current * Low Shutdown Current * Short-Circuit and Thermal Protection * Space Saving Packages - 2,01 mm X 2,01 mm NanoFreeTM WCSP (YZH) - 4 mm X 4 mm Thin QFN (RTJ) with PowerPADTM * * * * * * * 1 2 (1) Wireless or Cellular Handsets and PDAs Portable DVD Player Notebook PC Portable Radio Portable Gaming Educational Toys USB Speakers DESCRIPTION The TPA2012D2 is a stereo, filter-free, Class-D audio amplifier (class-D amp) available in a WCSP, QFN, or PWP package. The TPA2012D2 only requires two external components for operation. The TPA2012D2 features independent shutdown controls for each channel. The gain can be selected to 6, 12, 18, or 24 dB utilizing the G0 and G1 gain select pins. High PSRR and differential architecture provide increased immunity to noise and RF rectification. In addition to these features, a fast startup time and small package size make the TPA2012D2 class-D amp an ideal choice for both cellular handsets and PDAs. Thermally limited 2.50 PO - Output Power - W WCSP Thermally Limited Region VDD = 2.5 V, 1% 2 VDD = 2.5 V, 10% VDD = 3.6 V, 1% 1.50 VDD = 3.6 V, 10% VDD = 5 V, 1% VDD = 3.6 V, 10% 1 0.50 0 4 9 14 19 24 29 34 RL - Load Resistance - W 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2008, Texas Instruments Incorporated TPA2012D2 SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 .................................................................................................................................................. www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The TPA2012D2 is capable of driving 1.4 W/Ch at 5 V or 720 mW/Ch at 3.6 V into 8 . The TPA2012D2 is also capable of driving 4 . The TPA2012D2 is thermally limited in WCSP and may not achieve 2.1 W/Ch for 4 . The maximum output power in the WCSP is determined by the ability of the circuit board to remove heat. The output power versus load resistance graph below shows thermally limited region of the WCSP in relation to the QFN package. The TPA2012D2 provides thermal and short circuit protection. AVAILABLE OPTIONS TA -40C to 85C PACKAGE PART NUMBER SYMBOL 2 mm x 2 mm, 16-ball WCSP (YZH) TPA2012D2YZH AKR 4 mm x 4 mm, 20-pin QFN (RTJ) TPA2012D2RTJ AKS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted) (1) VSS Supply voltage, AVDD, PVDD VI Input voltage VALUE UNIT In active mode -0.3 to 6.0 V In shutdown mode -0.3 to 7.0 V -0.3 to VDD + 0.3 V Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range -40 to 85 C TJ Operating junction temperature range -40 to 150 C Tstg Storage temperature range -65 to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE (1) PACKAGE TA = 25C POWER RATING (1) DERATING FACTOR TA = 75C POWER RATING TA = 85C POWER RATING RTJ 5.2 W 41.6 mW/C 3.12 W 2.7 W YZH 1.2 W 9.12 mW/C 690 mW 600 mW This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard 4-layer 3 in x 3 in PCB. RECOMMENDED OPERATING CONDITIONS MIN MAX 5.5 VSS Supply voltage AVDD, PVDD 2.5 VIH High-level input voltage SDL, SDR, G0, G1 1.3 VIL Low-level input voltage SDL, SDR, G0, G1 TA Operating free-air temperature 2 /40 Submit Documentation Feedback UNIT V V 0.35 V 85 C Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 TPA2012D2 www.ti.com .................................................................................................................................................. SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 ELECTRICAL CHARACTERISTICS TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS |VOO| Output offset voltage (measured differentially) Inputs ac grounded, AV = 6 dB, VDD = 2.5 to 5.5 V PSRR Power supply rejection ratio VDD = 2.5 to 5.5 V Vicm Common-mode input voltage MIN TYP MAX 5 25 mV -75 0.5 UNIT -55 dB VDD-0.8 V -50 dB CMRR Common-mode rejection ration Inputs shorted together, VDD = 2.5 to 5.5 V |IIH| High-level input current VDD = 5.5 V, VI = VDD 50 A |IIL| Low-level input current VDD = 5.5 V, VI = 0 V 5 A IDD Supply current -69 VDD = 5.5 V, No load or output filter 6 9 VDD = 3.6 V, No load or output filter 5 7.5 VDD = 2.5 V, No load or output filter 4 6 Shutdown mode rDS(on) f(sw) Static drain-source on-state resistance 1.5 VDD = 5.5 V 500 VDD = 3.6 V 570 VDD = 2.5 V 700 Output impedance in shutdown mode V(SDR, SDL)= 0.35 V Switching frequency VDD = 2.5 V to 5.5 V G0, G1 = 0.35 V Closed-loop voltage gain 300 A m 2 250 mA k 350 5.5 6 6.5 G0 = VDD, G1 = 0.35 V 11.5 12 12.5 G0 = 0.35 V, G1 = VDD 17.5 18 18.5 G0, G1 = VDD 23.5 24 24.5 kHz dB OPERATING CHARACTERISTICS TA = 25C, RL = 8 (unless otherwise noted) PARAMETER PO Output power (per channel) TEST CONDITIONS RL = 8 RL = 4 THD+N Total harmonic distortion plus noise Channel crosstalk kSVR Supply ripple rejection ratio CMRR Common mode rejection ratio Input impedance Vn MIN TYP VDD = 5.0 V, f = 1 kHz, THD = 10% 1.4 VDD = 3.6 V, f = 1 kHz, THD = 10% 0.72 VDD = 5.0 V, f = 1 kHz, THD = 10% 2.1 PO = 1 W, VDD = 5 V, AV = 6 dB, f = 1 kHz 0.14% PO = 0.5 W, VDD = 5 V, AV = 6 dB, f = 1 kHz 0.11% f = 1 kHz -85 VDD = 5 V, AV = 6 dB, f = 217 Hz -77 VDD = 3.6 V, AV = 6 dB, f = 217 Hz -73 VDD = 3.6 V, VIC = 1 Vpp, f = 217 Hz -69 Av = 6 dB 28.1 Av = 12 dB 17.3 Av = 18 dB 9.8 Av = 24 dB 5.2 Start-up time from shutdown VDD = 3.6 V Output voltage noise VDD = 3.6 V, f = 20 to 20 kHz, Inputs are ac grounded, AV = 6 dB MAX 3.5 No weighting 35 A weighting 27 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 UNIT W dB dB dB k ms V 3 TPA2012D2 SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 .................................................................................................................................................. www.ti.com BLOCK DIAGRAM V DD to Battery CS INR+ OUTR+ Gain Adjust Right Input PWM H- Bridge OUTR- INR- Internal Oscillator GND OUTL+ INL+ Gain Adjust Left Input PWM H- Bridge OUTL- INL- G0 G1 SDR 300 k Bias Circuitry Short-Circuit Protection SDL 300 k 4 Submit Documentation Feedback Gain V/V dB G1 G0 0 0 2 6 0 1 4 12 1 0 8 18 1 1 16 24 Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 TPA2012D2 www.ti.com .................................................................................................................................................. SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 Terminal Functions TERMINAL NAME I/O DESCRIPTION QFN WCSP INR+ 16 D1 I Right channel positive input INR- 17 C1 I Right channel negative input INL+ 20 A1 I Left channel positive input INL- 19 B1 I Left channel negative input SDR 8 B3 I Right channel shutdown terminal (active low) SDL 7 B4 I Left channel shutdown terminal (active low) G0 15 C2 I Gain select (LSB) G1 1 B2 I Gain select (MSB) 3, 13 A2 I Power supply (Must be same voltage as AVDD) AVDD 9 D2 I Analog supply (Must be same voltage as PVDD) PGND 4, 12 C4 I Power ground AGND 18 C3 I Analog ground OUTR+ 14 D3 O Right channel positive differential output OUTR- 11 D4 O Right channel negative differential output OUTL+ 2 A3 O Left channel positive differential output OUTL- 5 A4 O Left channel negative differential output 6, 10 N/A PVDD NC No internal connection Thermal Pad Connect the thermal pad of QFN or PWP package to PCB GND B1 INL- G1 SDR SDL C1 INR- G0 AGND PGND D1 INR+ AVDD OUTR+ OUTR- 16 INR+ OUTL- 17 G0 1 G1 2 OUTL+ OUTR+ 14 3 PVDD PVDD 13 4 PGND PGND 12 5 OUTL- OUTR- 11 NC OUTL+ 18 INR- PVDD 19 AVDD INL+ 20 AGND A4 SDR A3 SDL A2 NC A1 INL- RTJ PIN OUT TOP VIEW INL+ WCSP PIN OUT TOP VIEW 6 7 8 9 10 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 15 5 TPA2012D2 SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 .................................................................................................................................................. www.ti.com TEST SET-UP FOR GRAPHS (per channel) CI TPA2012D2 RI IN+ + Measurement Output CI - OUT+ + Load RI INVDD + OUT- 30 kHz Low Pass Filter Measurement Input - GND 1 mF VDD - 6 (1) CI was Shorted for any Common-Mode input voltage measurement. (2) A 33-H inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements. (3) The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low pass filter (100 , 47 nF) is used on each output for the data sheet graphs. Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 TPA2012D2 www.ti.com .................................................................................................................................................. SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs OUTPUT POWER 1 3.6 V 0.1 5V 0.1 PO - Output Power - W 1 2.5 V 1 3.6 V 0.1 5V 0.1 PO - Output Power - W RL = 4 , f = 1 kHz, AV 24 dB 2.5 V 1 3.6 V 0.1 5V 0.01 0.01 3 0.1 1 4 PO - Output Power - W Figure 3. TOTAL HARMONIC DISTORTION vs OUTPUT POWER TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 1 1 3.6 V 0.1 5V 0.1 1 VDD = 2.5 V, RL = 4 W, CI = 1 mF, AV = 6 dB 350 mW 0.1 240 mW 0.01 20 4 120 mW 100 1k f - Frequency - Hz PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % 1 RL = 4 , f = 1 kHz, AV 6 dB 0.01 0.01 VDD = 2.5 V, RL = 8 W, CI = 1 mF, AV = 6 dB 260 mW 0.1 180 mW 0.01 20 10 k 20 k 90 mW 100 1k f - Frequency - Hz 10 k 20 k Figure 4. Figure 5. Figure 6. TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 1 THD+N - Total Harmonic Distortion + Noise - % VDD = 3.6 V, RL = 4 W, CI = 1 mF, AV = 6 dB 275 mW 825 mW 0.1 550 mW 100 1k f - Frequency - Hz 10 k 20 k Figure 7. VDD = 3.6 V, RL = 8 W, CI = 1 mF, AV = 6 dB THD+N - Total Harmonic Distortion + Noise - % 1 1 THD+N - Total Harmonic Distortion + Noise - % 10 Figure 2. 2.5 V 0.01 20 1 20 Figure 1. THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % RL = 8 , f = 1 kHz, AV 6 dB 0.01 0.01 3 20 10 10 THD+N - Total Harmonic Distortion + Noise - % 2.5 V 0.01 0.01 TOTAL HARMONIC DISTORTION vs OUTPUT POWER 20 RL = 8 , f = 1 kHz, AV 24 dB THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 20 10 TOTAL HARMONIC DISTORTION vs OUTPUT POWER 190 mW 560 mW 0.1 375 mW 0.01 20 100 1k f - Frequency - Hz 10 k 20 k Figure 8. VDD = 5 V, RL = 4 W, CI = 1 mF, AV = 6 dB 550 mW 0.1 1.65 W 1.1 W 0.01 20 100 1k f - Frequency - Hz Figure 9. Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 10 k 20 k 7 TPA2012D2 SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs FREQUENCY SUPPLY CURRENT vs SHUTDOWN VOLTAGE 6 1 VDD = 5 V, RL = 8 W, CI = 1 mF, AV = 6 dB VDD = 5 V 380 mW 5 I DD - Supply Current - mA THD+N - Total Harmonic Distortion + Noise - % SUPPLY CURRENT vs SUPPLY VOLTAGE 1.16 W 0.1 775 mW VDD = 3.6 V 4 VDD = 2.5 V 3 2 1 0.01 20 100 1k f - Frequency - Hz 10 k 0 20 k No Output Filter 0 1 2 3 4 VSD - Shutdown Voltage - V 5 Figure 10. Figure 11. Figure 12. SUPPLY CURRENT vs OUTPUT POWER SUPPLY CURRENT vs OUTPUT POWER CROSSTALK vs FREQUENCY 800 0 1200 IDD is for Both Channels IDD is for Both Channels 700 500 400 300 VDD = 5 V, RL = 8 W, 33 mH 0.2 0.4 0.6 0.8 1 1.4 0 1k f - Frequency - Hz POWER SUPPLY REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY -40 -60 2.5 V R to L 3.6 V L to R 5 V L to R 3.6 V R to L PSRR - Power Supply Rejection Ratio - dB Crosstalk - dB 100 CROSSTALK vs FREQUENCY -100 -40 -30 Inputs AC, Grounded, CI = 1 mF, RI = 4 W, AV = 6 dB -50 VDD = 2.7 V -60 -70 -80 VDD = 3.6 V -90 VDD = 5 V 5 V R to L 1k f - Frequency - Hz 10 k 20 k Figure 16. 8 -140 20 2.2 Figure 15. -20 100 2 Figure 14. -30 20 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 PO - Output Power/Channel - W 5 V L to R Figure 13. RI = 4 W -120 3.6 V L to R 3.6 V R to L 0 1.6 0 2.5 V L to R 5 V R to L -120 VDD = 2.5 V, RL = 4 W, 33 mH PO - Output Power/Channel - W -80 2.5 V L to R -100 200 1.2 2.5 V R to L -80 VDD = 3.6 V, RL = 4 W, 33 mH VDD = 2.5 V, RL = 8 W, 33 mH 0 -60 VDD = 5 V, RL = 4 W, 33 mH 400 VDD = 3.6 V, RL = 8 W, 33 mH 100 0 600 PSRR - Power Supply Rejection Ratio - dB 200 -40 800 Crosstalk - dB I DD - Supply Current - mA I DD - Supply Current - mA 600 RI = 8 W -20 1000 -100 20 100 1k f - Frequency - Hz 10 k Figure 17. Submit Documentation Feedback 20 k -40 10 k 20 k Inputs AC Grounded, CI = 1 mF, RI = 8 W, AV = 6 dB -50 VDD = 2.7 V -60 -70 -80 VDD = 3.6 V -90 VDD = 5 V -100 20 100 1k 10 k 20 k f - Frequency - Hz Figure 18. Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 TPA2012D2 www.ti.com .................................................................................................................................................. SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) COMMOM-MODE REJECTION RATIO vs COMMON-MODE INPUT VOLTAGE COMMON-MODE REJECTION RATIO vs FREQUENCY -50 -20 VDD = 5.5 V -40 -60 -80 -55 -60 -65 C1 - High, 3.6 V C1 - Amp, 512 mV C1 - Duty, 12% VDD 200 mV/div VDD = 3.6 V 0 VIC = 1 VPP, RL = 8 W, AV = 6 dB VDD = 2.5 V VDD = 3.6 V VOUT 20 mV/div VDD = 2.5 V CMRR - Common-Mode Rejection Ratio - dB -70 VDD = 5 V -75 -100 1k f - Frequency - Hz 10 k 20 k t - Time - 2 ms/div Figure 19. Figure 20. Figure 21. POWER SUPPLY REJECTION vs FREQUENCY SUPLY VOLTAGE REJECTION RATIO vs DC COMMON-MODE VOLTAGE POWER DISSIPATION vs OUTPUT POWER CI = 1 mF, Inputs AC Grounded, AV = 6 dB VDD = 3.6 V Input -20 -20 -40 -40 -60 -60 -80 -80 -100 -100 -120 -120 -140 -140 Output -160 2500 -160 500 1000 1500 2000 0.7 0 0 Power-Supply Rejection Output - V 0 0 100 20 1 2 3 4 5 VICR - Common-Mode Input Voltage Range - V k SVR - Supply Voltage Rejection Ratio - dB 0 -10 RL = 8 W, VIN = 200 mVPP f = 217 Hz RL = 4 Class-AB, VDD = 3.6 V 0.6 PD - Power Dissipation - W CMRR - Common-Mode Rejection Ratio - dB 20 Supply Signal Ripple - V GSM POWER SUPPLY REJECTION vs TIME -20 VDD = 3.6 V -30 VDD = 5 V -40 VDD = 2.7 V -50 -60 0.5 Class-AB, VDD = 3.6 V 0.4 RL = 8 QFN 0.2 0.1 -70 RL = 8 Powers are per Channel 0 -80 0 f - Frequency - Hz -90 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 RL = 4 0.3 0.2 0.4 0.6 0.8 1 1.2 1.4 PO - Output Power - W 5 DC Common Mode Voltage - V Figure 22. Figure 23. Figure 24. POWER DISSIPATION vs OUTPUT POWER EFFICIENCY vs OUTPUT POWER EFFICIENCY vs OUTPUT POWER 1.4 Class-AB, VDD = 5 V RL = 4 90 1.2 Class-AB, VDD = 5 V RL = 8 0.8 RL = 4 0.6 VDD = 5 V 70 60 VDD 50 VDD = 3.6 = 2.5 VV 40 Class-AB 30 QFN 0.4 RL = 8 10 Powers are per Channel 0 0 0.5 1 1.5 2 0 2.5 PO - Output Power - W Figure 25. 0.5 1 1.5 2 PO - Output Power - W Figure 26. VDD = 2.5 V 60 50 Class-AB 40 QFN 20 10 Powers are per Channel 0 VDD = 3.6 V 70 30 QFN 20 0.2 VDD = 5 V 80 Efficiency - % 1 RL = 8 90 80 Efficiency - % PD - Power Dissipation - W 100 100 RL = 4 2.5 Powers are per Channel 0 0 0.2 0.4 0.6 0.8 1 Product Folder Link(s): TPA2012D2 1.4 Figure 27. Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated 1.2 PO - Output Power - W 9 TPA2012D2 SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) POWER DISSIPATION vs OUTPUT POWER PD - Power Dissipation - W Class-AB, VDD = 3.6 V 0.5 Class-AB, VDD = 3.6 V RL = 8 0.4 RL = 4 0.3 WCSP RL = 8 0.2 Class-AB, VDD = 5 V RL = 8 0.8 WCSP 0.6 0.4 0.6 0.8 1 1.2 0.5 PO - Output Power - W 1 1.5 2 0.2 VDD = 5 V 0.6 0.8 1 1.2 1.4 1.6 PO - Output Power - W Figure 30. 1.6 60 50 40 Class-AB, VDD = 5 V 30 WCSP 20 RL = 4 W, THD+N = 10% 1.8 VDD = 3.6 V 70 RL = 4 W, THD+N = 1% 1.4 1.2 RL = 8 W, THD+N = 10% 1 0.8 0.6 0.4 10 0.2 0.4 2 RL = 8 PO - Output Power - W Efficiency - % 0 OUTPUT POWER vs SUPPLY VOLTAGE 80 0.4 0.6 0.8 1 PO - Output Power - W 1.2 1.4 RL = 8 W, THD+N = 1% 0.2 0 2.5 3 3.5 4 4.5 VDD - Supply Voltage - V Figure 31. 10 WCSP Figure 29. 90 0 Class-AB, VDD = 5 V 0 2.5 EFFICIENCY vs OUTPUT POWER 0 40 PO - Output Power - W Figure 28. 100 50 10 Powers are per Channel 0 1.4 VDD = 5 V 60 20 RL = 8 0 0.4 VDD = 3.6 V 30 RL = 4 0.2 0.2 80 70 Powers are per Channel 0 RL = 4 90 RL = 4 1 0.1 0 100 Class-AB, VDD = 5 V 1.2 0.6 PD - Power Dissipation - W 1.4 RL = 4 EFFICIENCY vs OUTPUT POWER Efficiency - % 0.7 POWER DISSIPATION vs OUTPUT POWER Submit Documentation Feedback 5 Figure 32. Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 TPA2012D2 www.ti.com .................................................................................................................................................. SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 APPLICATION INFORMATION To Battery 4.7 mF 1 mF 0.1 mF PVDD* 0.1 mF AVDD INL- OUTL+ 1 nF INL+ 0.1 mF DAC OUTL- 1 nF 0.1 mF INR- OUTR+ INR+ 1 nF 0.1 mF OUTR- Shutdown Control SDL G0 SDR 1 nF G1 PGND AGND * For QFN, an additional capacitor is recomended for the second PVDD pin. Figure 33. Typical Application Circuit V DD to Battery V DD CS CI INR+ Right Differential Input CS OUTR+ Gain Adjust H- Bridge PWM INR+ OUTR- INR- Right Single-Ended Input OUTR+ Gain Adjust CI CI H- Bridge PWM OUTR- CI Internal Oscillator to Battery INR- GND Internal Oscillator GND CI INL+ Left Differential Input OUTL+ Gain Adjust PWM H- Bridge OUTL- INL- CI INL+ Left CI Single-Ended Input PWM H- Bridge OUTL- CI G0 G0 G1 G1 SDR OUTL+ Gain Adjust INL- SDR 300 k Bias Circuitry 300 k Short-Circuit Protection Bias Circuitry Short-Circuit Protection SDL SDL 300 k 300 k Figure 34. TPA2012D2 Application Schematic With Differential Input and Input Capacitors Figure 35. TPA2012D2 Application Schematic With Single-Ended Input Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 11 TPA2012D2 SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 .................................................................................................................................................. www.ti.com Decoupling Capacitor (CS) The TPA2012D2 is a high-performance Class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients, spikes, or digital hash on the line a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 F, placed as close as possible to the device PVDD lead works best. Placing this decoupling capacitor close to the TPA2012D2 is important for the efficiency of the Class-D amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 4.7 F or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. Table 1. Gain Setting G1 G0 GAIN (V/V) GAIN (dB) INPUT IMPEDANCE (RI) (k) 0 0 2 6 28.1 0 1 4 12 17.3 1 0 8 18 9.8 1 1 16 24 5.2 Input Capacitors (CI) The TPA2012D2 does not require input coupling capacitors if the design uses a differential source that is biased from 0.5 V to VDD - 0.8 V. If the input signal is not biased within the recommended common-mode input range, if high pass filtering is needed (see Figure 34), or if using a single-ended source (see Figure 35), input coupling capacitors are required. The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in Equation 1. 1 fc + 2p RIC I (1) The value of the input capacitor is important to consider as it directly affects the bass (low frequency) performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the corner frequency can be set to block low frequencies in this application. Not using input capacitors can increase output offset. Equation 2 is used to solve for the input coupling capacitance. 1 CI + 2p RI f c (2) If the corner frequency is within the audio band, the capacitors should have a tolerance of 10% or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below. 12 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 TPA2012D2 www.ti.com .................................................................................................................................................. SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 BOARD LAYOUT In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 36 and Table 2 shows the appropriate diameters for a WCSP layout. The TPA2012D2 evaluation module (EVM) layout is shown in the next section as a layout example. Copper Trace Width Solder Pad Width Solder Mask Opening Copper Trace Thickness Solder Mask Thickness Figure 36. Land Pattern Dimensions Table 2. Land Pattern Dimensions (1) (2) (3) (4) SOLDER PAD DEFINITIONS COPPER PAD Nonsolder mask defined (NSMD) 275 m (+0.0, -25 m) (1) (2) (3) (4) (5) (6) (7) SOLDER MASK OPENING (5) 375 m (+0.0, -25 m) COPPER THICKNESS STENCIL (6) (7) OPENING STENCIL THICKNESS 1 oz max (32 m) 275 m x 275 m Sq. (rounded corners) 125 m thick Circuit traces from NSMD defined PWB lands should be 75 m to 100 m wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability. Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application. Recommend solder paste is Type 3 or Type 4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance. Solder mask thickness should be less than 20 m on top of the copper circuit pattern Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces. Component Location Place all the external components very close to the TPA2012D2. Placing the decoupling capacitor, CS, close to the TPA2012D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 13 TPA2012D2 SLOS438D - DECEMBER 2004 - REVISED JUNE 2008 .................................................................................................................................................. www.ti.com Trace Width Recommended trace width at the solder balls is 75 m to 100 m to prevent solder wicking onto wider PCB traces. For high current pins (PVDD, PGND, and audio output pins) of the TPA2012D2, use 100-m trace widths at the solder balls and at least 500-m PCB traces to ensure proper performance and output power for the device. For the remaining signals of the TPA2012D2, use 75-m to 100-m trace widths at the solder balls. The audio input pins (INR+/- and INL+/-) must run side-by-side to maximize common-mode noise cancellation. EFFICIENCY AND THERMAL INFORMATION The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the packages are shown in the dissipation rating table. Converting this to JA for the QFN package: 1 q + + 1 + 24CW JA 0.041 Derating Factor (3) Given JA of 24C/W, the maximum allowable junction temperature of 150C, and the maximum internal dissipation of 1.5W (0.75 W per channel) for 2.1 W per channel, 4- load, 5-V supply, from Figure 25, the maximum ambient temperature can be calculated with the following equation. T Max + T Max * q P + 150 * 24 (1.5) + 114C A J JA Dmax (4) Equation 4 shows that the calculated maximum ambient temperature is 114C at maximum power dissipation with a 5-V supply and 4- a load. The TPA2012D2 is designed with thermal protection that turns the device off when the junction temperature surpasses 150C to prevent damage to the IC. Also, using speakers more resistive than 4- dramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier. OPERATION WITH DACs AND CODECs In using Class-D amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor from the audio amplifier. This occurs when mixing of the output frequencies of the CODEC/DAC mix with the switching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a low-pass filter between the CODEC/DAC and audio amplifier. This filters off the high frequencies that cause the problem and allow proper performance. See Figure 33 for the block diagram. FILTER FREE OPERATION AND FERRITE BEAD FILTERS A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and the frequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCC and CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead, choose one with high impedance at high frequencies, and very low impedance at low frequencies. In addition, select a ferrite bead with adequate current rating to prevent distortion of the output signal. Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads from amplifier to speaker. Figure 37 shows typical ferrite bead and LC output filters. Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF Figure 37. Typical Ferrite Chip Bead Filter (Chip bead example: TDK: MPZ1608S221A) 14 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPA2012D2 PACKAGE OPTION ADDENDUM www.ti.com 12-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPA2012D2RTJR ACTIVE QFN RTJ 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA2012D2RTJRG4 ACTIVE QFN RTJ 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA2012D2RTJT ACTIVE QFN RTJ 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA2012D2RTJTG4 ACTIVE QFN RTJ 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA2012D2YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPA2012D2YZHT ACTIVE DSBGA YZH 16 250 SNAGCU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPA2012D2RTJR QFN RTJ 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPA2012D2RTJR QFN RTJ 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPA2012D2RTJT QFN RTJ 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPA2012D2YZHR DSBGA YZH 16 3000 178.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPA2012D2YZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPA2012D2YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPA2012D2YZHT DSBGA YZH 16 250 178.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA2012D2RTJR QFN RTJ 20 3000 367.0 367.0 35.0 TPA2012D2RTJR QFN RTJ 20 3000 367.0 367.0 35.0 TPA2012D2RTJT QFN RTJ 20 250 210.0 185.0 35.0 TPA2012D2YZHR DSBGA YZH 16 3000 217.0 193.0 35.0 TPA2012D2YZHR DSBGA YZH 16 3000 210.0 185.0 35.0 TPA2012D2YZHT DSBGA YZH 16 250 210.0 185.0 35.0 TPA2012D2YZHT DSBGA YZH 16 250 217.0 193.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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