RTJYZH
1
FEATURES APPLICATIONS
DESCRIPTION
VDD = 3.6 V, 10%
0
0.50
1
1.50
2
2.50
4 9 14 19 24 29 34
PO− Output Power − W
RL − Load Resistance − W
WCSP Thermally Limited Region
VDD = 5 V, 1%
VDD = 2.5 V, 1%
VDD = 2.5 V, 10%
VDD = 3.6 V, 1%
VDD = 3.6 V, 10%
TPA2012D2
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.................................................................................................................................................. SLOS438D – DECEMBER 2004 – REVISED JUNE 2008
2.1 W/CH STEREO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER
•Wireless or Cellular Handsets and PDAs2
•Output Power By Package:
•Portable DVD Player– QFN:
•Notebook PC– 2.1 W/Ch Into 4 Ωat 5 V
•Portable Radio– 1.4 W/Ch Into 8 Ωat 5 V
•Portable Gaming– 720 mW/Ch Into 8 Ωat 3.6 V
•Educational Toys– WCSP:
•USB Speakers– 1.2 W/Ch Into 4 Ωat 5 V
(1)
– 1.3 W/Ch Into 8 Ωat 5 V– 720 mW/Ch Into 8 Ωat 3.6 V
The TPA2012D2 is a stereo, filter-free, Class-D audio•Only Two External Components Required
amplifier (class-D amp) available in a WCSP, QFN, orPWP package. The TPA2012D2 only requires two•Power Supply Range: 2.5 V to 5.5 V
external components for operation.•Independent Shutdown Control for EachChannel The TPA2012D2 features independent shutdowncontrols for each channel. The gain can be selected•Selectable Gain of 6, 12, 18, and 24 dB
to 6, 12, 18, or 24 dB utilizing the G0 and G1 gain•Internal Pulldown Resistor On Shutdown Pins
select pins. High PSRR and differential architecture•High PSRR: 77 dB at 217 Hz
provide increased immunity to noise and RFrectification. In addition to these features, a fast•Fast Startup Time (3.5 ms)
startup time and small package size make the•Low Supply Current
TPA2012D2 class-D amp an ideal choice for both•Low Shutdown Current
cellular handsets and PDAs.•Short-Circuit and Thermal Protection•Space Saving Packages– 2,01 mm X 2,01 mm NanoFree™ WCSP(YZH)
– 4 mm X 4 mm Thin QFN (RTJ) withPowerPAD™
(1)
Thermally limited
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION (CONTINUED)
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPA2012D2
SLOS438D – DECEMBER 2004 – REVISED JUNE 2008 ..................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
The TPA2012D2 is capable of driving 1.4 W/Ch at 5 V or 720 mW/Ch at 3.6 V into 8 Ω. The TPA2012D2 is alsocapable of driving 4 Ω. The TPA2012D2 is thermally limited in WCSP and may not achieve 2.1 W/Ch for 4 Ω.The maximum output power in the WCSP is determined by the ability of the circuit board to remove heat. Theoutput power versus load resistance graph below shows thermally limited region of the WCSP in relation to theQFN package. The TPA2012D2 provides thermal and short circuit protection.
AVAILABLE OPTIONS
T
A
PACKAGE PART NUMBER SYMBOL
2 mm x 2 mm, 16-ball WCSP (YZH) TPA2012D2YZH AKR– 40 ° C to 85 ° C
4 mm x 4 mm, 20-pin QFN (RTJ) TPA2012D2RTJ AKS
over operating free-air temperature (unless otherwise noted)
(1)
VALUE UNIT
In active mode – 0.3 to 6.0 VV
SS
Supply voltage, AVDD, PVDD
In shutdown mode – 0.3 to 7.0 VV
I
Input voltage – 0.3 to V
DD
+ 0.3 VContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range – 40 to 85 ° CT
J
Operating junction temperature range – 40 to 150 ° CT
stg
Storage temperature range – 65 to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
T
A
= 25 ° C DERATING T
A
= 75 ° C T
A
= 85 ° CPACKAGE
POWER RATING
(1)
FACTOR POWER RATING POWER RATING
RTJ 5.2 W 41.6 mW/ ° C 3.12 W 2.7 WYZH 1.2 W 9.12 mW/ ° C 690 mW 600 mW
(1) This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard 4-layer 3 in × 3 in PCB.
MIN MAX UNIT
V
SS
Supply voltage AVDD, PVDD 2.5 5.5 VV
IH
High-level input voltage SDL, SDR, G0, G1 1.3 VV
IL
Low-level input voltage SDL, SDR, G0, G1 0.35 VT
A
Operating free-air temperature ÷ 40 85 ° C
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ELECTRICAL CHARACTERISTICS
OPERATING CHARACTERISTICS
TPA2012D2
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.................................................................................................................................................. SLOS438D – DECEMBER 2004 – REVISED JUNE 2008
T
A
= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Inputs ac grounded, A
V
= 6 dB,|V
OO
| Output offset voltage (measured differentially) 5 25 mVV
DD
= 2.5 to 5.5 V
PSRR Power supply rejection ratio V
DD
= 2.5 to 5.5 V – 75 – 55 dB
V
icm
Common-mode input voltage 0.5 V
DD
– 0.8 V
Inputs shorted together,CMRR Common-mode rejection ration – 69 – 50 dBV
DD
= 2.5 to 5.5 V
|I
IH
| High-level input current V
DD
= 5.5 V, V
I
= V
DD
50 µA
|I
IL
| Low-level input current V
DD
= 5.5 V, V
I
= 0 V 5 µA
V
DD
= 5.5 V, No load or output filter 6 9
V
DD
= 3.6 V, No load or output filter 5 7.5 mAI
DD
Supply current
V
DD
= 2.5 V, No load or output filter 4 6
Shutdown mode 1.5 µA
V
DD
= 5.5 V 500
r
DS(on)
Static drain-source on-state resistance V
DD
= 3.6 V 570 m Ω
V
DD
= 2.5 V 700
Output impedance in shutdown mode V
( SDR, SDL)
= 0.35 V 2 k Ω
f
(sw)
Switching frequency V
DD
= 2.5 V to 5.5 V 250 300 350 kHz
G0, G1 = 0.35 V 5.5 6 6.5
G0 = V
DD
, G1 = 0.35 V 11.5 12 12.5Closed-loop voltage gain dBG0 = 0.35 V, G1 = V
DD
17.5 18 18.5
G0, G1 = V
DD
23.5 24 24.5
T
A
= 25 ° C, R
L
= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 5.0 V, f = 1 kHz, THD = 10% 1.4R
L
= 8 ΩP
O
Output power (per channel) V
DD
= 3.6 V, f = 1 kHz, THD = 10% 0.72 W
R
L
= 4 ΩV
DD
= 5.0 V, f = 1 kHz, THD = 10% 2.1
P
O
= 1 W, V
DD
= 5 V, A
V
= 6 dB, f = 1 kHz 0.14%THD+N Total harmonic distortion plus noise
P
O
= 0.5 W, V
DD
= 5 V, A
V
= 6 dB, f = 1 kHz 0.11%
Channel crosstalk f = 1 kHz – 85 dB
V
DD
= 5 V, A
V
= 6 dB, f = 217 Hz – 77k
SVR
Supply ripple rejection ratio dBV
DD
= 3.6 V, A
V
= 6 dB, f = 217 Hz – 73
CMRR Common mode rejection ratio V
DD
= 3.6 V, V
IC
= 1 V
pp
, f = 217 Hz – 69 dB
Av = 6 dB 28.1
Av = 12 dB 17.3Input impedance k ΩAv = 18 dB 9.8
Av = 24 dB 5.2
Start-up time from shutdown V
DD
= 3.6 V 3.5 ms
No weighting 35V
DD
= 3.6 V, f = 20 to 20 kHz,V
n
Output voltage noise µVInputs are ac grounded, A
V
= 6 dB
A weighting 27
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BLOCK DIAGRAM
to Battery
VDD
OUTR+
GND
SDR
INR+
300 k
CS
Right Input
SDL 300 k
G0
OUTR−
OUTL+
OUTL−
G1
INR−
INL+
INL−
G1 Gain
G0 V/V dB
Left Input Gain
Adjust PWM
Gain
Adjust PWM
H −
Bridge
H −
Bridge
Internal
Oscillator
Bias
Circuitry
6
12
18
24
2
4
8
16
0
1
0
1
0
0
1
1
Short−Circuit
Protection
TPA2012D2
SLOS438D – DECEMBER 2004 – REVISED JUNE 2008 ..................................................................................................................................................
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AGND
OUTL+
PGND
INL− G1
G0
SDR
INL+
AVDD
SDL
OUTR−
INR−
PVDD
OUTR+
OUTL−
INR+
A1
B1
C1
D1
A2 A3 A4
AGND
INR+
INR−
INL+
INL−
G0
OUTR+
PVDD
PGND
OUTR−
NC
SDL
SDR
AVDD
NC
OUTL+
PVDD
PGND
G1
OUTL−
20 19 18 17 16
6 7 8 9 10
1
2
3
4
5
15
14
13
12
11
TPA2012D2
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.................................................................................................................................................. SLOS438D – DECEMBER 2004 – REVISED JUNE 2008
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME QFN WCSP
INR+ 16 D1 I Right channel positive inputINR- 17 C1 I Right channel negative inputINL+ 20 A1 I Left channel positive inputINL- 19 B1 I Left channel negative inputSDR 8 B3 I Right channel shutdown terminal (active low)SDL 7 B4 I Left channel shutdown terminal (active low)G0 15 C2 I Gain select (LSB)G1 1 B2 I Gain select (MSB)PVDD 3, 13 A2 I Power supply (Must be same voltage as AVDD)AVDD 9 D2 I Analog supply (Must be same voltage as PVDD)PGND 4, 12 C4 I Power groundAGND 18 C3 I Analog groundOUTR+ 14 D3 O Right channel positive differential outputOUTR- 11 D4 O Right channel negative differential outputOUTL+ 2 A3 O Left channel positive differential outputOUTL- 5 A4 O Left channel negative differential outputNC 6, 10 N/A No internal connectionThermal Pad Connect the thermal pad of QFN or PWP package to PCB GND
WCSP PIN OUT RTJ PIN OUTTOP VIEW TOP VIEW
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TEST SET-UP FOR GRAPHS (per channel)
TPA2012D2
IN+
IN-
OUT+
OUT-
VDD GND
CI
CI
RI
RI
Measurement
Output
+
-
1 Fm
+
-
Load 30kHz
Filter
LowPass Measurement
Input
+
-
VDD
TPA2012D2
SLOS438D – DECEMBER 2004 – REVISED JUNE 2008 ..................................................................................................................................................
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(1) C
I
was Shorted for any Common-Mode input voltage measurement.(2) A 33- µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.(3) The 30 – kHz low – pass filter is required even if the analyzer has an internal low – pass filter. An RC low pass filter (100
Ω, 47 nF) is used on each output for the data sheet graphs.
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TYPICAL CHARACTERISTICS
0.01
0.1
1
10
0.01 0.1 1 3
2.5 V
3.6 V
THD+N − Total Harmonic Distortion + Noise − %
PO − Output Power − W
RL = 8 ,
f = 1 kHz,
AV 24 dB
5 V
20
0.01
0.1
1
10
20
0.01 0.1 1 3
2.5 V
3.6 V
PO − Output Power − W
RL = 8 ,
f = 1 kHz,
AV 6 dB
5 V
THD+N − Total Harmonic Distortion + Noise − %
0.01
0.1
1
10
20
0.01 0.1 1 4
2.5 V
3.6 V
5 V
PO − Output Power − W
RL = 4 ,
f = 1 kHz,
AV 24 dB
THD+N − Total Harmonic Distortion + Noise − %
0.1
1
20 100 1 k 10 k 20 k
f − Frequency − Hz
VDD = 2.5 V,
RL = 4 W,
CI = 1 mF,
AV = 6 dB
0.01
120 mW
350 mW
240 mW
THD+N − Total Harmonic Distortion + Noise − %
0.1
1
20 100 1 k 10 k 20 k
f − Frequency − Hz
VDD = 2.5 V,
RL = 8 W,
CI = 1 mF,
AV = 6 dB
0.01
90 mW
180 mW
THD+N − Total Harmonic Distortion + Noise − %
260 mW
0.01
0.1
1
10
20
0.01 0.1 1 4
2.5 V
3.6 V
5 V
PO − Output Power − W
RL = 4 ,
f = 1 kHz,
AV 6 dB
THD+N − Total Harmonic Distortion + Noise − %
0.1
1
20 100 1 k 10 k 20 k
f − Frequency − Hz
VDD = 3.6 V,
RL = 8 W,
CI = 1 mF,
AV = 6 dB
0.01
190 mW
375 mW
560 mW
THD+N − Total Harmonic Distortion + Noise − %
0.1
1
20 100 1 k 10 k 20 k
f − Frequency − Hz
VDD = 5 V,
RL = 4 W,
CI = 1 mF,
AV = 6 dB
0.01
550 mW
1.1 W
1.65 W
THD+N − Total Harmonic Distortion + Noise − %
0.1
1
20 100 1 k 10 k 20 k
f − Frequency − Hz
VDD = 3.6 V,
RL = 4 W,
CI = 1 mF,
AV = 6 dB
0.01
275 mW
550 mW
825 mW
THD+N − Total Harmonic Distortion + Noise − %
TPA2012D2
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.................................................................................................................................................. SLOS438D – DECEMBER 2004 – REVISED JUNE 2008
TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTIONvs vs vsOUTPUT POWER OUTPUT POWER OUTPUT POWER
Figure 1. Figure 2. Figure 3.
TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTIONvs vs vsOUTPUT POWER FREQUENCY FREQUENCY
Figure 4. Figure 5. Figure 6.
TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTIONvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 7. Figure 8. Figure 9.
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0.1
1
20 100 1 k 10 k 20 k
f − Frequency − Hz
VDD = 5 V,
RL = 8 W,
CI = 1 mF,
AV = 6 dB
0.01
380 mW
775 mW
1.16 W
THD+N − Total Harmonic Distortion + Noise − %
NoOutputFilter
0
1
2
3
4
5
6
0 1 2 3 4 5
VDD = 5 V
VDD = 3.6 V
VDD = 2.5 V
IDD − Supply Current − mA
VSD − Shutdown Voltage − V
0
200
400
600
800
1000
1200
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
VDD = 2.5 V, RL = 4 W, 33 mH
IDD is for Both Channels
VDD = 5 V, RL = 4 W, 33 mH
VDD = 3.6 V, RL = 4 W, 33 mH
IDD − Supply Current − mA
PO − Output Power/Channel − W
IDD − Supply Current − mA
0
100
200
300
400
500
600
700
800
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
VDD = 2.5 V, RL = 8 W, 33 mH
VDD = 3.6 V, RL = 8 W, 33 mH
VDD = 5 V, RL = 8 W, 33 mH
IDD is for Both Channels
PO − Output Power/Channel − W
−140
−120
−100
−80
−60
−40
−20
0
100 1 k 10 k
f − Frequency − Hz
2.5 V R to L
5 V R to L
3.6 V R to L 5 V L to R
3.6 V L to R
Crosstalk − dB
RI = 8 W
20 k20
2.5 V L to R
−100
−90
−80
−70
−60
−50
−40
−30
100 1 k 10 k
Inputs AC, Grounded,
CI = 1 mF,
RI = 4 W,
AV = 6 dB
VDD = 2.7 V
VDD = 5 V
VDD = 3.6 V
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz 20 k20
−120
−100
−80
−60
−40
−20
0
100 1 k 10 k
f − Frequency − Hz
2.5 V R to L
2.5 V L to R 3.6 V L to R
3.6 V R to L 5 V R to L
5 V L to R
Crosstalk − dB
20 k20
RI = 4 W
−100
−90
−80
−70
−60
−50
−40
−30
100 1 k 10 k
Inputs AC Grounded,
CI = 1 mF,
RI = 8 W,
AV = 6 dB
VDD = 2.7 V
VDD = 5 V
VDD = 3.6 V
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz
20 k20
TPA2012D2
SLOS438D – DECEMBER 2004 – REVISED JUNE 2008 ..................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION SUPPLY CURRENT SUPPLY CURRENTvs vs vsFREQUENCY SHUTDOWN VOLTAGE SUPPLY VOLTAGE
Figure 10. Figure 11. Figure 12.
SUPPLY CURRENT SUPPLY CURRENT CROSSTALKvs vs vsOUTPUT POWER OUTPUT POWER FREQUENCY
Figure 13. Figure 14. Figure 15.
POWER SUPPLY POWER SUPPLYCROSSTALK REJECTION RATIO REJECTION RATIOvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 16. Figure 17. Figure 18.
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−75
−70
−65
−60
−55
−50
100 1 k 10 k
VDD = 2.5 V VDD = 3.6 V
VDD = 5 V
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz
VIC = 1 VPP,
RL = 8 W,
AV = 6 dB
20 k20
CMRR − Common-Mode Rejection Ratio − dB
−100
−80
−60
−40
−20
0
20
012345
VICR − Common-Mode Input Voltage Range − V
VDD = 5.5 V
VDD = 3.6 V
VDD = 2.5 V
t − Time − 2 ms/div
VDD
200 mV/div
VOUT
20 mV/div
C1 − High, 3.6 V
C1 − Amp, 512 mV
C1 − Duty, 12%
−160
−140
−120
−100
−80
−60
−40
−20
0
0 500 1000 1500 2000 2500
−160
−140
−120
−100
−80
−60
−40
−20
0
CI = 1 mF,
Inputs AC Grounded,
AV = 6 dB
VDD = 3.6 V
Input
Output
Supply Signal Ripple − V
Power-Supply Rejection Output − V
f − Frequency − Hz
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Class-AB,
VDD = 3.6 V
RL = 4 Ω
RL = 8 ΩRL = 4 Ω
RL = 8 Ω
Powers are per Channel
QFN
− Power Dissipation − W
PD
PO − Output Power − W
Class-AB,
VDD = 3.6 V
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DC Common Mode Voltage − V
VDD = 2.7 V
VDD = 5 V
VDD = 3.6 V
RL = 8 W,
VIN = 200 mVPP
f = 217 Hz
kSVR − Supply Voltage Rejection Ratio − dB
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5
Efficiency − %
PO − Output Power − W
RL = 4 Ω
VDD = 5 V
VDD = 3.6
V
VDD = 2.5 V
QFN
Class-AB
Powers are per Channel
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VDD = 5 V
VDD = 3.6 V
VDD = 2.5 V
Class-AB
RL = 8 Ω
Powers are per Channel
QFN
Efficiency − %
PO − Output Power − W
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.5 1 1.5 2 2.5
Class-AB, VDD = 5 V RL = 4 Ω
RL = 4 Ω
RL = 8 Ω
Powers are per Channel
QFN
− Power Dissipation − W
PD
PO − Output Power − W
Class-AB, VDD = 5 V
RL = 8 Ω
TPA2012D2
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.................................................................................................................................................. SLOS438D – DECEMBER 2004 – REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
COMMOM-MODE
REJECTION RATIO COMMON-MODE GSM POWERvs REJECTION RATIO SUPPLY REJECTIONCOMMON-MODE vs vsINPUT VOLTAGE FREQUENCY TIME
Figure 19. Figure 20. Figure 21.
SUPLY VOLTAGEPOWER SUPPLY REJECTION REJECTION RATIO POWER DISSIPATIONvs vs vsFREQUENCY DC COMMON-MODE VOLTAGE OUTPUT POWER
Figure 22. Figure 23. Figure 24.
POWER DISSIPATION EFFICIENCY EFFICIENCYvs vs vsOUTPUT POWER OUTPUT POWER OUTPUT POWER
Figure 25. Figure 26. Figure 27.
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0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Class-AB, VDD = 3.6 V
RL = 4 Ω
RL = 8 ΩRL = 4 Ω
RL = 8 Ω
Powers are per Channel
WCSP
− Power Dissipation − W
PD
PO − Output Power − W
Class-AB,
VDD = 3.6 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.5 1 1.5 2 2.5
Class-AB, VDD = 5 V
RL = 4 Ω
RL = 4 Ω
RL = 8 Ω
Powers are per Channel
WCSP
− Power Dissipation − W
PD
PO − Output Power − W
RL = 8 Ω
Class-AB, VDD = 5 V
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
VDD = 5 V
RL = 4 Ω
VDD = 3.6 V
Class-AB, VDD = 5 V
WCSP
Efficiency − %
PO − Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VDD = 5 V
RL = 8 Ω
VDD = 3.6 V
Class-AB, VDD = 5 V
WCSP
Efficiency − %
PO − Output Power − W
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.5 3 3.5 4 4.5 5
PO− Output Power − W
VDD − Supply Voltage − V
RL = 4 W,
THD+N = 10%
RL = 4 W,
THD+N = 1%
RL = 8 W,
THD+N = 10%
RL = 8 W,
THD+N = 1%
TPA2012D2
SLOS438D – DECEMBER 2004 – REVISED JUNE 2008 ..................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
POWER DISSIPATION POWER DISSIPATION EFFICIENCYvs vs vsOUTPUT POWER OUTPUT POWER OUTPUT POWER
Figure 28. Figure 29. Figure 30.
EFFICIENCY OUTPUT POWERvs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 31. Figure 32.
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APPLICATION INFORMATION
AVDD
PVDD*
Shutdown
Control
0.1 mF
SDR
SDL
PGND AGND
INR+
INR−
INL+
INL−
OUTR+
OUTR−
OUTL+
OUTL−
1 nF
0.1 mF
DAC
G0
G1
1 mF0.1 mF
4.7 mF
* For QFN, an additional capacitor is recomended for the second PVDD pin.
To Battery
1 nF
1 nF
1 nF
0.1 mF
0.1 mF
to Battery
VDD
OUTR+
GND
INR+
300 k
CS
300 k
G0
OUTR−
OUTL+
OUTL−
G1
INR−
INL+
INL−
Gain
Adjust PWM
Gain
Adjust PWM
H −
Bridge
H −
Bridge
Internal
Oscillator
Bias
Circuitry Short−Circuit
Protection
Right
Single−Ended
Input
CI
CI
SDR
SDL
CI
CI
Left
Single−Ended
Input
to Battery
VDD
OUTR+
GND
INR+
300 k
CS
300 k
G0
OUTR−
OUTL+
OUTL−
G1
INR−
INL+
INL−
Gain
Adjust PWM
Gain
Adjust PWM
H −
Bridge
H −
Bridge
Internal
Oscillator
Bias
Circuitry Short−Circuit
Protection
Right
Differential
Input
CI
CI
Left
Differential
Input
CI
CI
SDR
SDL
TPA2012D2
www.ti.com
.................................................................................................................................................. SLOS438D – DECEMBER 2004 – REVISED JUNE 2008
Figure 33. Typical Application Circuit
Figure 35. TPA2012D2 Application SchematicFigure 34. TPA2012D2 Application Schematic
With Single-Ended InputWith Differential Input and Input Capacitors
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPA2012D2
Decoupling Capacitor (C
S
)
Input Capacitors (C
I
)
fc+1
ǒ2pRICIǓ
(1)
CI+1
ǒ2pRIfcǓ
(2)
TPA2012D2
SLOS438D – DECEMBER 2004 – REVISED JUNE 2008 ..................................................................................................................................................
www.ti.com
The TPA2012D2 is a high-performance Class-D audio amplifier that requires adequate power supply decouplingto ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,spikes, or digital hash on the line a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1µF, placed as close as possible to the device PV
DD
lead works best. Placing this decoupling capacitor close tothe TPA2012D2 is important for the efficiency of the Class-D amplifier, because any resistance or inductance inthe trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noisesignals, a 4.7 µF or greater capacitor placed near the audio power amplifier would also help, but it is not requiredin most applications because of the high PSRR of this device.
Table 1. Gain Setting
INPUT IMPEDANCEGAIN GAING1 G0 (R
I
)(V/V) (dB)
(k Ω)
0 0 2 6 28.10 1 4 12 17.31 0 8 18 9.81 1 16 24 5.2
The TPA2012D2 does not require input coupling capacitors if the design uses a differential source that is biasedfrom 0.5 V to V
DD
– 0.8 V. If the input signal is not biased within the recommended common-mode input range, ifhigh pass filtering is needed (see Figure 34 ), or if using a single-ended source (see Figure 35 ), input couplingcapacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, f
c
, determined inEquation 1 .
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so thecorner frequency can be set to block low frequencies in this application. Not using input capacitors can increaseoutput offset.
Equation 2 is used to solve for the input coupling capacitance.
If the corner frequency is within the audio band, the capacitors should have a tolerance of ± 10% or better,because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
12 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPA2012D2
BOARD LAYOUT
Copper
Trace Width
Solder Mask
Thickness
Solder
Pad Width
Solder Mask
Opening
Copper Trace
Thickness
Component Location
TPA2012D2
www.ti.com
.................................................................................................................................................. SLOS438D – DECEMBER 2004 – REVISED JUNE 2008
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and theopening size is defined by the copper pad width. Figure 36 and Table 2 shows the appropriate diameters for aWCSP layout. The TPA2012D2 evaluation module (EVM) layout is shown in the next section as a layoutexample.
Figure 36. Land Pattern Dimensions
Table 2. Land Pattern Dimensions
(1) (2) (3) (4)
SOLDER PAD COPPER SOLDER MASK
(5)
COPPER STENCIL
(6) (7)
STENCILDEFINITIONS PAD OPENING THICKNESS OPENING THICKNESS
Nonsolder mask 275 µm 275 µm x 275 µm Sq.375 µm (+0.0, -25 µm) 1 oz max (32 µm) 125 µm thickdefined (NSMD) (+0.0, -25 µm) (rounded corners)
(1) Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening.Wider trace widths reduce device stand off and impact reliability.(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of theintended application.(3) Recommend solder paste is Type 3 or Type 4.(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.(5) Solder mask thickness should be less than 20 µm on top of the copper circuit pattern(6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results ininferior solder paste volume control.(7) Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due tosolder wetting forces.
Place all the external components very close to the TPA2012D2. Placing the decoupling capacitor, C
S
, close tothe TPA2012D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the tracebetween the device and the capacitor can cause a loss in efficiency.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPA2012D2
Trace Width
EFFICIENCY AND THERMAL INFORMATION
qJA +1
Derating Factor +1
0.041 +24°CńW
(3)
TAMax +TJMax *qJAPDmax +150 *24 (1.5) +114°C
(4)
OPERATION WITH DACs AND CODECs
FILTER FREE OPERATION AND FERRITE BEAD FILTERS
1 nF
Ferrite
Chip Bead
OUTP
OUTN
Ferrite
Chip Bead
1 nF
TPA2012D2
SLOS438D – DECEMBER 2004 – REVISED JUNE 2008 ..................................................................................................................................................
www.ti.com
Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCBtraces.
For high current pins (PV
DD
, PGND, and audio output pins) of the TPA2012D2, use 100- µm trace widths at thesolder balls and at least 500- µm PCB traces to ensure proper performance and output power for the device.
For the remaining signals of the TPA2012D2, use 75- µm to 100- µm trace widths at the solder balls. The audioinput pins (INR+/- and INL+/-) must run side-by-side to maximize common-mode noise cancellation.
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factorfor the packages are shown in the dissipation rating table. Converting this to θ
JA
for the QFN package:
Given θ
JA
of 24 ° C/W, the maximum allowable junction temperature of 150 ° C, and the maximum internaldissipation of 1.5W (0.75 W per channel) for 2.1 W per channel, 4- Ωload, 5-V supply, from Figure 25 , themaximum ambient temperature can be calculated with the following equation.
Equation 4 shows that the calculated maximum ambient temperature is 114 ° C at maximum power dissipationwith a 5-V supply and 4- Ωa load. The TPA2012D2 is designed with thermal protection that turns the device offwhen the junction temperature surpasses 150 ° C to prevent damage to the IC. Also, using speakers moreresistive than 4- Ωdramatically increases the thermal performance by reducing the output current and increasingthe efficiency of the amplifier.
In using Class-D amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floorfrom the audio amplifier. This occurs when mixing of the output frequencies of the CODEC/DAC mix with theswitching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a low-passfilter between the CODEC/DAC and audio amplifier. This filters off the high frequencies that cause the problemand allow proper performance. See Figure 33 for the block diagram.
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and thefrequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCCand CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead,choose one with high impedance at high frequencies, and very low impedance at low frequencies. In addition,select a ferrite bead with adequate current rating to prevent distortion of the output signal.
Use an LC output filter if there are low frequency ( < 1 MHz) EMI sensitive circuits and/or there are long leadsfrom amplifier to speaker.
Figure 37 shows typical ferrite bead and LC output filters.
Figure 37. Typical Ferrite Chip Bead Filter (Chip bead example: TDK: MPZ1608S221A)
14 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPA2012D2
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPA2012D2RTJR ACTIVE QFN RTJ 20 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA2012D2RTJRG4 ACTIVE QFN RTJ 20 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA2012D2RTJT ACTIVE QFN RTJ 20 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA2012D2RTJTG4 ACTIVE QFN RTJ 20 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA2012D2YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS &
no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPA2012D2YZHT ACTIVE DSBGA YZH 16 250 Green (RoHS &
no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 12-May-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA2012D2RTJR QFN RTJ 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPA2012D2RTJR QFN RTJ 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPA2012D2RTJT QFN RTJ 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPA2012D2YZHR DSBGA YZH 16 3000 178.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPA2012D2YZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPA2012D2YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPA2012D2YZHT DSBGA YZH 16 250 178.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA2012D2RTJR QFN RTJ 20 3000 367.0 367.0 35.0
TPA2012D2RTJR QFN RTJ 20 3000 367.0 367.0 35.0
TPA2012D2RTJT QFN RTJ 20 250 210.0 185.0 35.0
TPA2012D2YZHR DSBGA YZH 16 3000 217.0 193.0 35.0
TPA2012D2YZHR DSBGA YZH 16 3000 210.0 185.0 35.0
TPA2012D2YZHT DSBGA YZH 16 250 210.0 185.0 35.0
TPA2012D2YZHT DSBGA YZH 16 250 217.0 193.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Aug-2012
Pack Materials-Page 2
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