PEX 8524 Versatile PCI Express Switch PR EL IM IN AR Y Data Book Version 0.99 June 2005 Website www.plxtech.com Technical Support www.plxtech.com/support/ Phone 408 774-9060 800 759-3735 FAX 408 774-2169 PLX Technology Confidential - Version 0.99 June, 2005 Data Book PLX Technology, Inc. Revision History Preface The information contained in this document is subject to change without notice. This PLX Document to be updated periodically as new information is made available. Audience This data book provides the functional details of the PLX Technology PEX 8524 Versatile PCI Express Switch, for both hardware designers and software/firmware engineers. Supplemental Documentation This data book assumes that the reader is familiar with the documents referenced below. * PCI Special Interest Group (PCI-SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA PR EL IM IN AR Y Tel: 503 291-2569, Fax: 503 297-1090, http://www.pcisig.com - PCI Local Bus Specification, Revision 2.3 - PCI Express Base Specification 1.0a - PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Express Card Electromechanical Specification, Revision 1.0a - PCI Hot Plug Specification, Revision 1.1 - PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 * The Institute of Electrical and Electronics Engineers, Inc. 445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855-1331, USA Tel: 800 678-4333 (domestic only) or 732 981-0060, Fax: 732 981-1721, http://www.ieee.org - IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 - IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture - IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions - IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions Note: In this data book, shortened titles are provided to the previously listed documents. The following table lists these abbreviations. Abbreviation ii Document PCI r2.3 PCI Local Bus Specification, Revision 2.3 PCI Express Base 1.0a PCI Express Base Specification 1.0a PCI Power Mgmt. r1.1 PCI Bus Power Management Interface Specification, Revision 1.1 PCI ExpressCard 1.0a PCI Express Card Electromechanical Specification, Revision 1.0a PCI HotPlug 1.1 PCI Hot Plug Specification, Revision 1.1 PCI Standard Hot Plug r1.0 PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PLX Technology, Inc. Terms and Abbreviations The following table lists common terms and abbreviations used in this document. Terms and abbreviations defined in the PCI Express Base 1.0a are not included in this table. Terms and Abbreviations Terms and Abbreviations Definitions AMCAM Address mapping CAM that determines a memory request route. It contains mirror copies of the PCI-to-PCI Bridges Memory Base and Limit registers in the switch. BusNoCAM Bus Number mapping CAM that determines the completion route. It contains mirror copies of the PCI-to-PCI Bridges Secondary Bus-Number and Subordinate Bus-Number registers in the switch. CAM Content Addressable Memory. CSRs Configuration Space registers. Egress Q Foreign PR EL IM IN AR Y Downstream Station Ingress Q A station that contains only Downstream ports. * Egress - Outgoing traffic from chip. * Egress Q - Egress queuing/scheduling mechanism. Reference to PCI Express attributes that belong to (off-chip) PCI Express components located on the other side of PCI Express links. * Ingress - Incoming traffic to chip. * Ingress Q - Ingress queuing/scheduling mechanism. IOAMCAM I/O Address mapping CAM that determines an I/O request route. It contains mirror copies of the PCI-to-PCI Bridges I/O Base and Limit registers in the switch. Lane Lanes are comprised of a bi-directional pair of differential PCI Express I/O signals. Local Reference to PCI Express attributes (such as, credits) that belong to the PCI Express station. Copyright Information Copyright (c) 2003, 2004, 2005 PLX Technology, Inc. All rights reserved. The information in this document is proprietary and confidential to PLX Technology, Inc. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology, Inc. products. PLX Technology, the PLX logo, and Data Pipe Architecture are registered trademarks of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group. All product names are trademarks, registered trademarks, or service marks of their respective owners. iii PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Data Book PLX Technology, Inc. Terms and Abbreviations (Cont.) Terms and Abbreviations A bridging technique used in the PCI Express Switch to isolate memory spaces by presenting the processor as an endpoint rather than another memory system. PCI Express Station A functional unit that provides the PCI Express conforming system interface. It includes the Serializer and De-serializer (SerDes) hardware interface modules and PCI Express Interface, which provides the Physical Layer, Data Link Layer, and Transaction Layer logic. PHY Physical Layer. Port Ports are a collection of lanes configured at startup which contain the functional logic and memory resources to communicate with like resources in other PCI Express devices. QoS Quality of Service. RAS Reliability, Availability, and Serviceability. RR Round-Robin scheduling. TC TDM TLC TLP PR EL IM IN AR Y Non-Transparent SerDes Serializer/De-serializer. A high-speed differential-signaling parallel-to-serial and serial-toparallel conversion logic attached to lane pads. Traffic Class. Time Division Multiplexing. Transaction Layer Control. The module performing PCI Express Transaction Layer functions. Transaction Layer Packet. PCI-Express packet formation and organization. Transparent Refers to standard PCI Express upstream-to-downstream routing protocol. Upstream station Upstream station. Contains the component's Upstream port. An upstream station may contain Downstream ports. VC Virtual Channel. WRR iv Definitions Weighted Round-Robin scheduling. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Register Types Register Types The following table describes the PEX 8524 register types, grouped by accessibility. Register Types Description HwInit Hardware Initialized Register or Bit. Refers to the PEX 8524 hardware initialization mechanism or PEX 8524 EEPROM register initialization feature. Read-Only after initialization and can only be reset with Fundamental Reset. R/W Read-Write Register. Read/write and is set or cleared to the desired state by software. R/W1C Read-Only Status. Write "1b" to clear Status register or bit. Indicate status when read. A status bit set by the system to "1b" (to indicate status) is cleared by writing a "1b" to that bit. Writing "0b" has no effect. R/W1CS Read-Only Status. Write "1b" to clear status register or bit. Indicate status when read. A status bit set by the system to "1b" to indicate status is cleared by writing a "1b" to that bit. Writing "0b" does not have an effect. Bits are not initialized or modified by Hot Reset. PR EL IM IN AR Y Type R/W1S Write "1b" to Set Register. Non-transparent ports contain these types of Device-Specific Control registers. Software writes "1b" to the register to enable control and "1b" to a register with R/W1C privilege to clear the control. Writing "0b" has no effect. R/WS Read-Write Register or Bit. Read/write and is set or cleared to the desired state by software. Bits are not initialized or modified by Hot Reset. RO Read-Only register. Read-Only and cannot be altered by software. Initialized by the PEX 8524 hardware initialization mechanism or PEX 8524 EEPROM register initialization feature. ROS Read-Only Sticky. Read-Only and cannot be altered by software. Initialized by the PEX 8524 hardware initialization mechanism or PEX 8524 EEPROM register initialization feature. Bits are not initialized or modified by Hot Reset. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential v Data Book PLX Technology, Inc. Conventions The following notations and conventions are used in this manual. Notations and Conventions Notation Description # = Active Low signals Unless specified otherwise, Active-Low signals are identified by a "#" appended to the term (for example, PEX_PERST#). Program/code samples Monospace font (program or code samples) is used to identify code samples or programming references. These code samples are case sensitive, unless specified otherwise. command_done Interrupt format. PR EL IM IN AR Y PEX_HSIp[15:0] When the signal name appears in all CAPS, with the primary port description listed first, field [15:0] indicates number of signal balls/pads assigned to that port. The lower case "p = positive" or "n = negative" suffix indicates the differential pair of signal, which are always used together. Status/Command Register names. Parity Error Detected Register parameter [field] or control function. UPPER BASE ADDRESS[31:16] Specific Function in 32-bit register bounded by bits [31:16]. k = 1000 (103)is generally used with frequency response. Number multipliers 01Fh 1010b vi K = 1024 (210) is used for memory size references. KB = 1024 bytes. M = meg. = 1,000,000 when referring to frequency (decimal notation) = 1,048,576 when referring to memory sizes (binary notation). h = suffix which identifies hex values. Each prefix term is equivalent to a 4-bit binary value (nibble). Legal prefix terms are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. Formats are right justified b = suffix which identifies binary notation (for example, 0b, 1b, 1010b, and so forth). 0 through 9 Decimal numbers. byte Eight bits - abbreviated to "B" (for example, 4B = 4 bytes) LSB Least-Significant Byte. lsb Least-significant bit. MSB Most-Significant Byte. msb Most-significant bit. DWord DWord (32-bits) is the primary register size in these devices. Reserved Do not modify Reserved bits and words. Unless specified otherwise, these bits read as 0 and are to be written as 0. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential PEX 8524 Versatile PCI Express Switch PR EL IM IN AR Y Data Book Version 0.99 June 2005 Website www.plxtech.com Technical Support www.plxtech.com/support/ Phone 408 774-9060 800 759-3735 FAX 408 774-2169 PLX Technology Confidential - Version 0.99 June, 2005 Data Book PLX Technology, Inc. Revision History Revision History Version Date 0.99 June, 2005 Description of Changes Initial Release Blue Book, Silicon revision BA. Preface The information contained in this document is subject to change without notice. This PLX Document to be updated periodically as new information is made available. Audience This data book provides the functional details of the PLX Technology PEX 8524 Versatile PCI Express Switch, for both hardware designers and software/firmware engineers. PR EL IM IN AR Y Supplemental Documentation This data book assumes that the reader is familiar with the documents referenced below. * PCI Special Interest Group (PCI-SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 503 291-2569, Fax: 503 297-1090, http://www.pcisig.com - PCI Local Bus Specification, Revision 2.3 - PCI Express Base Specification 1.0a - PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Express Card Electromechanical Specification, Revision 1.0a - PCI Hot Plug Specification, Revision 1.1 - PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 * The Institute of Electrical and Electronics Engineers, Inc. 445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855-1331, USA Tel: 800 678-4333 (domestic only) or 732 981-0060, Fax: 732 981-1721, http://www.ieee.org - IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 - IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture - IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions - IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions Note: In this data book, shortened titles are provided to the previously listed documents. The following table lists these abbreviations. Abbreviation viii Document PCI r2.3 PCI Local Bus Specification, Revision 2.3 PCI Express Base 1.0a PCI Express Base Specification 1.0a PCI Power Mgmt. r1.1 PCI Bus Power Management Interface Specification, Revision 1.1 PCI ExpressCard 1.0a PCI Express Card Electromechanical Specification, Revision 1.0a PCI HotPlug 1.1 PCI Hot Plug Specification, Revision 1.1 PCI Standard Hot Plug r1.0 PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PLX Technology, Inc. Terms and Abbreviations The following table lists common terms and abbreviations used in this document. Terms and abbreviations defined in the PCI Express Base 1.0a are not included in this table. Terms and Abbreviations Terms and Abbreviations Definitions AMCAM Address mapping CAM that determines a memory request route. It contains mirror copies of the PCI-to-PCI Bridges Memory Base and Limit registers in the switch. BusNoCAM Bus Number mapping CAM that determines the completion route. It contains mirror copies of the PCI-to-PCI Bridges Secondary Bus-Number and Subordinate Bus-Number registers in the switch. CAM Content Addressable Memory. CSRs Configuration Space registers. Egress Q Foreign PR EL IM IN AR Y Downstream Station Ingress Q A station that contains only Downstream ports. * Egress - Outgoing traffic from chip. * Egress Q - Egress queuing/scheduling mechanism. Reference to PCI Express attributes that belong to (off-chip) PCI Express components located on the other side of PCI Express links. * Ingress - Incoming traffic to chip. * Ingress Q - Ingress queuing/scheduling mechanism. IOAMCAM I/O Address mapping CAM that determines an I/O request route. It contains mirror copies of the PCI-to-PCI Bridges I/O Base and Limit registers in the switch. Lane Lanes are comprised of a bi-directional pair of differential PCI Express I/O signals. Local Reference to PCI Express attributes (such as, credits) that belong to the PCI Express station. Copyright Information Copyright (c) 2003, 2004, 2005 PLX Technology, Inc. All rights reserved. The information in this document is proprietary and confidential to PLX Technology, Inc. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology, Inc. products. PLX Technology, the PLX logo, and Data Pipe Architecture are registered trademarks of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group. All product names are trademarks, registered trademarks, or service marks of their respective owners. ix PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Data Book PLX Technology, Inc. Terms and Abbreviations (Cont.) Terms and Abbreviations A bridging technique used in the PCI Express Switch to isolate memory spaces by presenting the processor as an endpoint rather than another memory system. PCI Express Station A functional unit that provides the PCI Express conforming system interface. It includes the Serializer and De-serializer (SerDes) hardware interface modules and PCI Express Interface, which provides the Physical Layer, Data Link Layer, and Transaction Layer logic. PHY Physical Layer. Port Ports are a collection of lanes configured at startup which contain the functional logic and memory resources to communicate with like resources in other PCI Express devices. QoS Quality of Service. RAS Reliability, Availability, and Serviceability. RR Round-Robin scheduling. TC TDM TLC TLP PR EL IM IN AR Y Non-Transparent SerDes Serializer/De-serializer. A high-speed differential-signaling parallel-to-serial and serial-toparallel conversion logic attached to lane pads. Traffic Class. Time Division Multiplexing. Transaction Layer Control. The module performing PCI Express Transaction Layer functions. Transaction Layer Packet. PCI-Express packet formation and organization. Transparent Refers to standard PCI Express upstream-to-downstream routing protocol. Upstream station Upstream station. Contains the component's Upstream port. An upstream station may contain Downstream ports. VC Virtual Channel. WRR x Definitions Weighted Round-Robin scheduling. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Register Types Register Types The following table describes the PEX 8524 register types, grouped by accessibility. Register Types Description HwInit Hardware Initialized Register or Bit. Refers to the PEX 8524 hardware initialization mechanism or PEX 8524 EEPROM register initialization feature. Read-Only after initialization and can only be reset with Fundamental Reset. R/W Read-Write Register. Read/write and is set or cleared to the desired state by software. R/W1C Read-Only Status. Write "1b" to clear Status register or bit. Indicate status when read. A status bit set by the system to "1b" (to indicate status) is cleared by writing a "1b" to that bit. Writing "0b" has no effect. R/W1CS Read-Only Status. Write "1b" to clear status register or bit. Indicate status when read. A status bit set by the system to "1b" to indicate status is cleared by writing a "1b" to that bit. Writing "0b" does not have an effect. Bits are not initialized or modified by Hot Reset. PR EL IM IN AR Y Type R/W1S Write "1b" to Set Register. Non-transparent ports contain these types of Device-Specific Control registers. Software writes "1b" to the register to enable control and "1b" to a register with R/W1C privilege to clear the control. Writing "0b" has no effect. R/WS Read-Write Register or Bit. Read/write and is set or cleared to the desired state by software. Bits are not initialized or modified by Hot Reset. RO Read-Only register. Read-Only and cannot be altered by software. Initialized by the PEX 8524 hardware initialization mechanism or PEX 8524 EEPROM register initialization feature. ROS Read-Only Sticky. Read-Only and cannot be altered by software. Initialized by the PEX 8524 hardware initialization mechanism or PEX 8524 EEPROM register initialization feature. Bits are not initialized or modified by Hot Reset. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential xi PLX Technology, Inc. Conventions The following notations and conventions are used in this manual. Notations and Conventions Notation Description # = Active Low signals Unless specified otherwise, Active-Low signals are identified by a "#" appended to the term (for example, PEX_PERST#). Program/code samples Monospace font (program or code samples) is used to identify code samples or programming references. These code samples are case sensitive, unless specified otherwise. command_done Interrupt format. PR EL IM IN AR Y PEX_HSIp[15:0] When the signal name appears in all CAPS, with the primary port description listed first, field [15:0] indicates number of signal balls/pads assigned to that port. The lower case "p = positive" or "n = negative" suffix indicates the differential pair of signal, which are always used together. Status/Command Register names. Parity Error Detected Register parameter [field] or control function. UPPER BASE ADDRESS[31:16] Specific Function in 32-bit register bounded by bits [31:16]. k = 1000 (103)is generally used with frequency response. Number multipliers 01Fh 1010b K = 1024 (210) is used for memory size references. KB = 1024 bytes. M = meg. = 1,000,000 when referring to frequency (decimal notation) = 1,048,576 when referring to memory sizes (binary notation). h = suffix which identifies hex values. Each prefix term is equivalent to a 4-bit binary value (nibble). Legal prefix terms are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. Formats are right justified b = suffix which identifies binary notation (for example, 0b, 1b, 1010b, and so forth). 0 through 9 Decimal numbers. byte Eight bits - abbreviated to "B" (for example, 4B = 4 bytes) LSB Least-Significant Byte. lsb Least-significant bit. MSB Most-Significant Byte. msb Most-significant bit. DWord DWord (32-bits) is the primary register size in these devices. Reserved Do not modify Reserved bits and words. Unless specified otherwise, these bits read as 0 and are to be written as 0. Table of Contents Table of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 xii PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Conventions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Lane Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Chapter 2 PEX 8524 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chapter 3 PR EL IM IN AR Y Multi-Purpose and Feature-Rich PCI ExpressLaneTM Switch . . . . . . . . . . . . . . . . . . . End-to-End Packet Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Switch Non-Transparent "Bridging" . . . . . . . . . . . . . . . . . . . . . . . . . Two Virtual Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power with Granular SerDes Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flexible Port-Width Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Plug in High Availability Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fully Compliant Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SerDes Power and Signal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flexible Virtual Channel Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Centric Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peer-to-Peer Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphics Fan-Out Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intelligent Adapter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Port Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Sources/Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Pull-Up Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Plug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Strapping Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 4 3 3 4 4 4 4 5 5 5 5 5 5 6 6 7 7 8 8 9 11 11 12 12 13 14 16 17 19 19 20 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PEX 8524 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ingress and Egress Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Station and Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI-Compatible Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Station Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Link Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transaction Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Blocking Crossbar Switch Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special PEX 8524 Relaxed Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Transparent Bridging Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intelligent Adapter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 23 23 24 25 26 26 27 27 29 29 30 32 32 33 33 xiii PLX Technology, Inc. Dual-Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Chapter 5 Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Reset Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cold Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLX-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 PR EL IM IN AR Y Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTx-Type Interrupt Message Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTx Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remapping and Collapsing of INTx Type Interrupts . . . . . . . . . . . . . . . . . . . . . . . Message Signaled Interrupt (MSI) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Signaled Interrupt Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . Chapter 7 55 55 55 56 58 60 61 62 62 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Blocking Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queuing Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port-to-Station Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM and Queue Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packet Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Theoretical Upper Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Stream Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Stream Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Throughput and Packet Size Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Link Layer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queuing Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Division Multiplex Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv 51 51 52 52 52 53 53 53 Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 PEX 8524 Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Configuration and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Configuration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Device Number Assignment Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Packet Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Base Address Registers (BARs) to Access Registers . . . . . . . . . . . . . . . . . Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Plug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 8 37 37 37 38 39 39 39 40 40 46 63 64 64 65 66 66 66 67 71 71 72 77 77 78 80 80 80 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Conventions High-Priority Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Smaller Size Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Chapter 9 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Power Management Capabilities Summary . . . . . . . . . . . . . . . . . . . . . Device Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Power Management State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 PCI Express Power Management Support . . . . . . . . . . . . . . . . . . . . . . Chapter 10 PEX 8524 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PR EL IM IN AR Y Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1 PEX 8524 Port Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Port Register Configuration and Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Base 1.0a Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . . . PLX-Specific Memory-Mapped Configuration Space Access Mechanism . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Header Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Signaled Interrupt Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Serial Number Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . Device Power Budgeting Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . Virtual Channel Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Channel Arbitration Table (All Ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLX-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Checking and Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Layer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAM Routing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Base and Limit Upper 16 Bits Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Address Registers (BARs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shadow Virtual Channel (VC) Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . Shadow Port Virtual Channel Capability_1 Registers . . . . . . . . . . . . . . . . . . . . . . Ingress Credit Handler (INCH) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Egress Credit Handler (EGCH) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLX-Specific Relaxed Ordering Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Credit Handler (ITCH) VC&T Threshold Registers . . . . . . . . . . . . . . . . . . Non-Transparent Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Error Reporting Capability Registers (All Ports) . . . . . . . . . . . . . . . . . . . . . Chapter 11 83 84 84 85 86 95 96 97 98 98 99 100 101 111 113 115 127 128 130 135 136 137 148 163 178 179 181 189 196 198 202 203 204 206 206 Non-Transparent (NT) Bridging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Type Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Transparent-Port (NT Port) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scratchpad Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Doorbell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BAR Setup Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Requester ID Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transaction Originating in Local Host Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 213 213 213 214 214 215 217 221 223 xv PLX Technology, Inc. System Host Domain Transaction Originating . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Port Power Management Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active State Power Management (ASPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI-PM and PME Turn Off Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Hot Plug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Plug Sequence during Host-Failover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 12 Non-Transparent Bridging Software Architecture . . . . . . . . . . . . . . . . . . . .229 229 229 230 232 234 234 235 PR EL IM IN AR Y Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Intelligent Adapter Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . Sample PEX 8524 Configuration Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Dual-Host Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host-Failover Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer through NT Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 13 224 225 225 226 226 226 228 NT Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Doorbell Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Doorbell Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Chapter 14 NT Port Virtual Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 PCI Express Base 1.0a Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . . . 241 PLX-Specific Memory-Mapped Configuration Space Access Mechanism . . . . . . . 242 PLX-Specific I/O-Mapped Configuration Space Access Mechanism . . . . . . . . . . . 243 PLX-Specific Cursor Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Configuration Header Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Power Management Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Message Signaled Interrupt Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 PCI Express Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Virtual Interface IRQ Doorbell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 NT Port Scratchpad (Mailbox) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 NT Port BAR Setup Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Cursor Mechanism Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Device Serial Number Extended Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . 268 Device Power-Budgeting Extended Capabilities Registers . . . . . . . . . . . . . . . . . . . . . 268 Virtual Channel Extended Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 PLX-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 PEX 8524 Non-Transparent Bridging-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . 270 NT Port Memory Address Translation Registers - BAR Limit Registers . . . . . . . . 271 Lookup Table-Based Address Translation Registers . . . . . . . . . . . . . . . . . . . . . . . 273 NT Port Virtual Interface Base Address Registers (BARs) and BAR Setup Registers 275 NT Port Virtual Interface Send LUT Entry Registers . . . . . . . . . . . . . . . . . . . . . . . 282 Advanced Error Reporting Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Chapter 15 NT Port Link Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 xvi PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Conventions Chapter 16 PR EL IM IN AR Y PCI Express Base 1.0a Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . . . PLX-Specific Memory-Mapped Configuration Space Access Mechanism . . . . . . PLX-Specific I/O-Mapped Configuration Space Access Mechanism . . . . . . . . . . . PLX-Specific Cursor Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Header Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Signaled Interrupt Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Port Link Interface Interrupt Request (IRQ) Doorbell Registers . . . . . . . . . . . . . . . NT Port Scratchpad (Mailbox) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Port BAR Setup Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cursor Mechanism Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Serial Number Extended Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . Device Power Budgeting Extended Capabilities Registers . . . . . . . . . . . . . . . . . . . . . Virtual Channel Extended Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLX-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Checking and Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Port Link Interface Physical Layer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . PLX-Specific Relaxed Ordering Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Port Link Interface Memory Address Translation and Limit BAR Registers . . . NT Port Link Interface Receive LUT Entry Registers . . . . . . . . . . . . . . . . . . . . . . Advanced Error Reporting Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Physical Layer Loop-Back Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Loop-Back Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Loop-Back Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Loop-Back Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Loop-Back Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Diagnostic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pseudo-Random and Bit-Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 and 1149.6 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Boundary Scan Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Reset Input Signal JTAG_TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lane-Good Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 17 323 323 324 325 326 327 328 328 328 329 329 330 331 332 332 Hot Plug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Hot Plug Purpose and Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Plug Controller Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Plug Port External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Capabilities Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Plug Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Plug Card Insertion and Removal Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 18 287 289 290 290 290 291 299 301 302 308 308 309 311 312 312 313 314 314 317 317 318 321 322 333 333 334 335 335 336 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 PEX 8524 Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential xvii PLX Technology, Inc. Digital Interface Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 SerDes/Lane Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Chapter 19 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 PEX 8524 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8524 Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A 347 347 348 349 Serial EEPROM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 Serial EEPROM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Appendix B General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 PR EL IM IN AR Y Product Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 United States and International Representatives, and Distributors . . . . . . . . . . . . . . . 373 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 xviii PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 1 1.1 Introduction Features * Standards Compliant - PCI Express Base 1.0a - PCI Standard Hot Plug r1.0 * High Performance - PEX 8524 = 24 PCI Express lanes provide 120 Gbps aggregate bandwidth [2.5 Gbps/lane x 24 lanes x 2 (full duplex)] - Non-blocking internal crossbar architecture supports full wire speed PR EL IM IN AR Y - Maximum packet payload size of 256 bytes - Performance tuning * Flexible Configuration - PEX 8524 = 24 PCI Express lanes, up to 6 ports - Up to 40 possible port configurations - Assign x1, x2, x4, or x8 lanes to ports - Designate any port as Upstream port - Configure with strapping balls and/or serial EEPROM - Lane reversal support * PCI Express Power Management - Link Power Management states - L0, L0s, L1, L2/L3 Ready, and L3 - Device Power Management states - D0 and D3hot * Quality of Service (QoS) - All ports support two, full-featured Virtual Channels (VCs) - All ports support eight Traffic Class (TC) mapping, independent of other ports - Port arbitration - Round-Robin or Hardware-fixed arbitration scheme - Virtual channel arbitration - Weighted Round-Robin (WRR) * Non-Transparent Bridging - Program any one port as non-transparent - Enables dual-host, dual-fabric, fail-over applications * Transaction Forwarding with Address Translation * Reliability, Availability, Serviceability (RAS) - Each Downstream port includes PCI Express Hot Plug Controller - Upstream port supports Hot Plug as a client - Transaction Layer Packet Digest support * Poison bit * End-to-end CRC - Advanced Error Reporting capability - Per port diagnostics * TLP errors * CRC errors - All on-chip RAMs are ECC protected PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 1 Introduction PLX Technology, Inc. - EEPROM content is CRC protected * Testability - JTAG boundary scan 1.2 Overview The PEX 8524 Versatile PCI Express Switch conforms to the PCI Express Base 1.0a. The PEX 8524 products enable users to add scalable high-bandwidth I/Os to a wide variety of applications including servers, communication products, storage systems, routers, blade servers, and other embedded products. The PEX 8524 switch is hardware configurable and software programmable; therefore, port configurations and Quality of Service operating characteristics can be tailored to suit a variety of application requirements. 1.3 Lane Configuration PR EL IM IN AR Y The PEX 8524 switch is suitable for host-centric and peer-to-peer communication. The PEX 8524 contains 24 PCI Express lanes and up to six ports. Figure 1-1 illustrates the way in which the PEX 8524 flexible-lane configuration feature supports a variety of switch applications. Figure 1-1 (a) illustrates a host-centric port configuration, where a wide PCI Express link is fanned out into smaller ports with different bandwidth requirements. Figure 1-1 (b) illustrates backplane port configuration, where the wide PCI Express port provides a high-bandwidth path to a host or a switch fabric from a large number of line cards with smaller ports. Figure 1-1 (c) illustrates an 8-slot symmetric backplane, with x4 links traveling to each slot for peer-to-peer applications. Figure 1-1. PEX 8524 Flexible-Lane Configuration x8 x8 x8 PEX 8524 PCI Express Switch x2 x4 x2 x4 x4 x4 x4 (a) System I/O x4 PEX 8524 PCI Express Switch x4 PEX 8524 PCI Express Switch x4 x4 (b) Line Card x4 x4 (c) Host or Line Card 2 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 2 2.1 PEX 8524 Applications Multi-Purpose and Feature-Rich PCI ExpressLaneTM Switch The ExpressLane PEX 8524 device offers PCI Express switching capability conforming to the latest PCI Express Base 1.0a revision. These products allow addition of scalable high bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage systems, communications platforms, Blade servers, and embedded-control products. The PEX 8524 switch can be used as fan-out, aggregation, dual graphics, or peer-to-peer switching, and is equally well-suited for intelligent I/O module applications. 2.1.1 End-to-End Packet Integrity The PEX 8524 provides end-to-end CRC protection (ECRC) and Poison-Bit support to enable designs that require guaranteed error-free packets. These features are optional in the PCI Express Base 1.0a; however, PLX provides them across its entire ExpressLane switch product line. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 3 PEX 8524 Applications 2.1.2 PLX Technology, Inc. PCI Express Switch Non-Transparent "Bridging" The PEX 8524 supports full non-transparent bridging functionality to allow implementation of multihost systems and intelligent I/O modules in applications such as communications, storage, and graphics fan-out. To ensure prompt product migration, non-transparency features are implemented in the same manner as standard PCI applications. Non-transparent bridges allow systems to isolate memory domains by presenting the processor subsystem as an endpoint, rather than another memory system: * Base Address registers (BARs) are used to translate addresses * Doorbell registers are used to transmit interrupts between the address domains * Scratchpad registers are accessible from both address domains, to allow inter-processor communication 2.1.3 Two Virtual Channels 2.1.4 PR EL IM IN AR Y The PEX 8524 switch supports two full-featured Virtual Channels (VCs) and eight Traffic Classes (TCs). Traffic-class mapping to port-specific Virtual Channels allows different mappings on different ports. In addition, this device offers user-selectable Virtual Channel arbitration algorithms to enable fine-tuning of Quality of Service (QoS), required for specific applications. Low Power with Granular SerDes Control The PEX 8524 provides low-power capability, which is fully compliant with the PCI Power Mgmt. r1.1. In addition, the SerDes physical links can be turned off when unused to further lower power. 2.1.5 Flexible Port-Width Configuration The lane width per port can be individually configured through auto-negotiation, hardware strapping, upstream software configuration, or an optional serial EEPROM. The PEX 8524 supports a large number of port configurations. For example, if the PEX 8524 is used in a fan-out application (as illustrated in Figure 2-1), the Upstream port can be configured as x8 and the Downstream ports as four x4 ports; two x8 ports; or any other combination provided that available lanes or ports are not exceeded. For peer-to-peer applications, all six ports can be configured as x4 or x2, or a combination of the two. In port aggregation applications, four x2 or x4 ports can be configured for aggregation into one x8 port. Each port supports lane reversal for more flexibility in system design. Figure 2-1. Fan-In/Fan-Out Usage CPU CPU M em ory Root Com plex South Bridge x8 PCI or PCI-X PEX 8114 4 PCI x4 PEX 8524 PEX 8111 GbE USB HDD x4 x1 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 2.1.6 Hot Plug in High Availability Applications Hot Plug in High Availability Applications Hot Plug capability allows replacement of hardware modules and maintenance performance without system power down. The PEX 8524 Hot Plug capability and Advanced Error Reporting features make the ExpressLane PEX 8524 suitable for High Availability (HA) applications. Each Downstream port includes a Standard Hot Plug controller. If the PEX 8524 is used in an application where one or more of its Downstream ports connects to PCI Express slots, the individual port Hot Plug controller is used to manage the Hot Plug event of its associated slot. Furthermore, its Upstream port is a Hot Plug client, allowing it to be used on Hot Pluggable adapter cards, backplanes, and fabric modules. 2.1.7 Fully Compliant Power Management 2.1.8 PR EL IM IN AR Y For applications that require power management, the PEX 8524 supports link (L0, L0s, L1, L2/L3 Ready, and L3) and device (D0 and D3hot) power management states, in compliance with the PCI Power Mgmt. r1.1. SerDes Power and Signal Management The ExpressLane PEX 8524 supports SerDes output software control to allow power optimization and system signal strength. The PLX SerDes implementation supports four levels of power - off, low, typical, and high. The SerDes block also supports Loop-Back modes and advanced reporting of error conditions, which enables efficient debug and entire system management. 2.1.9 Flexible Virtual Channel Arbitration The PEX 8524 switch supports Hardware-fixed and Weighted Round-Robin arbitration schemes for two virtual channels. This allows fine-tuning of Quality of Service, optimum buffer use, and efficient system bandwidth use. 2.2 Applications Suitable for host-centric and peer-to-peer traffic patterns, the ExpressLane PEX 8524 can be configured for a wide variety of form factors and applications. 2.2.1 Host Centric Fan-Out The PEX 8524, with versatile symmetric or asymmetric lane configuration capability, allows application-specific tuning to a variety of host-centric applications. Figure 2-1 illustrates a typical server-based design, where the root complex provides a PCI Express link needing to be broken into a larger number of smaller ports for a variety of I/O functions with different bandwidth requirements. In this example, the PEX 8524 contains an 8-lane Upstream port, and as many as five Downstream ports. The Downstream ports can be of differing widths if required. Figure 2-1 also illustrates in what ways various ports can be bridged to provide PCI or PCI-X using ExpressLane PCI Express bridges, such as the PEX 8114 or PEX 8111. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 5 PEX 8524 Applications PLX Technology, Inc. Figure 2-2. PowerPC/MIPS CPUs Fan-Out MIPS or PowerPC x8 x4 x4 x4 PEX 8524 x2 x2 2.2.2 PR EL IM IN AR Y Almost all (non-x86-based) RISC microprocessor manufacturers are offering PCI Express interfaces. For enhanced connectivity, the PEX 8524 can be directly connected to a processor to fan-out its PCI Express port to a larger number of ports, as illustrated in Figure 2-2. Peer-to-Peer Communication Figure 2-3 represents a ExpressLane PEX 8524 backplane that provides peer-to-peer data exchange for a large number of line cards wherein the CPU/Host plays the management role. Figure 2-3. Peer-to-Peer Usage I/O Host I/O x4 I/O x4 I/O PEX 8524 I/O 2.2.3 Graphics Fan-Out Switch The number and variety of PCI Express native-mode devices is rapidly growing. These devices such as PCI Express graphics cards are expected to rapidly become mainstream. As that occurs, it becomes necessary to use an x8 port on the root complex device and fan it out to two x4 (or x8) ports for dualgraphic applications. Root Complex (Northbridge) devices are available with multiple PCI Express ports, which can be further expanded to connect to a larger number of I/Os or to support dual-graphics, using the PEX 8524, as illustrated in Figure 2-4. 6 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Intelligent Adapter Card Figure 2-4. Graphics Fan-Out CPU x8 x8 PEX 8524 x8 Memory Root Complex PCI PEX 8111 x8 x1 South Bridge PCI PEX 8516 PEX 8114 USB GbE HDD x4 PCI Express PCI-X 2.2.4 PR EL IM IN AR Y x1 Intelligent Adapter Card The PEX 8524 supports non-transparency bridging (NTB). Figure 2-5 illustrates a host system using an intelligent adapter card. In Figure 2-5, the CPU on the adapter card is isolated from the host CPU. The PEX 8524 non-transparent port allows the two CPUs to be isolated but communicate with one another by way of various registers designed for that purpose. The host CPU can dynamically re-assign the Upstream port and non-transparent port, allowing system reconfiguration. Figure 2-5. Intelligent Adapter Usage Intelligent I/O Adapter I/O CPU CPU Blade PEX 8524 I/O NTB I/O I/O I/O 2.2.5 PEX 8532 PCI Express Port Expansion The PEX 8524 enables, for example, two x8 PCI Express ports to be expanded into ten ports. Certain PCI Express ports can be bridged to PCI or PCI-X using bridging products from PLX. Figure 2-6 illustrates one of the many configurations the PEX 8524 supports. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 7 PEX 8524 Applications PLX Technology, Inc. Figure 2-6. PCI Express Port Expansion CPU Memory North Bridge USB GbE South bridge x8 HDD PCI x8 PEX 8524 x4 ports PEX 8111 x4 ports 2.2.6 PEX 8524 PR EL IM IN AR Y PEX 8114 Port Adapters The number and variety of PCI Express native-mode devices is rapidly growing. This makes it necessary to create multifunction and multi-port adapter cards with PCI Express capability. The PEX 8524 can be used to create an adapter or mezzanine card that aggregates the PCI Express devices into a single port that can be plugged into a backplane or motherboard. Figure 2-7 illustrates the PEX 8524 in this application. Figure 2-7. 4G FC PEx Adapter Cards x4 Device 4G FC PEx x4 Device PEx 4G FC Device x4 PEX PEX 8524 x4 4G FC PEx Device 2.2.7 x8 Software Usage Model From a system model viewpoint, each PCI Express port is a virtual PCI-to-PCI bridge device and retains its own set of PCI Express configuration registers. It is by way of the Upstream port that the BIOS or host can configure the other ports using standard PCI enumeration. The PEX 8524 virtual PCI-to-PCI bridges are compliant to the PCI and PCI Express system models. The Configuration Space Registers (CSRs) in a virtual primary/secondary PCI-to-PCI bridge are accessible by Type 0 Configuration cycles by way of the virtual primary bus interface (matching bus number, device number, and function number). 8 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 2.2.8 Interrupt Sources/Events Interrupt Sources/Events PR EL IM IN AR Y The ExpressLane PEX 8524 switch supports the INTx interrupt message type (compatible with PCI r2.3 Interrupt signals) or Message Signaled Interrupts (MSI) when enabled. Interrupts/messages are generated by the PEX 8524 for Hot Plug events, baseline error reporting, and advanced error reporting. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 9 PLX Technology, Inc. PR EL IM IN AR Y PEX 8524 Applications 10 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 3 3.1 Ball Description Introduction This section provides descriptions of the PEX 8524 signal balls. The signals are divided into seven groups: * PCI Express Signals * Hot Plug Signals * Serial EEPROM Signals * Strapping Signals * JTAG Signals * No Connect Signals * Power and Ground Signals The signal name, type, location, and a brief description are provided for each signal ball. 3.2 Abbreviations The following abbreviations are used in the signal tables provided in this chapter. Table 3-1. Ball Assignment Abbreviations Abbreviation Type # Description Active Low. APWR 1.0V Power (VDD10A) balls for SerDes Analog circuits. CPWR 1.0V Power (VDD10) balls for low-voltage Core circuits. GND I I/O I/OPWR Common Ground (VSS) for all circuits. Input (signals with weak internal pull-up resistors). Bi-Directional programmable signal (input or output). 3.3V Power (VDD33) balls for Input and Output interfaces. LVDSCLKn Differential low-voltage, high-speed, LVDS negative Clock Inputs. LVDSCLKp Differential low-voltage, high-speed, LVDS positive Clock Inputs. LVDSRn Differential low-voltage, high-speed, LVDS negative Receiver Inputs. LVDSRp Differential low-voltage, high-speed, LVDS positive Receiver Inputs. LVDSTn Differential low-voltage, high-speed, LVDS negative Transmitter Outputs. LVDSTp Differential low-voltage, high-speed, LVDS positive Transmitter Outputs. O PLLPWR Output. 3.3V Power (VDD33A) balls for PLL circuits. SerDes Differential low-voltage, high-speed, I/O signal pairs (negative and positive). SPWR 1.0V Power (VDD10S) balls for SerDes Digital circuits. STRAP Strapping balls must be connected to H or L on the card. TS Three-State (bi-directional I/O signal, or output that can be set to High-Impedance state). PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 11 Ball Description 3.3 PLX Technology, Inc. Packaging Information For the PEX 8524 mechanical specifications, including the physical layout, refer to Chapter 19, "Mechanical Specifications." 3.4 Internal Pull-Up Resistors Due to the weak value of internal pull-up resistors for the balls listed in Table 3-2, it is recommended that a 3K- and 10K-Ohm resistor be tied from each ball to VDD33. Table 3-2. Balls with Internal Pull-Up Resistors Signal Name HP_PRSNT[3:0]# HP_BUTTON[3:0]# EE_PR# HP_PRSNT[11:8]# HP_BUTTON[11:8]# JTAG_TDI HP_PWRFLT[3:0]# HP_MRL[3:0]# PR EL IM IN AR Y EE_DO JTAG_TMS HP_PWRFLT[11:8]# HP_MRL[11:8]# JTAG_TRST# 12 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Signals 3.5 PCI Express Signals The PCI Express SerDes and control signals are detailed in Table 3-3. Note: The ball numbers are ordered in sequence to follow the Signal Name sequencing [n to 0]. Table 3-3. PEX 8524 PCI Express Signals - 124 Balls Location Type Description PEX_PERn[7:0] AK18, AK16, AK14, AK12, AK10, AK8, AK6, AK4 LVDSRn Negative half of PCI Express receiver differential signal pairs for PEX 8524 Station 0. PEX_PERn[31:16] E34, E32, E30, E28, E26, E24, E22, E20, E18, E16, E14, E12, E10, E8, E6, E1 LVDSRn Negative half of PCI Express receiver differential signal pairs for PEX 8524 Station 1. PEX_PERp[7:0] AL18, AL16, AL14, AL12, AL10, AL8, AL6, AL4 LVDSRp Positive half of PCI Express receiver differential signal pairs for PEX 8524 Station 0. D34, D32, D30, D28, D26, D24, D22, D20, D18, D16, D14, D12, D10, D8, D6, D1 LVDSRp Positive half of PCI Express receiver differential signal pairs for PEX 8524 Station 1. AP18, AP16, AP14, AP12, AP10, AP8, AP6, AP4 LVDSTn Negative half of PCI Express transmitter differential signal pairs for PEX 8524 Station 0. A34, A32, A30, A28, A26, A24, A22, A20, A18, A16, A14, A12, A10, A8, A6, A4 LVDSTn Negative half of PCI Express transmitter differential signal pairs for PEX 8524 Station 1. AN18, AN16, AN14, AN12, AN10, AN8, AN6, AN4 LVDSTp Positive half of PCI Express transmitter differential signal pairs for PEX 8524 Station 0. B34, B32, B30, B28, B26, B24, B22, B20, B18, B16, B14, B12, B10, B8, B6, B4 LVDSTp Positive half of PCI Express transmitter differential signal pairs for PEX 8524 Station 1. PEX_REFCLKn AL1 LVDSCLKn Negative half of 100-MHz PCI Express reference clock input signal pair for PEX 8524. PEX_REFCLKp AL2 LVDSCLKp Positive half of 100-MHz PCI Express reference clock input signal pair for PEX 8524. AA3, Y3, W3, V3, U3, T3, R3, P3 O AB31, AA31, Y31, W31, V31, U31, T31, R31, P4, R4, T4, U4, V4, W4, Y4, AA4 O PEX_PERST# H1 I Used to Cause a Fundamental Reset. (Refer to Chapter 5, "Reset and Initialization" for further details.) PEX_NT_RESET# J1 O Active-Low Output Used to Propagate Reset in NT Mode. PEX_PERp[31:16] PEX_PETn[7:0] PEX_PETn[31:16] PEX_PETp[7:0] PEX_PETp[31:16] PR EL IM IN AR Y Signal Name PEX_LANE_GOOD[7:0]# PEX_LANE_GOOD[31:16]# Active-Low PCI Express Lane Status Indicator Output for Lanes [7:0] and [31:16]. These signal balls can directly drive common-anode LED modules. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 13 Ball Description 3.6 PLX Technology, Inc. Hot Plug Signals The PEX 8532 includes nine Hot Plug signals for each PCI Express port, which totals 54 Hot Plug signals (6 ports * 9 signals/port). These signals are active only for ports that are configured at start-up. The Hot Plug signals are detailed in Table 3-4. Table 3-4. PEX 8524 Hot Plug Signals - 72Balls Location Type HP_ATNLED[3:0]# K34, W34, L1, Y1 O Hot Plug Attention LED Outputs for Station 0 Ports. Active-Low Slot Control Logic output used to drive the Attention Indicator. These outputs are set low to illuminate the indicator. HP_ATNLED[11:8]# AE33, T33, AF2, U2 O Hot Plug Attention LED Outputs for Station 1 Ports. Active-Low Slot Control Logic output used to drive the Attention Indicator. These outputs are set low to illuminate the indicator. HP_BUTTON[3:0]# HP_BUTTON[11:8]# HP_CLKEN[3:0]# HP_CLKEN[11:8]# HP_MRL[3:0]# HP_MRL[11:8]# HP_PERST[3:0]# HP_PERST[11:8]# HP_PRSNT[3:0]# Description PR EL IM IN AR Y Signal Name J34, V34, K1, W1 Ia Hot Plug Attention Button Inputs for Station 0 Ports. Active-Low Slot Control Logic input directly connected to the Attention Button. AF33, U33, AG2, V2 Ia Hot Plug Attention Button Inputs for Station 1 Ports. Active-Low Slot Control Logic input directly connected to the Attention Button. U34, AF34, V1, AG1 O Reference Clock Enable Outputs for Station 0 Ports. V33, J33, W2, K2 O Reference Clock Enable Outputs for Station 1 Ports. L34, Y34, M1, AA1 Ia Hot Plug Manually Operated Retention Latch Sensor Inputs for Station 0 Ports. Active-Low Slot Control Logic and Power Controller input directly connected to the MRL Sensor. AD33, R33, AE2, T2 Ia Hot Plug Manually Operated Retention Latch Sensor Inputs for Station 1 Ports. Active-Low Slot Control Logic and Power Controller input directly connected to the MRL Sensor. R34, AD34, T1, AE1 O Active-Low Reset Outputs for Station 0 Ports. Y33, L33, AA2, M2 O Active-Low Reset Outputs for Station 1 Ports. Ia Combination of Hot Plug PRSNT1# and PRSNT2# Inputs for Station 0 Ports. Active-Low inputs connected to external logic that directly outputs PRSNT1# and PRSNT2# from the slot's PRSNT1# and PRSNT2# signals. P34, AC34, R1, AD1 HP_PRSNT[11:8]# AA33, M33, AB2, N2 Ia Combination of Hot Plug PRSNT1# and PRSNT2# Inputs for Station 1 Ports. Active-Low inputs connected to external logic that directly outputs PRSNT1# and PRSNT2# from the slot's PRSNT1# and PRSNT2# signals. HP_PWREN[3:0]# N34, AB34, P1, AC1 O Active-Low Hot Plug Power Enable Output for Station 0 Ports. A Slot Control Logic output that controls the slot power state. When this signal is low, power is enabled to the slot. 14 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Table 3-4. Hot Plug Signals PEX 8524 Hot Plug Signals - 72Balls (Cont.) Location Type Description HP_PWREN[11:8]# AB33, N33, AC2, P2 O Active-Low Hot Plug Power Enable Output for Station 1 Ports. A Slot Control Logic output that controls the slot power state. When this signal is low, power is enabled to the slot. HP_PWRFLT[3:0]# M34, AA34, N1, AB1 Ia Hot Plug Power Fault Input for Station 0 Ports. Active-Low input indicating that the slot power controller detected a power fault on one or more supply rails. HP_PWRFLT[11:8]# AC33, P33, AD2, R2 Ia Hot Plug Power Fault Input for Station 1 Ports. Active-Low input indicating that the slot power controller detected a power fault on one or more supply rails. HP_PWRLED[3:0]# T34, AE34, U1, AF1 O Hot Plug Power LED Output for Station 0 Ports. Active-Low Slot Control Logic output used to drive the Power Indicator. This output is set low to illuminate the indicator. HP_PWRLED[11:8]# Hot Plug Power LED Output for Station 1 Ports. Active-Low Slot Control Logic output used to drive the Power Indicator. This output is set low to illuminate the indicator. PR EL IM IN AR Y Signal Name W33, K33, Y2, L2 O a.When Hot Plug inputs are not used, pull-up to VDD33 with a resistor between 3K and 10K Ohms. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 15 Ball Description 3.7 PLX Technology, Inc. Serial EEPROM Signals The PEX 8524 includes five signals for interfacing to a serial EEPROM. These signals are detailed in Table 3-5. Table 3-5. PEX 8524 Serial EEPROM Signals - 5 Balls Location Type Description EE_CS# AG32 O Serial EEPROM Active-Low Chip Select Output. EE_DI AH34 O PEX 8524 Output to Serial EEPROM Data Input. EE_DO AG34 I PEX 8524 Input from Serial EEPROM Data Output. EE_PR# AH33 I Serial EEPROM Present Active-Low Input. Must be tied to VSS to indicate serial EEPROM presence. EE_SK AG33 O 7.8 MHz Serial EEPROM Clock Output. PR EL IM IN AR Y Signal Name 16 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 3.8 Strapping Signals Strapping Signals The PEX 8524 strapping signals set the configuration of Upstream and NT port assignment, port width, and various setup and test modes. These balls must be hardwired to H (VDD33) or L (VSS). Following a Fundamental Reset, ball status is captured in the Link Capabilities, Debug Control and Port Configuration registers. Strap ball Configuration data can be changed by writing new data to these registers from the Configuration serial EEPROM. Table 3-6. PEX 8524 Strapping Signals - 24 Balls Signal Name STRAP_FAST_BRINGUP# Type Description AH2 STRAP Used for simulation models and production test. Not relevant for functional usage. STRAP Mode Select balls. Register/Bits - Mode Select LL = Reserved LH = Intelligent Adapter mode HL = Dual-Host mode HH = Transparent mode (T mode) STRAP Select Non-Transparent Upstream Port. Register/Bits - NT Port Number LLLL = Port 0 LLLH = Port 1 LLHL to LHHH = Reserved HLLL = Port 8 HLLH = Port 9 HLHL = Port 10 HLHH = Port 11 HHLL to HHHH = Reserved If NT Port is not used, set to HHHH. STRAP Strapping Signals to Select Number of Lanes in Station 0, Port(s)[0, 1]. Register/Bits - Port Configuration Note: x0 means the port is not enabled. LLLLL = x4, x4 LLLHL = x8 All other configurations are Reserved H2, G1 PR EL IM IN AR Y STRAP_MODE_SEL[1:0] Location STRAP_NT_UPSTRM_PORT_SEL[3:0] STRAP_STN0_PORTCFG[4:0] M31, L31, L32, K32 AC32, AC31, AD32, AD31, AE32 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 17 Ball Description Table 3-6. PLX Technology, Inc. PEX 8524 Strapping Signals - 24 Balls (Cont.) Signal Name Location P31, N32, N31, M32 STRAP_STN1_ PORTCFG[3:0] H33, H34, G33, G34 STRAP_UPSTRM_PORT_SEL[3:0] 18 Description STRAP Strapping Signals to Select Number of Lanes in Station 0, Port(s)[8, 9, 10, 11]. Register/Bits - Port Configuration Note: x0 means the port is not enabled. LLLL = x4, x4, x4, x4 LLHL = x8, x8, x0, x0 LLHH = x8, x4, x4, x0 LHLL = x8, x4, x2, x2 LHLH = x8, x2, x2, x4 LHHL = x8, x2, x4, x2 All other configurations are Reserved STRAP Test Mode Select. Reserved for Factory testing. Register - Physical Layer Test HHHH = Default (Test Modes Disabled) STRAP Strapping Signals to Select Upstream Port. Register/Bits - Upstream Port Number LLLL = Port 0 LLLH = Port 1 LLHL to LHHH = Reserved HLLL = Port 8 HLLH = Port 9 HLHL = Port 10 HLHH = Port 11 HHLL to HHHH = Reserved PR EL IM IN AR Y STRAP_TEST_MODE[3:0] Type N4, M4, N3, M3 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 JTAG Signals 3.9 JTAG Signals The PEX 8524 includes five signals for performing JTAG boundary scan. These signals are detailed in Table 3-7. Table 3-7. PEX 8524 JTAG Signals-5 Balls Location Type JTAG_TCK J2 I JTAG_TDI K3 I PU JTAG Test Data Input. Used to input data into the TAP. JTAG_TDO J3 O JTAG Test Data Output. Used to transmit data from the TAP. JTAG_TMS JTAG_TRST# 3.10 J4 I PU JTAG Test Mode Select. When high, JTAG Test mode is enabled. K4 I PU JTAG Test Reset. Active-Low input used to reset the Test Access Port. Tie to ground through a 1.5K Ohm resistor to disable the TAP when not being used. Do not connect the following PEX 8524 balls to card electrical paths, as these balls are not connected within PEX 8524. PEX 8524 No Connect Signals-54 Balls Signal Name N/C JTAG Test Clock Input. JTAG Test Access Port (TAP) clock source. JTAG_TCK can be a frequency from 0 to 10 MHz. No Connect Signals Caution: Table 3-8. Description PR EL IM IN AR Y Signal Name Location Type AA32, AB3, AB32, AC3, AD3, AE3, AE31, AF3, AF31, AF32, AF4, AG3, AH32, AK20, AK22, AK24, AK26, AK28, AK30, AK32, AK34, AL20, AL22, AL24, AL26, AL28, AL30, AL32, AL34, AN20, AN22, AN24, AN26, AN28, AN30, AN32, AN34, AP20, AP22, AP24, AP26, AP28, AP30, AP32, AP34, G2, G32, H31, R32, T32, U32, V32, W32, Y32 Reserved Description No Connect. Do not connect these balls to card electrical paths. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 19 Ball Description 3.11 Table 3-9. PLX Technology, Inc. Power and Ground Signals PEX 8524 Power and Ground Signals-275 Balls Location Type AJ30, AK23, AP21, AP25, AP29, AP33, E9, E11, E13, E17, E19, E21, E25, E27, E29, F5, G5, G30, J30, K5, M5, M30, P30, T5, T30, V5, V30, AA5, AA30, AC5, AC30, AE5, AE30, AG5, AG30, AK9, AK11, AK13, AK17, AK19, AK21, AK25, AK27, AK29 CPWR 1.0V Power for Core Logic. VDD10A AJ5, AK7, AK15, E7, E15, E23, F30 APWR 1.0V Power for SerDes Analog Circuits. VDD10S B3, B5, B7, B9, B11, B13, B15, B17, B19, B21, B23, B25, B27, B29, B31, B33, C3, C7, C11, C15, C19, C23, C27, C31, D4, E5, E31, E33, F33, AJ33, AK5, AK31, AK33, AM3, AM7, AM11, AM15, AM19, AM23, AM27, AM31, AN3, AN5, AN7, AN9, AN11, AN13, AN15, AN17, AN19, AN21, AN23, AN25, AN27, AN29, AN31, AN33 SPWR H5, H32, K30, J31, J32, K31, L5, N5, N30, R5, U5, U30, Y5, Y30, AB5, AB30, AF5, AF30, AG31, AH1, AH30 I/OPWR 3.3V Power for I/O Logic Functions. AH5 PLLPWR 3.3V Power for PLL Circuits. AH4 PLL_GND PLL Ground Connection. A3, A7, A11, A15, A19, A23, A27, A31, C1, C2, C4, C5, C6, C8, C9, C10, C12, C13, C14, C16, C17, C18, C20, C21, C22, C24, C25, C26, C28, C29, C30, C32, C33, C34, D2, D5, D7, D9, D11, D13, D15, D17, D19, D21, D23, D25, D27, D29, D31, D33, E2, E4, F1, F2, F4, F31, F32, F34, G4, G31, H30, J5, L30, P5, P32, R30, W5, W30, AD5, AD30, AG4, AH31, AJ1, AJ2, AJ3, AJ4, AJ31, AJ32, AJ34, AK1, AK2, AK3, AL3, AL5, AL7, AL9, AL11, AL13, AL15, AL17, AL19, AL21, AL23, AL25, AL27, AL29, AL31, AL33, AM1, AM2, AM4, AM5, AM6, AM8, AM9, AM10, AM12, AM13, AM14, AM16, AM17, AM18, AM20, AM21, AM22, AM24, AM25, AM26, AM28, AM29, AM30, AM32, AM33, AM34, AP3, AP7, AP11, AP15, AP19, AP23, AP27, AP31 GND VDD10 VDD33 VDD33A VSSA VSS 20 Description PR EL IM IN AR Y Signal Name 1.0V Power for SerDes Digital Circuits. Ground Connections. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Table 3-9. Power and Ground Signals PEX 8524 Power and Ground Signals-275 Balls (Cont.) Signal Name Location Type Description VTT_PEX[3:0] AP17, AP13, AP9, AP5 SerDes SerDes Termination for Station 0a. Tied to SerDes termination voltage (typically 1.5V). VTT_PEX[15:8] A33, A29, A25, A21, A17, A13, A9, A5 SerDes SerDes Termination for Station 1a. Tied to SerDes termination voltage (typically 1.5V). a.PEX_PETx SerDes termination voltage controls transmitter Common mode voltage (VTX - CM) value and output voltage swing (VTX - DIFFp), per the following formula: - DIFFp PR EL IM IN AR Y VTX-CM = VTT - VTX PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 21 PLX Technology, Inc. PR EL IM IN AR Y Ball Description 22 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 4 4.1 Functional Overview PEX 8524 Architecture The PEX 8524 switch is designed with a flexible, modular architecture. The two main building blocks of this architecture are the non-blocking Crossbar Switch fabric and protocol-specific input-output module termed Station. The PEX 8524 architecture is based on two PCI Express stations, connected by way of its non-blocking Crossbar Switch fabric. A block diagram of the PEX 8524 is illustrated in Figure 4-1. Figure 4-1. PEX 8524 Block Diagram Station 0 Station 1 Ingress Scheduler Lanes Port 0 Egress Scheduler Crossbar Switch Egress Crossbar Switch Ingress Non-Blocking Crossbar Switch Fabric PCI Express Upstream Station 0 Crossbar Switch Egress Egress Scheduler 4.1.1 Lanes PCI Express Downstream Station 1 Crossbar Switch Ingress Ingress Scheduler Ingress and Egress Functions The Crossbar Switch Ingress Q interfaces the PCI Express station to the Crossbar Switch Fabric. It contains a centralized packet buffer for incoming ports, ingress port scheduler, and Crossbar Switch Fabric scheduler. The Crossbar Switch Egress Q interfaces the non-blocking Crossbar Switch Fabric to the PCI Express station. It contains a centralized packet buffer for all outgoing ports and the Egress Port scheduler. All ingress traffic flows from the PCI Express station by way of the Crossbar Switch Ingress Q, Crossbar Switch fabric, Crossbar Switch Egress Q and finally to the outgoing PCI Express station. Ingress and Egress Scheduler modules contain a Virtual Channel (VC) scheduler for each port. The Ingress Scheduler supports a port-width-based arbitration scheme. The Egress Scheduler supports a device-specific port arbitration scheme, to avoid port starvation. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 23 Functional Overview 4.1.2 PLX Technology, Inc. Station and Port Functions The stations implement the PCI Express Base 1.0a Physical, Data Link, and Transaction layers. Each PCI Express station can support up to 16 integrated Serializer/De-serializer (SerDes) modules, which provide PCI Express hardware interface lanes. These lanes can be configured to support up to four PCI Express ports per station. The PEX 8524 contains two stations (Station 0 and Station 1), connected by non-blocking Crossbar Switch fabric. In Figure 4-1, Port 0 is configured as the Upstream port, and Station 0, which contains this port, is considered the Upstream station. Port 0 is delineated as a 4-lane port; however, it can be configured to other port widths, as delineated in Table 4-1. From the system model viewpoint, each PCI Express port is a virtual PCI-to-PCI bridge device and contains its own set of PCI Express Configuration registers. One of the ports on either station can be designated the Upstream port (or primary bus in PCI terms). It is by way of the Upstream port that the BIOS is used to configure the other ports during standard PCI enumeration. 4.1.2.1 PR EL IM IN AR Y Note: The PCI Express Upstream Station supports Upstream ports and Downstream ports at the same time, but lanes from different stations cannot be combined to form ports. Port Combinations The PEX 8524 contains two stations, whose ports can be configured as delineated in Table 4-1. Ports that are not configured/enabled are not visible to software. There are 8 lanes per Station, numbered 0-7 for Station 0 and 16-31 for Station 1. Configuration Code defines the levels set by Strapping Signals STRAP_STN0_PORTCFG[4:0] and STRAP_STN1_ PORTCFG[3:0]. Table 4-1. PEX 8524 Port Configurations Configuration Codea Station 0 (Lanes/ SerDes)/Portb Port 0 Port 1 0h x4 (0-3) x4 (4-7) 1h - 2h Configuration Codea Station 1 (Lanes/SerDes)/Portb Port 8 Port 9 Port 10 Port 11 0h x4 (16-19) x4 (20-23) x4 (24-27) x4 (28-31) - 1h - - - - x8 (0-7) - 2h x8 (16-23) x8 (24-31) - - 3h - - 3h x8 (16-23) x4 (24-27) x4 (28-31) - 4h - - 4h x8 (16-23) x4 (24-27) x2 (28-29) x2 (30-31) 5h - - 5h x8 (16-23) x2 (24-25) x2 (26-27) x4 (28-31) 6h - - 6h x8 (16-23) x2 (24-25) x4 (26-29) x2 (30-31) a.The PEX 8524 can be re-configured by link-width negotiation to smaller widths of 4, 2, or 1. b.The lanes are assigned to each enabled port in sequence, as shown in (parenthesis). 24 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Port Numbering The PEX 8524 supports a wide variety of configurations per station (as delineated in Table 4-1) and supports two stations and up to four ports per station, providing an extensive set of possible port/station configurations. The equivalent system model contains an Upstream port PCI-to-PCI bridge and seven Downstream port PCI-to-PCI bridges as delineated in Figure 4-2. The upstream station contains one upstream PCI-to-PCI bridge and up to three downstream PCI-to-PCI bridges; the downstream station contains up to four downstream PCI-to-PCI bridges. The upstream and downstream ports' lane width is initially set by the hardwired Strapping balls. (Refer to Section 3.8, "Strapping Signals.") The serial EEPROM option is used to reconfigure the ports by using the options delineated in Table 4-1. The serial EEPROM configuration occurs following fundamental reset, and overrides strapped ball configurations. (Refer to Section 5.2.3.5, "Setting Port Configuration Using Serial EEPROM.") PR EL IM IN AR Y The final port width can be changed by link-width negotiation when the ports are connected to external PCI Express ports. The narrowest of the two connected ports determines the final port width for both ends of the link. Note: P-P is used to represent PCI-to-PCI in the illustrations that follow. Figure 4-2. Equivalent System Model with Maximum Number of Ports and Lanes PCI Express x4 Upstream Port P-P Bridge Upstream Station P-P Downstream Port P-P Bridges Crossbar Switch Fabric P-P PCI Express x4 4.1.3 Downstream Station P-P P-P P-P P-P PCI PCI PCI PCI Express Express Express Express x4 x4 x4 x4 Port Numbering The PEX 8524 port numbers are 0, 1 (Station 0) and 8, 9, 10, 11 (Station 1), as delineated in Table 4-1. Port numbers 2, 3, 4, 5, 6, 7, and 12, 13, 14, 15 are reserved for future use. The port number and Device Number are the same (in the Type 1 Headers) that map to all ports, with an exception for a non-zero Upstream port. Any PEX 8524 port can be upstream. If Port 0 is the Upstream port, the Device Number matches and is 0 for this port, as illustrated in Figure 4-3. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 25 Functional Overview Figure 4-3. PLX Technology, Inc. PLX Port Numbering Convention Example (when Port 0 Is Upstream Port) Port/Device 0 (Upstream Port) Port/Device 1 PCI Express Upstream Station 0 Port 2 Port 3 Port 4 Port 5 Port/Device 8 Non-Blocking Crossbar Switch Fabric Port/Device 9 PCI Express Downstream Port/Device 10 Station 1 Port/Device 11 Reserved for Future Expansion Port 6 Port 12 Reserved Port 13 for Future Expansion Port 14 4.2 Port 15 PR EL IM IN AR Y Port 7 PCI-Compatible Software Model The PEX 8524 upstream PCI-to-PCI bridges are compliant with the PCI and PCI Express system model. The CSRs in the Upstream port PCI-to-PCI bridge are accessible by Type 0 Configuration cycles by way of the Upstream Bus interface (matching Bus, Device, and Function Numbers). The CSRs in the Downstream port PCI-to-PCI bridges are accessible by Type 1 Configuration cycles, by way of the Upstream Bus interface. A bridge forwards Configuration cycles from its Upstream Bus Interface downstream, when the Configuration cycle targets one of its subordinate buses. That is, the Bus Number is within the range specified by the Secondary Bus Number register and the bridge Subordinate Bus Number registers. Routing tables are used to make routing decisions for Memory or I/O, and completions received by the switch. To simplify routing decisions for Memory or I/O requests and completions, the PEX 8524 includes Vendor-Specific Routing tables. The tables are transparently and automatically updated by way of corresponding Type 0 Configuration cycles to the Base and Limit registers and Secondary and Subordinate Bus Number registers of the virtual secondary PCI-to-PCI bridges. 4.2.1 System Reset There are four reset sources: * Fundamental Reset input by way of the PEX_PERST# signal * Reset propagates from upstream by virtue of the Physical Layer mechanism, which communicates a reset by way of a training sequence (TS1/TS2 Ordered Set Hot Reset or Disable Link bit is set) * PCI Express link enters the DL_Down state on the Upstream port * Bridge-Control register Secondary Bus Reset bit of an Upstream or Downstream port PCI-to-PCI bridge is set Reset is propagated from upstream to downstream. Reset is propagated to the downstream PCI Express device by way of the PCI Express link with the physical layer mechanism (Training Order Reset bit is set) or with the link entering DL_Down state. An example of reset propagation is illustrated in Figure 4-4. Upon receiving a reset from the upstream PCI Express link, the Upstream port PCI-to-PCI bridge propagates the reset to the Downstream port PCI-to-PCI bridges in the upstream station, as well as to the Downstream port PCI-to-PCI bridges in its downstream station. 26 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Interrupts Figure 4-4. PEX 8524 System Reset Propagation Reset Propagation Upstream Port P-P Bridge P-P Downstream Port P-P Bridges P-P P-P Upstream Station P-P P-P Downstream Station Interrupts PR EL IM IN AR Y 4.2.2 P-P Generated interrupts are INTx interrupt message type (compatible with the PCI r2.3 Interrupt signals) or Message Signaled Interrupts (MSI), when enabled. (Refer to Message Signaled Interrupt Control register.) 4.2.2.1 Interrupt Sources or Events The source of the PEX 8524 generated interrupts/messages is as follows: * Hot Plug events * Device-specific error 4.2.2.2 INTx Switch Mapping The PEX 8524 collapses and re-maps the INTx "virtual wires" for its downstream links. Each virtual PCI-to-PCI bridge of a Downstream port specifies the port number associated INTx (interrupt) messages it receives or generates and forwards them in the upstream direction. 4.3 PCI Express Station Functional Description The PEX 8524 stations contain 16 transmit/receive (Tx/Rx) pairs of PCI Express SerDes I/O modules, offering up to four configurable PCI Express ports that scale from x1 to x8 in lane width, as delineated in Table 4-1. Each station implements the PCI Express PHY and DLL layer functions for each of its ports and aggregates traffic from these ports on to a transaction-based Non-blocking Crossbar Switch interface. The PCI Express station also performs many Transaction Layer functions, while the packet queuing and ordering aspects of this layer are handled by the Crossbar Switch Control blocks. During system initialization, by way of the Upstream port, software initiates Configuration transactions that setup the PCI Express Buses, Device Numbers, and address maps across the various ports. These maps are used to direct traffic between ports during normal system operation. Because a PCI Express station can contain multiple ports (one upstream and multiple downstream), traffic can flow between different ports of the same station, or ports on both stations as supported by the central Crossbar Switch fabric. At the top-level, the PCI Express Station contains a layered organization consisting of the Physical Layer (PHY), Data Link Layer (DLL), and Transaction Layer Control (TLC) blocks, as illustrated in Figure 4-5. The PHY and DLL blocks include four nearly identical port-specific datapaths (one per PCI Express port) that operate independently of one another. The Transaction Layer Control blocks manage traffic belonging to up to four active ports. The TLC processes aggregate traffic and passes it to the Crossbar switch that connects to the destination station by way of the non-blocking Crossbar Switch fabric. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 27 Functional Overview PLX Technology, Inc. Figure 4-5. PCI Express Station Block Diagram Non-Blocking Crossbar Switch Fabric Transaction Layer Control TLC Ingress TLC Egress CSR Handling Ingress Credit Unit Egress Credit Unit PR EL IM IN AR Y Data Link Layer DLL Ingress 0-3 DLL Egress 0-3 Physical Layer Port Receive Logic Port Enum. Logic Link Receive and Transmit Logic Serial Lanes 28 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 4.3.1 Physical Layer Physical Layer This module interfaces to the PCI Express lanes and implements the PHY Layer functions. The number of ports per station can vary from 1-to-4 with a cumulative lane-bandwidth of x8. When there are fewer than four configured/enabled ports, the x8 bandwidth is shared by the remaining active ports, as delineated in Table 4-1. PHY Layer functions include: * Establishing port configurations and SerDes to port assignments * Establishing internal bandwidth division among ports * Supporting cross-linked upstream and Downstream ports * 8b/10b encoding/decoding * Data scrambling/unscrambling * Packet framing * Loopback master and slave support PR EL IM IN AR Y * PRBS data generation and checking * User-defined test pattern with SKP OS insertion and return data checking * Driver and input buffers * Parallel-to-serial and serial-to-parallel conversion * PLLs and clock circuitry * Impedance matching circuitry * Interface initialization and maintenance functions 4.3.1.1 Hardware Link Interface Configuration The PEX 8524 Physical Layer ports can contain up to 16 integrated Serializer/De-serializer (SerDes) modules, which provide the PCI Express hardware interface lanes. The SerDes modules provide all physical communication controls and functions required by the PCI Express Base 1.0a. SerDes modules are clustered into ports, to provide the links that connect to other PCI Express devices. 4.3.1.2 Physical Layer Control and Status Registers The Physical Layer operating conditions are defined in the Physical Layer Registers. The system host can keep track of the various link operating status, and reconfigure the link parameters by way of these registers. 4.3.2 Data Link Layer The Data Link Layer (DLL) primary responsibilities include link management and data integrity, including error detection and correction. The transmission side of the DLL accepts TLPs assembled by the Transaction Layer, applies a TLP sequence number and calculates and applies a a 32-bit Link CRC DWord (LCRC), which is appended to the combined field. The combined Link Packet is submitted to the Physical Layer for transmission across the Link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and submitting them to the Transaction Layer for further processing. On detection of TLP error(s), this Layer is responsible for requesting retransmission of TLPs until information is correctly received, or the Link is determined to have failed. 4.3.2.1 Data Link Layer Packet (DLLP) The Data Link Layer also generates and consumes packets used for Link management functions. To differentiate these packets from those used by the Transaction Layer (TLP), the term Data Link Layer Packet (DLLP) is used when referring to packets that are generated and consumed at the Data Link Layer. The rules governing the identification and formation of these packets is defined in the PCI Express Base 1.0a, Section 3.4.1. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 29 Functional Overview 4.3.2.2 PLX Technology, Inc. Flow-Control Credits The initial number of flow-control credits for Virtual Channel 0 advertised is listed in Section 8.4.2.1, "Ingress Side." The flow-control credits are also programmable through the serial EEPROM. The Transaction Layer must schedule an Update FC DLLP for transmission to replenish the number of advertised credits or to meet an updated VC timer. When enabled, the Transaction Layer initiates flowcredit initialization for VC1, following VC0 initialization. 4.3.2.3 Packet Arbiter The packet arbiter logic decides what packet type is to be transmitted on a per-port basis and arbitrates between the DLLPs and TLPs. The priority implemented by the packet arbiter is as specified in the PCI Express Base 1.0a, Section 3.5.2.1. 4.3.3 Transaction Layer PR EL IM IN AR Y The Transaction Layer primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer is also responsible for managing credit-based flow control for TLPs. The Transaction Layer supports four address spaces, as delineated in Table 4-2. Table 4-2. Address Spaces Support Different Transaction Types Address Space Transaction Types Configuration Read/Write Device configuration or setup. Transaction Functions Input/Output Read/Write Transfer data from/to an I/O-mapped location. Memory Read/Write Transfer data from/to a memory location. Message Baseline/Virtual Wires General-purpose messages. Event signaling (such as status, interrupts, and so forth). Message space is added to Conventional PCI spaces, and used to support all prior sideband signals such as interrupts, power management requests, and so forth. PCI Express Message transactions can be considered "virtual wires" that support "virtual pins." Request packets requiring a response packet are implemented as a Split transaction. Each packet contains a unique identifier that enables response packets to be directed to the correct originator. The packet format supports different forms of addressing depending on transaction type (Memory, I/O, Configuration, or Message). 30 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Transaction Layer Functions provided by the Transaction Layer include: * Decoding and checking incoming TLP * Memory-mapped CSR access * Checking the incoming packets for Malformed packets or Unsupported Requests (UR) * ECRC checking the incoming packets * Error signaling for incoming packets * Destination lookup and TC-VC mapping * Virtual Channel Management * TLP packet scheduling * PCI/PCI-X-compatible ordering * QoS support * External Credit Control PR EL IM IN AR Y * Power Management support * Hot Plug support * Message Signal Interrupt or INTx generation 4.3.3.1 Transaction Layer Receive/Ingress Protocol The ingress side Transaction Layer collects and stores inbound TLP traffic in virtual channel buffers. The incoming data is checked for ECRC errors, valid type field, length matching the Header "Transfer size" field, and other TLP-specific errors defined by the PCI Express Base 1.0a. When the data is without error, Header and Data Payload are forwarded to the source scheduler, to be routed to the switch outgoing port. 4.3.3.2 Transaction Layer Transmit/Egress Protocol The egress side Transaction Layer receives information from other switch ports and generates outbound requests and completion TLPs which it stores in Virtual Channel buffers. This layer assembles Transaction Layer packets which consist of identification Headers, Data Payloads, and ECRC. Details for these fields are defined in the PCI Express Base 1.0a, Section 2.2. The PEX 8524 implements an egress flow-control (FC) protocol that ensures it does not transmit a TLP over a link to a remote receiver unless the receiving device contains sufficient Virtual Channel (VC) buffer space to accommodate the packet. This flow control is automatically managed by the hardware and is transparent to software. Software is used only to enable additional buffers to supplement the initial default buffer assignment. 4.3.3.3 Virtual Channels and Traffic Classes The PEX 8524 supports two Virtual Channels (VC0 and VC1), and up to eight Traffic Classes (TC[7:0]). VC0 and TC0 are required by the PCI Express Base 1.0a, and configured at device start up. The second Virtual Channel (VC1) is enabled by the PEX 8524 default configuration procedure, but can be disabled by using serial EEPROM configuration to set the Extended VC Count bits to 000b. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 31 Functional Overview 4.4 PLX Technology, Inc. Non-Blocking Crossbar Switch Architecture The non-blocking Crossbar Switch is an on-chip interconnect switch-fabric module to link multiple stations. The physical topology of the Crossbar Switch interconnect is a Packet Beat-based internal fabric designed to simultaneously connect multiple on-chip logic stations. The Crossbar Switch protocol is sufficiently flexible and robust to support a variety of embedded system needs. The protocol is specifically designed to ease chip integration by strongly enforcing station boundaries and standardizing communication between stations. The Crossbar Switch architecture incorporates the following functions: * Multiple concurrent data transfers with maximum throughput * Global ordering within the switch * Internal credit guarantees packet forward progress once scheduled * Deadlock avoidance PR EL IM IN AR Y * Priority preemption * Two independent Virtual Channels (VCs) * PCI Express ordering rules * Packet fair queuing * Oldest first scheduling 4.4.1 Special PEX 8524 Relaxed Ordering The PEX 8524 switch does not support the TLP Optional Relaxed-Ordering bit as specified in the PCI Express Base 1.0a, Table 2-23. By default, all packets entering from a specific port are dispatched to their respective destinations based on strict ordering. However, to remove unnecessary head-of-line blocking caused by PCI ordering in applications where ordering is not important, the PEX 8524 offers a PLX-Specific Relaxed Ordering mode. (For details, refer to Section 8.3.2.3, "PLX-Specific Relaxed Ordering.") The ingress scheduler on a specific port (for a specific traffic class) picks packets without using ordering requirements and dispatches to the egress ports. Because the ingress ordering relaxation is completed on a Traffic Class (TC) basis (irrespective of the VC enabled), a special TC (such as TC 7) is used to enable special permissions on this TC. Once the packets reach the egress ports, strict ordering is used in these queues, irrespective of the bits set on the ingress port. 32 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 4.5 Non-Transparent Bridging Implementation Non-Transparent Bridging Implementation The PEX 8524 product family supports non-transparent bridge functionality, which is used to implement high-availability systems or intelligent I/O modules using PCI Express technology. The following discusses the basic non-transparent bridging concept, as it applies to a PCI Express system. Non-Transparent (NT) bridges allow systems to isolate address spaces by appearing as an endpoint to the Host. A non-transparent bridge exposes a Type 0 CSR header and forwards transactions from one domain to the other with address translation. A non-transparent bridge is used to connect two independent address/host domains. It includes Doorbell registers to transmit interrupts from one side of the bridge to the other. It also maintains Scratchpad registers accessible from both domains for inter-host communications. The PEX 8524 PCI Express Switch, with a single port configured to operate in NonTransparent Bridge mode, supports two system models: * Intelligent Adapter Mode PR EL IM IN AR Y * Dual-Host Mode The PEX 8524 switch initial operating mode is determined by the STRAP_MODE_SEL[1:0] balls. The mode can later be changed by the configuration serial EEPROM by writing to the Mode Select register/bits. 4.5.1 Intelligent Adapter Mode The use of non-transparent bridges in PCI systems is well established for supporting intelligent adapters in enterprise and multi-host systems. This same concept is used in PCI Express bridges and switches. In Figure 4-6, there are two Type 0 CSR headers in the non-transparent PCI-to-PCI bridge. The one nearer the PCI Express link is referred to as the "Link Interface." The one nearer the internal virtual bus is referred to as the "Virtual Interface." In Intelligent Adapter mode, the NT Port Link Interface is connected to the System domain. System host manages only the NT Port Link Interface Type 0 function. The Local host manages all PEX 8524 Transparent Port Type 1 and NT Port Virtual Interface Type 0 functions. Cross-domain traffic is routed through an address translation mechanism. (Refer to Section 11.1.6, "Address Translation.") After power-up, the PEX 8524 transparent Type 1 ports, including the NT Port Virtual Interface, are enumerated by the Local Host connected to PEX 8524 Upstream port. The Local Host enables/ resizes the BARs by programming the NT Port Link Interface BAR Setup/Limit registers, before the System Host assigns resources for these BARs. This behavior is changed with serial EEPROM initialization. After the Local Host finishes its enumeration, it enables the NT Port Link Interface to be enumerated by the System Host connected to the NT Port Link Interface. The NT Port Link Interface Retries the System Host Configuration transaction until the Local Host enables the NT Port Link Interface to process the System Host Configuration transaction. The Link Interface Access Enable bit (register 1DCh[29]) enables access to the Link Interface Configuration registers and the Virtual Interface Access Enable bit (register 1DCh[28]) enables access to the Virtual Interface Configuration registers. These bits do not affect normal Memory, Memory-Mapped CSRs, nor I/O-Mapped CSR transactions. Intelligent Adapter mode does not support host-failover applications. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 33 Functional Overview PLX Technology, Inc. Figure 4-6. PEX 8524 Intelligent Adapter Software Model Fabric/ System Host Local Host I/O Fabric PEX 8524 Upstream Port Link Interface Primary P-P Bridge CSR BAR Transparent P-P Bridge Upstream Port CSR / BAR Non-Transparent P-P Bridge Addr Translation PR EL IM IN AR Y CSR / BAR Virtual Interface Transparent P-P Bridges P-P P-P P-P Downstream Ports 4.5.2 Dual-Host Mode The PEX 8524 transparent Upstream port is connected to the active host and the NT Port Link Interface is connected to the Backup Host. After power-up, the Active and Backup Hosts can enumerate their domain at the same time, which is modified using the serial EEPROM. The serial EEPROM is necessary to enable or resize the BAR Setup/Limit registers. Dual-Host mode supports host-failover applications. Figure 4-7. I n t e l l i g e n t I/ O A d a p t e r CPU I/ O Dual-Host Model B ackUp CPU CPU B la d e A c t iv e CCPPUU B la d e PEX 8516 I/ O NT I /O I/ O NT I/O PE X 8524 N o n -T ra n s p a re n t P o rt 34 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 4.5.2.1 Dual-Host Mode Host-Failover Application The host-failover application is based on the basic dual-host configuration. The active host periodically transmits heartbeat messages by way of the switch to the Backup Host to state it remains active. When the Backup Host fails to receive heartbeat messages before the fail-detect timer expires, it starts the failover process. The Backup Host halts cross-domain traffic before it starts the failover. The Backup Host uses the Memory-Mapped access to the Configuration register to execute the failover. The Backup Host follows the ensuing procedure to take control: 1. Failover Detected. 2. Upstream Port Demotion. 3. NT Port (Self) Promotion as a New Upstream Port. PR EL IM IN AR Y Refer to Section 12.2.4, "Host-Failover Application," for further details. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 35 PLX Technology, Inc. PR EL IM IN AR Y Functional Overview 36 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 5 5.1 Reset and Initialization Reset Overview Reset is a mechanism that returns a device to its initial state. Hardware or software mechanisms can trigger a reset. The reinitialized states following a reset vary depending on the reset type and condition. The PCI Express Base 1.0a, Section 6.6 defines the hardware mechanism as a "Fundamental Reset." There are two actions that can trigger a Fundamental Reset: * Cold Reset * Warm Reset There is also a type of reset triggered by an in-band signal from an upstream PCI Express link to all of its Downstream ports. This reset is termed a Hot Reset. On exit from a Cold or Warm Reset, all port configuration, port registers and state machines are set to initial (start up) values as specified in Section 5.2, "Initialization Procedure." 5.1.1 Cold Reset A Cold Reset is a Fundamental Reset which occurs following a proper PEX 8524 power on. When the PEX_PERST# signal is held low following the proper application of power to the component, a Fundamental Reset occurs. A Fundamental Reset initializes PEX 8524 components, such as configuration information, clocks, state machines, registers, and so forth. When power is removed from the device, or the power travels outside of the required ranges, all settings and configuration information is lost. The device must cycle through the entire Initialization Procedure after power is accurately reapplied. 5.1.2 Warm Reset The Fundamental Reset mechanism can also be triggered by driving PEX 8524 hardware reset signal (PEX_PERST#) low, without the removal and re-application (recycling) of power. This is considered a Warm Reset. This signal can be controlled by on-card toggle switches or other external hardware resets to the device. The device must cycle through the entire Initialization Procedure after the PEX_PERST# input signal is returned to high. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 37 Reset and Initialization 5.1.3 PLX Technology, Inc. Hot Reset A Hot Reset, triggered by an in-band signal from an upstream PCI Express link to all Downstream ports, causes all ports that are downstream from the initiating port to set their registers and state machines to initial values. This type of reset does not require power cycling, nor does it cause PEX 8524 port reconfiguration. This is equivalent to a traditional Software Reset. In the following, the terms virtual PCI-to-PCI bridge and port refer to a given Station port. A Hot Reset is triggered by the following: * Physical layer (at the Upstream port) receives a reset through a training sequence leading to a Hot Reset * Upstream PCI Express port enters the DL_Inactive state, which has the same effect as a Hot Reset Hot Reset Propagation PR EL IM IN AR Y 5.1.3.1 Reset is propagated to a downstream PCI Express device through the PCI Express link, using the physical layer Hot Reset mechanism (that is, a Reset bit in the training ordered-set from the upstream device is set). PCI Express views a "switch" as a hierarchy of virtual PCI-to-PCI bridges. An example of reset propagation across the PEX 8524 switch is illustrated in Figure 5-1. On receiving a Hot Reset from the upstream PCI Express link, the virtual primary PCI-to-PCI bridge propagates the reset to virtual secondary PCI-to-PCI bridges in the upstream and downstream stations. Each virtual secondary PCI-to-PCI bridge propagates the reset to its downstream links, and initializes its internal states to initial/default conditions. Note that the clock logic, port configuration, and sticky register bits are not impacted by a Hot Reset. Figure 5-1. 5.1.3.2 PEX 8524 System Reset Propagation Hot Reset Disable Reset Propagation Upstream Port Upstream P-P Bridge Downstream P-P Bridges P-P P-P P-P P-P P-P P-P Downstream Ports Upstream Station Downstream Station The PEX 8524 contains a configuration option (Port 0, Offset 1DCh[20]) to ignore the Hot Reset sequence from the upstream PCI Express link. Enabling this bit prevents the switch from propagating a reset to the Downstream ports. The Upstream port ignores the Hot Reset training sequence. There is a resulting DL_Down event on the Upstream port; however, this does not manifest as an internal reset in the device and the state of all configuration registers remain intact. 38 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 5.1.4 Secondary Bus Reset Secondary Bus Reset When the upstream PCI-to-PCI bridge Bridge Control and Interrupt Signal register (BCR) Secondary Bus Reset bit is set to 1b, all ports that are downstream from that port are reset to their initial/default states. The Downstream ports propagate an in-band Hot Reset to their respective downstream links. In addition, the Downstream ports' CSRs are re-initialized. The upstream PCI-to-PCI bridge (Upstream port) with its CSRs are not affected, but the queues to/from all Downstream ports are drained because their upstream to downstream virtual connections are re-initialized. When the downstream PCI-to-PCI bridge Bridge Control and Interrupt Signal register (BCR) Secondary Bus Reset bit is set to 1b, a Hot Reset is transmitted to its Downstream ports, which resets all devices downstream from that port to their initial/default states. All other PEX 8524 ports consistently re-initialize queues and credit information corresponding to traffic to/from the affected Downstream port. 5.2 PR EL IM IN AR Y The downstream links are held in reset until software removes the condition by clearing the BCR's Secondary Bus Reset bit. The PHY layer of the Downstream port in question propagates the reset condition in-band to its downstream link, and remains in the Hot Reset state until the reset condition (BCR) is cleared. The Transaction Layer draining of non-empty queues to/from the affected port(s) is handled in a fashion similar to the case of that port proceeding to the DL_Inactive state, as defined in the PCI Express Base 1.0a, Section 2.9. Initialization Procedure Upon exit from a Fundamental Reset, the PEX 8524 initialization process is started. There are two or three steps in the process, depending on the availability of an external initialization serial EEPROM: 1. PEX 8524 reads the Strapping signal balls to determine system mode, Upstream port, and lane configuration of all ports. 2. If a serial EEPROM is present (EE_PR# ball is low), the serial EEPROM data is downloaded to PEX 8524 Configuration registers. The configuration from the strapping signal balls can be changed by serial EEPROM data. 3. After the configuration from the Strapping signal balls and serial EEPROM completes, the Physical Layer of the configured ports attempts to bring up the Links. After both components on a Link enter the initial Link Training state, they proceed through Physical-Layer Link initialization and then through Flow Control initialization for VC0, preparing the Data Link and Transaction Layers to use the Link. Following Flow Control initialization for VC0, it is possible for Transaction Layer Packets (TLPs) and Data Link Layer packets (DLLPs) to be transferred across the Link. The final port widths and frequency of operation are determined during the training sequence with the attached ports. The ports can maintain fewer lanes than originally set by strapping or the serial EEPROM; however, they cannot be wider. The narrowest port on each link sets that port's final lane width. 5.2.1 Default Port Configuration The default Upstream port selection and overall port lane-width configuration is determined by the Strapping signal ball levels. All strapping balls must be tied to VDD33 or VSS, which sets the default device configuration. (Refer to Section 3.8, "Strapping Signals.") Some of these settings can be changed by downloading serial EEPROM data, or through initial port negotiation. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 39 Reset and Initialization 5.2.2 PLX Technology, Inc. Default Register Initialization The PEX 8524 ports defined in the port configuration process contain a set of assigned registers that control port activities and status during normal operation. These registers are set to default/initial settings as defined in Chapter 10, "PEX 8524 Port Registers." Following a Fundamental Reset, the basic PCI Express Support registers are initially set to the values specified in the PCI Express Base 1.0a. The PLX-specific values are specified in their register description tables. These registers can be changed by loading new data with the attached serial EEPROM, or by way of the Transaction Layer communication processes. The PEX 8524 supports two methods for accessing registers, as described in the following sections: * PCI Express Base 1.0a Configuration Mechanism * PLX-Specific Memory-Mapped Configuration Space Access Mechanism Serial EEPROM Initialization PR EL IM IN AR Y 5.2.3 The on-chip serial EEPROM controller is contained in PEX 8524 Station_0 as illustrated in Figure 5-2. The controller performs a serial EEPROM download when a serial EEPROM is present, as indicated by the EE_PR# Strapping ball = low, and one of the following occurs: * PEX_PERST# is returned high, following a Fundamental Reset (such as, a Cold or Warm Reset) * Hot Reset is received at the Upstream port (downloading upon this event can be optionally disabled) * Upstream port exits a DL-Down condition (downloading upon this event can be optionally disabled) Figure 5-2. PEX 8524 Serial EEPROM Connections PEX 8524 EE_CS# EE_DI Initialization Serial EEPROM EE_DO EE_SK Serial EEPROM Controller Station 0 Station 1 Configuration Data EE_PR# Port 0 40 Port 1 Port 8 Port 9 Port 10 Port 11 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 5.2.3.1 Serial EEPROM Initialization Configuration Data Download The serial data is downloaded from the serial EEPROM and converted to parallel data which is then routed to the PEX 8524 ports. The serial EEPROM controller generates a 7.8-MHz EE_SK signal and reads a total of 3044 DWords from the serial EEPROM, which represents all necessary data to initialize the PEX 8524 registers. The serial EEPROM memory map reflects the basic device register map discussed in Chapter 10, "PEX 8524 Port Registers." Because these registers are duplicated for each port, the serial EEPROM data starts with Station_0, Port_0, Register 00h, and progresses through the registers for all eight Ports in sequence. Certain general device registers are appended at the end of the space for Port 0, and various address space is skipped due to unused/Reserved register space. A detailed description of the serial EEPROM memory map is discussed in Appendix A, "Serial EEPROM Memory Map." While downloading data, the PEX 8524 generates a CRC value from the read data. When the serial EEPROM download is completed, the generated CRC value is compared to a CRC value stored in the last DWord location of serial EEPROM. PR EL IM IN AR Y If the CRC values match, the PEX 8524 sets the EEPROM Status and Control register EEPROM Present bits [17:16] to 01b (serial EEPROM download complete and serial EEPROM CRC check is validated). If the CRC check fails, all port registers are reset/initialized to default values, the serial EEPROM download complete bit is set, and the EEPROM Status and Control register EEPROM Present check bits [17:16] are set to 11b to indicate failure. During the serial EEPROM download, the Class Code 060400h is monitored. If the correct code is not found, the download is terminated. Note: It is the system software's responsibility to verify that the serial EEPROM download completes without error. 5.2.3.2 PCI Express Configuration, Control, and Status Registers The PCI Express Configuration, Control, and Status registers that can be initialized are discussed in the following sections. However, this is not a complete list of programmable registers. For a complete list, refer to Appendix A, "Serial EEPROM Memory Map." * Section 5.2.3.3, "Selecting Configuration Values Using Serial EEPROM" * Section 5.2.3.4, "Selecting Upstream Port Using Serial EEPROM" * Section 5.2.3.5, "Setting Port Configuration Using Serial EEPROM" * Section 5.2.3.6, "Power Management Parameters Using Serial EEPROM" * Section 5.2.3.7, "Message Signaled Interrupt Capabilities Using Serial EEPROM" * Section 5.2.3.8, "PCI Express Capabilities Using Serial EEPROM" * Section 5.2.3.9, "Device Serial Number Extended Capabilities Using Serial EEPROM" * Section 5.2.3.10, "Device Power Budgeting Extended Capabilities Using Serial EEPROM" * Section 5.2.3.11, "Virtual Channel Extended Capabilities Using Serial EEPROM" * Advanced Error Reporting Capability PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 41 Reset and Initialization 5.2.3.3 PLX Technology, Inc. Selecting Configuration Values Using Serial EEPROM All Configuration values delineated in Table 5-1 can be changed using the serial EEPROM, with the exception of those fixed by the PCI Express Base 1.0a, or not supported by the PEX 8524. (Refer to Section 10.6, "Configuration Header Registers," for detailed register descriptions.) Table 5-1. Type 1 Configuration Space Header Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEVICE ID VENDOR ID 00h Status Bits Command Bit(s) 04h Class Code PRIMARY LATENCY TIMER HEADER TYPE SECONDARY LATENCY TIMER 08h CACHE LINE SIZE 0Ch Base Address 0 10h Base Address 1 14h PR EL IM IN AR Y BIST REVISION ID Subordinate Bus Number Secondary Bus Number PRIMARY Bus Number 18h I/O Limit I/O Base 1Ch Secondary Status Memory Limit Address[31:20] Memory Base Address[31:20] 20h Prefetchable Memory Limit Address[31:20] Prefetchable Memory Base Address[63:32] 24h Prefetchable Memory Upper Base Address[63:32] 28h Prefetchable Memory Upper Limit Address[63:32] 2Ch I/O Base Upper 16 Bits I/O Limit Upper 16 Bits Reserved Capability Pointer Expansion ROM Base Address Bridge Control and Interrupt Signal 5.2.3.4 Interrupt Pin 30h 34h 38h Interrupt Line 3Ch Selecting Upstream Port Using Serial EEPROM The Debug Control register Upstream Port Number bits [11:8] determine the Upstream Port selection for the PCI Express station containing the register. Station 0 LOAD_UPSTREAM_PORT_ID[11:8] 0000b = Port 0 0001b = Port 1 0010b to 0111b = Reserved Station 1 LOAD_UPSTREAM_PORT_ID[11:8] 1000b = Port 8 1001b = Port 9 1010b = Port 10 1011b = Port 11 1100b to 1111b = Reserved Note: Bit 12 is set to 0b and is considered Reserved. 42 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Serial EEPROM Initialization 5.2.3.5 Setting Port Configuration Using Serial EEPROM To use the serial EEPROM to set the port configuration, the following registers must be programmed on a per station basis (each station retains its own copy of these registers): * Port Configuration register sets the port configuration * Debug Control register sets the port number and parameters for the Upstream port The Port Configuration register determines the port configuration for the PCI Express station that contains the register. The register contains a 4-bit field that sets the number of lanes per port, as delineated in Table 5-2. PEX 8524 Port Configurations Configuration Codea 0h 1h 2h 3h 4h 5h 6h Station 0 (Lanes/ SerDes)/Portb Station 1 (Lanes/SerDes)/Portb Configuration Codea PR EL IM IN AR Y Table 5-2. Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 x4 (0-3) x4 (4-7) 0h x4 (16-19) x4 (20-23) x4 (24-27) x4 (28-31) - - 1h - - - - x8 (0-7) - 2h x8 (16-23) x8 (24-31) - - - - 3h x8 (16-23) x4 (24-27) x4 (28-31) - - - 4h x8 (16-23) x4 (24-27) x2 (28-29) x2 (30-31) - - 5h x8 (16-23) x2 (24-25) x2 (26-27) x4 (28-31) - - 6h x8 (16-23) x2 (24-25) x4 (26-29) x2 (30-31) a.The PEX 8524 can be re-configured by link-width negotiation to smaller widths of 4, 2, or 1. b.The lanes are assigned to each enabled port in sequence, as shown in (parenthesis). 5.2.3.6 Power Management Parameters Using Serial EEPROM All Power Management parameters delineated in Table 5-3 can be changed using the serial EEPROM, with the exception of those fixed by PCI Express Base 1.0a or those not supported by the PEX 8524. (Refer to Section 10.7, "Power Management Capability Registers," for detailed register descriptions.) Table 5-3. Power Management Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Power Management Capability Data PM Control/Status Bridge Extensions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEXT POINTER CAPABILITIES ID Power Management Status and Control PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 40h 44h 43 Reset and Initialization 5.2.3.7 PLX Technology, Inc. Message Signaled Interrupt Capabilities Using Serial EEPROM All Message Signaled Interrupt (MSI) capabilities parameters delineated in Table 5-4 can be changed using the serial EEPROM, with the exception of those fixed by PCI Express Base 1.0a or those not supported by the PEX 8524. (Refer to Section 10.8, "Message Signaled Interrupt Capability Registers," for detailed register descriptions.) Table 5-4. Message Signaled Interrupt Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEXT CAPABILITY POINTER Message Signaled Interrupt Control 48h Lower Message Address[31:0] 4Ch Upper Message Address[63:32] 50h Message Data PR EL IM IN AR Y Reserved 5.2.3.8 CAPABILITY ID 54h PCI Express Capabilities Using Serial EEPROM All PCI Express Capabilities parameters delineated in Table 5-5 can be changed using the serial EEPROM, with the exception of those fixed by PCI Express Base 1.0a or those not supported by the PEX 8524. (Refer to Section 10.9, "PCI Express Capabilities Registers," for detailed register descriptions.) Table 5-5. PCI Express Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEXT CAPABILITY POINTER PCI Express Capabilities CAPABILITY ID Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control Slot Capabilities Slot Status 5.2.3.9 68h 6Ch 70h 74h 78h 7Ch Slot Control 80h Device Serial Number Extended Capabilities Using Serial EEPROM All Device Serial Number Extended Capabilities registers delineated in Table 5-6 can be modified using the serial EEPROM. (Refer to Section 10.10, "Device Serial Number Extended Capability Registers," for detailed register descriptions.) Table 5-6. Device Serial Number Extended Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Next Capability Pointer 44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPABILITY VERSION EXTENDED CAPABILITY ID 100h Serial Number (Low) 104h Serial Number (High) 108h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 5.2.3.10 Serial EEPROM Initialization Device Power Budgeting Extended Capabilities Using Serial EEPROM All Device Power Budgeting Extended Capabilities registers delineated in Table 5-7 can be modified using the serial EEPROM. (Refer to Section 10.11, "Device Power Budgeting Extended Capability Registers," for detailed register descriptions.) Table 5-7. Device Power Budgeting Extended Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPABILITY VERSION NEXT CAPABILITY OFFSET EXTENDED CAPABILITY ID Reserved Data Select Power Data 13Ch 140h Power Budget Capability PR EL IM IN AR Y Reserved 5.2.3.11 138h 144h Virtual Channel Extended Capabilities Using Serial EEPROM The following sections detail the PEX 8524 Virtual Channel Extended Capabilities registers. The register map is delineated in Table 5-8, with Hyperlink to Chapter 10, "PEX 8524 Port Registers," for details. Table 5-8. Virtual Channel Extended Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPABILITY VERSION NEXT CAPABILITY OFFSET EXTENDED CAPABILITY ID 148h Port VC Capability 1 14Ch Port VC Capability 2 150h Port VC Status Port VC Control 154h VC0 Resource Capability 158h VC0 Resource Control 15Ch VC0 Resource Status Reserved 160h VC1 Resource Capability 164h VC1 Resource Control 168h VC1 Resource Status Reserved 16Ch 170h Reserved ... 1B4h 1B8h Virtual Channel Arbitration Table (All Ports) ... 1C4h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 45 Reset and Initialization 5.2.4 PLX Technology, Inc. PLX-Specific Registers The following registers are unique to the PEX 8524 device, and are not referenced in PCI Express documentation. The PLX-Specific registers are organized into the following sections: * Section 10.13.1, "Error Checking and Debug Registers" * Section 10.13.2, "Physical Layer Registers" * Section 10.13.3, "CAM Routing Registers" * Section 10.13.4, "TIC Control Registers" * Section 10.13.5, "I/O Base and Limit Upper 16 Bits Registers" * Section 10.13.6, "Base Address Registers (BARs)" * Section 10.13.7, "Shadow Virtual Channel (VC) Capability Registers" * Section 10.13.8, "Shadow Port Virtual Channel Capability_1 Registers" * Section 10.13.9, "Ingress Credit Handler (INCH) Registers" PR EL IM IN AR Y * Section 10.13.10, "Egress Credit Handler (EGCH) Registers" * Section 10.13.11, "PLX-Specific Relaxed Ordering Mode Register" * Section 10.13.12, "Internal Credit Handler (ITCH) VC&T Threshold Registers" 46 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 5.2.4.1 PLX-Specific Registers Serial EEPROM Status and Control Registers Register 5-1. 260h EEPROM Status and Control(Only Port 0 and NT Link) Bit(s) Description Type Serial EEPROM Default EEPROM Control EEPROM Block Address EEPROM Block Address for 32 KB. R/W Yes 0000h 15:13 EEPROM Command Commands to serial EEPROM Controller: 001b = Data from EEPROM STATUS[31:24] bits written to EEPROM internal status register 010b = Write four bytes of data from the EEPROM Buffer into memory location pointed to by the EEPROM Block Address 011b = Read four bytes of data from memory location pointed to by the EEPROM Block Address into EEPROM Buffer 100b = Reset Write Enable latch 101b = Data from EEPROM internal status register written to EEPROM STATUS[31:24] bits 110b = Set Write Enable latch All other encodings are Reserved. R/W Yes 000b PR EL IM IN AR Y 12:0 EEPROM Status 17:16 EEPROM Present Serial EEPROM Present status. 00b = Not present 01b = EEPROM Present - no CRC error 10b = Reserved 11b = EEPROM Present, but with CRC error - default reset value used RO Yes 00b 19:18 EEPROM Command Status Serial EEPROM Command status 00b = EEPROM Command complete 01b = EEPROM Command not complete 10b = EEPROM Command complete with CRC error 11b = Reserved RO Yes 00b 20 EEPROM Block Address Upper Bit EEPROM BLOCK ADDRESS upper bit[13] Extends EEPROM to 64 KB R/W Yes 0b 21 CRC Disable 0b = EEPROM input data uses CRC 1b = EEPROM input data CRC disabled R/W Yes 0b 23:22 Reserved 00b Status Data from EEPROM 24 EEPROM_RDY# 0b = EEPROM is ready to transmit data 1b = Write cycle is in progress R/W Yes 0b 25 EEPROM_WEN 0b = EEPROM Write is disabled 1b = EEPROM Write is enabled R/W Yes 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 47 Reset and Initialization PLX Technology, Inc. Register 5-1. 260h EEPROM Status and Control(Only Port 0 and NT Link) (Cont.) Bit(s) Description 27:26 EEPROM_BP[1:0] EEPROM Block-Write Protect bits 30:28 EEPROM Write Status 000b when EEPROM is not in an internal Write cycle. 31 Serial EEPROM Default R/W Yes 00b 000b EEPROM_WPEN EEPROM Write Protect Enable When: = 0b and EEPROM_WEN = 1b, the EEPROM Status register is writable = 1b, the EEPROM Status register is protected R/W Yes 0b Serial EEPROM Block-Write Protect Bits PR EL IM IN AR Y Table 5-9. Type BP[1:0] Level 00b Array Addresses Protected 32 KB Device 64 KB Device 0 None None 01b 1(1/4) 6000h - 7FFFh - 10b 2(1/2) 4000h - 7FFFh - 11b 3(All) 0000h - 7FFFh - Register 5-2. 264h EEPROM Buffer (Only Port 0 and NT Port Link Interface) Bit(s) 31:0 Description Serial EEPROM Buffer Table 5-10. Serial EEPROM Default R/W Yes 0-h Reset and Clock Initialization Timing Symbol 48 Type Description Typical Delay td1 REF Clock stable to PEX_Reset release time 100 s td2 PEX_Reset release to PLL Clock Stable and Reset debounce 1.32 ms td3 Clock and Reset Stable to PLL Lock 125 s td4 PLL Lock to BIST Done time which causes Core Reset release 4.5 ms td5 Core Reset release to SerDes Resets active delay 10 s td6 SerDes Reset active time 60 s td7 Serial EEPROM load time 12.6 ms PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Figure 5-3. PLX-Specific Registers Reset and Clock Initialization Timing Clock Stable PEX_REFCLK 100 MHz td1 PEX_PERST# Clock Stable td2 PLL/SCLK 250 MHz PLL_LOCK PR EL IM IN AR Y td3 td4 BIST_DONE CORE_RESET# td5 SerDes_RESET SerDes_ CLOCK Serial EEPROM LOAD Inactive td6 Active PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Inactive Clock Stable td7 49 PLX Technology, Inc. PR EL IM IN AR Y Reset and Initialization 50 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 6 6.1 Interrupts Interrupt Support The PEX 8524 supports the PCI Express interrupt model which uses two mechanisms: * INTx Emulation * Message Signaled Interrupt (MSI) For legacy compatibility, the PCI INTx emulation mechanism is used to signal interrupts to the system interrupt controller. This mechanism is compatible with existing PCI software, provides the same level of service as the corresponding PCI interrupt signaling mechanism, and is independent of system interrupt controller specifics. This legacy compatibility mechanism virtualizes PCI physical interrupt signals by using an in-band signaling mechanism. In addition to PCI INTx compatible interrupt emulation, the PEX 8524 supports the Message Signaled Interrupt (MSI) mechanism. The PCI Express MSI mechanism is compatible with the MSI Capability defined in the PCI r2.3. The following events are supported for interrupts: * Hot Plug events - Attention Button pressed - MRL sensor change event - Presence detect change event - Power fault detected - Command complete event * ECC Error detected in internal packet RAM * Credit Overflow / Underflow * Internal Error FIFO Overflow 6.1.1 PEX 8524 Interrupt Handling The PEX 8524 provides an interrupt-generation module with each port. The primary function of the interrupt module is to read the request for interrupts from different sources and generate a PCI-compatible INTx interrupt assertion/de-assertion message or a Message Signal Interrupt (MSI). Assert_INTx and de-assert_INTx Message transactions emulate the PCI level-triggered interrupt signaling, whereas the MSI supports a PCI Express edge-triggered interrupt. The Interrupt controller functions include: * Sensing interrupt events * Setting Interrupt Status bit * Signaling Interrupt by way of the MSI mechanism * Signaling Interrupt by way of the INTx mechanism * Handling INTx# type interrupt messages from downstream devices PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 51 Interrupts 6.1.2 PLX Technology, Inc. INTx-Type Interrupt Message Forwarding INTx-type Interrupt messages from downstream devices are terminated at a PEX 8524 switch-linked Downstream port, and the Downstream port generates the same INTx-type Interrupt message. The Downstream port then transmits this message to the switch Upstream port. The Upstream port interrupt generator collapses and remaps INTx messages from each of the Downstream ports, generates new interrupt messages as a result of remapping and collapsing, then forwards the new message upstream by way of its link. 6.2 INTx Emulation Support The PEX 8524 supports the PCI INTx emulation to signal interrupts to the system interrupt controller. This mechanism is compatible with existing PCI software. It virtualizes PCI physical interrupt signals by using the in-band signaling mechanism. PR EL IM IN AR Y PCI Interrupt registers, as the Interrupt registers defined in the PCI r2.3, are supported. PCI Interrupt Status and Interrupt Disable bits, defined in the PCI r2.3 Command and Status registers, are also supported. Although the PCI Express Base 1.0a provides INTA#, INTB#, INTC#, and INTD# for INTx signaling, the PEX 8524 uses only INTA# for its internal interrupt message generation, because it is a single-function device. However, the incoming messages from downstream devices can be of INTA#, INTB#, INTC#, or INTD# type. On receiving the Assert_INTx or De-assert_INTx interrupt message, the interrupt module in the Downstream port terminates the received message and transmits an interrupt message of the same type upstream with its own Device Number and Received-Device Number from the downstream device. When there is an Interrupt request, the PCI Command Status register Interrupt Status bit is set. If INTx interrupts are enabled (Interrupt Disable = 0 and MSI Enable = 0), an Assert_INTA message is generated and transmitted upstream to indicate the port interrupt status. Software reads and clears the event and interrupt status bits after servicing the interrupt. 6.2.1 Remapping and Collapsing of INTx Type Interrupts Remapping and collapsing of INTx type Interrupts is enabled only in the Upstream port. Incoming interrupts are terminated at the Downstream port, which generates an interrupt message to the Upstream port. The Upstream port contains seven 4-bit registers representing seven Downstream ports and four INTx interrupt types. Whenever an Assert_INTx message is received from a Downstream port interrupt handler, the corresponding bit is set. For example, if Assert_INTC is received from Downstream port 1, the third bit in the first register is set. In a similar manner, De-assert_INTx from a device clears the corresponding register bit. Based on the Device Number and INTx type, the interrupt is remapped to the same or different INTx type message as specified in the PCI Express Base 1.0a, Table 2-13. The entire source is ORed to generate INTA#, INTB#, INTC#, or INTD# level-sensitive signals. The edge-detection circuitry is used to generate Assert_INTx and De-assert_INTx messages upstream, based on level change from L -> H or H -> L. In the event that a downstream link advances to DL_Down state, the corresponding Upstream port 4-bit internal register is reset. If the register reset results in a "virtual wire" de-assertion, a corresponding INTx de-assertion message is transmitted upstream from the Upstream port Interrupt Generation module. 52 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 6.3 Message Signaled Interrupt (MSI) Support Message Signaled Interrupt (MSI) Support One of the interrupt schemes supported by the PEX 8524 is the MSI mechanism, which is required for PCI Express devices. The MSI method uses Memory Write transactions to deliver interrupts. MSI is an edge-triggered interrupt. Note: MSI and INTx are mutually exclusive. These interrupt mechanisms cannot be simultaneously enabled. 6.3.1 MSI Operation At configuration time, system software traverses the function capability list. If a Capability ID of 05h is found, the function implements MSI. System software reads the MSI Capability Structure registers to determine function capabilities. The PEX 8524 only supports one message for MSI; therefore, multiple message enable and capable fields are always 0. PR EL IM IN AR Y The MSI 64-Bit Address Capable bits are enabled by default. System software initializes the MSI Capability Structure registers with a system-specified message. If the MSI function is enabled, after an interrupt event occurs, the interrupt module generates a DWord Memory write to the address specified by the message address register contents. The data written is the contents of message data register lower two bytes and zeros (0) in the upper two bytes. Because the multiple message enable field is always zero (0), the Interrupt Generation module is not permitted to change the low-order bits of message data. When the event bits that caused the interrupt are cleared, the device can generate a new MSI Memory write as a result of new events. 6.3.2 Message Signaled Interrupt Capabilities Registers The PEX 8524 Message Signaled Interrupt (MSI) Capabilities Register map is delineated in Table 10-6, and a detailed description of the Message Signaled Interrupt Control registers follow the table. (Refer to Section 10.8, "Message Signaled Interrupt Capability Registers," for further information regarding these registers.) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 53 PLX Technology, Inc. PR EL IM IN AR Y Interrupts 54 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 7 7.1 Software Architecture PEX 8524 Software Model The PEX 8524 require software support in the following areas: * Configuration of the switch and all its downstream links * Moving data forward and back through the links * Monitoring and servicing interrupts throughout the connected fabric * Monitoring and adjusting performance-related mechanisms The Configuration Mechanism is fairly straightforward and uses legacy PCI software structures and procedures to setup and identify all ports and links connected through the PEX 8524. An optional serial EEPROM interface is supported by the switch to simplify the downloading of configuration data to the switch. An example configuration procedure is discussed in Section 7.3, "Sample Configuration Procedure." After the switch and its links are set up, data can be routed from a port by way of the switch to any other port. Responses and other communications are returned by way of the same links to the initiator. The switch is transparent to these data transfers. An example data transfer is discussed in Section 7.3.2, "Sample Packet Transfer." When errors occur during data transfer due to data corruption in the internal RAMs, or an external device violates its credits, an interrupt is returned by way of the switch fabric to the Host identifying the problem. It is up to the Host software to implement interrupt-service routines to handle the problem. 7.2 Configuration Mechanism As described in the PCI Express Base 1.0a, the PEX 8524 supports two Configuration mechanisms: * PCI-compatible configuration mechanism, which supports entire binary compatibility with the PCI r2.3 and corresponding bus enumeration and configuration software * PCI Express Extended Configuration mechanism, which is provided to increase the size of available configuration space and to optimize access mechanisms The PEX 8524 ports are PCI-to-PCI bridges. PCI-to-PCI bridges must retain uniquely assigned Bus Numbers and Device Numbers. The PEX 8524 ports retain a set of PCI Express Configuration registers. One port is selected at power up as the Upstream port. The BIOS configures the Upstream port and other Downstream ports by PCI enumeration, by way of the Upstream port. 7.2.1 Software Configuration and Routing Configuration cycles must be routed from the Host by way of the Switch Upstream port. All Type 0 Configuration accesses by way of the PEX 8524 Upstream Link access to the Upstream Port Configuration registers. A bridge forwards Type 1 Configuration cycles from its Upstream interface as Type 0 Configuration cycles to the Downstream port when the Configuration cycles target a device on its secondary bus interface. To configure the Switch Downstream ports, the Bus Number in the Type 1 Configuration access must match the Secondary Bus Number of the Upstream port. The Device Number in that Type 1 Configuration access must be the Device Number of the Downstream port. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 55 Software Architecture PLX Technology, Inc. Figure 7-1. PEX 8524 System Configuration Propagation Configuration Propagation Upstream Port Upstream P-P Bridge P-P Downstream P-P Bridges P-P P-P P-P P-P P-P Downstream Ports 7.3 Downstream Station PR EL IM IN AR Y Upstream Station Sample Configuration Procedure Consideration must be given to the configuration procedure when setting up and initializing a PEX 8524 switch. Certain items are processed by initial hardware configuration, connections, and operating selections. The PCI/PCI-Express configuration software can be written from the Host by way of the Upstream port to all Downstream ports and their links, or from a Configuration Serial EEPROM, by way of the serial EEPROM interface. 1. Ports and lanes, per port: * Refer to Section 4.1.2.1, "Port Combinations," for options * PEX 8524 must be connected to PCI Express-compatible devices * Strapping balls must be set to identify the selected port configuration * For Station 0, refer to STRAP_STN0_PORTCFG[4:0] * For Station 1, refer to STRAP_STN1_ PORTCFG[3:0] * Software/serial EEPROM is used to override the Strapping ball selections 2. Select the Upstream port - set Strapping balls STRAP_UPSTRM_PORT_SEL[3:0]. 3. Select address spaces: * 32-bit addressing * 64-bit addressing * I/O addressing 4. Software/serial EEPROM programs the following registers for the Upstream port: * Primary Bus Number - identifies the Upstream link * Secondary Bus Number - identifies the switch internal Virtual PCI Bus * Subordinate Bus Number - must be the last Bus Number in the downstream hierarchy of this Upstream port * Set Master Enable and Memory Enable bits * Base and Limit registers - includes the Base and Limit values of all downstream devices * BAR0/BAR1 (used for memory-mapped CSR access) 5. Software/Serial EEPROM programs the following registers for the Downstream ports: * Primary Bus Number - all Downstream port-numbers are the Device Numbers on the internal Virtual PCI Bus * Secondary Bus Number - identifies the port's downstream link 56 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Sample Configuration Procedure * Subordinate Bus Number - must be the last Bus Number in the downstream hierarchy of each Downstream port * Set Master Enable and Memory Enable bits * Base and Limit registers - includes the Base and Limit values of all downstream devices On the Upstream port, the primary side is accessed by a Type 0 Configuration access. The Downstream ports are accessed with a Type 1 Configuration access on the Upstream port primary side, with the Bus Number of each transaction equal to the Upstream port Secondary Bus Number (Virtual PCI Bus). Figure 7-2. PEX 8524 System Configuration Example Type 0 Configuration Access Upstream Port Type 1 Configuration Accesses PR EL IM IN AR Y Port 0 Virtual PCI Bus Downstream Ports Port 1 Upstream Station 0 Port 8 Port 9 Port 10 Port 11 Downstream Station 1 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 57 Software Architecture 7.3.1 PLX Technology, Inc. Switch Device Number Assignment Example * The Upstream port (which is configured as Port 0 with 8 lanes for this example), by default, contains a primary Bus Number of 0. * Port 1 registers are accessed with a Type 1 Configuration transaction: - Bus Number is the internal Virtual PCI bus (which is the Upstream port secondary Bus Number) - Device Number is 01h - Function Number to be 000b * Port 8 registers are accessed with a Type 1 Configuration transaction: - Bus Number is the internal Virtual PCI Bus - Device Number is 08h - Function Number is 000b PR EL IM IN AR Y * Port 9 registers are accessed with a Type 1 Configuration transaction: - Bus Number is the internal Virtual PCI Bus - Device Number is 09h - Function Number is 000b * Port 10 registers are accessed with a Type 1 Configuration transaction: - Bus Number is the internal Virtual PCI Bus - Device Number is 0Ah - Function Number is 000b * Port 11 registers are accessed with a Type 1 Configuration transaction: - Bus Number is the internal Virtual PCI Bus - Device Number is 0Bh - Function Number is 000b 58 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 7.3.1.1 Switch Device Number Assignment Example Configuration Register Programming Sequence To program a configuration register 1. Program the Bus Number register on Upstream port (18h). 2. Program the Bus Number registers on all Downstream ports (18h). 3. Program the Memory Base and Limit Address registers on all Downstream ports (20h). 4. Program BAR0/1 on the Upstream port (optional). 5. Program the Memory Base and Limit Address registers on the Upstream port ensuring that this value claims all the space that is requested by all Downstream ports (20h). 6. Program the Bus Master Enable and Memory Access Enable bits on all ports (04h). Programming Base and Limit Values PR EL IM IN AR Y Figure 7-3. The Base and Limit values of the Upstream port must include the cumulative Base and Limit values of all the Downstream ports which in turn include the cumulative Base and Limit values of their downstream links Port 0 Upstream Port Virtual PCI Bus Port 1 Upstream Station 0 Port 8 Port 9 Port 10 Port 11 Downstream Station 1 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 59 Software Architecture 7.3.1.2 PLX Technology, Inc. Pseudo Code Sample PR EL IM IN AR Y CFGTYPE0 Write busnum 01,devicenum 00 function 0 address 18h data 00090201h //Primary Bus Number 01, secondary Bus Number 02 and subordinate Bus Number 09. At this step the virtual PCI bus in the PEX 8524 gets the Bus Number 02. After this any access to Bus Number 02 from the Upstream port would refer to this bus. CFGTYPE1 Write busnum 02,devicenum 01 function 0 address 18h data 00030302h //Primary Bus Number 02,secondary Bus Number 03 and subordinate Bus Number 03. an endpoint is attached to Port 1 of PEX 8524 CFGTYPE1 Write busnum 02,devicenum 08 function 0 address 18h data 00050502h //Primary Bus Number 02,secondary Bus Number 05 and subordinate Bus Number 05. an endpoint attached to Port 8 CFGTYPE1 Write busnum 02,devicenum 09 function 0 address 18h data 00060602h //Primary Bus Number 02,secondary Bus Number 06 and subordinate Bus Number 06. an endpoint attached to Port 9 CFGTYPE1 Write busnum 02,devicenum 10 function 0 address 18h data 00070702h //Primary Bus Number 02,secondary Bus Number 07 and subordinate Bus Number 07. an endpoint attached to Port 10 CFGTYPE1 Write busnum 02,devicenum 11 function 0 address 18h data 00090802h //Primary Bus Number 02,secondary Bus Number 08 and subordinate Bus Number 09. This means that we have a P2P bridge attached to Port 11 of Vega and only 1 more level of PCI hierarchy. CFGTYPE1 Write busnum 02,devicenum 01 function 0 address 20h data 02FF0200h // need 0200_0000h to 02FF_FFFFh memory space for Port 1. CFGTYPE1 Write busnum 02,devicenum 08 function 0 address 20h data 04FF0400H // need 0x0400_0000 to 04FF_FFFFh memory space for Port 8. CFGTYPE1 Write busnum 02,devicenum 09 function 0 address 20h data 05FF0500h // need 0x0500_0000h to 05FF_FFFFh memory space for Port 9. CFGTYPE1 Write busnum 02,devicenum 10 function 0 address 20h data 060006FFh // need 0x0600_0000h to 0x06FF_FFFFh memory space for Port 10. CFGTYPE1 Write busnum 02,devicenum 11 function 0 address 20h data 070007FFh // need 0x0700_0000h to 0x07FF_FFFFh memory space for Port 11. CFGTYPE0 Write busnum 01,devicenum 00 function 0 address 20h data 07FF0200h // the Upstream port claims all accesses from 0200_0000h to 07FF_FFFFh and would send it to the appropriate port. // Now set the BUS MASTER ENABLE and MEMORY ACCESS ENABLE bits on all these ports. CFGTYPE0 Write busnum 01,devicenum 00 function 0 address 04h data 0x0000_0006h CFGTYPE1 Write busnum 02,devicenum 01 function 0 address 04h data 0000_0006h CFGTYPE1 Write busnum 02,devicenum 02 function 0 address 04h data 0000_0006 h CFGTYPE1 Write busnum 02,devicenum 08 function 0 address 04h data 0000_0006h CFGTYPE1 Write busnum 02,devicenum 09 function 0 address 04h data 0000_0006h CFGTYPE1 Write busnum 02,devicenum 10 function 0 address 04h data 0000_0006h CFGTYPE1 Write busnum 02,devicenum 11 function 0 address 04h data 0000_0006h // Now any 32-bit memory transaction from Upstream port between the addresses 0200_0000h to 07FF_FFFFh would go to the appropriate port. // Now any 32-bit memory transaction from any Downstream port between the addresses 0200_0000h to 07FF_FFFFh would go to the appropriate port (as long as it is not in the base-limit range of that port itself). // Any transaction from any Downstream port outside the range of 0200_0000h to 07FF_FFFFh would go to the Upstream port. 7.3.2 Sample Packet Transfer When all ports are configured, the following occurs: * 32-Bit Memory transactions from the Upstream port destined between addresses 0200_0000h to 07FF_FFFFh advance to the appropriate port. * 32-Bit Memory transactions from a Downstream port between the addresses 0200_0000h to 07FF_FFFFh advance to the appropriate port (if it is not in the Base-Limit range of that port). * Transactions from a Downstream port outside the range of 0200_0000h to 07FF_FFFFh advance to the Upstream port. 60 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 7.3.3 Using Base Address Registers (BARs) to Access Registers Using Base Address Registers (BARs) to Access Registers Besides using Configuration accesses to PLX-specific read/write registers, BARs are used to access all registers: * BAR0 requests 128 KB memory space. * Additionally, BAR1 is used to place this memory space anywhere in 64-bit system memory space * Using this method, after the Upstream port BAR0 (and optionally, BAR1) is programmed, all register locations inside the PEX 8524 can be accessed using Memory transactions. Using the example configuration, if BAR0 is programmed to 0100_0000h using a Type 0 Configuration transaction, and if the Memory Access bit is programmed using a Type 0 Configuration transaction, then all other registers can be accessed using Memory-Mapped Register accesses, as delineated in Table 7-1. Using Memory-Mapped Access PR EL IM IN AR Y Figure 7-4. PEX 8524 BAR0 = 0100_0000h Port 0 Base and Limit for Port 0 = 0100_0020h Port 1 0K 4K 8K 12K 16K Reserved Base and Limit for Port 8 = 0100_8020h 32K Port 8 36K Port 9 40K Port 10 44K Port 11 48K Reserved 64K NT-Port Virtual Interface 68K NT-Port Link Interface 72K Reserved 128K Table 7-1. Memory-Mapped Register Access Register Location Address Port 0 Base and Limit 0100_0020h Port 1 Base and Limit 0100_1020h Port 8 Base and Limit 0100_8020h Port 9 Base and Limit 0100_9020h Port 10 Bus Number 0100_A018h Port 11 Bus Number 0100_B018h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 61 Software Architecture 7.4 PLX Technology, Inc. Interrupt Support The PEX 8524 supports the PCI Express interrupt model, which uses two mechanisms: * INTx Emulation * Message Signaled Interrupt (MSI) These interrupt mechanisms are explained in Chapter 6, "Interrupts." 7.5 Hot Plug Support PR EL IM IN AR Y The PEX 8524 supports the Standard Hot Plug Controller (HPC) on all its Downstream ports. Hot Plug mechanisms are detailed in Chapter 17, "Hot Plug Support." 62 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 8 8.1 Performance Metrics Overview The PEX 8524 includes features that optimize performance under several application scenarios. The four major performance metrics discussed in this chapter are as follows: * Internal fabric non-blocking nature * Quality of Service (QoS) * Sustained link throughput * Port-to-port latency These approaches emphasize metric optimization. In general, host-centric applications, with transactions traveling between a wide Upstream port and narrow Downstream ports, are more latencyoriented. In comparison, peer-to-peer applications, where transactions are evenly distributed among all ports in a switch, are more throughput oriented. However, achieving best performance is strongly application dependent and the above principles are not necessarily always correct. For example, if the PEX 8524 is linked with a graphics card in a host-centric application, graphics port throughput becomes the most important performance consideration, not latency. Conversely, if traffic pattern in a peer-to-peer application is lightly loaded and bursty, latency can overweigh throughput to become the highest performance concern. Therefore, it becomes important to understand the interaction and dynamics among performance metrics when tuning performance. For example, avoiding a scenario, traffic from multiple ingress ports target a narrow egress port, which improves overall throughput and latency by reducing system hot-spot congestion. After application dynamics are comprehended, how to exchange the performance metrics against one another takes on a clear direction. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 63 Performance Metrics 8.2 PLX Technology, Inc. Non-Blocking Switch Switch literature defines non-blocking as a packet that can be routed from an ingress port to an egress port, provided that not more than one packet is received by the same ingress port and not more than one packet is destined to the same egress port. A non-blocking switch is expected to fully route all packets for independent ingress traffic stream with destination uniformly distributed. 8.2.1 Queuing Topology Three major queuing topologies are used in switch architecture: * Output Queuing (OQ) - When a packet arrives at an ingress port, it is immediately placed into a buffer that resides in the corresponding ingress port. If, in the worst case, there are N ingress ports simultaneously attempting to transmit packets to the same egress port, the output buffer is required to enqueue traffic N times faster than the egress port's dequeuing rate. PR EL IM IN AR Y * Input Queuing (IQ) - In this architecture, ingress port packets maintain a set of Virtual Output Queues (VOQ). One of the packets, among all head packets in different VOQs to the same egress port, is allowed to be scheduled out of that egress port during a given time slot. The key factor in achieving high performance using VOQ is the global scheduling algorithm, which is responsible for the selection of packets to be transmitted from the ingress ports to the egress ports in each time unit. The complexity of such scheduling algorithm is O(N2). * Combined Input-Output Queuing (CIOQ) - This approach adopts a queuing structure that is a combination of input and output queuing. It provides VOQ buffers at the ingress side, and also provides O(1) bandwidth buffers at the egress side. The design goal is to achieve the same level of throughput and non-blocking nature as an OQ switch, but without requiring O(N) times bandwidth to buffers as an OQ switch and without building a centralized scheduler whose complexity is proportional to O(N2) as an IQ switch. To achieve this goal, moderate internal fabric speedup is required in the CIOQ approach to compensate for transient conflict. The PEX 8524 uses CIOQ as its internal switching topology to process traffic from different stations. In both switches, packets from one or more ports are aggregated first into a station, whose data path is sufficiently wide to accommodate traffic from all ports within it at any time. The PEX 8524 implementation includes two stations. For independent ingress traffic, it is possible for the CIOQ approach to achieve complete egress throughput with internal fabric to issue a speedup of only 2 - 1/N. That is, for the two-station PEX 8524 implementation, the internal speedup factor of 1 (no speedup), is sufficient to achieve non-blocking status. After extensive simulation to consider standard switching performance factors including input traffic distribution, packet size distribution, output throughput, port-to-port latency, latency jitter, egress to ingress backpressure, as well as PCI Express-specific performance factors such as Physical Layer, Data Link Layer overhead, and packet-to-packet dependency caused by PCI ordering, PLX determined that using an internal speed-up factor of 1.25 allows the PEX 8524 to be non-blocking. 64 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Port-to-Station Aggregation 8.2.2 Port-to-Station Aggregation As previously stated, a single PEX 8524 PCI Express station is aggregated from multiple ports, provided that the combined port width is less than or equal to 24 lanes. Figure 8-1 redraws the PEX 8524 Transaction Layer architecture by explicitly dividing a PCI Express station into individual ingress and egress parts. In a PCI Express source station, the write port to the ingress packet RAM is shared by up to four ingress ports in a TDM (Time Domain Multiplex) fashion. The wider the port, the more TDM slots are assigned to that port. Within VOQs of a single source station, if multiple packets from different ingress ports are available to be dispatched to the same destination, a Round-Robin arbiter controls which ingress port to select next. Moving to the internal fabric, the read ports to ingress packet RAMs and the write ports to egress packet RAMs are controlled by the PLX implementation of the CIOQ scheduling algorithm, where a unit in scheduling is a station instead of a port. PEX 8524 Queuing Data Structures P1 Ingress Destination Station 0 Internal Fabric 1376x20B = 27520B Ingress Packet RAM 32- entry P0 VOQ Ctl 32-entry P1 VOQ Ctl VOQ Scheduler P0 Ingress TDM-Controlled Port to Station Aggregation Source Station 0 2048x20B = 40960B Egress Packet RAM P0 VC link list Egress Scheduler P1 VC link list Egress Scheduler P7 Ingress 2048x20B = 40960B Egress Packet RAM 1376x20B = 27520B Ingress Packet RAM 32-entry P4 VOQ Ctl 32-entry P5 VOQ Ctl 32-entry P6 VOQ Ctl 32-entry P7 VOQ Ctl VOQ Scheduler P6 Ingress TDM-Controlled Port to Station Aggregation P5 Ingress P0 Egress P1 Egress Destination Station 1 Source Station 1 P4 Ingress TDM-Controlled Station to Port De-Aggregation Station 0 P4 VC link list Egress Scheduler P5 VC link list Egress Scheduler P6 VC link list Egress Scheduler P7 VC link list Egress Scheduler TDM-Controlled Station to Port De-Aggregation Figure 8-1. PR EL IM IN AR Y In a PCI Express destination station, the read port to the egress packet RAM is shared by up to four egress ports in a TDM fashion as well. Furthermore, there are four independent egress schedulers. Egress schedulers follow Virtual Channel arbitration as required by the PCI Express Base 1.0a. P4 Egress P5 Egress P6 Egress P7 Egress Station 1 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 65 Performance Metrics 8.2.3 PLX Technology, Inc. RAM and Queue Size Table 8-1 delineates the RAM and queue size built into the PEX 8524. The smallest unit of ingress packet RAM and egress packet RAM is defined as a beat, which can store 20 bytes of data. In the PEX 8524, the smallest packet (12B header) takes 1 beat to store in a packet RAM, and the largest packet (16B header + 256B payload + 4B digest = 276B) takes 14 beats to store in packet RAMs. In Table 8-1, the number 32 under the cell "Ingress VOQ Entries Per Port" delineates the maximum number of VOQ entries allocated to each ingress port. Each VOQ entry holds one Transaction Layer packet. For ingress ports, the incoming packet can travel to two destination stations with each station containing up to four egress ports. Also, for egress ports, up to two VCs are supported with each VC potentially having three different packet types - posted, non-posted, and completion (P, NP, and C, respectively). PR EL IM IN AR Y Ports on the egress side, can retain up to six queues to hold packets from two supported VCs and three supported Types. A queue that stores packets of a unique VC and a unique type is referred to as a VCnT queue. Again, some queues can be completely empty and some queues can contain more than one packet. The maximum number of packets held by a single egress port is limited by the number of egress packet RAM beats allocated to that port. It can be calculated from Table 8-1 that the total packet RAM size for the PEX 8524 is 136960 bytes. Assume the max TLP size is 276B with a max payload size (MPS) of 256B. Theoretically, the PEX 8524 can store up to 496 MPS packets. 8.3 Quality of Service Table 8-1. PEX 8524 Data Structure Size Data Structure Name Per Port Per Station Overall Ingress Packet Name Programmable 1376 beats or 27520 bytes 55040 bytes Ingress VOQ Entries 32 128 256 Egress Packet RAM 1024 beats or 20480 bytes for 1 to 2 ports; 512 beats or 10240 bytes for 3 to 4 ports 2048 beats or 40960 bytes 81920 bytes Egress VCnT Queues 6 24 48 Quality of Service (QoS) is a performance differentiation feature offered by PCI Express to manage multiple traffic classes of different characteristics. An application assigns a Traffic Class (TC) value to individual Transaction Layer packets according to the QoS requested by the class to which the transaction belongs. The static TC value tagged to each packet is dynamically mapped to a VC as it is passed through a system PCI Express capable device. The TC value ultimately determines the relative priority of a single packet as it traverses the PCI Express fabric, as well as the accumulated bandwidth allocated to the packets that belong to the same class. 8.3.1 Virtual Channel Up to two VCs, VC0 and VC1, are supported by the PEX 8524. Each VC retains its own buffer resource allocation and data path. For a single port, the configuration and property of VCs are determined by the Virtual Channel Extended Capability Register map (address 148h to 1C4h). 66 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Packet Arbitration Registers described in the Virtual Channel Extended Capability Register map cover not only a switch egress port, but a switch ingress port. Registers related to packet arbitration are egress specific, whereas registers defining TC/VC mapping and low-priority VC count are applicable to both ingress and egress ports. (Refer to Table 10-10, "PEX 8524 Virtual Channel Extended Capability Register Map (All Ports)," on page 130 for further Virtual Channel mapping information.) Virtual channel, combined with traffic labeling, enables deployment of independent physical resources to handle differentiated traffic. Registers 15Ch, VC0 Resource Control, and 168h, VC1 Resource Control, delineate register bits that control TC/VC mapping. Across various ports, the PEX 8524 supports both symmetric TC/VC mapping and asymmetric TC/VC mapping. In the latter approach, the TC/VC mapping is port independent and configured with different values per port. The PEX 8524 default configuration sets all TC[0-7] to VC0, as provided in TC/VC0 Map bits. For applications requiring two VCs, TC[1-7] can be mapped to VC1 by removing them from the TC/VC0 Map bits and adding them to the TC/VC1 Map bits. Packet Arbitration PR EL IM IN AR Y 8.3.2 Because of CIOQ switch architecture and multiple VC support, the PEX 8524 functions with several arbitration/scheduling points distributed in the data path from an ingress port to an egress port. In the following section, the arbitration/scheduling/backpressure algorithm used in the source scheduler, internal fabric, and egress scheduler are discussed. 8.3.2.1 Source Scheduler Source Scheduler is essentially the VOQ scheduler depicted in Figure 8-1. The Source Scheduler functions as follows: * From all 32 VOQ entries (each entry represents a single packet) belonging to a single ingress port, identifies one packet to be dispatched to the appropriate destination station, when egress RAM space is available. * Arbitrates among multiple-ready packets from different ingress ports with a Round-Robin mechanism. * Breaks deadlock potential by following PCI ordering rules. Note: Packets to different egress ports are selected with oldest first criteria on a per queue basis. This policy offers the best fairness and performance properties at low complexity. Packets to different VCs are selected by allowing VC1 higher priority if configured as such. PCI ordering is enforced. The Source scheduler is capable of handling variable-length packets. It can schedule one packet out of a source station every Clock cycle, regardless of packet size. There are two programmable fields in the Source scheduler: * High-priority VC * PLX relaxed ordering 8.3.2.2 High-Priority Virtual Channel When two VCs are enabled, packets from VC1 are achieved by setting the low-priority extended VC Count register to 00h in the 14Ch, Port VC Capability 1 register, scheduled with high priority. The default setup can be changed by serial EEPROM initialization. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 67 Performance Metrics 8.3.2.3 PLX Technology, Inc. PLX-Specific Relaxed Ordering PLX relaxed ordering capability is supported to enhance the performance of "push only" traffic (posted packets, such as Memory writes and messages) in the PEX 8524. (Refer to the BFCh, PLX-Specific Relaxed Ordering Mode register (only Ports 0 and 8) for further details.) According to PCI ordering rules, posted packets are not allowed to bypass any of the previously posted packets of the same VCnT, although they are targeting different egress ports. In applications such as storage area networks or IP networks, where posted PCI Express packets are used to transmit encapsulated data traffic through switches, unnecessary serial dependency might be created in the source scheduler for those posted packets coming from the same ingress ports, but going to different egress ports if strict PCI ordering rules were followed. This can result in dramatically degraded overall switch throughput. PR EL IM IN AR Y The PEX 8524 provides a PLX-specific relaxed ordering implementation. The mode is enabled by setting the BFCh register. There is an enable bit for TCs in each ingress port. All packets are allowed to bypass older packets from the same ingress port and TC. In the current implementation, packets targeting different egress ports are free to proceed without waiting for ordering dependency to be cleared. Meanwhile, packets targeting the same egress port are processed "in order" because there is no performance gain. Because the enable bit is TC-based, taking advantage of PLX-Specific Relaxed Ordering mode requires the PEX 8524 to be programmed with symmetric TC/VC mapping first. The traffic type that benefits most from this mode is "posted traffic." To take advantage of PLX-Specific Relaxed Ordering mode, without violating other ordering rules defined by the PCI r2.3, it is suggested to restrict outstanding traffic flow to be "posted only" and shut down all non-posted packets. There are two usage models: * Restrict all posted traffic requiring high throughput in VC1 and program all TCs belonging to VC1 to enable relaxed ordering. * Software disables PLX-Specific Relaxed Ordering mode in all TCs in the front, performing all setups that involve non-posted packet, and then enabling the PLX relaxed ordering bit when the system enters pure Data Transfer mode. When data transfer completes, disable the PLX-Specific Relaxed Ordering mode. 68 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 8.3.2.4 Packet Arbitration Internal Fabric Backpressure Internal fabric provides egress packet RAM space available status from destination stations to source stations. The source scheduler never transmits a packet to an overflow/overwrite egress packet RAM. Moreover, to prevent packets in a particular VCnT from occupying the majority of egress packet RAM, and to speedup backpressure from egress queues to ingress queues and ultimately to external devices in the case of congestion avoidance, VCnT-based (VC and Type - P, NP, C) packet cut off information is passed from egress ports to each source station. Egress queue congestion occurs when packet arrival rate overcomes the packet dispatching rate. There are two causes of congestion: * Insufficient credit to transmit the packets * Insufficient bandwidth to transmit the packets as quickly as they arrive In either case, if the cause continues, eventually the egress queues of the congested port fill. PR EL IM IN AR Y The PEX 8524 utilizes a watermark mechanism to cut off further packets from the ingress side when the egress queues back up. With some egress ports cut off, ingress queues that contain packets targeting those egress ports could then fill. A filled ingress queue prevents additional credit to its link partner, which causes that external device to stop transmitting further packets in that VCnT. The registers listed below are per VCnT based in an egress port. All ports in a station share the same programmed value. Each VCnT contains its own upper and lower limit. If more data than the programmed upper limit are queued, no further packets of that VCnT can be scheduled across the internal fabric, cutting off that VCnT flow. After cutting off the VCnT flow, an egress queue eventually drops below its lower limit as packets are scheduled out of the egress port. This event turns on internal fabric VCnT enabling flags, which allow that VCnT to resume flow. (Refer to C00h, ITCH VC&T Threshold_1, C04h, ITCH VC&T Threshold_2, and C08h, ITCH VC&T Threshold_3 registers for further information.) There are two rules to program the C00h to C08h registers: * The unit value for the upper and lower limits is equivalent to eight beats. The Max value programmable in the upper limit is a function of the port width, delineated in Table 8-2. An x8 egress port can handle no more than 1024 beats, a meaningful value for the upper and lower limits is bounded by 1024/8=128 (or 80h). In the device, the default value used by the upper and lower limits (FFh) is larger than its maximum legal value (80h). Therefore, by default, the backpressure mechanism is not triggered. * The upper and lower limits must be different, with the upper number being larger than the lower number by at least two units. Table 8-2. VC&T Threshold Limits Port-Width Maximum Upper Limit in Beats x1 128 x2 256 x4 512 x8 1024 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 69 Performance Metrics PLX Technology, Inc. For example, programming upper = 14 and lower = 7 for VC0 posted allows each port in the station to accumulate 14 x 8 beats = 112 beats = 112 x 20 bytes = 2240B VC0 Posted bytes before any one port cuts off VC0 Posted internal traffic. If there are four ports in the station, then 8960 bytes can be stored in the RAM without the upper limit being crossed. After a port receives more than 112 beats of VC0 posted, no further VC0 posted is forwarded from the ingress port. The egress port must drain 7 x 8 beats before resuming VC0 posted forwarding. The main objective is to avoid clogging the egress RAM with excessive packets of the same type which might prevent packets of other types from making fast forward progress inside the switch. If necessary, program upper and lower limits. 8.3.2.5 Egress Scheduler In each egress port, the PEX 8524 strictly follows VC and port arbitration mechanisms defined by the PCI r2.3. PR EL IM IN AR Y Virtual Channel Arbitration In the context of scheduling traffic in VC0 and VC1, the main goal of the egress scheduler's VC arbitration is to provide differentiated services between data flows within the fabric. There are three VC arbitration choices: * Strict priority - VC1 always prevails over VC0 * Round-Robin, or "Hardware-Fixed Arbitration" in the PCI Express Base 1.0a - alternate between VC0 and VC1 * Weighted Round-Robin (WRR) with 32 phases - select VC0 or VC1, based on 32 values programmed with the VC&T Arbitration table (refer to Table 8-3) The strict priority selection is made by setting the low-priority extended VC Count register to 00h in the Port VC Capability 1 register (at 14Ch). The default value is strict priority and can only be changed by serial EEPROM initialization. (Refer to 14Ch, Port VC Capability 1 register Low-Priority Extended VC Count bit.) If the low-priority extended VC Count is set to 1 (by way of serial EEPROM), then VC0 and VC1 share the low-priority pool. Within the low-priority pool, Round-Robin or Weighted Round-Robin arbitration can be selected. Register bits [1:0] in address 150h describe the two types of VC arbitrate for mechanisms supported by the PEX 8524, and register bit 1 in address 154h defines programming. (Refer to 150h, Port VC Capability 2, and 154h, Port VC Status and Control, registers VC Arbitration Capabilities bits.) When using Weighted Round-Robin, the 32-phase VC Arbitration Table must be programmed before loading the table. Table entries represent one phase that is loaded by software with a low-priority VC ID value. The VC arbiter repeatedly sequentially scans all table entries, and transmits transactions from the VC buffer specified in the table entries. After a transaction is dispatched, the arbiter moves to the next phase. (Refer to the VC Arbitration Table Phase n register.) Table 8-3. Virtual Channel Arbitration Table Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 70 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Phase 7 Phase 6 Phase 5 Phase 4 Phase 3 Phase 2 Phase 1 Phase 0 1B8h Phase 15 Phase 14 Phase 13 Phase 12 Phase 11 Phase 10 Phase 9 Phase 8 1BCh Phase 23 Phase 22 Phase 21 Phase 20 Phase 19 Phase 18 Phase 17 Phase 16 1C0h Phase 31 Phase 30 Phase 29 Phase 28 Phase 27 Phase 26 Phase 25 Phase 24 1C4h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Throughput Egress Port Arbitration Regarding egress ports, the PEX 8524 supports only one port arbitration mechanism: non-configurable hardware arbitration scheme. In particular, the oldest ready packet from all ingress ports arriving at the current egress port are selected first. "Ready" packet is defined as a packet with available egress credit and no ordering violations. 8.4 Throughput 8.4.1 Theoretical Upper Limit PCI Express allows for bidirectional traffic capability and scalable widths, allowing it to closely match the desired bandwidth. As discussed below, compared to 2.5 Gbps raw bandwidth provided by each SerDes lane, the achievable data payload efficiency, assume the max payload size (MPS) of 256B, is approximately 70%. Physical Layer Overhead PR EL IM IN AR Y 8.4.1.1 The 2.5 Gbps serial data on a serdes is encoded with additional information for clock recovery and error detection through 8b/10b encoding. When additional information is removed, a 2.0 Gbps data rate remains, which is 80% of the starting bandwidth. PHY layer also adds a 1-byte start symbol (STP) and a 1-byte end symbol (END or EDB) to the packet length. In other words, 2 bytes of overhead per TLP is introduced. Also in PHY, SKP-ordered sets are used to compensate for differences in frequency between bit rates at two ends of a Link. The PCI Express Base 1.0a maintains a clock frequency tolerance of 600 parts per million (ppm), which in turn requires a SKP-ordered set to be transmitted in the range of 1180 to 1530 symbol times. This makes the achievable efficiency drop another 4/1180 = 0.34%. 8.4.1.2 Data Link Layer Overhead To ensure data integrity passing over the wire, the PCI Express Base 1.0a states that the DLL (Data Link Layer) adds a sequence number at the start of the packet and an LCRC integrity check at the end of the packet. The sequence number is two bytes, and the LCRC is four bytes (that is, 6 bytes of overhead per TLP is introduced). In addition to the overhead inherent in a TLP transmitting a payload, the PCI Express Base 1.0a uses the same wire to transmit DLLPs (Data Link Layer Packets). ACK and UpdateFC are the two most frequently used type of DLLPs. ACK (acknowledge) is used to correctly flag a TLP, and UpdateFC is used to provide credits that enable TLP transaction. DLLPs are structured that a single ACK can represent receiving multiple TLPs, reducing the total number of ACKs required. Similarly, a single UpdateFC is structured that credit for more than one packet can be extended at a time, reducing the number of required UpdateFCs per TLP. The size of a single DLLP is 8 bytes. In the worst case, two outgoing DLLPs are formed for each incoming TLP, which makes the per TLP overhead to be 16B. In cases where there is zero DLLP overhead for incoming TLPs, note that certain DLLPs and their associated TLPs travel in opposite directions. 8.4.1.3 Transaction Layer Overhead All PCI Express payloads are encapsulated in a Transaction Layer Packet (TLP). A TLP contains a header portion that provides the PCI Express switch with routing information for the packet. The header can be 12 or 16 bytes. According to the PCI Express Base 1.0a, maximum payload size (MPS) can range from 128 to 4096 bytes. the PEX 8524 supports MPS up to 256 bytes. This optimizes overall design cost at the expense of sacrificing a portion of the header to payload efficiency. A TLP can also incur additional overhead when end-to-end data integrity is essential. In such cases, a 4-byte ECRC is added as another type of overhead to the end of the packet. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 71 Performance Metrics 8.4.1.4 PLX Technology, Inc. PCI Express Efficiency Upper Bound Summary Table 8-4 summarizes PCI Express inherent efficiency for 0B, 4B, 8B, 40B, 128B, 256B, and 4096B payload sizes on various negotiated link widths. The 4096B row is provided for reference only. The table columns provide three types of variations: * Comparing to raw serdes bandwidth of 2.5 Gbps versus 2.0 Gbps after 8b/10b decoding. * 0% additional DLLP generation versus 100% DLLP generation, assuming traffic is equal in both directions. 0% DLLP assumes that DLLP traffic is not injected into the TLP stream. 100% DLLP assumes that for every TLP transmitted, an additional ACK DLLP and UpdateFC DLLP are generated in the reverse direction. * Non-payload TLP overhead of 12B versus 20B (16B header + ECRC). PR EL IM IN AR Y In summary, the larger the payload, the more efficient the PCI Express communication. For 256-byte maximum payload size supported by the PEX 8524, the limit efficiency compared to the raw 2.5-Gbps bandwidth is between 68 to 73.92%. Note: Not all factors are reflected in this table. SKP-ordered set drops another 0.3%. Any credit shortage or transient congestion can significantly drop. Table 8-4. Throughput Theoretical Upper Limit 2.5 Gbps Raw Bandwidth Bytes of Payload 0% DLLP 12B 0 0.00% 4 13.28% 8 22.80% 40 53.12% 128 68.96% 256 73.92% 4096 79.36% 8.4.2 2.0 Gbps Raw Bandwidth after 8b/10b Decoding 100% DLLP 0% DLLP 100% DLLP 20B+ 12B 20B+ 12B 20B+ 12B 20B+ ECRC 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 10.00% 8.00% 6.64% 16.60% 12.50% 10.00% 8.30% 17.68% 14.48% 12.24% 28.50% 22.10% 18.10% 15.30% 46.88% 42.00% 38.00% 66.40% 58.60% 52.50% 47.50% 65.44% 62.24% 59.36% 86.20% 81.80% 77.80% 74.20% 71.84% 69.92% 68.00% 92.40% 89.80% 87.40% 85.00% 79.20% 79.04% 78.88% 99.20% 99.00% 98.80% 98.60% Single Stream Throughput For a single packet stream to flow from a fixed ingress port to a fixed egress port, throughput optimization can be further broken down into the ingress and egress sides. 8.4.2.1 Ingress Side Accept More than One Packet in Same Symbol Time The PEX 8524 ingress port is designed to accept incoming traffic at the fastest rate possible. For x8 ports, the PEX 8524 allows the ending part of a TLP and beginning part of the next TLP to arrive in the same symbol time. It also allows a partial TLP and a partial or full DLLP to simultaneously arrive. 72 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Single Stream Throughput Optimize Ingress Credit Allocation A TLP cannot be transmitted to the switch without the switch providing sufficient ingress credits in the front. When a credit is advertised, it indicates a guaranteed storage available in the credit transmitter at that time. If there is insufficient or in-timely ingress credits advertised from the PEX 8524 to its link partner, the incoming TLP stream does not sustain at the highest possible rate. Amount of Ingress Credit Required Calculation The PEX 8524 supports up to six VCnTs per port. The amount of ingress credits advertised in each VCnT is expected to be sufficient to cover the round-trip delay from the time the external device schedules a TLP for transmission in its Transaction Layer to the time the external device receives the replenishing credit from the PEX 8524 in the same VCnT. To enable a burst of TLPs of the same VCnT to enter the PEX 8524 without interruption, the following empirical equation can be used: PR EL IM IN AR Y Ingress_Credit_Advertised = (Round_trip_time_in_symbol times x link_width) / packet_size_in_bytes Round-trip latency consists of the following: * Latency for incoming TLP to travel the entire the PEX 8524 ingress data path * Delay from writing the first byte of the packet into ingress packet RAM until writing the last byte of the packet into ingress packet RAM * Latency for source scheduler to transmit the packet to egress packet RAM and free up the ingress buffers for this TLP packet * Latency for the PEX 8524's ingress credit scheduler to generate an UpdateFC packet * Latency for this UpdateFC DLLP to travel the PEX 8524 egress data path to serdes * Delay in serdes * Latency for this UpdateFC DLLP to travel the ingress data path of the external device * Latency for external device to process the UpdateFC DLLP and update its credit_limit counter * Latency for external device to schedule the next TLP in the same VCnT out * Latency for the external device to move the new TLP across its egress data path to the serdes * Final delay in serdes From the above description, it becomes obvious that the round-trip latency is determined by both the PEX 8524 and external device. Realistically speaking, this round-trip latency can range from 160 to 400 ns/40 to 100 symbol times. For example, suppose a link contains eight lanes and a stream of posted transactions is chopped into packets of 64B payload each. The amount of posted type header credit to sustain non-interrupt incoming traffic flow is approximately 100 x 8 / (16 + 64) = 10. The smaller the payload size, the higher demand on the ingress credit to be advertised. Using the same example provided above (except for a stream of 4B payload-only posted packets), the number of the ingress header credit required is 40. As stated earlier, the PEX 8524 contains a total of 32 VOQ entries in its ingress ports. Although 30 VOQ entries can be allocated to the posted traffic, there is no way to sustain the incoming traffic without stalling due to lack of credits. Program Ingress Credit Threshold Rules The PEX 8524 provides capability to program the ingress credit value for each VCnT in ingress ports. (Refer to Section 10.13.9.1, "INCH Threshold Port Virtual Channel Register (Ports 0 and 8 Only)," to view the registers to program the range from address A00h to A5Ch.) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 73 Performance Metrics PLX Technology, Inc. Register 8-1. A00h, A18h, A30h, A48h INCH Threshold Port n VC0 Posted (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Bit(s) Description 2:0 Reserved 8:3 Payload Payload = 00_1011b 13:9 Header Header = 0_0101b 31:14 Reserved Type Serial EEPROM Default 000b R/W Yes 14Bh 0-0h Register 8-2. A04h, A1Ch, A34h, A4Ch, INCH Threshold Port n VC0 Non-Posted Bit(s) PR EL IM IN AR Y (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Description 8:0 Payload Payload = 0_0000_1001b 13:9 Header Header = 0_1001b 31:14 Reserved Type Serial EEPROM Default R/W Yes 1209h 0-0h Register 8-3. A08h, A20h, A38h, A50h, INCH Threshold Port n VC0 Completion (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Bit(s) Description 2:0 Reserved 8:3 Payload Payload = 00_1011b 13:9 Header Header = 0_0101b 31:14 Reserved Type R/W Serial EEPROM Default 000b Yes 14Bh 0-0h Register 8-4. A0Ch, A24h, A3Ch, A54h, INCH Threshold Port n VC1 Posted (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Bit(s) 74 Description 2:0 Reserved 8:3 Payload Payload = 00_0010b 13:9 Header Header = 0_0001b 31:14 Reserved Type Serial EEPROM Default 000b R/W Yes 042h 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Single Stream Throughput Register 8-5. A10h, A28h, A40h, A58h, INCH Threshold Port n VC1 Non-Posted (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Bit(s) Description 8:0 Payload Payload = 0_0000_0001b 13:9 Header Header = 0_0001b 31:14 Reserved Type Serial EEPROM Default R/W Yes 0201h 0-0h Register 8-6. A14h, A2Ch, A44h, A5Ch, INCH Threshold Port n VC1 Completion Bit(s) PR EL IM IN AR Y (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Description 2:0 Reserved 8:3 Payload Payload = 00_0010b 13:9 Header Header = 0_0001b 31:14 Reserved Type R/W Serial EEPROM Default 000b Yes 042h 0-0h In the above registers, both header credit and payload credit threshold are writable. The following rules are used to program these registers: * One unit of header credit threshold stands for one packet. A value of 1 allows the PEX 8524 to advertise 1 header credit, 2 allows 2 header credits, and so forth. Bits [13:9] allow a maximum of 31 header credits to be programmed to VCnT. * One unit of payload credit threshold stands for any 16B worth of data. When the PEX 8524 maximum payload size is set as 256, a value of at least 16 is required to be programmed for posted and completion packets. Bits [8:0] allow a maximum value of 29 payload credit units to be advertised. For posted and completion types, bits [2:0] are reserved, which forces the payload credit threshold to be aligned to 8. This effectively makes the unit for posted and completion types increase to 16B x 8 = 128B. For non-posted types, similar restrictions do not apply, because the payload size is never more than 4B. * For all ingress VCnTs, the total header credit cannot exceed 32 in a port. * For all VCnTs in all four potential ports in a source station, the total payload credit cannot exceed 1376. The default ingress header credit threshold for VC0 posted, non-posted, and completion type are 5, 9, 5, respectively, and the default payload credit threshold for these three types are 88, 9, and 88 (accepting 1408B, 144B, 1408B payload, respectively). It is strongly recommended that to achieve better ingress throughput for a particular type, fine-tuning ingress credit thresholds is an indispensable step. For example, when the PEX 8524 is "talking" to an x8 graphics card, almost 28.5% throughput boost is observed by modifying the ingress header credit for VC0 posted, non-posted and completion type to be 15, 4, 13, and ingress payload credit to be 40, 4, and 40, respectively. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 75 Performance Metrics PLX Technology, Inc. Ingress Credit Threshold Programming There are two ways in which to change the ingress credit threshold, by way of a serial EEPROM or direct CSR programming. The first approach is straightforward - program the desired values and the link produces the programmed values. However, the latter approach requires further explanation. In the direct CSR programming approach, if a credit threshold requires an increase, perform a CSR write. This immediately results in a new UpdateFC to be transmitted carrying the newly increased credits. In contrast, if a credit threshold requires a decrease, the PCI Express Base 1.0a does not provide a predefined method to reclaim unused credit previously advertised to the external device. The danger of this is that excessive credits are advertised and the ingress queues overflow, losing data. Use the following approach to avoid data loss: * Upstream ports - Use CSR access to program the VCnTs whose credit requires a decrease. PR EL IM IN AR Y - Transmit "side-impact free" traffic from host to those VCnTs to deplete all credits to be reclaimed. Before the surplus credits are completely reclaimed, the PEX 8524 transmits UpdateFC for that VCnT. After the amount of incoming traffic attains the difference between the old and new credit thresholds, the PEX 8524 starts transmitting fresh UpdateFC DLLPs for incoming TLPs. * Downstream ports - Program all ingress credit threshold CSRs in all VCnTs to the desired values. - Execute a secondary bus reset in the Bridge Control register. - Release the reset. The newly programmed values take effect afterward. Ingress credit threshold registers are not sticky after a primary reset; therefore, this sequence requires repeating after any primary reset. 8.4.2.2 Egress Side Provide Sufficient Egress Credit The simplest way to improve an egress port's throughput is to allow the PEX 8524 sufficient egress credit. In general, the number of egress credit required by the PEX 8524 follows the same equation as the ingress credit calculation: Egress_Credit_Required = (Round_trip_time_in_clocks x link_width) / packet_size_in_bytes For the PEX 8524 to achieve pipelined performance, the external device is suggested to advertise at least two MPS worth of payload credits. For 128B MPS, the payload credit is larger than or equal to 16 (16 credits = 296B credit = 2 MPS). For 256B MPS, the payload credit must be larger than or equal to 32 (2 MPS). Without a 2 MPS credit, the PEX 8524 schedules one packet out, waits for the updateFC to return, then schedules the next packet out, although a packet's payload is smaller than MPS. Egress Schedulers Pick Frequency To simplify the egress scheduler design, one limitation incurred is that one packet can be scheduled out every other Clock cycle. This restriction does not cause a performance degradation. x8 Port PAD Slots When a port in the PEX 8524 is configured as an x8 port, only bytes belonging to one TLP are transmitted in single-symbol time. The residue lanes are filled with PAD. Also, for x8 ports, the PEX 8524 does not attempt to optimize throughput by placing a partial TLP and DLLP in single-symbol time. 76 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Multiple Stream Throughput 8.4.3 Multiple Stream Throughput 8.4.3.1 Enable PLX-Specific Relaxed Ordering The PEX 8524 does not support optional relaxed ordering bits in TLP as specified in the PCI Express Base 1.0a, Table 2-23. By default, all packets entering from a specific port are dispatched to their respective destinations, based on strict ordering. However, as described in Section 8.3.2.1, "Source Scheduler," the PEX 8524 provides its own relaxed ordering to overcome the packet-to-packet dependency in a burst of posted traffic from the same ingress port, but to different egress ports. 8.4.3.2 Avoid Hot Spots 8.4.4 PR EL IM IN AR Y When multiple ingress ports attempt to transmit packets to the same egress port, and the overall influx bandwidth outweigh the efflux bandwidth, a hot spot is formed. If the hot spot is not transient, the hot spot port throughput can appear high. However, eventually the egress queues fill, backpressuring the ingress queues. When the ingress queues fill, ingress traffic is backpressured, potentially impacting traffic flow not targeting the congested egress port. As a result, the switch overall average throughput is dramatically reduced. Throughput and Packet Size Relationship In general, sustained throughput increases as payload size increases due to the increased PCI Express protocol efficiency. However, the following second order effects can also affect throughput: * In peer-to-peer applications, longer packets can result in less interleaved or randomized egress port distribution compared to shorter packets. This increases the chance of building up transient congestion in egress ports and can negatively impact overall throughput. * Longer packets require fewer header credits per unit time, and are therefore less likely to idle the link while waiting for additional credit. * Posted packets block younger packets of other types (non-posted and completions). In a system with minimal credits, posted packets receive the strongest consideration when allocating credits. It is recommended to carefully compare the benefits and drawbacks of using longer packets. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 77 Performance Metrics PLX Technology, Inc. 8.4.5 Data Link Layer Considerations 8.4.5.1 Arbitration between DLLP and TLP To reduce DLLP overhead on the wire, the PEX 8524 uses the following fixed-priority scheme to determine what transmits next: 1. Packet completion of a TLP or DLLP currently in transmission. 2. Initialization of Flow Control (FC-Init) DLLPs. 3. NAK DLLP. 4. ACK DLLP, due to receipt of a duplicate TLP or ACK Latency Timer expiration.* 5. Update FC DLLP, due to the FC Update timer expiration. 6. Retry Buffer TLP, due to received Nak or Retry timeout. PR EL IM IN AR Y 7. New TLPs.* 8. Update FC DLLP, due to change in available credits.* 9. Power Management DLLP. 10. ACK DLLP for the last received TLP.* Among these ten categories, the four most frequently seen new packets are noted with an asterisk (*). Updated FC-Init and ACK DLLPs appear twice -- once as higher priority than TLPs, and once as lower priority than TLPS. A regular DLLP turns into a higher priority DLLP based on a programmable timer. The timers are discussed in the following sections. 8.4.5.2 DLLP ACK Frequency Control The ACK latency-limit register places a minimum amount of time (in clocks) that the switch waits before prioritizing an ACK. By setting this register to the minimum value of 2 (see note below), ACKs are transmitted with high priority, allowing the most DLLP traffic. Note: 2 is the minimum value that has an effect; 0 or 1 wait for 255 clocks. The larger the number written into this CSR, the larger the chance of ACK collapse, and the more efficient the outgoing TLP throughput. However, by setting the ACK Transmission Latency Limit to the maximum (255), 255 symbol times (4 ns each) follows before prioritizing an ACK. If the Retry buffer in the external device is not sufficiently deep, it can slow down the incoming TLP rate. On an x4 link, 1020B can be transmitted in 2.55 symbol times, which is 51 20B packets. Because programming a smaller value into this CSR decreases egress TLP throughput but can increase the ingress TLP throughput, a tradeoff must be addressed. If there is no TLP traffic, an ACK can be transmitted earlier than the timer indicates. (Refer to 1F8h, ACK Transmission Latency Limit register.) The initial value depends on the programmed link width. However, the value can be overwritten by serial EEPROM or a regular CSR write. 78 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 8.4.5.3 Data Link Layer Considerations DLLP UpdateFC Frequency Control An INCH FC Update Pending Timer register controls the amount of time a port can wait before prioritizing an UpdateFC DLLP. Before the timer expires, TLPs retain priority over UpdateFC DLLPs. After the timer expires, UpdateFC DLLPs retain higher priority. The value programmed into this CSR is only a counter expiration value. All six VCnTs in an ingress port share the same counter upper limit, but maintain their own counters to count up. (Refer to 9F4h, INCH FC Update Pending Timer register.) The smaller the value written into these registers, the sooner an UpdateFC DLLP becomes higher priority; therefore, the sooner it is transmitted. The sooner an UpdateFC is transmitted, the less likely the chance to collapse two VCnT UpdateFCs. Note: Each VC and type maintains its own UpdateFC. Only UpdateFCs for the same VCnT can be collapsed. The PCI Express Base 1.0a guidelines for the FC Update Pending Timer are provided in Table 8-5. PR EL IM IN AR Y For implementation, a 1 or 0 into the CSR, results in waiting 255 symbol times. Therefore, the smallest value is 2. The initial value of 0 is effectively 255 symbol times. Table 8-5. FC Update Pending Timer Guidelines Maximum Packet Size 128 bytes 256 bytes Link Width Default Timer Count x1 76h x2 80h x4 48h x8 42h x1 1A0h x2 D8h x4 76h x8 72h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 79 Performance Metrics PLX Technology, Inc. 8.5 Latency 8.5.1 Queuing Effect In switches with large internal buffers, the latency exponentially increases after internal queuing is developed. The packet at the end of an egress VCnT queue does not transmit until all packets in front of it are transmitted. Assume the egress RAM of an x4 port is packed with packets of the same VCnT, draining the entire egress RAM takes (512 beat x 20B per beat / 4B/clock) = 2560 clocks. The worst-case packet latency can be as low as 10 s. To overcome the queuing effect, attempt the following: * Avoid creating hot spots in application. In particular, ensure that the Upstream port width in a host-centric application matches the sum width of all Downstream ports. Otherwise, the Upstream port can easily become a hot spot when all Downstream ports are attempting to transmit packets to it. PR EL IM IN AR Y * Program a small egress queue packet upper and lower limit to avoid packet accumulation in an egress port. Section 8.3.2.4, "Internal Fabric Backpressure," describes how to program these thresholds. Note that the lower latency is achieved at the cost of reducing the PEX 8524's capability to buffer transient congestion. * Reduce traffic load. Lighter traffic is less likely to experience congestion and can quickly drain. 8.5.2 Time Division Multiplex Effect As illustrated earlier, the PEX 8524 source station employs port-to-station aggregation, and the destination station employs station-to-port de-aggregation. Both aggregation and de-aggregation are controlled by Time Division Multiplex (TDM). Usually, waiting for a proper TDM slot to process packet coming from or going to a particular port increases the latency. The wider the port, the more TDM slots that port owns; therefore, the less latency contributed by TDM. Within a station, only a subset of 16 lanes are connected to SerDes. One approach to reduce latency is to strap the port as a wider port and allow it to negotiate down to the expected link width. For example, if there is only an x2 port owned by a station, the port can be strapped as an x8 and allowed to become x2 later through normal link training process. As a result, all TDM slots in this station are acquired by the x2 port. The worst case TDM effect is 14 symbol times = 57 ns for an x1 or x2 port. 8.5.3 High-Priority Packets The previous sections discussed methods to optimize the latency in a single VC system. However, a better solution for some traffic scenarios that require consistently low latency is to use a different VC. The PEX 8524 does not support isochronous traffic which requires high priority packets by way of a switch with a time limit. However, it does provide a high-priority packet path throughout the entire switch if there are two VCs and VC1 is configured with higher priority compared to VC0 in both ingress and egress ports. VC1 includes independent credit, storage, and scheduling with respect to VC0. However, it shares the wires in and out of the switch. At any point where there may be congestion between the two VCs, VC1 is treated separately and preferentially to VC0. This occurs at the ingress queues, the internal fabric, and the egress queues. For contention, VC1 packets are given priority over VC0 packets. In this case, VC0 is earmarked for slower, bulk data transfer, and VC1 processes packets with a much shorter latency if there is no over-subscription. 80 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Smaller Size Packets Two conditions are required to make the high-priority path meaningful: * TC/VC mapping is symmetric across all ports * All ports configure the Low-Priority Extended VC Count as 0, in egress 14Ch (default) * Certain TCs map to VC1 (15Ch or 168h registers) * VC1 is enabled on ingress and egress ports 8.5.4 Smaller Size Packets The PEX 8524 uses a store-and-forward architecture. Without cut through, a packet must be completely written into the PEX 8524's internal packet RAM before the first byte of the packet can be transmitted out of the egress port. Fall-through latency is a function of the packet size; therefore, the shorter the packet size, the shorter the fall-through latency. The bulk of the latency is dictated by the amount of time it takes for the packet to arrive. Narrower ingress ports contain correspondingly higher latency than wider egress ports. Power Management PR EL IM IN AR Y 8.5.5 Saving power and optimizing latency are typically two conflicting tasks. Once a chip enters Power Saving mode, the wake-up time when new burst packets come in always contributes to latency. For latency sensitive applications, it is recommended to use software to turn off the ASPM L0s entrance/ exit, as well as L1 entrance/exit. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 81 PLX Technology, Inc. PR EL IM IN AR Y Performance Metrics 82 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 9 9.1 Power Management Power Management Capabilities The PEX 8524 Power Management (PM) module interface with chip sections to reduce power consumption. The PEX 8524 support hardware autonomous Power Management and software-driven D-State Power Management. It supports L0s and L1 link states in hardware autonomous active state Link PM. It also supports L1, L2/L3 Ready, and L3 PCI Express link states in PCI-compatible Power Management states. D0, D3hot, and D3cold device power states are supported in PCI-compatible Power Management. Because the PEX 8524 does not support AUX-Power, PME generation from D3cold is not supported. The PM module interfaces with Physical Layer electrical sub block to transition the Link State into low-power states when it receives a power state change request from a upstream component, or an internal event forces the Link State entry into low-power states in Hardware Autonomous PM (Active Link State PM) mode. PCI Express Link states are not directly visible to legacy bus driver software, but are derived from the Power Management state of the components residing on those links. The PEX 8524 Power Management controller functional block diagram is illustrated in Figure 9-1. Figure 9-1. Power Management Controller Functional Block Diagram Power Management Controller PM Event Hot Plug Controller Device State PME Handler Device States Link State Physical Layer Interface Control DLLP Receive Data Link Layer Interface TLP Egress Power Management CSR CSR Write Path CSR Read Path Link State Management DLLP Transmit Suspend Timers TLP Availability/Credits Message Write Message Control CSR, Interrupt, and Message Control Message Response PM_Message_Req Arb_Message_Ack PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Port Arbiter 83 Power Management 9.1.1 PLX Technology, Inc. PEX 8524 Power Management Capabilities Summary * Link Power Management State (L-States) - PCI Bus Power Management - L1, L2/L3readyand L3 (Auxiliary power not supported) - Active State Power Management - L0s and L1 * Device Power Management State (D-States) - D0 (D0_uninitialized and D0_active) and D3 (D3hot and D3cold) support * Power Management Event (PME) support from D3hot * Power Management Event due to Hot Plug events * Downstream Ports generate and forward PME_Turn_Off broadcast messages 9.1.2 Device Power States 9.1.2.1 PR EL IM IN AR Y The PEX 8524 supports the PCI Express PCI-PM D0, D3hot, and D3cold (no VAUX) device Power Management states. The D1 and D2 states, which are optional in the PCI Express Base 1.0a, are not supported by the PEX 8524. D0 State D0 is divided into two distinct sub-states, the "un-initialized" sub-state and the "active" sub-state. When power is initially applied to a PCI Express component, it defaults to the D0_uninitialized state. The component remains in the D0_uninitialized state until the serial EEPROM loading and initial link training are completed. A device enters the D0_active state when any one or combination of the following is set by system software: * Memory Space Enable * I/O Space Enable * Bus Master Enable D3hot state A device in a D3hot state must be able to respond to configuration accesses to be transitioned by software to the D0_uninitialized state. Once in a D3hot state, the device can later be transitioned into the D3cold state, by removing power from the device. When in the D3hot state, Hot Plug operations cause a PME event in the PEX 8524. D3cold State The PEX 8524 transitions to the D3cold state when power is removed. Re-applying power causes the PEX 8524 to transition from the D3cold state into D0_uninitialized, followed by a configuration and the link training sequence. The D3cold state assumes that all previous context is lost; therefore, software must save the required context while the PEX 8524 remains in the D3hot state. 84 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 9.1.3 Link Power Management State Link Power Management State The Power Management state of a link is determined by the D-state of its downstream link. The PEX 8524 switch retains its upstream and downstream links in L0 state when it is in normal operational mode (PCI PM state in D0_active). Active-State Link Power Management defines a protocol for components in the D0 state to reduce link power by placing their links into a low-power state and instructs the other end of the link to do likewise. This capability allows hardware autonomous, dynamiclink power reduction beyond what is achievable by Software-Only Power Management. Table 9-1 depicts the relationship between a PEX 8524 power state and its downstream link. Table 9-1. Power States of Connected Link Components Downstream Component D State D State Permissible Interconnect State Power Saving Actions L0 Full power L0s, L1 (optional) PHY Transmit lanes in high-impedance state D0 D1 D0 L1 D0 L1 D0 or D3hota L1, L2/L3 ready PHY Transmit lanes in high-impedance state FC and DLL ACK/NACK timers suspended, PLL may be disabled D0, D3hot or D3cold L3 Link-off State No power to component D2 D3hot D3cold (no AUX-Pwr) PR EL IM IN AR Y D0 PHY Transmit lanes in high-impedance state a. The PEX 8524 initiates a Link-state transition of its Upstream port to L1 when the port is programmed to D3hot. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 85 Power Management 9.1.4 PLX Technology, Inc. PEX 8524 PCI Express Power Management Support The PEX 8524 supports PCI Express features which are required or important for PCI Express Switch Power Management. Table 9-2 lists supported and non-supported features and the register bits used for configuration or activation. PCI Express Power Management Capabilities Supported Register Offset Bit(s) Supported Yes No 7:0 Capability ID Set to 01h as required by the PCI Power Mgmt. r1.1. 15:8 Next Pointer Default 48h points to the Message Signaled Interrupt Control register. 18:16 Version Default 010b indicates compliance with the PCI Power Mgmt. r1.1. 19 PME Clock Set to 0b as required by the PCI Express Base 1.0a. 21 Device-Specific Initialization Default 0b indicates that Device Specific Initialization is not required. AUX Current Default 000b indicates that the PEX 8524 does not support Auxiliary Current requirements. 25 D1 Support Default 0b indicates that the PEX 8524 does not support D1 power state. 26 D2 Support Default 0b indicates that the PEX 8524 does not support D2 power state. 40h 24:22 31:27 86 Description PR EL IM IN AR Y Table 9-2. PME Support Default 11001b indicates the corresponding PEX 8524 port forwards PME Messages in the D0, D3hot, and D3cold power states. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Table 9-2. PEX 8524 PCI Express Power Management Support PCI Express Power Management Capabilities Supported (Cont.) Register Offset Description Bit(s) Supported Yes No Power Management Status and Control 1:0 8 Power State PEX 8524 reports the power state of its corresponding ports. 00b = D0 01b and 10b not supported 11b = D3hot PME Enable 0b = Disables PME generation by corresponding PEX 8524 port 1b = Enables PME generation by corresponding PEX 8524 port Data Select PR EL IM IN AR Y 12:9 R/W by Serial EEPROM mode onlyb. Bits [12:9] select the Data and Data Scale registers. 0h = D0 power consumed 3h = D3hot power consumed 4h = D0 power dissipated 7h = D3hot power dissipated RO for hardware auto configuration. Not Supported. 44h Data Scale 14:13 15 R/W by Serial EEPROM mode onlyb. There are four internal Data Scale registers per port. Bits [12:9], Data Select, select the Data Scale register. PME Status 0b = PME is not generated by corresponding PEX 8524 port 1b = PME is generated by corresponding PEX 8524 port PM Control/Status Bridge Extensions 22 23 B2/B3 Support Set to 0b as required by the PCI Power Mgmt. r1.1. Bus Power/Clock CNTRL Enable Set to 0b as required by the PCI Power Mgmt. r1.1. Data Data 31:24 R/W by Serial EEPROM mode onlya. There are four internal Data registers per port. Bits [12:9], Data Select, select the Data register. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 87 Power Management Table 9-2. PCI Express Power Management Capabilities Supported (Cont.) Register Offset PLX Technology, Inc. Bit(s) Description Supported Yes No Device Capabilities Register 8:6 11:9 Endpoint L0s Acceptable Latency Endpoint L1 Acceptable Latency Because the PEX 8524 is a switch and not an endpoint, it does not support these features. 000b = Disables the capability for each feature. 13 Attention Indicator Present (Upstream Port) For PEX 8524 Upstream ports, when 1b, indicates that an Attention Indicator is implemented on the adapter card. PEX 8524 EEPROM register initialization capability is used to change this value to 0b, indicating an Attention Indicator is not present on an adapter card for which PEX 8524 provides the system interface. Do not change this bit for Downstream ports. 14 Power Indicator Present (Upstream Port) For PEX 8524 Upstream ports, when 1b, indicates that a Power Indicator is implemented on the adapter card. PEX 8524 EEPROM register initialization capability is used to change this value to 0b, indicating that a Power Indicator is not present on an adapter card for which PEX 8524 provides the system interface. Do not change this bit for Downstream ports. 25:18 Captured Slot Power Limit Value (Upstream Port) For PEX 8524 Upstream ports, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the Captured Slot Limit Power Scale (Upstream Port) field. Do not change these bits for Downstream ports 27:26 Captured Slot Limit Power Scale (Upstream Port) For PEX 8524 Upstream ports, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the Captured Slot Power Limit Value (Upstream Port) field. 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 Do not change these bits for Downstream ports. 6Ch PR EL IM IN AR Y 12 Attention Button Present (Upstream Port) For PEX 8524 Upstream ports, when 1b, indicates that an Attention Button is implemented on that adapter card. PEX 8524 EEPROM register initialization capability is used to change this value to 0b, indicating that an Attention Button is not present on an adapter card for which PEX 8524 provides the system interface. Do not change this bit for Downstream ports. Device Status and Control Register 10 AUX Power PM Enable PEX 8524 does not support this function and sets AUX Power PM Enable to 0b, per port. 20 AUX Power Detected PEX 8524 does not support this function and sets AUX Power Detected to 0b, per port. 70h 88 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Table 9-2. PEX 8524 PCI Express Power Management Support PCI Express Power Management Capabilities Supported (Cont.) Register Offset Bit(s) Description Supported Yes No Link Capabilities Register 11:10 Active-State Power Management Support 01b = NT port, when enabled, supports the L0s link power state 11b = Corresponding PEX 8524 port supports the L0s and L1 Link power states 14:12 L0s Exit Latency 101b = Corresponding PEX 8524 port L0s Exit Latency is between 1 and 2 s 17:15 L1 Exit Latency 101b = Corresponding PEX 8524 port L1 Exit Latency is between 16 and 32 s 74h Link Status and Control Register 78h 1:0 PR EL IM IN AR Y Active-State Power Management Control 00b = Disables L0s and L1 Entry for corresponding PEX 8524 portb 01b = Enables L0s Entry 10b = Enables L1 Entry 11b = Enables L0s and L1 Entry PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 89 Power Management Table 9-2. PCI Express Power Management Capabilities Supported (Cont.) Register Offset PLX Technology, Inc. Bit(s) Description Supported Yes No Slot Capabilities Register 1 Power Controller Present (Downstream Port) 0b = Power Controller is not implemented. 1b = Power Controller is implemented for the slot of the corresponding PEX 8524 Downstream port. Do not change for Upstream ports. 2 MRL Sensor Present (Downstream Port) 0b = MRL Sensor is not implemented. 1b = MRL Sensor is implemented on the slot chassis of the corresponding PEX 8524 Downstream port. Do not change for Upstream ports. 3 Attention Indicator Present (Downstream Port) 0b = Attention Indicator is not implemented. 1b = Attention Indicator is implemented on the slot chassis of the corresponding PEX 8524 Downstream port. Do not change for Upstream ports. 4 Power Indicator Present (Downstream Port) 0b = Power Indicator is not implemented. 1b = Power Indicator is implemented on the slot chassis of the corresponding PEX 8524 Downstream port. Do not change for Upstream ports. 5 Hot Plug Surprise (Downstream Port) 0b = No device in the corresponding PEX 8524 Downstream port slot is removed from the system without prior notification. 1b = Device in the corresponding PEX 8524 Downstream port slot can be removed from the system without prior notification. Do not change for Upstream ports. 6 Hot Plug Capable (Downstream Port) 0b = Corresponding PEX 8524 Downstream port slot is not capable of supporting Hot Plug operations. 1b = Corresponding PEX 8524 Downstream port slot is capable of supporting Hot Plug operations. Do not change for Upstream ports. 14:7 Slot Power Limit Value (Downstream Port) The max power available from the corresponding PEX 8524 Downstream port is determined by multiplying the value in this field (expressed in decimal; 25d = 19h) by the value specified by the Slot Power Limit Scale (Downstream Port). Do not change for Upstream ports. 7Ch 90 PR EL IM IN AR Y 0 Attention Button Present (Downstream Port) 0b = Attention Button is not implemented. 1b = Attention Button is implemented on the slot chassis of the corresponding PEX 8524 Downstream port. Do not change for Upstream ports. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Table 9-2. PEX 8524 PCI Express Power Management Support PCI Express Power Management Capabilities Supported (Cont.) Register Offset 7Ch Bit(s) 16:15 Description Slot Power Limit Scale (Downstream Port) The max power available from the corresponding PEX 8524 Downstream port is determined by multiplying the value in this field by the Slot Power Limit Value (Downstream Port). 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x Do not change for Upstream ports. Supported Yes No Slot Status and Control Register (for Downstream Ports) 9:8 80h 10 17 Power Indicator Control (Downstream Port) Controls the Power Indicator on the corresponding PEX 8524 Downstream port slot: 00b = Reserved - Do not use 01b = Turns ON indicator to constant ON state 10b = Causes indicator to BLINK 11b = Turns OFF indicator Writes cause the corresponding PEX 8524 Downstream port to transmit the appropriate Power Indicator message. Reads return to corresponding PEX 8524 Downstream port's Power indicator's current state. Do not change for Upstream ports. Power Controller Control (Downstream Port) Controls the Power Controller on the corresponding PEX 8524 Downstream port slot: 0b = Turns ON Power Controller 1b = Turns OFF Power Controller Do not change for Upstream ports. Power Fault Detected (Downstream Port) Set to 1b, when the Power Controller of the corresponding PEX 8524 Downstream port slot detects a Power Fault at the slot. Do not change for Upstream ports. PR EL IM IN AR Y 1 Power Fault Detected Enable (Downstream Port) 0b = Function is disabled. 1b = Enables a Hot Plug Interrupt or Wake-up event on a Power Fault event on the corresponding PEX 8524 Downstream port. Do not change for Upstream ports. Device Power Budgeting Extended Capability Register 138h 15:0 Extended Capability ID Set to 0004h as required by the PCI Express Base 1.0a. 19:16 Capability Version Set to 1h as required by the PCI Express Base 1.0a. 31:20 Next Capability Offset Set to 148h, which addresses the PEX 8524 Device Serial Number for the Extended Capability registers. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 91 Power Management Table 9-2. PLX Technology, Inc. PCI Express Power Management Capabilities Supported (Cont.) Register Offset Description Bit(s) Supported Yes No Data Select Register 13Ch 7:0 Data Select Indexes the Power Budgeting Data reported by way of eight Data register and selects the DWORD of Power Budgeting Data that appears in the Data Register. Index values for this register start at 0 to select the first DWord of Power Budgeting Data; subsequent DWords of Power Budgeting Data are selected by increasing index values 1 to 7. Note: Power Data register - There are eight registers per port that can be programmed by way of the serial EEPROM. Each register retains a different port power configuration. Each configuration is selected by writing to the Data Select register Data Select bits.a 92 Base Power Specifies in watts the base power value in the operating condition.This value must be multiplied by the Data Scale to produce the actual power consumption value. 9:8 Data Scale Specifies the scale to apply to the Base Power value.The device power consumption is determined by multiplying the Base Power field contents with the value corresponding to the encoding returned by this field. Defined encodings are: 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x 12:10 PM Sub State 000b = Power Management sub-state of the operating condition. 14:13 PM State Power Management sub-state of the operating condition. 00b = D0 state 01b = Not used - D1 state not supported 10b = Not used - D2 state not supported 11b = D3 state 17:15 Type Type of operating condition: 000b = PME Auxiliary 001b = Auxiliary 010b = Idle 011b = Sustained 111b = Maximum All other values are Reserved. 20:18 Power Rail Operating condition power rail: 000b = Power is 12V 001b = Power is 3.3V 010b = Power is 1.8V 111b = Thermal All other values are Reserved. PR EL IM IN AR Y 140h 7:0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Table 9-2. PEX 8524 PCI Express Power Management Support PCI Express Power Management Capabilities Supported (Cont.) Register Offset Description Bit(s) Supported Yes No Power Budget Capability Register 144h 0 System Allocated 1b = Power budget for the device is included within the system power budget Power Management Hot Plug User Configuration Register 1 L1 Upstream Port Receiver Idle Count For active L1 entry: 0b = Upstream port receiver idle for 2 ms 1b = Upstream port receiver idle for 3 s HPE PME Turn-Off Enable HPC PME Turn-off enable: 1b = PME Turn-off message is transmitted before the port is turned-off on Downstream port HPC TPEPV Enable Slot power-applied to power-valid delay time: 00b = 16 ms 01b = 32 ms 10b = 64 ms 11b = 128 ms HPC Inband Presence-Detect Enable 0b = HP_PRSNT[3:0]# or HP_PRSNT[11:8]# input balls are used to detect a card present in the slot 1b = SerDes receiver detect mechanism is used to detect a card present in the slot HPC TPVPERL Downstream port power-valid to reset signal release time: 0b = 20 ms 1b = 100 ms (default) 2 1E0h 4:3 5 6 PR EL IM IN AR Y 0 L0s Entry Idle Count Time to meet to enter L0s: 0b = Idle condition lasts for 1 s 1b = Idle condition lasts for 4 s a.With no serial EEPROM, reads return 0h for Data Scale and Data registers (for all Data Selects). b.The port receiver must be capable of entering L0s state even when disabled. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 93 PLX Technology, Inc. PR EL IM IN AR Y Power Management 94 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 10 10.1 PEX 8524 Port Registers Introduction This chapter details the PEX 8524 port registers. The PEX 8524 ports include their own configuration, capability, control, and status register space. The register mapping is the same for each port (as delineated in Table 10-1). This chapter also presents PEX 8524 user-programmable registers and the order in which they appear in the register map. Register descriptions, when applicable, include details regarding their use and meaning in the Upstream and Downstream ports. (Refer to the Memory map in Figure 10-1.) NT port registers are discussed in Chapter 14, "NT Port Virtual Interface Registers," and Chapter 15, "NT Port Link Interface Registers." For additional information regarding register names and descriptions, refer to the following specifications: * PCI r2.3 * PCI Express Base 1.0a * PCI Power Mgmt. r1.1 * PCI ExpressCard 1.0a * PCI HotPlug 1.1 * PCI Standard Hot Plug r1.0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 95 PEX 8524 Port Registers 10.2 PLX Technology, Inc. Type 1 PEX 8524 Port Register Map Table 10-1. Type 1 PEX 8524 Port Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h Configuration Header Registers ... Capability Pointer (40h) 34h ... 3Ch Next Capability Ptr (48h) Capability ID (01h) Power Management Capability Registers PR EL IM IN AR Y Next Capability Ptr (68h) 40h 44h Capability ID (05h) 48h ... Message Signaled Interrupt Capability Registers Next Capability Ptr (00h) 54h Capability ID (10h) 68h ... PCI Express Capabilities Registers Reserved Next Capability Offset (FB4h) 1h Extended Capability ID (0003h) 80h 84h ... FFh 100h 104h Device Serial Number Extended Capability Registers Reserved Next Capability Offset (148h) 1h Extended Capability ID (0004h) 108h 10Ch ... 134h 138h ... Device Power Budgeting Extended Capability Registers 144h Next Capability Offset (000h) 1h Extended Capability ID (0002h) 148h ... Virtual Channel Extended Capability Registers 1C4h 1C8h Reserved ... FB0h Next Capability Offset (138h) 1h Extended Capability ID (0001h) FB4h ... Advanced Error Reporting Capability Registers (All Ports) FFFh 96 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 10.3 PEX 8524 Port Register Configuration and Map PEX 8524 Port Register Configuration and Map The PEX 8524 port registers are configured similarly - not all the same. Port 0 of Station 0 and Port 8 of Station 1 include more device-specific registers than the other station ports. These two registers contain setup and control information specific to the station. Also, Port 0 of Station 0 contains registers used to setup and control the routing logic in the switch, and serial EEPROM interface logic and control. The register map for these ports is delineated in Table 10-2. (Refer to Appendix A, "Serial EEPROM Memory Map," for a detailed description of this register map.) Table 10-2. PEX 8524 Port Register Types and Map Station 0, Port 0 Station 1, Port 8 Station 0, Port 1 Station 1, Ports 9, 10, 11 Configuration Header 000h - 03Ch 000h - 03Ch 000h - 03Ch Power Management Capability 040h - 044h 040h - 044h 040h - 044h PR EL IM IN AR Y Register Types Message Signaled Interrupt Capability 048h - 054h 048h - 054h 048h - 054h PCI Express Capabilities 068h - 080h 068h - 080h 068h - 080h Device Serial Number Extended Capability 100h - 108h 100h - 108h 100h - 108h Device Power Budgeting Extended Capability 138h - 144h 138h - 144h 138h - 144h Virtual Channel Extended Capability 148h - 1C4h 148h - 1C4h 148h - 1C4h 1C8h 1C8h 1CCh - 1D0h 1CCh - 1D0h 1CCh - 1D0h 1E0h - 1F8h Error Check Disable Error Handler Debug Registers 1D4h - 1DCh Power Management, Hot Plug and Miscellaneous Control 1E0h - 1F8h 1E0h - 1F8h Physical Layer 210h - 25Ch 210h - 25Ch EEPROM Bus Number CAM Station 0 260h - 264h 2C8h - 2D4h Bus Number CAM Station 1 I/O CAM Station 0 I/O CAM Station 1 AMCAM Memory Base and Limit TIC I/O CAM (upper) Station 0 2E8h - 2F4h 308h - 30Ch 318h - 31Ch 348h - 384h 3C8h - 404h 660h and 668h 660h and 668h 680h - 68Ch I/O CAM (upper) Station 1 Station 0 BAR 6A0h - 6ACh 6C0h - 6DCh Station 1 BAR Virtual Channel Station 0 700h - 71Ch 740h - 75Ch 840h - 84Ch 780h - 79Ch 860h - 86Ch Virtual Channel Station 1 Ingress Credit Handler (INCH) 9F4h - A5Ch 9F4h- A5Ch PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential A00h - A5Ch 97 PEX 8524 Port Registers PLX Technology, Inc. Table 10-2. PEX 8524 Port Register Types and Map (Cont.) Station 0, Port 0 Station 1, Port 8 Station 0, Port 1 Station 1, Ports 9, 10, 11 C00h - C08h C00h - C08h C00h - C08h C3Ch - DF8h C3Ch - DF8h FB4h - FDCh FB4h - FDCh Register Types Internal Credit Handler (ITCH) BAR Translation and Setup Register and Lookup Table Entry Advanced Error Reporting Capability 10.4 FB4h - FDCh Register Access The PEX 8524 supports two methods for accessing registers: * PCI Express Base 1.0a Configuration Mechanism 10.4.1 PR EL IM IN AR Y * PLX-Specific Memory-Mapped Configuration Space Access Mechanism PCI Express Base 1.0a Configuration Mechanism The PCI Express Base 1.0a Configuration mechanism provides standard access to the PEX 8524 ports' first 256 bytes (the bytes at offsets 00h through FFh) of the Configuration Register space, and PCI Express Extended Capability registers. This method is used to access the PEX 8524 port Type 1 (PCI-to-PCI Bridge) registers: * Configuration Header Registers * Power Management Capability Registers * Message Signaled Interrupt Capability Registers * PCI Express Capabilities Registers The PCI r2.3-Compatible Configuration mechanism uses PCI Type 0 and Type 1 Configuration transactions to access the PEX 8524 ports' configuration registers. The PEX 8524 Upstream port captures the Device Number assigned by the upstream device on the PCI Express link attached to the PEX 8524 Upstream port, as required by the PCI Express Base 1.0a. The PEX 8524 decodes all Type 1 Configuration accesses received on its Upstream port: * If the Bus Number specified in the Configuration access is the number of the PEX 8524 internal Virtual PCI Bus, the PEX 8524 automatically converts the Type 1 configuration access into the appropriate Type 0 configuration access for the specified device. * If the specified device corresponds to the PCI-to-PCI Bridge in one of the PEX 8524 Downstream ports, the PEX 8524 processes the Read or Write request to the specified Downstream port register specified in the original Type 1 Configuration access. * If the specified Device Number does not correspond to any of the PEX 8524 Downstream port Device Numbers, the PEX 8524 responds with an "unsupported request." * If the Bus Number specified in the Type 1 configuration access is not the number of the PEX 8524 internal virtual PCI bus, but is the number of one of the PEX 8524 Downstream port secondary/ subordinate buses, the PEX 8524 passes the configuration access onto the PCI Express link attached to that PEX 8524 Downstream port. * If the specified Bus Number is the Downstream port secondary Bus Number, and specified Device Number is 0, the PEX 8524 converts the Type 1 configuration access to a Type 0 configuration access before passing it on. 98 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PLX-Specific Memory-Mapped Configuration Space Access Mechanism * If the specified Device Number is not 0, the Downstream port drops the TLP and generates an "unsupported request" (UR). * If the specified Bus Number is not the Downstream port secondary Bus Number, the PEX 8524 passes the Type 1 Configuration access on without change. Because the PCI r2.3-Compatible Configuration mechanism is limited to the first 256 bytes of the Configuration register space of the PEX 8524 ports, the PCI Express Enhanced Configuration mechanism or PLX-Specific Memory-Mapped Configuration Space Access mechanism (described in the next section) must be used to access beyond byte FFh. 10.4.2 PLX-Specific Memory-Mapped Configuration Space Access Mechanism PR EL IM IN AR Y The PLX-Specific Memory-Mapped Configuration Space Access mechanism provides a method to access the Configuration registers of each port in a single Memory map, as illustrated in Figure 10-1. The port registers are contained within a 4-KB range. The PEX 8524 supports up to six simultaneously active ports. The PEX 8524 requires a single contiguous Memory space of 128 KB to contain all of the PEX 8524 configuration registers, and sufficient Memory space to support software compatibility for future device expansion. To use the PLX-Specific Memory-Mapped Configuration Space Access mechanism, program the Type 1 Configuration Space Base Address 0 and Base Address 1 registers. After the PEX 8524 Upstream port Memory-Mapped register base address is set, the Upstream port registers can be accessed with memory reads from and writes to the first 4 KB, and the PEX 8524 Downstream port 01h device registers can be accessed with Memory reads from and writes to the second 4 KB, and so forth. Within each of these 4-KB windows, individual registers are located at the DWord offsets indicated in Table 10-1. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 99 PEX 8524 Port Registers PLX Technology, Inc. Figure 10-1. PEX 8524 Memory Map PEX 8524 Port 0 0K 4K Port 1 8K 12K Reserved 16K 32K Port 8 36K Port 9 Port 10 44K PR EL IM IN AR Y Port 11 40K 48K Reserved 64K NT-Port Virtual Interface NT-Port Link Interface 68K 72K Reserved 128K 10.5 Register Descriptions The following sections detail the PEX 8524 registers, including: * Bit/field names * Register function in the PEX 8524 upstream and Downstream ports description * Type * Default power-on/reset value * Whether the power on/reset value can be modified by way of the PEX 8524 serial EEPROM initialization feature * Relevant specifications 100 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers 10.6 Configuration Header Registers Table 10-3. Type 1 Configuration Space Header Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEVICE ID VENDOR ID 00h Status Bits Command Bit(s) 04h Class Code BIST HEADER TYPE 08h CACHE LINE SIZE 0Ch Base Address 0 10h Base Address 1 14h SUBORDINATE Bus Number SECONDARY Bus Number PR EL IM IN AR Y SECONDARY LATENCY TIMER PRIMARY LATENCY TIMER REVISION ID Secondary Status PRIMARY Bus Number 18h I/O Base 1Ch I/O Limit MEMORY LIMIT Address[31:20] MEMORY BASE Address[31:20] 20h PREFETCHABLE MEMORY LIMIT Address[31:20] PREFETCHABLE MEMORY BASE Address[31:20] 24h Prefetchable Memory Upper Base Address[63:32] 28h Prefetchable Memory Upper Limit Address[63:32] 2Ch I/O LIMIT UPPER 16 BITS I/O BASE UPPER 16 BITS Reserved 30h CAPABILITIES POINTER Expansion ROM Base Address Bridge Control and Interrupt Signal Interrupt Pin 34h 38h Interrupt Line 3Ch Register 10-1. 00h Product Identification (All Ports) Type Serial EEPROM Default 15:0 Vendor ID Unless overwritten by the serial EEPROM, returns the PLX PCI-SIG assigned Vendor ID, for each port. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX Vendor ID with another Vendor ID. HwInit Yes 10B5h 31:16 Device ID Unless overwritten by the serial EEPROM, the PEX 8524 returns 8524h, the PLX-assigned Device ID. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX-assigned Device ID with another Device ID. HwInit Yes 8524h Bit(s) Description PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 101 PEX 8524 Port Registers PLX Technology, Inc. Register 10-2. 04h Command/Status (All Ports) Type Serial EEPROM Default 0 I/O Access Enable 0b = PEX 8524 ignores I/O accesses on the corresponding port's primary interface. 1b = PEX 8524 responds to I/O accesses on the corresponding port's primary interface. R/W Yes 0b 1 Memory Access Enable 0b = PEX 8524 ignores memory accesses on the corresponding port's primary interface. 1b = PEX 8524 responds to memory accesses on the corresponding port's primary interface R/W Yes 0b 2 Bus Master Enable Controls the PEX 8524 memory forwarding and I/O requests in the upstream direction. BUS MASTER ENABLE does not affect message forwarding nor completions in upstream or downstream direction. 0b = PEX 8524 handles memory and I/O requests received on the corresponding port downstream/secondary interface as Unsupported Requests (UR), and for Non-Posted Requests PEX 8524 return a Completion with UR completion status. 1b = PEX 8524 forwards memory and I/O requests. R/W Yes 0b 3 Special Cycle Enable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 4 Memory Write and Invalidate Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 5 VGA Palette Snoop Set to 0b as required by the PCI Express Base 1.0a. RO No 0b R/W Yes 0b RO No 0b R/W Yes 0b Bit(s) Description 6 7 PR EL IM IN AR Y Command Bit(s) Parity Error Response Enable Controls Master Data Parity Error bit. IDSEL Stepping/Write-Cycle Control Set to 0b as required by the PCI Express Base 1.0a. SERR# Enable 8 Controls the Signaled System Error bit. When 1b, enables reporting of non-fatal and fatal errors detected by the device to the Root Complex. 9 Fast Back-to-Back Transaction Enabled Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 10 Interrupt Disable 0b = Corresponding PEX 8524 port is enabled to generate INTx Interrupt messages 1b = Corresponding PEX 8524 port is prevented from generating INTx Interrupt messages R/W Yes 0b 15:11 102 Reserved 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers Register 10-2. 04h Command/Status (All Ports) (Cont.) Bit(s) Description Type Serial EEPROM Default Status Bits 18:16 Reserved 000b RO Yes 0b 20 Capabilities List Required by the PCI Express Base 1.0a to be 1b at all times. RO Yes 1b 21 66-MHz Capable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 22 Reserved 23 Fast Back-to-Back Transaction Enabled Set to 0b as required by the PCI Express Base 1.0a. PR EL IM IN AR Y 19 Interrupt Status 0 = No INTx Interrupt message is pending 1 = INTx Interrupt message is pending internally to the corresponding PEX 8524 port 0b RO No 0b R/W1C Yes 0b RO No 00b R/W1C Yes 0b Master Data Parity Error 24 26:25 If the Parity Error Response Enable bit = 1b, the corresponding PEX 8524 port sets this bit to 1b when it forwards the poisoned TLP write request from the Secondary Interface to Primary Interface, or receives a Completion marked poisoned on the Primary Interface. If the Parity Error Response Enable bit = 0b, the PEX 8524 never sets this bit. DEVSEL Timing Set to 00b as required by the PCI Express Base 1.0a. 27 Target Abort Signaled When a memory-mapped access payload length is greater than one DW, the PEX 8524 Upstream port sets this bit to 1b. 28 Target Abort Received Set to 0b. It is never set to 1b. RO No 0b 29 Master Abort Received Set to 0b. It is never set to 1b. RO No 0b R/W1C Yes 0b R/W1C Yes 0b Signaled System Error 30 31 If the SERR# Enable bit = 1b, the corresponding PEX 8524 port sets this bit to 1b when it transmits an ERR_FATAL or ERR_NONFATAL message to its upstream device. Detected Parity Error Set to 1b when the corresponding port receives a Poisoned TLP on its primary side, regardless of the Parity Error Response Enable bit state. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 103 PEX 8524 Port Registers PLX Technology, Inc. Register 10-3. 08h Class Code and Revision ID (All Ports) Bit(s) 7:0 Description Revision ID Unless overwritten by the serial EEPROM, returns BAh, the PLX-assigned Revision ID for this version of PEX 8524. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX Revision ID with another Revision ID. Type Serial EEPROM Default RO Yes BAh Class Code 31:8 15:8 Programming Interface PEX 8524 port supports the P-to-P Bridge r1.1 requirements, but not subtractive decoding on its upstream interface. 23:16 Sub-Class Code PCI-to-PCI bridge. 31:24 Base Class Code Bridge Device. 060400h 00h RO Yes PR EL IM IN AR Y 04h 06h Register 10-4. 0Ch Miscellaneous Control (All Ports) Bit(s) Description Type Serial EEPROM Default 7:0 Cache Line Size Implemented as a read-write field for legacy compatibility purposes and does not impact PEX 8524 functionality. R/W Yes 00h 15:8 Primary Latency Timer Set to 00h as required by the PCI Express Base 1.0a. RO No 00h 22:16 Header Type Corresponding PEX 8524 port configuration space header adheres to the Type 1 PCI-to-PCI Bridge Configuration Space layout defined by the P-to-P Bridge r1.1. 23 31:24 104 01h Multi-function Always 0b, because PEX 8524 is a single-function device. RO Yes 0b BIST Not Supported. RO No 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers Register 10-5. 10h Base Address 0 Register (All Ports) Bit(s) 2:1 3 Type Serial EEPROM Memory Space Indicator When enabled, the Base Address register maps the corresponding PEX 8524 port Configuration registers into Memory space. Upstream RO Yes Downstream RO No Memory Map Type 00b = Corresponding PEX 8524 port Configuration registers can be mapped anywhere in 32-bit memory addressing space 10b = Corresponding PEX 8524 port Configuration registers can be mapped anywhere in 64-bit memory addressing space 01b, 11b = Reserved Upstream RO Yes Downstream RO No Prefetchable Base Address register maps the corresponding PEX 8524 port Configuration registers into non-prefetchable memory space by default. Upstream RO Yes RO No PR EL IM IN AR Y 0 Ports Description 16:4 Reserved 31:17 Base Address Base Address for PEX 8524-specific Memory-Mapped Configuration-Space Access mechanism. Downstream Default 0b 00b 0b 0-0h Upstream R/W Yes Downstream RO No 0000h Register 10-6. 14h Base Address 1 (All Ports) Bit(s) 31:0 Description Base Address 1 For 64-bit addressing (Base Address 0 MEMORY MAP TYPE = 10b), Base Address 1 extends Base Address 0 to provide the upper 32 Address bits. Ports Type Serial EEPROM Upstream R/W Yes Downstream RO No Default 0000_0000h Register 10-7. 18h Bus Number (All Ports) Bit(s) Description Type Serial EEPROM Default 7:0 Primary Bus Number Records the Bus Number of the PCI Bus segment to which the primary interface of this port is connected. Set by Configuration software. R/W Yes 00h 15:8 Secondary Bus Number Records the Bus Number of the PCI Bus segment that is the secondary interface of this port. Set by Configuration software. R/W Yes 00h 23:16 Subordinate Bus Number Records the Bus Number of the highest numbered PCI Bus segment that is subordinate to this port. Set by Configuration software. R/W Yes 00h 31:24 Secondary Latency Timer Set to 00h as required by the PCI Express Base 1.0a. RO No 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 105 PEX 8524 Port Registers PLX Technology, Inc. Register 10-8. 1Ch Secondary Status (All Ports) Bit(s) Description Type Serial EEPROM Default I/O Base I/O Base Addressing Capability 1h = 32-bit Addressing decoding is supported. Other values not allowed. RO Yes 1h 7:4 I/O Base Address[15:12] PEX 8524 ports use their I/O Base and I/O Limit registers to determine the address range of I/O transactions to forward from the primary interface to the secondary interface. I/O Base Address[15:12] bits specify the corresponding PEX 8524 port I/O Base Address[15:12]. PEX 8524 assumes I/O Base Address[11:0] = 000h. For 16-bit I/O addressing, PEX 8524 assumes address[31:16] = 0000h. For 32-bit addressing, the PEX 8524 decodes address[31:0], and uses the I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits. R/W Yes Fh PR EL IM IN AR Y 3:0 I/O Limit 11:8 I/O Limit Addressing Capability 1h = 32-bit Addressing decoding is supported Other values not allowed. RO Yes 1h 15:12 I/O Limit Address[15:12] PEX 8524 ports use their I/O Base and I/O Limit registers to determine the address range of I/O transactions to forward from the primary interface to the secondary interface. I/O Limit Address[15:12] specify the corresponding PEX 8524 port I/O Limit Address[15:12]. PEX 8524 assumes address bits [11:0] of the I/O Limit Address are FFFh. For 16-bit I/O addressing, PEX 8524 decode address bits 31:16 and assume address bits 31:16 of the I/O Limit Address are 0000h. For 32-bit addressing, PEX 8524 decode address bits 31:0, and use the I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits. If the I/O Limit Address is less than the I/O Base Address, the PEX 8524 does not forward I/O transactions from the corresponding port primary/upstream bus to its secondary/downstream bus. However, PEX 8524 forwards all I/O transactions from the secondary bus of the corresponding port to its primary bus. R/W Yes 0h 106 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers Register 10-8. 1Ch Secondary Status (All Ports) (Cont.) Bit(s) Description Type Serial EEPROM Default Secondary Status 20:16 Reserved 0-0h 21 66-MHz Enabled 0b = Not enabled, as PCI Express does not support 66 MHz 22 Reserved 23 Fast Back-to-Back Transaction Enabled 0b = Not enabled, as PCI Express does not support this function RO No 0b 0b RO No 0b R/W1C Yes 0b RO No 00b Master Data Parity Error PR EL IM IN AR Y 24 If the Parity Error Enable bit 4 = 1b, the corresponding PEX 8524 port sets this bit to 1b when it transmits or receives a TLP on its downstream side, and when either of the following two conditions occur: * Port receives Completion marked poisoned * Port forwards poisoned TLP write request If the Parity Error Enable bit = 0b, the PEX 8524 never sets this bit. 26:25 DEVSEL Timing Set to 00b as required by the PCI Express Base 1.0a. 29:27 Reserved 000b 30 Received System Error Set to 1b when a port receives an ERR_FATAL or ERR_NONFATAL message on its secondary interface. R/W1C Yes 0b 31 Detected Parity Error Set to 1b by the Secondary Side for a Type 1 Configuration Space Header device whenever it receives a poisoned TLP, regardless of the Parity Error Enable bit state. R/W1C Yes 0b Note: PEX 8524 ports use the Memory Base and Memory Limit registers to determine the address range of Memory-Mapped I/O transactions to forward from one of its interfaces to the other. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 107 PEX 8524 Port Registers PLX Technology, Inc. Register 10-9. 20h Memory Base and Limit Address (All Ports) Bit(s) Description 3:0 Reserved 15:4 Memory Base Address[31:20] Memory Base Address[31:20] specify the corresponding PEX 8524 port Memory Base Address[31:20]. PEX 8524 assumes Memory Base Address[19:0] = 00000h. 19:16 Reserved 31:20 Memory Limit Address[31:20] Memory Limit Address[31:20] specify the corresponding PEX 8524 port non-prefetchable Memory Limit Address[31:20]. PEX 8524 assume Memory Limit Address[19:0] = FFFFFh. Type Serial EEPROM Default 0h R/W Yes FFFh 0h PR EL IM IN AR Y R/W Yes 000h Note: PEX 8524 ports use their Prefetchable Memory Base and Prefetchable Memory Limit fields to determine the address range of Prefetchable Memory transactions to forward from one of its interfaces to the other. Register 10-10. 24h Prefetchable Memory Base and Limit Addressing (All Ports) Bit(s) Description Type Serial EEPROM Default 3:0 Prefetchable Memory Base Capability 1h = Corresponding PEX 8524 port defaults to 64-bit Prefetchable Memory Addressing support. RO Yes 1h 15:4 Prefetchable Memory Base Address[31:20] Prefetchable Memory Base Address[31:20] specifies the corresponding PEX 8524 port Prefetchable Memory Base Address[31:20]. PEX 8524 assumes Prefetchable Memory Base Address[19:0] = 00000h. Note: If the Prefetchable Memory Limit Address is less than the Prefetchable Memory Base Address, PEX 8524 does not forward Prefetchable Memory transactions from the corresponding port's upstream bus to its downstream bus. However, PEX 8524 forwards all Memory transactions from the corresponding port's downstream bus to its upstream bus. R/W Yes FFFh 19:16 Prefetchable Memory Limit Capability 1h = Corresponding PEX 8524 port defaults to 64-bit Prefetchable Memory Addressing support RO Yes 1h 31:20 Prefetchable Memory Limit Address[31:20] Prefetchable Memory Limit Address[31:20] specifies the corresponding PEX 8524 port Prefetchable Memory Base Address[31:20]. PEX 8524 assumes Prefetchable Memory Base Address[19:0] = FFFFFh. R/W Yes 000h 108 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers Register 10-11. 28h Prefetchable Memory Upper Base Address[63:32] (All Ports) Bit(s) 31:0 Description Prefetchable Memory Base Address[63:32] PEX 8524 uses this register for Prefetchable Memory Upper Base Address[63:32]. Type Serial EEPROM Default R/W Yes 0000_0000h Register 10-12. 2Ch Prefetchable Memory Upper Limit Address[63:32] (All Ports) Bit(s) Prefetchable Memory Limit Address[63:32] PEX 8524 uses this register for Prefetchable Memory Upper Limit Address[63:32]. Type Serial EEPROM Default R/W Yes FFFF-FFFFh PR EL IM IN AR Y 31:0 Description Register 10-13. 30h I/O Base Address[31:16] and I/O Limit Address[31:16] (All Ports) Bit(s) Description Type Serial EEPROM Default 15:0 I/O Base Upper 16 Bits PEX 8524 uses this register for I/O Base Address[31:16]. R/W Yes FFFFh 31:16 I/O Limit Upper 16 Bits PEX 8524 uses this register for I/O Limit Address[31:16]. R/W Yes 0000h Type Serial EEPROM Default RO Yes 40h Register 10-14. 34h Capabilities Pointer (All Ports) Bit(s) Description 7:0 Capability Pointer Initial value = 40h, which is the Power Management Capability registers offset. 31:8 Reserved 0000_00h Register 10-15. 38h Expansion ROM Base Address (All Ports) Bit(s) 31:0 Description Expansion ROM Base Address Expansion ROM Addressing not supported in T mode. Set to 0000_0000h. Type Serial EEPROM Default RO No 0000_0000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 109 PEX 8524 Port Registers PLX Technology, Inc. Register 10-16. 3Ch Bridge Control and Interrupt Signal (All Ports) Description Type Serial EEPROM Default 7:0 Interrupt Line PEX 8524 does not use this register, but provides it for operating system and device driver use. R/W Yes 00h 15:8 Interrupt Pin Read-Only field that identifies the legacy interrupt message(s) the device (or device function) uses. When values = 0h, 1h, 2h, 3h, and 4h, maps to legacy interrupt messages for INTA#, INTB#, INTC#, and INTD#, respectively. When 00h, indicates that the device does not use legacy interrupt message(s). Only values 00h or 01h are allowed in the PEX 8524. RO Yes 01h 16 Parity Error Enable Controls the response to Poisoned TLPs. When = 1b, enables the Secondary Master Data Parity Error bit. R/W Yes 0b 17 SERR# Enable Controls forwarding of ERR_COR, ERR_FATAL, and ERR_NONFATAL from the secondary interface to the primary interface. When = 1b, and the SERR# ENABLE bit in the Command register = 1b, enables the Signaled System Error bit. R/W Yes 0b 18 ISA Enable Not Supported. Set to 0b. RO No 0b 19 VGA Enable PEX 8524 does not support this feature and sets this bit to 0b. RO No 0b 20 Reserved 21 Master Abort Mode Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 22 Secondary Bus Reset 1b = Causes a Hot Reset on the corresponding PEX 8524 port secondary/ downstream PCI Bus. R/W Yes 0b RO No 0b RO No 0b RO No 0b RO No 0b RO No 0b 23 24 25 26 27 31:28 110 PR EL IM IN AR Y Bit(s) Fast Back-to-Back Transaction Enable Set to 0b as required by the PCI Express Base 1.0a. Primary Discard Timer Set to 0b as required by the PCI Express Base 1.0a. Secondary Discard Timer Set to 0b as required by the PCI Express Base 1.0a. Discard Timer Status Set to 0b as required by the PCI Express Base 1.0a. Discard Timer SERR# Enable Set to 0b as required by the PCI Express Base 1.0a. Reserved 0b 0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Power Management Capability Registers 10.7 Power Management Capability Registers The following sections detail the PEX 8524 Power Management registers. The register map is delineated in Table 10-4. Table 10-4. Power Management Capability Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Power Management Capability DATA NEXT POINTER Capability ID 40h Power Management Status and Control 44h 40h Power Management Capability (All Ports) Bit(s) PR EL IM IN AR Y Table 10-5. PM Control/Status Bridge Extensions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description Type Serial EEPROM Default 7:0 Capability ID Set to 01h as required by the PCI Power Mgmt. r1.1. RO Yes 01h 15:8 Next Pointer Default 48h points to Message Signaled Interrupt Control register. RO Yes 48h 18:16 Version Default 010b indicates compliance with the PCI Power Mgmt. r1.1. RO Yes 010b 19 PME Clock Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 20 Reserved 21 Device-Specific Initialization Default 0b indicates that Device Specific Initialization is not required. RO Yes 0b AUX Current Default 000b indicates that PEX 8524 does not contain Auxiliary Current requirements. RO Yes 000b 25 D1 Support Default 0b indicates that PEX 8524 does not support D1 Power state. RO No 0b 26 D2 Support Default 0b indicates that PEX 8524 does not support D2 Power state. RO No 0b PME Support Default 11001b indicates that the corresponding PEX 8524 port forwards PME messages. RO Yes 11001b 24:22 31:27 0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 111 PEX 8524 Port Registers PLX Technology, Inc. Register 10-17. 44h Power Management Status and Control (All Ports) Bit(s) Description Type Serial EEPROM Default R/W Yes 00b Power Management Status and Control 1:0 Power State PEX 8524 reports the power state of its corresponding ports. 00b = D0 01b and 10b are not supported 11b = D3hot 7:2 Reserved PME Enable 0b = Disables PME generation by corresponding PEX 8524 port 1b = Enables PME generation by corresponding PEX 8524 port Data Select 12:9 No 0bb Yes 0h No 0h RO Yes 00b R/W1C No 0ba R/WS PR EL IM IN AR Y 8 0h R/W by EEPROM mode onlyb. Bits [12:9] select the Data and Data Scale registers. 0h = D0 power consumed 3h = D3hot power consumed 4h = D0 power dissipated 7h = D3hot power dissipated RO RO for hardware auto configuration. Not Supported. Data Scale 14:13 15 R/W by EEPROM mode onlyb There are four internal Data Scale register per port. Bits [12:9], Data Select, select the Data Scale register PME Status 0b = PME is not generated by corresponding PEX 8524 port 1b = PME is being generated by corresponding PEX 8524 port PM Control/Status Bridge Extensions 21:16 Reserved 0-0h 22 B2/B3 Support Set to 0b as required by the PCI Power Mgmt. r1.1. RO No 0b 23 Bus Power/Clock CNTRL Enable Set to 0b as required by the PCI Power Mgmt. r1.1. RO No 0b RO Yes 00h Data Data 31:24 R/W by serial EEPROM mode onlyb. There are four internal Data registers per port. Bits [12:9], Data Select, select the Data register. a.Because the PEX 8524 does not support auxiliary power, this bit is not sticky, and is always set to 0b at power-on reset. b.With no serial EEPROM, reads return 0h for Data Scale and Data registers (for all Data Selects). 112 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Message Signaled Interrupt Capability Registers 10.8 Message Signaled Interrupt Capability Registers The following sections detail PEX 8524 Message Signaled Interrupt (MSI) Capability registers. The register map is delineated in Table 10-6. Table 10-6. Message Signaled Interrupt Capability Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Message Signaled Interrupt Control 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEXT CAPABILITY POINTER CAPABILITY ID 48h Lower Message Address[31:0] 4Ch Upper Message Address[63:32] 50h Message Data PR EL IM IN AR Y Reserved 54h Register 10-18. 48h Message Signaled Interrupt Control (All Ports) Bit(s) Description Type Serial EEPROM Default 7:0 Capability ID Set to 05h as required by the PCI r2.3. RO Yes 05h 15:8 Next Capability Pointer Set to 68h to point to PEX 8524 PCI Express Capabilities registers. RO Yes 68h MSI Enable 0b = Message Signaled Interrupts for the corresponding port are disabled 1b = Message Signaled Interrupts for the corresponding port are enabled R/W Yes 0b 19:17 Multiple Message Capable 000b = PEX 8524 port is requesting one message - the only value supported. RO Yes 000b 22:20 Multiple Message Enable 000b = PEX 8524 port contains only one allocated message - the only value supported. R/W Yes 000b MSI 64-Bit Address Capable 1b = PEX 8524 is capable of generating 64-bit Message Signaled Interrupt addresses RO Yes 1b 16 23 31:24 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 00h 113 PEX 8524 Port Registers PLX Technology, Inc. s Register 10-19. 4Ch Lower Message Address[31:0] (All Ports) Bit(s) Description 1:0 Reserved 31:2 Message Address[31:2] MSI Write transaction lower address[31:2]. Note: Refer to 50h for Upper Message Address[63:32]. Serial EEPROM Type Default 00b R/W Yes 0000_0000h Register 10-20. 50h Upper Message Address[63:32] (All Ports) Bit(s) Message Address[63:32] MSI Write transaction upper address[63:32]. Note: Refer to 4Ch for Lower Message Address[31:0]. Type Serial EEPROM Default R/W Yes 0000_0000h PR EL IM IN AR Y 31:0 Description Register 10-21. 54h Message Data (All Ports) Bit(s) Description 15:0 Message Data MSI Write transaction TLP payload. 31:16 Reserved 114 Type Serial EEPROM Default R/W Yes 0000h 0000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 10.9 PCI Express Capabilities Registers PCI Express Capabilities Registers The following sections detail the PEX 8524 PCI Express Capabilities registers. Hot Plug capability, command, status, and events are included in these registers. The register map is delineated in Table 10-7. Table 10-7. PCI Express Capabilities Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEXT CAPABILITY POINTER PCI Express Capabilities CAPABILITY ID Device Capabilities 68h 6Ch Device Status Device Control 70h Link Capabilities 74h Link Control PR EL IM IN AR Y Link Status 78h Slot Capabilities Slot Status 7Ch Slot Control 80h Register 10-22. 68h PCI Express Capabilities (All Ports) Bit(s) Description Ports Type Serial EEPROM Default 7:0 Capability ID Set to 10h as required by the PCI Express Base 1.0a. RO Yes 10h 15:8 Next Capability Pointer 00h = PEX 8524 PCI Express Capabilities is the last capability in the PEX 8524 port Capabilities list. PEX 8524 port Extended Capabilities list starts at 100h. RO Yes 00h 19:16 Capability Version PEX 8524 ports set these bits to 1h as required by the PCI Express Base 1.0a. RO Yes 1h 23:20 Device/Port Type Set at reset as required by the PCI Express Base 1.0a. Upstream RO Yes 5h Downstream RO Yes 6h Upstream RO No 0b Downstream RO Yes 1b RO Yes 0000_0b Slot Implemented 0b = Disables or connects to an Upstream port 24 0b = Disables or connects to an integrated componenta 1b = Indicates that each Downstream port connects to a slot as opposed to being connected to an integrated component or being disabled 29:25 Interrupt Message Number EEPROM writes 0000_0b, because Base message and MSI messages are the same. 31:30 Reserved 00b a.The PEX 8524 EEPROM register initialization capability is used to change this value to 0h, specifying that the corresponding PEX 8524 Downstream port connects to an integrated component or is disabled. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 115 PEX 8524 Port Registers PLX Technology, Inc. Register 10-23. 6Ch Device Capabilities (All Ports) Type Serial EEPROM Default 2:0 Maximum Payload Size Supported 000b = PEX 8524 ports support 128-byte maximum payload 001b = PEX 8524 ports support 256-byte maximum payload No other values are supported. RO Yes 001b 4:3 Phantom Functions 00b = PEX 8524 does not support Phantom Functions RO Yes 00b Extended Tag Field 0b = Maximum Tag field is 5 bits 1b = Maximum Tag field is 8 bits RO Yes 0b 8:6 Endpoint L0s Acceptable Latency Because the PEX 8524 is a switch and not an endpoint, it does not support this feature. 000b = Disables the capability RO No 000b 11:9 Endpoint L1 Acceptable Latency Because the PEX 8524 is a switch and not an endpoint, it does not support this feature. 000b = Disables the capability RO No 000b 5 116 Description Ports PR EL IM IN AR Y Bit(s) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 10-23. 6Ch Device Capabilities (All Ports) (Cont.) Description Ports Type Serial EEPROM Default Attention Button Present For PEX 8524 Upstream port, when 1b, indicates that an Attention Button is implemented on that adapter card. PEX 8524 EEPROM register initialization capability is used to change this value to 0b, indicating that an Attention Button is not present on an adapter card for which PEX 8524 provides the system interface. Upstream HwInit Yes 1b Downstream RO No 0b Upstream HwInit Yes 1b Downstream RO No 0b Upstream HwInit Yes 1b Downstream RO No 0b Bit(s) 12 Not valid for Downstream ports. PR EL IM IN AR Y 13 Attention Indicator Present For PEX 8524 Upstream port, when 1b, indicates that an Attention Indicator is implemented on the adapter card. PEX 8524 EEPROM register initialization capability is used to change this value to 0b indicating an Attention Indicator is not present on an adapter card for which PEX 8524 provides the system interface. Not valid for Downstream ports. 14 Power Indicator Present For PEX 8524 Upstream port, when 1b, indicates that a Power Indicator is implemented on the adapter card PEX 8524 EEPROM register initialization capability is used to change this value to 0b, indicating that a Power Indicator is not present on an adapter card for which PEX 8524 provides the system interface. Not valid for Downstream ports. 17:15 25:18 Reserved Captured Slot Power Limit Value For PEX 8524 Upstream port, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the Captured Slot Limit Power Scale field. Not valid for Downstream ports. 27:26 Captured Slot Limit Power Scale For PEX 8524 Upstream port, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the Captured Slot Power Limit Value field. 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 Not valid for Downstream ports. 31:28 000b Upstream RO Yes 00h Downstream RO No 0b Upstream RO Yes 00b Downstream RO No 0b Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0h 117 PEX 8524 Port Registers PLX Technology, Inc. Register 10-24. 70h Device Status and Control (All Ports) Bit(s) Description Type Serial EEPROM Default Device Control Correctable Error Reporting Enabled 0b = Disables 1b = Enables corresponding PEX 8524 port to report correctable errors R/W Yes 0b 1 Non-Fatal Error Enabled 0b = Disables 1b = Enables corresponding PEX 8524 port to report non-fatal errors R/W Yes 0b 2 Fatal Error Reporting Enabled 0b = Disables 1b = Enables corresponding PEX 8524 port to report fatal errors R/W Yes 0b 3 Unsupported-Request Reporting Enable 0b = Disables 1b = Enables corresponding PEX 8524 port to report unsupported-request errors R/W Yes 0b 4 Relaxed Ordering Enabled Not supported. Set to 0b. RO No 0b Maximum Payload Size Power on/reset values for this field are 000b per PEX 8524 port, indicating that initially each PEX 8524 port is configured to support a maximum payload size of 128 bytes. Software can change this field to configure the PEX 8524 ports to support other payload sizes, but it does not change this field to a value larger than that indicated by the Maximum Payload Size Supported. R/W Yes 000b 8 Extended Tag Field Enabled Not Supported. Set to 0b for each port. RO No 0b 9 Phantom Functions Enable Not Supported. Set to 0b for each port. RO No 0b 10 AUX Power PM Enable Not Supported. Set to 0b for each port. RO No 0b 11 No Snoop Enable Not Supported. Set to 0b for each port. RO No 0b 14:12 Maximum Read-Request Size Not Supported. Set to 0b for each port. RO No 000b 7:5 15 118 PR EL IM IN AR Y 0 Reserved 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 10-24. 70h Device Status and Control (All Ports) (Cont.) Type Serial EEPROM Default 16 Correctable Error Detected 1b = Corresponding PEX 8524 port detected a Correctable Error. Set when the corresponding port detects a Correctable Error, regardless of the Correctable Error Reporting Enabled bit state. R/W1C Yes 0b 17 Non-Fatal Error Detected 1b = Corresponding PEX 8524 port detected a Non-Fatal Error. Set when the corresponding port detects a Non-Fatal Error, regardless of the Non-Fatal Error Enabled bit state. R/W1C Yes 0b 18 Fatal Error Detected 1b = Corresponding PEX 8524 port detected a Fatal Error. Set when the corresponding port detects a Fatal Error, regardless of the Fatal Error Reporting Enabled bit state. R/W1C Yes 0b 19 Unsupported Request Detected 1b = Corresponding PEX 8524 port detected an Unsupported-Request Set when the corresponding port detects an Unsupported-Request, regardless of the Unsupported-Request Reporting Enable bit state. R/W1C Yes 0b 20 AUX Power Detected Not supported. Set to 0b for each port. RO No 0b 21 Transactions Pending Not supported. Set to 0b for each port. RO No 0b Bit(s) Description 31:22 Reserved PR EL IM IN AR Y Device Status 000h Register 10-25. 74h Link Capabilities (All Ports) Bit(s) Description Type Serial EEPROM Default 3:0 Maximum Link Speed Set to 1h as required by the PCI Express Base 1.0a. RO Yes 1h 9:4 Maximum Link Width Actual link width is set by signal ball strapping options Maximum Link Width for PEX 8524 is x16 = 01_0000b. RO Yes Strap levels 11:10 Active-State Power Management Support 01b = NT port, when enabled, supports the L0s Link power state 11b = Corresponding PEX 8524 port supports the L0s and L1 Link power states RO Yes 11b 14:12 L0S Exit Latency 101b = Corresponding PEX 8524 port L0s Exit Latency is between 1 and 2 s RO Yes 101b 17:15 L1 Exit Latency 101b = Corresponding PEX 8524 port L1 Exit Latency is between 16 and 32 s RO Yes 101b 23:18 Reserved 0-0b Port Number Port number is set by signal ball strapping options: 31:24 HwInit STRAP_STN0_PORTCFG[4:0] - Port numbers 0, 1 STRAP_STN1_ PORTCFG[3:0] - Port numbers 8, 9, 10, 11 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes Set by strap levels 119 PEX 8524 Port Registers PLX Technology, Inc. Register 10-26. 78h Link Status and Control (All Ports) Bit(s) Description Ports Type Serial EEPROM Default R/W Yes 00b Link Control Active-State Power Management Control 1:0 00b = Disables L0s and L1 Entry for corresponding PEX 8524 porta 01b = Enables only L0s Entry 10b = Enables L1 Entry 11b = Enables both L0s and L1 Entry 2 Reserved 0b 3 Read Completion Boundary Set to 0b as required by the PCI Express Base 1.0a. RO Yes 0b Upstream RO No 0b Downstream R/W Yes 0b Upstream RO No 0b Downstream R/W Yes 0b 6 Common Clock Configuration When set to: 0b = Corresponding PEX 8524 port and the device at the other end of the corresponding port's PCI Express link are operating with an asynchronous reference clock 1b = Corresponding PEX 8524 port and the device at the other end of the corresponding port's PCI Express link are operating with a distributed common reference clock R/W Yes 0b 7 Extended Sync Set to 1b causes the corresponding PEX 8524 port to transmit: * 4,096 FTS ordered sets in the L0s state, * Followed by a single SKP-ordered set prior to entering the L0 state, * Finally, transmission of 1,024 TS1 ordered sets in the Recovery state. R/W Yes 0b PR EL IM IN AR Y 4 Link Disable Not valid for Upstream ports. Setting to 1b disables the corresponding PEX 8524 Downstream port PCI Express Link. Retrain Link Not valid for Upstream ports. 5 15:8 120 For PEX 8524 ports, when read, always returns 0b. Writing a 1b to this bit causes the corresponding PEX 8524 port to initiate retraining of its PCI Express link. Reserved 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 10-26. 78h Link Status and Control (All Ports) (Cont.) Bit(s) Description Ports Type Serial EEPROM Default Link Status 19:16 Link Speed Set to 1h as required by the PCI Express Base 1.0a for 2.5 Gbps PCI Express link. RO Yes 1h 25:20 Negotiated Link Width Link width is determined by negotiated value with attached port/lane: 00_0001b = x1 00_0010b = x2 00_0100b = x4 00_1000b = x8All other values are not supported. RO Yes 00_0001b RO No 0b Downstream RO Yes 0b Upstream RO No 0b Downstream RO No 0b HwInit Yes 0b When set to 1b, indicates that the corresponding PEX 8524 port detected a link training error. Link Training Not valid for Upstream ports. 27 28 31:29 Upstream PR EL IM IN AR Y 26 Training Error Not valid for Upstream ports. When set to 1b, indicates that the corresponding PEX 8524 Downstream port requested link training and either the link training is in process or about to start. Slot Clock Configuration 0b = Indicates PEX 8524 uses an independent clock 1b = Indicates PEX 8524 uses the same physical reference clock that the platform provides on the connector Reserved 0h a.The port receiver must be capable of entering L0s state, even when disabled. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 121 PEX 8524 Port Registers PLX Technology, Inc. Note: 7Ch is used only for Downstream ports. Register 10-27. 7Ch Slot Capabilities (All Ports) Bit(s) Description Attention Button Present Not valid for Upstream ports. 0 0b = Attention Button is not implemented 1b = Attention Button is implemented on the chassis for the slot of the corresponding PEX 8524 Downstream port Power Controller Present Not valid for Upstream ports. 0b = Power Controller is not implemented 1b = Power Controller is implemented for the slot of the corresponding PEX 8524 Downstream port MRL Sensor Present Not valid for Upstream ports. 2 0b = MRL Sensor is not implemented 1b = MRL Sensor is implemented on the chassis for the slot of the corresponding PEX 8524 Downstream port Attention Indicator Present Not valid for Upstream ports. 3 122 Type Serial EEPROM Default Upstream HwInit No 0b Downstream HwInit Yes 1b Upstream HwInit No 0b Downstream HwInit Yes 1b PR EL IM IN AR Y 1 Ports 0b = Attention Indicator is not implemented 1b = Attention Indicator is implemented on the chassis for the slot of the corresponding PEX 8524 Downstream port Upstream HwInit No 0b Downstream HwInit Yes 1b Upstream HwInit No 0b Downstream HwInit Yes 1b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 10-27. 7Ch Slot Capabilities (All Ports) (Cont.) Bit(s) Description Power Indicator Present Not valid for Upstream ports. 4 0b = Power Indicator is not implemented 1b = Power Indicator is implemented on the chassis for the slot of the corresponding PEX 8524 Downstream port Hot Plug Surprise Not valid for Upstream ports. 5 0b = No device in the corresponding PEX 8524 Downstream port slot is removed from the system without prior notification 1b = Device in the corresponding PEX 8524 Downstream port slot can be removed from the system without prior notification 6 0b = Corresponding PEX 8524 Downstream port slot is not capable of supporting Hot Plug operations 1b = Corresponding PEX 8524 Downstream port slot is capable of supporting Hot Plug operations Slot Power Limit Value Do not change for Upstream ports. 14:7 The max power available from the corresponding PEX 8524 Downstream port is determined by multiplying the value in this field (expressed in decimal; 25d = 19h) by the value specified by the Slot Power Limit Scale. Slot Power Limit Scale Not valid for Upstream ports. 16:15 18:17 31:19 Type Serial EEPROM Default Upstream HwInit No 0b Downstream HwInit Yes 1b Upstream HwInit No 0b Downstream HwInit Yes 0b Upstream HwInit No 0b Downstream HwInit Yes 1b Upstream HwInit No 00h Downstream HwInit Yes 19h Upstream HwInit No 00b Downstream HwInit Yes 00b PR EL IM IN AR Y Hot Plug Capable Not valid for Upstream ports. Ports The max power available from the corresponding PEX 8524 Downstream port is determined by multiplying the value in this field by the Slot Power Limit Value bit. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x Reserved Physical Slot Number Not valid for Upstream ports Specifies a non-zero identification number for the corresponding PEX 8524 Downstream port slot. 00b Upstream HwInit No 0-0h Downstream HwInit Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 123 PEX 8524 Port Registers PLX Technology, Inc. Note: 80h is used only for Downstream ports. Register 10-28. 80h Slot Status and Control (All Ports) Bit(s) Description Ports Type Serial EEPROM Default Upstream RO No 0b Downstream R/W Yes 0b Upstream RO No 0b Downstream R/W Yes 0b Upstream RO No 0b Downstream R/W Yes 0b Upstream RO No 0b Downstream R/W Yes 0b Slot Control Attention Button Pressed Enabled Not valid for Upstream ports. 0 0b = Function disabled 1b = Enables a Hot Plug Interrupt or Wakeup event on an Attention Button Pressed event on the corresponding PEX 8524 Downstream port Power Fault Detected Enable Not valid for Upstream ports. 0b = Function disabled 1b = Enables a Hot Plug Interrupt or Wakeup event on a Power Fault event on the corresponding PEX 8524 Downstream port PR EL IM IN AR Y 1 MRL Sensor Change Enable Not valid for Upstream ports. 2 0b = Function disabled 1b = Enables a Hot Plug Interrupt or Wakeup event on an MRL Sensor Change event on the corresponding PEX 8524 Downstream port Presence Detect Change Enable Not valid for Upstream ports. 3 124 0b = Function disabled 1b = Enables a Hot Plug Interrupt or Wakeup event on a Presence Detect Change event on the corresponding PEX 8524 Downstream port PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 10-28. 80h Slot Status and Control (All Ports) (Cont.) Bit(s) Description Command Completed Interrupt Enable Not valid for Upstream ports. 4 0b = Function disabled 1b = Enables a Hot Plug Interrupt or Wakeup event when a command is completed by the Hot Plug Controller on the corresponding PEX 8524 Downstream port Hot Plug Interrupt Enable Not valid for Upstream ports. 5 0b = Function disabled 1b = Enables a Hot Plug Interrupt on any enabled Hot Plug events for the corresponding PEX 8524 Downstream port 7:6 Control the Attention Indicator on the corresponding PEX 8524 Downstream port slot: 00b = Reserved - Do not use 01b = Turns ON indicator to constant ON state 10b = Causes indicator to BLINK 11b = Turns OFF indicator Writes cause the corresponding PEX 8524 Downstream port to transmit the appropriate Attention Indicator messages. Reads return the corresponding PEX 8524 Downstream port Attention indicator's current state. Power Indicator Control Do not change for Upstream ports. 9:8 Control the Power Indicator on the corresponding PEX 8524 Downstream port slot: 00b = Reserved - Do not use 01b = Turns ON indicator to constant ON state 10b = Causes indicator to BLINK 11b = Turns OFF indicator Writes cause the corresponding PEX 8524 Downstream port to transmit the appropriate Power Indicator message. Reads return the corresponding PEX 8524 Downstream port Power indicator's current state. Power Controller Control Not valid for Upstream ports. 10 15:11 Type Serial EEPROM Default Upstream RO No 0b Downstream R/W Yes 0b Upstream RO No 0b Downstream R/W Yes 0b Upstream RO No 00b Downstream R/W Yes 11b Upstream RO No 00b Downstream R/W Yes 11b Upstream RO No 0b Downstream R/W Yes 1b PR EL IM IN AR Y Attention Indicator Control Do not change for Upstream ports. Ports Controls the Power Controller on the corresponding PEX 8524 Downstream port slot: 0b = Turns ON Power Controller 1b = Turns OFF Power Controller Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h 125 PEX 8524 Port Registers PLX Technology, Inc. Register 10-28. 80h Slot Status and Control (All Ports) (Cont.) Bit(s) Description Ports Type Serial EEPROM Default Upstream RO No 0b Downstream R/W1C Yes 0b Upstream RO No 0b Downstream R/W1C Yes 0b Upstream RO No 0b Downstream R/W1C Yes 0b Upstream RO No 0b Downstream R/W1C Yes 0b Upstream RO No 0b Downstream R/W1C Yes 0b Upstream RO No 0b Slot Status 16 Attention Button Pressed Not valid for Upstream ports Set to 1b when the Attention Button of the corresponding PEX 8524 Downstream port slot is pressed. Power Fault Detected Not valid for Upstream ports. 18 Set to 1b when the Power Controller of the corresponding PEX 8524 Downstream port slot detects a Power Fault at the slot. MRL Sensor Changed Not valid for Upstream ports. PR EL IM IN AR Y 17 Set to 1b when an MRL state change is detected on the corresponding PEX 8524 Downstream port slot. 19 Presence Detect Change Not valid for Upstream ports Set to 1b when a Presence Detect Change is detected on the corresponding PEX 8524 Downstream port slot. Command Complete Do not change for Upstream ports. 20 Set to 1b when the Hot Plug controller on the corresponding PEX 8524 Downstream port slot completes an issued command. MRL Sensor State Do not change for Upstream ports. 21 Reveals the corresponding PEX 8524 Downstream port MRL sensor's current state: 0b = MRL sensor closed 1b = MRL sensor open Presence Detect State Do not use for Upstream ports. 22 31:23 126 Reveals the corresponding PEX 8524 Downstream port slot's current state: 0b = Slot empty 1b = Slot occupied Reserved Downstream Upstream Downstream Yes RO No 0b Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 10.10 Device Serial Number Extended Capability Registers Device Serial Number Extended Capability Registers The following sections detail the PEX 8524 Device Serial Number Extended Capability registers. The register map is delineated in Table 10-8. Table 10-8. PEX 8524 Device Serial Number Extended Capability Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NEXT CAPABILITY OFFSET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Capability Version EXTENDED CAPABILITY ID 100h Serial Number (Low) 104h Serial Number (High) 108h Bit(s) PR EL IM IN AR Y Register 10-29. 100h Device Serial Number Extended Capability Description Type Serial EEPROM Default 15:0 Extended Capability ID Set to 0003h as required by the PCI Express Base 1.0a. RO Yes 0003h 19:16 Capability Version Set to 1h as required by the PCI Express Base 1.0a. RO Yes 1h 31:20 Next Capability Offset Set to FB4h, which is the Advanced Error Reporting Enhanced Capability Header registers. RO Yes FB4h Register 10-30. 104h Serial Number (Low) (All Ports) Bit(s) 31:0 Description Serial Number[31:0] Lower half of a 64-bit register. Value set by EEPROM register initialization. Type Serial EEPROM Default RO Yes 0000_0EDFh Type Serial EEPROM Default RO Yes 0000_0001h Register 10-31. 108h Serial Number (High) (All Ports) Bit(s) 31:0 Description Serial Number[63:32] Upper half of a 64-bit register. Value set by EEPROM register initialization. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 127 PEX 8524 Port Registers 10.11 PLX Technology, Inc. Device Power Budgeting Extended Capability Registers The following sections detail the PEX 8524 Device Power Budgeting Extended Capability registers. The register map is delineated in Table 10-9. Table 10-9. PEX 8524 Device Power Budgeting Extended Capability Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NEXT CAPABILITY OFFSET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Capability Version EXTENDED CAPABILITY ID Reserved 138h Data Select 13Ch Power Data Power Budget Capability PR EL IM IN AR Y Reserved 140h 144h Register 10-32. 138h Device Power Budgeting Extended Capability (All Ports) Bit(s) Description Type Serial EEPROM Default 15:0 Extended Capability ID Set to 0004h as required by the PCI Express Base 1.0a. RO Yes 0004h 19:16 Capability Version Set to 1h as required by the PCI Express Base 1.0a. RO Yes 1h 31:20 Next Capability Offset Set to 148h, which addresses the PEX 8524 Virtual Channel Budgeting Extended Capability registers. RO Yes 148h Description Type Serial EEPROM Default 7:0 Data Select Indexes the Power Budgeting Data reported by way of eight Power Data registers per port and selects the DWord of Power Budgeting Data that appears in each Power Data register. Index values commence at 0 to select the first DWord of Power Budgeting Data; subsequent DWords of Power Budgeting Data are selected by increasing index values 1 to 7. R/W Yes 00h 31:8 Reserved Register 10-33. 3Ch Data Select (All Ports) Bit(s) 0-0h Note: There are eight registers per port that can be programmed through the EEPROM. Each register maintains a different power configuration for the port. Each configuration is selected by writing to the Data Select register Data Select bits . 128 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Device Power Budgeting Extended Capability Registers Register 10-34. 140h Power Data (All Ports) Type Serial EEPROM Default 7:0 Base Power Base Power - Four registers/port. Specifies in watts the base power value in the operating condition. This value must be multiplied by the Data Scale to produce the actual power consumption value. RO Yes 00h 9:8 Data Scale Specifies the scale to apply to the Base Power value. The power consumption of the device is determined by multiplying the contents of the BASE POWER field with the value corresponding to the encoding returned by this field. Defined encodings are: 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x RO Yes 00b 12:10 PM Sub State 000b = Corresponding PEX 8524 port is in the default Power Management sub-state RO Yes 000b 14:13 PM State Current power state: 00b = D0 state 01b = Not used - D1 state not supported 10b = Not used - D2 state not supported 11b = D3 state RO Yes 00b 17:15 Type Type of operating condition: 000b = PME Auxiliary 001b = Auxiliary 010b = Idle 011b = Sustained 111b = Maximum All other values are reserved. RO Yes 000b 20:18 Power Rail Power Rail of operating condition: 000b = Power 12V 001b = Power 3.3V 010b = Power 1.8V 111b = Thermal All other values are reserved. RO Yes 000b 31:21 Reserved Description PR EL IM IN AR Y Bit(s) 0-0h Register 10-35. 144h Power Budget Capability (All Ports) Bit(s) 0 31:1 Type Serial EEPROM Default HwInit Yes 1b Description System Allocated 1b = Power budget for the device is included within the system power budget Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h 129 PEX 8524 Port Registers 10.12 PLX Technology, Inc. Virtual Channel Extended Capability Registers The following sections detail the PEX 8524 Virtual Channel Extended Capability registers. These registers are duplicated for each port. The register map for one port is delineated in Table 10-10. Table 10-10. PEX 8524 Virtual Channel Extended Capability Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Capability Version NEXT CAPABILITY OFFSET EXTENDED CAPABILITY ID 148h Port VC Capability 1 14Ch Port VC Capability 2 150h Port VC Status Port VC Control (Port VC Status and Control) 158h PR EL IM IN AR Y VC0 Resource Capability VC0 Resource Control VC0 Resource Status 154h 15Ch Reserved 160h VC1 Resource Capability5 164h VC1 Resource Control 168h VC1 Resource Status Reserved 16Ch 170h Reserved ... 1B4h 1B8h Virtual Channel Arbitration Table Register Map ... 1C4h PEX 8524 port PLX vendor unique registers Register 10-36. 148h Virtual Channel Budgeting Extended Capability (All Ports) Bit(s) Description Type Serial EEPROM Default 15:0 Extended Capability ID Set to 0002h as required by the PCI Express Base 1.0a RO Yes 0002h 19:16 Capability Version Set to 1h as required by the PCI Express Base 1.0a RO Yes 1h 31:20 Next Capability Offset Set to 000h, indicating that the Virtual Channel Extended Capability is the last extended capability in the port Extended Capability list. RO Yes 000h 130 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Virtual Channel Extended Capability Registers Register 10-37. 14Ch Port VC Capability 1 (All Ports) Bit(s) 3:1 4 Extended VC Count 0b = PEX 8524 supports only the default Virtual Channel 0 1b = PEX 8524 ports support one extended virtual channel (VC1) Type Serial EEPROM Default RO Yes 1b Reserved 000b Low-Priority Extended VC Count For strict priority arbitration, these bits indicate the number of extended virtual channels (those in addition to the default Virtual Channel 0) that belong to the Low-Priority Virtual Channel group for a particular PEX 8524 port. 0b = For each PEX 8524 port, only the default Virtual Channel 0 belongs to the Low-priority Virtual Channel group PEX 8524 EEPROM register initialization capability is used to change this field to 1b to also set VC1 to the Low-Priority Virtual Channel group. PR EL IM IN AR Y 0 Description RO Yes 0b 7:5 Reserved 000b 9:8 Reference Clocks Not Supported. Set to 00b for each port. RO No 00b 11:10 Port Arbitration Table-Entry Size Not Supported. Set to 00b for each port. RO No 00b 31:12 Reserved 0-0h Register 10-38. 150h Port VC Capability 2 (All Ports) Bit(s) Description 1:0 VC Arbitration Capabilities 01b = Round-Robin (Hardware-Fixed) Arbitration scheme supported by each port 10b = Weighted Round-Robin Arbitration with 32 phases supported by each port 23:2 Reserved 31:24 VC Arbitration Table Offset Virtual Channel Arbitration-Table zero-based offset in QDWords (16 bytes) from the base address of PEX 8524 port Virtual Channel Capability structure. Type Serial EEPROM Default RO Yes 10b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h RO Yes 07h 131 PEX 8524 Port Registers PLX Technology, Inc. Register 10-39. 154h Port VC Status and Control (All Ports) Bit(s) Description Type Serial EEPROM Default Port VC Control Load VC Arbitration Table Writing 1b updates the VC Arbitration table for the corresponding PEX 8524 port. Reading this bit always returns a 0b. R/W Yes 0b 1 VC Arbitration Select Selects the VC arbitration type for the corresponding PEX 8524 port. Indicates the bit number in the VC Arbitration Capabilities field that corresponds to the arbitration type: 0b = bit[0]; Round-Robin (Hardware-Fixed) arbitration scheme 1b = bit[1]; Weighted Round-Robin with 32 Phases, and so forth Select only an arbitration type that corresponds to a bit that is set in the VC Arbitration Capabilities field. Cannot be modified when more than one VC in the LPVC group is enabled. R/W Yes 0b 15:2 Reserved PR EL IM IN AR Y 0 0-0h Port VC Status 16 31:17 VC Arbitration Table Status Set to 1b when there is a write to the VC Arbitration table. The corresponding PEX 8524 port clears VC Arbitration Table Status when it completes loading the values stored in its VC Arbitration table, and after software sets the Load VC Arbitration Table field bit[0]. Reserved RO Yes 0b 0-0h Register 10-40. 158h VC0 Resource Capability (All Ports) Bit(s) 0 13:1 Port Arbitration Capability 1b = Non-configurable hardware-fixed port arbitration The only configuration supported by the PEX 8524. Type Serial EEPROM Default RO Yes 1b Reserved 0-0h 14 Advanced Packet Switching Not Supported. Set to 0b. RO No 0b 15 Reject Snoop Transactions Not a PCI Express switch feature; therefore, Reject Snoop Transactions is set to 0b. RO No 0b Maximum Time Slots Not Supported. Set to 000_0000b. RO No 000_0000b 22:16 23 31:24 132 Description Reserved 0-0h Port Arbitration Table Offset Not Supported. Set to 00h. RO No 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Virtual Channel Extended Capability Registers Register 10-41. 15Ch VC0 Resource Control (All Ports) Bit(s) 0 7:1 15:8 Description Type Serial EEPROM RO Yes R/W Yes TC/VC0 Map Defines Traffic Classes 7:0, respectively, and indicates which TCs are mapped into Virtual Channel 0. Traffic Class 0 (TC0) must be mapped to Virtual Channel 0. Traffic Classes 1 through 7 are mapped by default to VC0, but may also be mapped to VC1. Reserved Default FFh 00h RO No 0b 19:17 Port Arbitration Select Not Supported. Set to 000b. RO No 000b 23:20 Reserved 26:24 VC0 ID Defines ID code for the corresponding PEX 8524 port Virtual Channel 0. Because this is the default VC0, set to 000b. 30:27 Reserved 31 PR EL IM IN AR Y Load Arbitration Table Not Supported. Set to 0b for each port. 16 VC0 Enable 0b = Not allowed 1b = Enables corresponding PEX 8524 port default Virtual Channel 0 0-0h RO Yes 000b 0-0h RO Yes 1b Type Serial EEPROM Default Register 10-42. 160h VC0 Resource Status (All Ports) Bit(s) 15:0 Description Reserved 0000h 16 Port Arbitration Table Status Not Supported. Set to 0b. RO No 0b 17 VC0 Negotiation Pending 0b = VC0 negotiation completed 1b = VC0 initialization is not complete for the corresponding PEX 8524 port RO Yes 1b 31:18 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h 133 PEX 8524 Port Registers PLX Technology, Inc. Register 10-43. 164h VC1 Resource Capability (All Ports) Bit(s) 0 13:1 Description Port Arbitration Capability 1b = Non-configurable hardware-fixed port arbitration. The only configuration supported by PEX 8524. Type Serial EEPROM Default RO Yes 1b Reserved 0-0h RO No 0b 15 Reject Snoop Transactions Not valid for PEX 8524. RO No 0b Maximum Time Slots Not Supported. Set to 000_0000b. RO No 000_0000b 22:16 23 31:24 Reserved PR EL IM IN AR Y 14 Advanced Packet Switching Not Supported. Set to 0b. Port Arbitration Table Offset Not Supported. Set to 00h. 0b RO No 00h Type Serial EEPROM Default RO No R/W Yes Register 10-44. 168h VC1 Resource Control (All Ports) Bit(s) 0 7:1 15:8 Description TC/VC1 Map Defines Traffic Classes 7:1, respectively, and indicate which TCs are mapped into Virtual Channel 1. Traffic Class 0 must be mapped to Virtual Channel 0. Traffic Classes 1 through 7 can be mapped to VC1. Reserved 00h 0-0h Load_Port Arbitration Table Not Supported. Set to 0b. RO No 0b 19:17 Port Arbitration Select Not Supported. Set to 0b. RO No 000b 23:20 Reserved 26:24 VC1 ID Defines ID code for the corresponding PEX 8524 port Virtual Channel 1 (001b is the only supported value). 30:27 Reserved 16 31 134 0-0h R/W Yes 001b 0000b VC1 Enable 0b = Disables corresponding PEX 8524 port Virtual Channel 1 1b = Enables corresponding PEX 8524 port Virtual Channel 1 R/W Yes 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Virtual Channel Arbitration Table (All Ports) Register 10-45. 16Ch VC1 Resource Status (All Ports) Bit(s) Description 15:0 Type Serial EEPROM Reserved Default 0000h 16 Port Arbitration Table Status Not Supported. Set to 0b. RO No 0b 17 VC1 Negotiation Pending 0b = VC1 negotiation completed 1b = VC1 initialization or disabling is pending for the corresponding PEX 8524 port RO Yes 0b Reserved 10.12.1 0-0h Virtual Channel Arbitration Table (All Ports) PR EL IM IN AR Y 31:18 The following sections detail the PEX 8524 Virtual Channel Arbitration registers. The register map is delineated in Table 10-11. Table 10-11. Virtual Channel Arbitration Table Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Phase 7 Phase 6 Phase 5 Phase 4 Phase 3 Phase 2 Phase 1 Phase 0 1B8h Phase 15 Phase 14 Phase 13 Phase 12 Phase 11 Phase 10 Phase 9 Phase 8 1BCh Phase 23 Phase 22 Phase 21 Phase 20 Phase 19 Phase 18 Phase 17 Phase 16 1C0h Phase 31 Phase 30 Phase 29 Phase 28 Phase 27 Phase 26 Phase 25 Phase 24 1C4h Register 10-46. 1B8h - 1C4h VC Arbitration Table Phase n Definition (where n = 0 to 31) Bit(s) 0 3:1 Description Type Serial EEPROM Default PHASEn[0] VC Arbitration Table phases are used to determine the weighting of the two Virtual Channels during "Weighted Round-Robin with 32 Phases" virtual channel arbitration. This table is used only if Weighted Round-Robin with 32 phases virtual channel arbitration is selected by way of the VC Arbitration Select bit. Phases are assigned by setting PHASEn[0] of that Phase: 0b = Virtual Channel 0 1b = Virtual Channel 1 R/W Yes 0b PHASEn[3:1] RO No 000b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 135 PEX 8524 Port Registers 10.13 PLX Technology, Inc. PLX-Specific Registers The following registers are unique to the PEX 8524 device, and are not referenced in the PCI Express Base 1.0a. The PLX-Specific registers are organized into the following sections: * Error Checking and Debug Registers * Physical Layer Registers * CAM Routing Registers * TIC Control Registers * I/O Base and Limit Upper 16 Bits Registers * Base Address Registers (BARs) * Shadow Virtual Channel (VC) Capability Registers * Shadow Port Virtual Channel Capability_1 Registers * Ingress Credit Handler (INCH) Registers PR EL IM IN AR Y * Egress Credit Handler (EGCH) Registers * PLX-Specific Relaxed Ordering Mode Register * Internal Credit Handler (ITCH) VC&T Threshold Registers Note: The latter two register types are accessed using a Memory-Mapped cycle. It is not recommended to change these register values 136 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 10.13.1 Table 10-12. Error Checking and Debug Registers Error Checking and Debug Registers PLX-Specific Error Check/Debug and Physical Layer Register Map (Portsa) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1C8h Error Handler 32-Bit Error Status (for Factory Testing only) 1CCh Error Handler 32-Bit Error Mask (for Factory Testing only) 1D0h Station 0 Probe-Select (for Factory Testing only) 1D4h Station 1 Probe-Select (for Factory Testing only) 1D8h Debug Control 1DCh Power Management Hot Plug User Configuration 1E0h PR EL IM IN AR Y ECC Error Check Disable (only for Ports 0 and 8) TEC Control and Status 1E4h Bad TLP Count 1E8h Bad DLLP Count 1ECh Reserved 1F0h Software-Controlled Lane Status 1F4h ACK Transmission Latency Limit 1F8h PLX DLL-Specific 208h a.Certain registers are port-specific, some are station-specific, while others are device-specific. Register 10-47. 1C8h ECC Error Check Disable (Only Ports 0 and 8) Bit(s) Description Type Serial EEPROM Default 0 ECC 1-Bit Error-Check Disable 0b = 1-Bit Error Check enabled 1b = Disables 1-Bit Error Check R/W Yes 0b 1 ECC 2-Bit Error-Check Disable 0b = 2-Bit Error Check enabled 1b = Disables 2-Bit Error Check R/W Yes 0b 31:2 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h 137 PEX 8524 Port Registers PLX Technology, Inc. Note: 1CCh is used for Factory Testing only. Register 10-48. 1CCh Error Handler 32-Bit Error Status Type Serial EEPROM Default 0 Error Handler Completion FIFO Overflow Status Implemented for each port: 0b = No overflow detected 1b = Completion FIFO Overflow detected whenever 4-deep completion FIFO for ingress, or 2-deep completion FIFO for egress, overflows R/W1CS Yes 0b 1 Egress PRAM Soft-Error Overflow Egress Packet RAM 1-bit soft error counter overflow: 0b = No error detected 1b = TEC PRAM 1-bit Soft-Error (8-bit counter) overflow when destination packet RAM 1-bit soft error count is greater than or equal to 256, it creates an MSI/INTx R/W1CS Yes 0b 2 Egress LLIST Soft-Error Overflow Egress Link-List RAM 1-bit soft error counter overflow: 0b = No error detected 1b = TEC Link-List 1-bit Soft-Error (8-bit Counter) overflow when destination module link lists RAMs 1-bit soft error count is greater than or equal to 256, it creates an MSI/INTx R/W1CS Yes 0b 3 Egress PRAM ECC Error Egress Packet RAM 2-bit error detection: 0b = No error detected 1b = TEC PRAM 2-bit ECC error detected R/W1CS Yes 0b 4 Egress LLIST ECC Error Egress Link-List RAMs 2-bit error detection: 0b = No error detected 1b = TEC Link-List 2-bit ECC error detected R/W1CS Yes 0b 5 Ingress RAM 1-Bit ECC Error Source Packet RAM 1-bit soft error detection: 0b = No error detected 1b = ISC RAM 1-BIT ECC error detected R/W1CS Yes 0b 6 Egress Memory Allocation Unit 1-Bit Soft-Error Counter Overflow Egress Memory Allocation/De-allocation RAM 1-bit soft error count is greater than or equal to 8: 0b = No error detected 1b = Egress MAU 1-bit soft-error overflow R/W1CS Yes 0b 7 Egress Memory Allocation Unit 2-Bit Soft Error Egress Packet Memory Allocation/De-allocation RAM 2-bit error detection: 0b = No 2-bit error detected 1b = Egress MAU 2-bit soft error detected R/W1CS Yes 0b 138 Description PR EL IM IN AR Y Bit(s) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Error Checking and Debug Registers Register 10-48. 1CCh Error Handler 32-Bit Error Status Type Serial EEPROM Default 8 Ingress RAM Uncorrectable ECC Error Ingress Packet RAM 2-bit Error detection: 0b = No 2-bit error detected 1b = Packet RAM Uncorrectable ECC error detected R/W 1CS Yes 0b 9 Ingress LLIST 1-Bit ECC Error Ingress Link-List RAM 1-bit soft error detection: 0b = No error detected 1b = 1-bit ECC error detected R/W 1CS Yes 0b 10 Ingress LLIST Uncorrectable ECC Error Ingress packet Link-List RAM 2-bit error detection: 0b = No 2-bit error detected 1b = ISC Link-List Uncorrectable ECC Error detected R/W1CS Yes 0b 11 Credit Update Timeout Status No useful credit update to make forward progress for 512 ms or 1s (disabled by default) Implemented for each port: 0b = No credit-update timeout detected 1b = Credit Update Timeout completed R/W1CS Yes 0b 12 INCH Underrun Error Ingress Credit Underrun Implemented for each port. 0b = No error detected 1b = Credit underrun error detected R/W1CS Yes 0b 13 Ingress Memory Allocation Unit 1-Bit Soft Error Counter Overflow Ingress Memory Allocation/De-allocation RAM 1-bit soft-error count greater than or equal to 8. 0b = No error detected 1b = 1-bit soft error counter is > 8 R/W1CS Yes 0b 14 Ingress Memory Allocation Unit 2-Bit Soft Error Ingress Memory Allocation/De-allocation RAM 2-bit error detection for Transaction Layer Ingress Memory Allocation/De-allocation unit. 0b = No error detected 1b = 2-bit soft error detected R/W1CS Yes 0b 31:15 Description PR EL IM IN AR Y Bit(s) Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h 139 PEX 8524 Port Registers Notes: PLX Technology, Inc. Register 1D0h is reserved. Error logging is enabled by default. Register 10-49. 1D0h Error Handler 32-Bit Error Mask (Only Ports 0 and 8) Type Serial EEPROM Default 0 Error Handler Completion FIFO Overflow Status Mask Implemented for each port 0b = No affect on reporting activity 1b = Error Handler Completion FIFO Overflow Status bit is masked/ disabled R/WS Yes 1b 1 Egress PRAM Soft-Error Overflow Mask 0b = No affect on reporting activity 1b = Egress PRAM Soft-Error Overflow bit is masked/disabled R/WS Yes 1b 2 Egress LLIST Soft-Error Overflow Mask 0b = No affect on reporting activity 1b = Egress LLIST Soft-Error Overflow bit is masked/disabled R/WS Yes 1b 3 Egress PRAM ECC Error Mask 0b = No affect on reporting activity 1b = Egress PRAM ECC Error bit is masked/disabled R/WS Yes 1b 4 Egress LLIST ECC Error Mask 0b = No affect on reporting activity 1b = Egress LLIST ECC Error bit is masked/disabled R/WS Yes 1b 5 Ingress RAM 1-Bit ECC Error Mask 0b = No affect on reporting activity 1b = Ingress RAM 1-Bit ECC Error bit is masked/disabled R/WS Yes 1b 6 Egress Memory Allocation Unit 1-Bit Soft-Error Counter Overflow Mask 0b = No affect on reporting activity 1b = Egress Memory Allocation Unit 1-Bit Soft-Error Counter Overflow bit is masked/disabled R/WS Yes 1b 7 Egress Memory Allocation Unit 2-Bit Soft Error Mask 0b = No affect on reporting activity 1b = Egress Memory Allocation Unit 2-Bit Soft Error bit is masked/ disabled R/WS Yes 1b 8 Ingress RAM Uncorrectable ECC Error Mask 0b = No affect on reporting activity 1b = Ingress RAM Uncorrectable ECC Error bit is masked/disabled R/WS Yes 1b 9 Ingress LLIST 1-Bit ECC Error Mask 0b = No affect on reporting activity 1b = Ingress RAM 1-Bit ECC Error bit is masked/disabled R/WS Yes 1b 10 Ingress LLIST Uncorrectable ECC Error Mask 0b = No affect on reporting activity 1b = Ingress LLIST Uncorrectable ECC Error bit is masked/disabled R/WS Yes 1b 140 Description PR EL IM IN AR Y Bit(s) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Error Checking and Debug Registers Register 10-49. 1D0h Error Handler 32-Bit Error Mask (Only Ports 0 and 8) (Cont.) Type Serial EEPROM Default 11 Credit Update Timeout Status Mask Implemented for each port 0b = No affect on reporting activity 1b = Credit Update Timeout Status bit is masked/disabled R/WS Yes 1b 12 INCH Underrun Error Mask Implemented for each port 0b = No affect on reporting activity 1b = INCH Underrun Error bit is masked/disabled R/WS Yes 1b R/WS Yes 0b Yes 0b Bit(s) Description Ingress Memory Allocation Unit 1-Bit Soft Error Counter Overflow Mask Mask for Ingress Memory Allocation Unit 1-Bit Soft Error Counter Overflow bit 0b = No affect on reporting activity 1b = TIC_MAU 1-bit soft error counter-overflow is masked/disabled PR EL IM IN AR Y 13 Ingress Memory Allocation Unit 2-Bit Soft Error Mask 14 31:15 Mask for Ingress Memory Allocation Unit 2-Bit Soft Error bit 0b = Error reporting enabled using interrupts 1b = 2-Bit soft error reporting is masked/disabled Reserved R/WS PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h 141 PEX 8524 Port Registers PLX Technology, Inc. Register 10-50. 1DCh Debug Control (Only Port 0) Type Serial EEPROM Default Debug Mode Select Reads Debug Mode Select value on the STRAP_PROBE# and STRAP_PROM# balls. If Probe or Promiscuous mode are selected by the Strapping balls, the default Hot Plug capability is disabled. 00b = Hot Plug capability enabled 01b = Probe mode enabled 1xb = Promiscuous mode enabled HwInit Yes Set by Strapping ball levels 2 Promiscuous_Mode - Data Path Select Promiscuous_mode - Ingress/Egress Data Path selected by Strap value on the DEBUG_SEL[0] ball - An L ball connection reads as 1b, and an H ball connection reads as 0b: 0b = Ingress 128-bit data path 1b = Egress 128-bit data path HwInit No Set by Strapping ball level 3 Promiscuous_Mode - Station Select Promiscuous_mode - Station 0/1 Selected by Strap value on the DEBUG_SEL1 ball - An L ball connection reads as 1b, and an H ball connection reads as 0b: 0b = Station 0 1b = Station 1 HwInit No Set by Strapping ball level Promiscuous_Mode -- Egress Port Selection Promiscuous_mode - Egress Port Selection The Station selected by bit[3] 000b = Port 0/8 selected for monitoring 001b = Port 1/9 selected for monitoring 010b = Port 10 selected for monitoring 011b = Port 11 selected for monitoring 100b to 111b = Reserved R/W Yes 000b Probe Selection Control 0b = External STRAP_PROBE# ball controls Station 0/1 Probe Select register 1b = Software controls Station 0/1 Probe Select register R/W Yes 0b HwInit Yes Set by Strapping ball levels R/Wa Yes 0h 1:0 6:4 7 Description PR EL IM IN AR Y Bit(s) Upstream Port Number When Mode Select bits = 01b or 10b and HW/SW Configuration Mode Control bit = 0b, Upstream Port Number - Reads External strap value on the STRAP_UPSTRM_PORT_SEL[3:0] balls. When Mode Select bits = 01b or 10b and HW/SW Configuration Mode Control bit = 1b, Upstream Port Number is set by software: 11:8 0h = Port 0 8h = Port 8 1h = Port 1 9h = Port 9 2h to 7h = Reserved 10h = Port 10 11h = Port 11 12h to 15h = Reserved 142 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Error Checking and Debug Registers Register 10-50. 1DCh Debug Control (Only Port 0) (Cont.) Bit(s) 14:12 Description Type Serial EEPROM Reserved Default 000b R/W Yes 0b 16 Upstream Hot Reset Severity Control 0b = Reset NT Port data path when Upstream port receives Hot Reset or DL-down condition 1b = Do not reset NT Port data path when Upstream port receives Hot Reset or DL-down condition (01b is automatically set as default in NT mode.) R/W Yes 0b 17 Hot Reset EEPROM Load Disable EEPROM load disable only for Hot Reset or DL-down condition; does not affect Fundamental reset. 0b = EEPROM load enabled upon Hot Reset 1b = EEPROM load disabled upon Hot Reset R/W Yes 0b HwInit Yes Set by Strapping ball levels When HW/SW Configuration Mode Control bit = 1b, the mode is selected by the following bits set by software: 00b = Reserved 01b = NT Intelligent Adapter mode 10b = NT Dual-Host mode 11b = T mode R/Wa Yes 11b Upstream Port Hot Reset Propagation Disable 0b = Internal Reset and Hot Reset propagation are enabled 1b = Internal Reset and Hot Reset propagation are disabled Set to 1b for NT Dual-Host mode. R/W Yes 0b PR EL IM IN AR Y 15 HW/SW Configuration Mode Control Hardware/Software Configuration Mode Control: 0b = Strapping balls control Upstream Port, NT Port, and Mode select 1b = Software controls Upstream Port, NT Port and Mode select Mode Select When HW/SW Configuration Mode Control bit = 0b, the Mode is selected by STRAP_MODE_SEL[1:0] Strapping balls. 19:18 20 23:21 Reserved 000b NT Port Number When Mode Select bits = 01b or 10b and HW/SW Configuration Mode Control bit = 0b, the NT port number is set by STRAP_NT_UPSTRM_PORT_SEL[3:0] Strapping balls. These bits are "don't care" for T mode. HwInit Yes Set by Strapping ball levels R/Wa Yes 0h When Mode Select bits = 01b or 10b and HW/SW Configuration Mode Control bit = 1b, the NT port number is selected by these bits set by software: 27:24 0h = Port 0 8h = Port 8 1h = Port 1 9h = Port 9 2h to 7h = Reserved 10h = Port 10 11h = Port 11 12h to 15h = Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 143 PEX 8524 Port Registers PLX Technology, Inc. Register 10-50. 1DCh Debug Control (Only Port 0) (Cont.) Type Serial EEPROM Default 28 Virtual Interface Access Enable Used only in NT mode. 0b = Retry the Type 0 Configuration TLP received on NT Port Virtual Interface - NT Intelligent Adapter mode 1b = Accepts Type 0 Configuration TLP on NT Port Virtual Interface - NT Dual Host mode Note: This bit does not affect the PEX 8524 in Transparent mode. R/W Yes 1b 29 Link Interface Access Enable Used only in NT mode. 0b = Retry the Type 0 Configuration TLP received on NT Port Link Interface 1b = Accepts Type 0 Configuration TLP on NT Port Link Interface Note: This bit does not affect the PEX 8524 in Transparent mode. R/W Yes 0b 30 SerDes Lane Status Control On Card SerDes Lane Status Control: 0b = Physical Layer signals control on card PEX_LANE_GOOD[7:0]# and PEX_LANE_GOOD[31:16]# outputs 1b = Software driven value to Offset 1F4h controls the On Card SerDes Lane-Good output R/W Yes 0b 31 Power-Up BIST Status Reports the power-up BIST result (RAM BIST result) 0b = No power-up BIST error 1b = Fatal Error detected - not recoverable; must replace PEX 8524 device R/W Yes 0b Description PR EL IM IN AR Y Bit(s) a.Although these bits are R/W, do not change by software. 144 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Error Checking and Debug Registers Register 10-51. 1E0h Power Management Hot Plug User Configuration (All Ports) Type Serial EEPROM Default 0 L0s Entry Idle Count Time to meet to enter L0s: 0b = Idle condition lasts for 1 s 1b = Idle condition lasts for 4 s R/W Yes 0b 1 L1 Upstream Port Receiver Idle Count For active L1 entry: 0b = Upstream port receiver idle for 2 s 1b = Upstream port receiver idle for 3 s R/W Yes 0b 2 HPC PME Turn-Off Enable 1b = PME Turn-off message is transmitted before the port is turned-off on Downstream port R/W Yes 0b HPC TPEPV Enable Slot power-applied to power-valid delay time: 00b = 16 ms 01b = 32 ms 10b = 64 ms 11b = 128 ms RO Yes 01b 5 HPC Inband Presence - Detect Enable 0b = HP_PRSNT[3:0]# or HP_PRSNT[11:8]# input balls are used to detect a card present in the slot 1b = SerDes receiver detect mechanism is used to detect a card present in the slot RO Yes 0b 6 HPC TPVPERL Enable Downstream port power valid to reset signal release time: 0b = 20 ms 1b = 100 ms (default) RO Yes 1b 12:7 HPC Test Bits Factory Only Testing bits - must be 000_000b. RO Yes 000_000b 31:13 Reserved 4:3 Description PR EL IM IN AR Y Bit(s) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h 145 PEX 8524 Port Registers PLX Technology, Inc. Register 10-52. 1E4h TEC Control and Status (All Ports) Type Serial EEPROM Default 0 Egress Credit Update Timer Enable In this mode, when the port is not receiving credits to make forward progress and the TEC TIMEOUT timer times out, the downstream link is brought down. 0b = Egress Credit update timer disabled 1b = Egress Credit update timer enabled R/W Yes 0b 1 TEC Timeout Value 0b = Minimum 512 ms (maximum 768 ms) 1b = Minimum 1.024 s (maximum 1.28 s) R/W Yes 0b 2 DL-Down Handling 0b = Reports unsupported request error for all TLP requests received in DL-Down state 1b = Reports unsupported request for first Posted/Non-posted TLP request in DL-Down state - silently drops subsequent TLP requests R/W Yes 0b Description PR EL IM IN AR Y Bit(s) 7:3 Reserved 0-0h 15:8 Link-List RAM Soft Error Count Link-List RAM 8-bit Soft Error Counter value: Counter shared by: * Packet Link-List RAM * Packet Link-List De-allocation RAM * Scheduler Data RAM Counter increments for 1-bit soft errors detected in any of these RAMs. RO Yes 00h 19:16 VC&T Encountered Timeout 0h = VC0 Posted 1h = VC0 Non-Posted 2h = VC0 Completion 3h = VC1 Posted 4h = VC1 Non-Posted 5h = VC1 Completion RO Yes 0h 23:20 Reserved 31:24 Packet RAM Soft Error Count Counter increments for each 1-bit soft error detected in RAM. 0h RO Yes 00h Type Serial EEPROM Default R/W Yes 00h Register 10-53. 1E8h Bad TLP Count (All Ports) Bit(s) Description 7:0 Bad TLP Count Counts number of bad TLP LCRC or sequence number mismatches errors. 31:8 Reserved 146 0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Error Checking and Debug Registers Register 10-54. 1ECh Bad DLLP Count (All Ports) Bit(s) Description 7:0 Bad DLLP Count Counts number of bad DLLP LCRC or sequence number mismatches errors. 31:8 Reserved Type Serial EEPROM Default R/W Yes 00h 0h Register 10-55. 1F4h Software-Controlled Lane Status (Only Port 0) Bit(s) Software-Controlled Lane Status Software Controlled Lane Status: Bit[31] controls SerDes Lane 31 Bit[30] controls SerDes Lane 30 ... Bit[0] controls SerDes Lane 0 Type Serial EEPROM Default RO Yes 0-0h When 1DCh[30] = 0b PR EL IM IN AR Y 31:0 Description When 1DCh[30] = 1b Register 10-56. 1F8h ACK Transmission Latency Limit (All Ports) Bit(s) Description Type Serial EEPROM Default R/W Yes FFh R/W Yes 00h ACK Transmission Latency Limit Value based on the programmed link width encoding, when PL_PORT_DATA is active: Register Value 7:0 Link Width Decimal Hex 255 FFh x1 217 D9h x2 118 76h x4 107 6Bh x8 15:8 HPC Test Bits Factory Only Testing bits - must be 00h 31:16 Reserved 0000h Register 10-57. 208h PLX DLL-Specific Bit(s) 31:0 Description Type Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Serial EEPROM Default 0-h 147 PEX 8524 Port Registers 10.13.2 Table 10-13. PLX Technology, Inc. Physical Layer Registers PLX-Specific Error Check/Debug and Physical Layer Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Test Pattern_0 210h Test Pattern_1 214h Test Pattern_2 218h Test Pattern_3 21Ch Physical Layer Status (Physical Layer Status and Control) Physical Layer Control (Physical Layer Status and Control) 220h 224h Physical Layer Test 228h Physical Layer 22Ch Physical Layer Port Command 230h Skip-Ordered Set Interval 234h Quad SerDes[0-3] Diagnostics Data 238h Quad SerDes[4-7] Diagnostics Data 23Ch Quad SerDes[8-11] Diagnostics Data 240h Quad SerDes[12-15] Diagnostics Data 244h SerDes Nominal Current Select 248h SerDes Driver Current Level_1 24Ch SerDes Driver Current Level_2 250h SerDes Driver Equalization Level Select_1 254h SerDes Driver Equalization Level Select_2 258h Physical Layer Miscellaneous 25Ch PR EL IM IN AR Y Port Configuration Status Data from EEPROM / EEPROM Status EEPROM Control (EEPROM Status and Control) EEPROM Buffer Reserved 260h 264h 268h - 2C4h Note: In this section the term "SerDes quad" or "quad" refers to assembling SerDes lanes into groups of four contiguous lanes for testing purposes. For Station_0, the quads are defined as SerDes[0-3], SerDes[4-7], SerDes[8-11], and SerDes[12-15]. For Station_1, the quads are SerDes[16-19], SerDes[20-23], SerDes[24-27], and SerDes[28-31]. 148 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Physical Layer Registers Register 10-58. 210h Test Pattern_0 (Only Ports 0, 8, and NT Port Link Interface) Bit(s) 31:0 Description Test Pattern_0 Used for digital far-end loop-back testing Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Register 10-59. 214h Test Pattern_1 (Only Ports 0, 8, and NT Port Link Interface) Bit(s) 31:0 Description Test Pattern_1 Used for digital far-end loop-back testing. Bit(s) 31:0 PR EL IM IN AR Y Register 10-60. 218h Test Pattern_2 (Only Ports 0, 8, and NT Port Link Interface) Description Test Pattern_2 Used for digital far-end loop-back testing. Register 10-61. 21Ch Test Pattern_3 (Only Ports 0, 8, and NT Port Link Interface) Bit(s) 31:0 Description Test Pattern_3 Used for digital far-end loop-back testing. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 149 PEX 8524 Port Registers PLX Technology, Inc. Register 10-62. 220h Physical Layer Status and Control (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description Type Serial EEPROM Default Physical Layer Control 0 Port Enumerator Enable 0b = Enumerate not enabled 1b = Enumerate enabled HwInit No 0b 1 TDM Enable 0b = TDM not enabled 1b = TDM enabled HwInit No 0b 2 Reserved 3 Upstream Port as Configuration Master Enable 0b = Upstream Port Cross-link not supported 1b = Upstream Port Cross-link supported R/W Yes 0b 4 Downstream Port as Configuration Slave Enable 0b = Downstream Port Cross-link not supported 1b = Downstream Port Cross-link supported R/W Yes 0b 5 Lane Reversal Disable 0b = Lane reversal supported 1b = Lane reversal not supported R/W Yes 0b 6 PLL Turn-Off Enable 0b = PLL turn-off disabled 1b = PLL turn-off enabled R/W Yes 0b 7 FC-Init Triplet Enable Flow control Initialization. 0b = Init FL1 Triplet can be interrupted by skip-ordered set/Idle-data symbol 1b = Init FL1 Triplet not interrupted R/W Yes 1b N_FTS Value N_FTS value to transmit in training sets. R/W Yes 40h 150 PR EL IM IN AR Y 15:8 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Physical Layer Registers Register 10-62. 220h Physical Layer Status and Control (Only Ports 0, 8, and NT Port Link Interface) (Cont.) Bit(s) Description Type Serial EEPROM Default Physical Layer Status 19:16 Reserved 0h 22:20 Number of Ports Enumerated Number of ports in current configuration. HwInit Yes 00b Reserved 24 Port_0 Deskew Buffer Error Status 1b = Deskew Buffer overflow or underflow R/W1C Yes 0b 25 Port_1 Deskew Buffer Error Status 1b = Deskew Buffer overflow or underflow R/W1C Yes 0b 26 Port_2 Deskew Buffer Error Status 1b = Deskew Buffer overflow or underflow R/W1C Yes 0b 27 Port_3 Deskew Buffer Error Status 1b = Deskew Buffer overflow or underflow R/W1C Yes 0b 31:28 Reserved 0b PR EL IM IN AR Y 23 0h Register 10-63. 224h Port Configuration (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description 2:0 Port Configuration Initialized with EEPROM, or value on strap inputs STRAP_STN0_PORTCFG[4:0] and STRAP_STN1_ PORTCFG[3:0]. Strapping balls/bits [4:3] are always LL or 00b. 31:3 Reserved Type Serial EEPROM Default HwInit Yes 000b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h 151 PEX 8524 Port Registers PLX Technology, Inc. Register 10-64. 228h Physical Layer Test (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Type Serial EEPROM Default Timer Test Mode Enable 0b = Normal Physical Layer Timer parameters used 1b = Shortens Timer scale from milliseconds to microseconds R/W Yes 0b 1 Skip-Timer Test Mode Enable 0b = Disables Skip-Timer Test mode 1b = Enables Skip-Timer Test mode R/W Yes 0b 2 Port_0_x1 1b = Ports 0 and 8 are configured as x1 only R/W Yes 0b 3 TCB Capture Disable 0b = Training Control Bit (TCB) Capture enabled 1b = Disables TCB Capture R/W Yes 0b 4 Analog Loop-Back Enable When = 1b, analog loop-back testing enabled (loop-back before elastic buffer). R/W Yes 0b 5 Port/SerDes Test-Pattern Enable Select When = 1b, the Test-Pattern Enable bits select ports rather than SerDes quads. R/W Yes 0b 6 Reserved 7 SerDes BIST Enable When = 1b by the EEPROM, enables SerDes internal loop-back PRBS test for 512 s before starting link initialization. RO Yes 0b PRBS Association Selects the SerDes within the quad for PRBS generation/checking: Value Selects SerDes 00b = [0, 4, 8, 12] 01b = [1, 5, 9, 13] 10b = [2, 6, 10, 14] 11b = [3, 7, 11, 15] R/W Yes 00b 15:10 Reserved PR EL IM IN AR Y 0 9:8 152 Description 0b 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Physical Layer Registers Register 10-64. 228h Physical Layer Test (Only Ports 0, 8, and NT Port Link Interface) Type Serial EEPROM Default R/W Yes 0h R/W Yes 0h 27:24 PRBS Error Count Reset Resets the PRBS error counter when 1b: Bit PRBS Error Count Offset Reset 24 238h[31:24] 25 23Ch[31:24] 26 240h[31:24] 27 244h[31:24] R/W Yes 0h 31:28 Test Pattern Enable Enables test pattern transmission in Digital Far mode and Loop-Back mode: SerDes Enabled When Bit [0-3] 28 = 1b [4-7] 29 = 1b [8-11] 30 = 1b 12-15] 31 = 1b R/W Yes 0h Bit(s) 19:16 Description PRBS Enable When set to 1b, enables PRBS sequence generation/checking on SerDes quads: Bit Controls SerDes [16] [0-3] [17] [4-7] [18] [8-11] [19] [12-15] 21 23:20 PR EL IM IN AR Y PRBS External Loop-Back The following bit commands are valid when Loop-Back Command is enabled in offset 230h: Bit Value 20 0b = SerDes[0-3] establishes internal analog loop-back when bit 16=1b 1b = SerDes[0-3] establishes external analog loop-back when bit 16=1b 0b = SerDes[4-7] establishes internal analog loop-back when bit 17=1b 1b = SerDes[4-7] establishes external analog loop-back when bit 17=1b 22 0b = SerDes[8-11] establishes internal analog loop-back when bit 18=1b 1b = SerDes[8-11] establishes external analog loop-back when bit 18=1b 23 0b = SerDes[12-15] establishes internal analog loop-back when bit 19=1b 1b = SerDes[12-15] establishes external analog loop-back when bit 19=1b Note: Parameters in register 228h are defined for Ports 0 and 8 of Station 0; the equivalent parameters, and the associated SerDes, apply to Ports 0 and 8 of Station 1. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 153 PEX 8524 Port Registers PLX Technology, Inc. Register 10-65. 22Ch Physical Layer Bit(s) 31:0 Description Factory Test Only. Type Serial EEPROM Default R/W Yes 0-0h Register 10-66. 230h Physical Layer Port Command (Only Ports 0, 8, and NT Port Link Interface) Bit(s) 154 Description Type Serial EEPROM Default Yes 0b Port_0 Loop-Back 0b = Port 0 not enabled to go to Loop-Back state 1b = Port 0 enabled to go to Loop-Back state R/W 1 Port_0 Scrambler Disable If EEPROM load sets this bit, scrambler disabled in ConfigurationComplete state. If software sets this bit when Link is in up state, hardware immediately disables its scrambler without executing Link Training protocol. The upstream/downstream device scrambler will not be disabled. 0b = Port 0 scrambler enabled 1b = Port 0 scrambler disabled R/W Yes 0b 2 Port_0 Rx L1 Only Port 0 Receiver Enters to ASPM L1. 0b = Port 0 receiver allowed to go to ASPM L0s or L1 state when it detects Electrical Idle ordered set in L0 state 1b = Port 0 receiver allowed to go to ASPM L1 only when it detects Electrical Idle ordered set in L0 state R/W Yes 0b 3 Port_0 Loop-Back Master Port 0 LTSSM established Loop-Back as a Master. 0b = Port 0 not in Loop-Back Master mode 1b = Port 0 in Loop-Back Master mode RO No 0b PR EL IM IN AR Y 0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Physical Layer Registers Register 10-66. 230h Physical Layer Port Command (Only Ports 0, 8, and NT Port Link Interface) (Cont.) Bit(s) Description Type Serial EEPROM Default Port_1 Loop-Back 0b = Port 1 not enabled to go to Loop-Back state 1b = Port 1 enabled to go to Loop-Back state R/W Yes 0b 5 Port_1 Scrambler Disable If EEPROM load sets this bit, scrambler disabled in ConfigurationComplete state. If software sets this bit when Link is in up state, hardware immediately disables its scrambler without executing Link Training protocol. The upstream/downstream device scrambler is not disabled. 0b = Port 1 scrambler enabled 1b = Port 1 scrambler disabled R/W Yes 0b 6 Port_1 Rx L1 Only Port 1 Receiver Enters to ASPM L1 0b = Port 1 receiver allowed to go to ASPM L0s or L1 state when it detects Electrical Idle ordered set in L0 state 1b = Port 1 receiver allowed to go to ASPM L1 only when it detects Electrical Idle ordered set in L0 state R/W Yes 0b 7 Port_1 Loop-Back Master Port 1 LTSSM established Loop-Back as a Master. 0b = Port 1 not in Loop-Back Master mode 1b = Port 1 in Loop-Back Master mode RO No 0b 31:8 Reserved PR EL IM IN AR Y 4 0-0h Register 10-67. 234h Skip-Ordered Set Interval (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description 11:0 SKP-Ordered Set Interval SKP-Ordered Set Interval, in symbol times. 31:12 Reserved Type Serial EEPROM Default R/WS Yes 49Ch PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0000_0h 155 PEX 8524 Port Registers PLX Technology, Inc. Register 10-68. 238h Quad SerDes[0-3] Diagnostics Data (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description Type Serial EEPROM Default 9:0 Expected PRBS Data Expected PRBS SerDes[0-3]/[16-19] Diagnostic data. RO Yes 00h 19:10 Received PRBS Data Received PRBS SerDes[0-3]/[16-19] Diagnostic data. RO Yes 00h 23:20 Reserved 31:24 PRBS Error Count PRBS SerDes[0-3]/[16-19] Error count (0 to 255). 0h RO Yes 00h PR EL IM IN AR Y Note: Parameters in register 238h are defined for Port 0 of Station 0, SerDes[0-3]; the equivalent parameters, and the associated SerDes, apply to Port 8 of Station 1, SerDes[16-19]. Register 10-69. 23Ch Quad SerDes[4-7] Diagnostics Data (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description Type Serial EEPROM Default 9:0 Expected PRBS Data Expected PRBS SerDes[4-7]/[20-23] Diagnostic data. RO Yes 00h 19:10 Received PRBS Data Received PRBS SerDes[4-7]/[20-23] Diagnostic data. RO Yes 00h 23:20 Reserved 31:24 PRBS Error Count PRBS SerDes[4-7]/[20-23] Error count (0 to 255). RO 0h Yes 00h Note: Parameters in register 23Ch are defined for Port 0 of Station_0, SerDes[4-7]; the equivalent parameters, and the associated SerDes, apply to Port 8 of Station_1, SerDes[20-23]. Register 10-70. 240h Quad SerDes[8-11] Diagnostics Data (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description Type Serial EEPROM Default 9:0 Expected PRBS Data Expected PRBS SerDes[8-11]/[24-27] Diagnostic data. RO Yes 00h 19:10 Received PRBS Data Received PRBS SerDes[8-11]/[24-27] Diagnostic data. RO Yes 00h 23:20 Reserved 31:24 PRBS Error Count PRBS SerDes[8-11]/[24-27] Error count (0-255). 0h RO Yes 00h Note: Parameters in register 240h are defined for Port 0 of Station_0, SerDes[8-11]; the equivalent parameters, and the associated SerDes, apply to Port 8 of Station_1, SerDes[24-27]. 156 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Physical Layer Registers Register 10-71. 244h Quad SerDes[12-15] Diagnostics Data (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description Type Serial EEPROM Default 9:0 Expected PRBS Data Expected PRBS SerDes[12-15]/[28-31] Diagnostic data. RO Yes 00h 19:10 Received PRBS Data Received PRBS SerDes[12-15]/[28-31] Diagnostic data. RO Yes 00h 23:20 Reserved 31:24 PRBS Error Count PRBS SerDes[12-15]/[28-31] Error count (0 to 255). 0h RO Yes 00h PR EL IM IN AR Y Note: Parameters in register 244h are defined for Port 0 of Station_0, SerDes[12-15]; the equivalent parameters, and the associated SerDes, apply to Port 8 of Station_1, SerDes[28-31]. Register 10-72. 248h SerDes Nominal Current Select (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description Type Serial EEPROM Default 1:0 SerDes_0 Nominal Drive Current R/WS Yes 00b 3:2 SerDes_1 Nominal Drive Current R/WS Yes 00b 5:4 SerDes_2 Nominal Drive Current R/WS Yes 00b 7:6 SerDes_3 Nominal Drive Current R/WS Yes 00b 9:8 SerDes_4 Nominal Drive Current R/WS Yes 00b 11:10 SerDes_5 Nominal Drive Current R/WS Yes 00b R/WS Yes 00b R/WS Yes 00b R/WS Yes 00b R/WS Yes 00b The following values for Nominal Current apply to each driver: * 00b = 20 mA * 01b = 10 mA * 10b = 28 mA * 11b = 20 mA 13:12 SerDes_6 Nominal Drive Current 15:14 SerDes_7 Nominal Drive Current 17:16 SerDes_8 Nominal Drive Current 19:18 SerDes_9 Nominal Drive Current 21:20 SerDes_10 Nominal Drive Current R/WS Yes 00b 23:22 SerDes_11 Nominal Drive Current R/WS Yes 00b 25:24 SerDes_12 Nominal Drive Current R/WS Yes 00b 27:26 SerDes_13 Nominal Drive Current R/WS Yes 00b 29:28 SerDes_14 Nominal Drive Current R/WS Yes 00b 31:30 SerDes_15 Nominal Drive Current R/WS Yes 00b Note: Parameters in register 248h are defined for Port 0 of Station 0; the equivalent parameters, and the associated SerDes, apply to Port 8 of Station 1. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 157 PEX 8524 Port Registers PLX Technology, Inc. Register 10-73. 24Ch SerDes Driver Current Level_1 (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description 3:0 SerDes_0 Driver Current Level 7:4 SerDes_1 Driver Current Level 11:8 SerDes_2 Driver Current Level SerDes_3 Driver Current Level 19:16 SerDes_4 Driver Current Level 23:20 SerDes_5 Driver Current Level 27:24 SerDes_6 Driver Current Level 31:28 SerDes_7 Driver Current Level 0h = 1.00 1h = 1.05 2h = 1.10 3h = 1.15 4h = 1.20 5h = 1.25 6h = 1.30 7h = 1.35 8h = 0.60 9h = 0.65 Ah = 0.70 Bh = 0.75 Ch = 0.80 Dh = 0.85 Eh = 0.90 Fh = 0.95 Serial EEPROM Default R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h PR EL IM IN AR Y 15:12 The following values represent the ratio of Actual Current/Nominal Current (selected in SerDes Nominal Current Select register) and apply to each driver: Type Note: Parameters in register 24Ch are defined for Port 0 of Station_0, SerDes[0-7]; the equivalent parameters, and the associated SerDes, apply to Port 8 of Station_1, SerDes[16-23]. Register 10-74. 250h SerDes Driver Current Level_2 (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description 3:0 SerDes_8 Driver Current Level 7:4 SerDes_9 Driver Current Level 11:8 SerDes_10 Driver Current Level 15:12 SerDes_11 Driver Current Level 19:16 SerDes_12 Driver Current Level 23:20 SerDes_13 Driver Current Level 27:24 SerDes_14 Driver Current Level 31:28 SerDes_15 Driver Current Level The following values represent the ratio of Actual Current / Nominal Current (selected in SerDes Nominal Current Select register) and apply to each driver: 0h = 1.00 1h = 1.05 2h = 1.10 3h = 1.15 4h = 1.20 5h = 1.25 6h = 1.30 7h = 1.35 8h = 0.60 9h = 0.65 Ah = 0.70 Bh = 0.75 Ch = 0.80 Dh = 0.85 Eh = 0.90 Fh = 0.95 Type Serial EEPROM Default R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h R/WS Yes 0h Note: Parameters in register 250h are defined for Port 0 of Station_0, SerDes[8-15]; the equivalent parameters, and the associated SerDes, apply to Port 8 of Station_1, SerDes[24-31]. 158 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Physical Layer Registers Register 10-75. 254h SerDes Driver Equalization Level Select_1 (Only Ports 0, 8, and NT Port Link Interface) Bit(s) Description SerDes_0 Driver Equalization Level 7:4 SerDes_1 Driver Equalization Level 11:8 SerDes_2 Driver Equalization Level 15:12 SerDes_3 Driver Equalization Level 19:16 SerDes_4 Driver Equalization Level 23:20 SerDes_5 Driver Equalization Level 27:24 SerDes_6 Driver Equalization Level 31:28 SerDes_7 Driver Equalization Level The following values represent the percentage of Drive current that is attributable to Equalization current, and apply to each driver: IEQ / IDR De-Emphasis (dB) 0h = 0.00 1h = 0.04 2h = 0.08 3h = 0.12 4h = 0.16 5h = 0.20 6h = 0.24 7h = 0.28 8h = 0.32 9h = 0.36 Ah = 0.40 Bh = 0.44 Ch = 0.48 Dh = 0.52 Eh = 0.56 Fh = 0.60 0.00 -0.35 -0.72 -1.11 -1.51 -1.94 -2.38 -2.85 -3.35 -3.88 -4.44 -5.04 -5.68 -6.38 -7.13 -7.96 PR EL IM IN AR Y 3:0 Type Serial EEPROM Default R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h Note: Parameters in register 254h are defined for Port 0 of Station_0, SerDes[0-7]; the equivalent parameters, and the associated SerDes, apply to Port 8 of Station_1, SerDes[16-23]. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 159 PEX 8524 Port Registers PLX Technology, Inc. Register 10-76. 258h SerDes Driver Equalization Level Select_2 (Only Ports 0, 8, and NT Port Link Interface) Description 3:0 SerDes_8 Driver Equalization Level 7:4 SerDes_9 Driver Equalization Level 11:8 SerDes_10 Driver Equalization Level 15:12 SerDes_11 Driver Equalization Level 19:16 SerDes_12 Driver Equalization Level 23:20 SerDes_13 Driver Equalization Level 27:24 SerDes_14 Driver Equalization Level 31:28 SerDes_15 Driver Equalization Level The following values represent the percentage of Drive current that is attributable to Equalization current, and apply to each driver: IEQ / IDR De-Emphasis (dB) 0h = 0.00 1h = 0.04 2h = 0.08 3h = 0.12 4h = 0.16 5h = 0.20 6h = 0.24 7h = 0.28 8h = 0.32 9h = 0.36 Ah = 0.40 Bh = 0.44 Ch = 0.48 Dh = 0.52 Eh = 0.56 Fh = 0.60 0.00 -0.35 -0.72 -1.11 -1.51 -1.94 -2.38 -2.85 -3.35 -3.88 -4.44 -5.04 -5.68 -6.38 -7.13 -7.96 Type Serial EEPROM Default R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h R/WS Yes 8h PR EL IM IN AR Y Bit(s) Note: Parameters in register 258h are defined for Port 0 of Station_0, SerDes[8-15]; the equivalent parameters, and the associated SerDes, apply to Port 8 of Station_1, SerDes[24-31]. Register 10-77. 25Ch Physical Layer Miscellaneous Bit(s) 31:0 160 Description Reserved Type Serial EEPROM Default 0-h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Physical Layer Registers Register 10-78. 260h EEPROM Status and Control (Only Port 0) Bit(s) Description Type Serial EEPROM Default 12:0 EEPROM Block Address EEPROM Block Address for 32 KB. R/W Yes 000h 15:13 EEPROM Command Commands to serial EEPROM Controller: 001b = Data from EEPROM STATUS[31:24] bits written to EEPROM internal status register. 010b = Write four bytes of data from the EEPROM Buffer into memory location pointed to by the EEPROM Block Address. 011b = Read four bytes of data from memory location pointed to by the EEPROM Block Address into EEPROM Buffer. 100b = Reset Write Enable latch 101b = Data from EEPROM internal status register written to EEPROM STATUS[31:24] bits 110b = Set Write Enable latch All other encodings are Reserved. R/W Yes 000b PR EL IM IN AR Y EEPROM Control EEPROM Status 17:16 EEPROM Present Serial EEPROM Present status. 00b = Not present 01b = EEPROM Present - no CRC error 10b = Reserved 11b = EEPROM Present, but with CRC error - default reset value used RO Yes 00b 19:18 EEPROM Command Status Serial EEPROM Command status. 00b = EEPROM Command complete 01b = EEPROM Command not complete 10b = EEPROM Command complete with CRC error 11b = Reserved RO Yes 00b R/W Yes 0b R/W Yes 0b EEPROM Block Address Upper Bit 20 21 23:22 EEPROM Block Address upper bit[13]. Extends EEPROM to 64 KB. CRC Disable 0b = EEPROM input data uses CRC 1b = EEPROM input data CRC disabled Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 00b 161 PEX 8524 Port Registers PLX Technology, Inc. Register 10-78. 260h EEPROM Status and Control (Only Port 0) (Cont.) Type Serial EEPROM Default 24 EEPROM_RDY# 0b = EEPROM ready to transmit data 1b = Write cycle in progress R/W Yes 0b 25 EEPROM_WEN 0b = EEPROM Write disabled 1b = EEPROM Write enabled R/W Yes 0b Yes 00b Bit(s) Description Status Data from EEPROM EEPROM_BP[1:0] EEPROM Block-Write Protect bits. 30:28 31 Level 32 KB Device 64 KB Device 00b 0 None None 01b 1 (1/4) 6000h - 7FFFh 10b 2 (1/2) 4000h - 7FFFh 11b 3 (All) 0000h - 7FFFh PR EL IM IN AR Y 27:26 Array Addresses Protected BP[1:0] R/W EEPROM Write Status EEPROM Write Status = 000b when EEPROM is not in an internal Write cycle. EEPROM_WPEN EEPROM Write Protect Enable. When: = 0b and EEPROM_WEN = 1b, the EEPROM Status register is writable. = 1b, EEPROM Status register is protected. R/W 000b Yes 0b Register 10-79. 264h EEPROM Buffer (Only Port 0 and NT Port Link Interface) Bit(s) 31:0 162 Description EEPROM Buffer Type Serial EEPROM Default R/W Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 10.13.3 CAM Routing Registers CAM Routing Registers The CAM Routing registers contain mirror copies of the registers used for: * Bus-Number CAM (Content Addressable Memory) - Used to determine completion route These registers contain mirror copies of the Secondary Bus Number registers and the Subordinate Bus Number registers of PCI-to-PCI bridges in the PEX 8524. * I/O CAM - Used to determine I/O request routing These registers contain mirror copies of the I/O Limit and I/O Base registers of the ports/virtual PCI-to-PCI bridges in the PEX 8524. * AMCAM (Address-Mapping CAM) - Used to determine Memory I/O request route These registers contain mirror images of the corresponding port Memory Base and Memory Limit, Prefetchable Base and Prefetchable Limit, and Prefetchable Base Upper and Prefetchable Limit Upper registers of the PEX 8524 PCI bridges. Table 10-14. PR EL IM IN AR Y These registers are automatically updated by hardware. Modifying these registers is not recommended. PLX-Specific CAM Register Map (Only Ports 0 and 8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bus Number CAM 0 2C8h Bus Number CAM 1 2CCh Bus Number CAM 2 2D0h Bus Number CAM 3 2D4h Reserved 2D8h - 2E4h Bus Number CAM 8 2E8h Bus Number CAM 9 2ECh Bus Number CAM 10 2F0h Bus Number CAM 11 2F4h Reserved 2F8h - 304h I/O CAM_1 I/O CAM_0 308h I/O CAM_3 I/O CAM_2 30Ch Reserved 310h - 314h I/O CAM_9 I/O CAM_8 318h I/O CAM_11 I/O CAM_10 31Ch Reserved 320h - 344h AMCAM_0 Memory Limit and Base 348h AMCAM_0 Prefetchable Memory Limit and Base[31:0] 34Ch AMCAM_0 Prefetchable Memory Base[63:32] 350h AMCAM_0 Prefetchable Memory Limit[63:32] 354h AMCAM_1 Memory Limit and Base 358h AMCAM_1 Prefetchable Memory Limit and Base[31:0] 35Ch AMCAM_1 Prefetchable Memory Base[63:32] 360h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 163 PEX 8524 Port Registers Table 10-14. PLX Technology, Inc. PLX-Specific CAM Register Map (Only Ports 0 and 8) (Cont.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AMCAM_1 Prefetchable Memory Limit[63:32] 364h AMCAM_2 Memory Limit and Base 368h AMCAM_2 Prefetchable Memory Limit and Base[31:0] 36Ch AMCAM_2 Prefetchable Memory Base[63:32] 370h AMCAM_2 Prefetchable Memory Limit[63:32] 374h AMCAM_3 Memory Limit and Base 378h AMCAM 3 Prefetchable Memory Limit and Base[31:0] 37Ch AMCAM 3 Prefetchable Memory Base[63:32] 380h AMCAM 3 Prefetchable Memory Limit[63:32] 384h PR EL IM IN AR Y Reserved 388h - AMCAM 8 Memory Limit and Base 3C8h AMCAM 8 Prefetchable Memory Limit and Base[31:0] 3CCh AMCAM 8 Prefetchable Memory Base[63:32] 3D0h AMCAM 8 Prefetchable Memory Limit[63:32] 3D4h AMCAM 9 Memory Limit and Base 3D8h AMCAM 9 Prefetchable Memory Limit and Base[31:0] 3DCh AMCAM 9 Prefetchable Memory Base[63:32] 3E0h AMCAM 9 Prefetchable Memory Limit[63:32] 3E4h AMCAM 10 Memory Limit and Base 3E8h AMCAM 10 Prefetchable Limit and Memory Base[31:0] 3ECh AMCAM 10 Prefetchable Memory Base[63:32] 3F0h AMCAM 10 Prefetchable Memory Limit[63:32] 3F4h AMCAM 11 Memory Limit and Base 3F8h AMCAM 11 Prefetchable Limit and Memory Base[31:0] 3FCh AMCAM 11 Prefetchable Memory Base[63:32] 400h AMCAM 11 Prefetchable Memory Limit[63:32] 404h Reserved 408h - Reserved 544h 548h Reserved 54Ch - 5C4h Reserved 5C8h - 65Ch TIC Control 660h Reserved 664h TIC Port Enable 668h Reserved 164 3C4h 66Ch - 67Ch I/OCAM_0 for Port 0 680h I/OCAM_1 for Port 1 684h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Table 10-14. CAM Routing Registers PLX-Specific CAM Register Map (Only Ports 0 and 8) (Cont.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I/OCAM_2 for Port 2 688h I/OCAM_3 for Port 3 68Ch Reserved 690h - I/OCAM_8 for Port 8 6A0h I/OCAM_9 for Port 9 6A4h I/OCAM_10 for Port 10 6A8h I/OCAM_11 for Port 11 6ACh Reserved 6B0h - 6BCh Bus Number CAM Registers PR EL IM IN AR Y 10.13.3.1 69Ch Register 10-80. 2C8h Bus Number CAM 0 (Only Ports 0 and 8) Bit(s) Description Type Serial EEPROM Default 7:0 Primary Bus Number Mirror copy of Port 0 Primary Bus Number. R/W Yes 00h 15:8 Secondary Bus Number Mirror copy of Port 0 Secondary Bus Number. R/W Yes FFh 23:16 Subordinate Bus Number Mirror copy of Port 0 Subordinate Bus Number. R/W Yes 00h 31:24 Reserved 00h Register 10-81. 2CCh Bus Number CAM 1 (Only Ports 0 and 8) Bit(s) Description Type Serial EEPROM Default 7:0 Primary Bus Number Mirror copy of Port 1 Primary Bus Number. R/W Yes 00h 15:8 Secondary Bus Number Mirror copy of Port 1 Secondary Bus Number. R/W Yes FFh 23:16 Subordinate Bus Number Mirror copy of Port 1 Subordinate Bus Number. R/W Yes 00h 31:24 Reserved 00h Register 10-82. 2D0h Bus Number CAM 2 (Only Ports 0 and 8) Bit(s) 31:0 Description Type Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Serial EEPROM Default 0h 165 PEX 8524 Port Registers PLX Technology, Inc. Register 10-83. 2D4h Bus Number CAM 3 (Only Ports 0 and 8) Bit(s) 31:0 Description Type Serial EEPROM Reserved Default 0h Register 10-84. 2E8h Bus Number CAM 8 (Only Ports 0 and 8) Type Serial EEPROM Default 7:0 Primary Bus Number Mirror copy of Port 8 Primary Bus Number. R/W Yes 00h 15:8 Secondary Bus Number Mirror copy of Port 8 Secondary Bus Number. R/W Yes FFh 23:16 Subordinate Bus Number Mirror copy of Port 8 Subordinate Bus Number. R/W Yes 00h 31:24 Reserved PR EL IM IN AR Y Description Bit(s) 00h Register 10-85. 2ECh Bus Number CAM 9 (Only Ports 0 and 8) Description Type Serial EEPROM Default 7:0 Primary Bus Number Mirror copy of Port 9 Primary Bus Number. R/W Yes 00h 15:8 Secondary Bus Number Mirror copy of Port 9 Secondary Bus Number. R/W Yes FFh 23:16 Subordinate Bus Number Mirror copy of Port 9 Subordinate Bus Number. R/W Yes 00h 31:24 Reserved Bit(s) 00h Register 10-86. 2F0h Bus Number CAM 10 (Only Ports 0 and 8) Description Type Serial EEPROM Default 7:0 Primary Bus Number Mirror copy of Port 10 Primary Bus Number. R/W Yes 00h 15:8 Secondary Bus Number Mirror copy of Port 10 Secondary Bus Number. R/W Yes FFh 23:16 Subordinate Bus Number Mirror copy of Port 10 Subordinate Bus Number. R/W Yes 00h 31:24 Reserved Bit(s) 166 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 CAM Routing Registers Register 10-87. 24h Bus Number CAM 11 (Only Ports 0 and 8) Description Type Serial EEPROM Default 7:0 Primary Bus Number Mirror copy of Port 11 Primary Bus Number. R/W Yes 00h 15:8 Secondary Bus Number Mirror copy of Port 11 Secondary Bus Number. R/W Yes FFh 23:16 Subordinate Bus Number Mirror copy of Port 11 Subordinate Bus Number. R/W Yes 00h 31:24 Reserved 00h PR EL IM IN AR Y Bit(s) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 167 PEX 8524 Port Registers 10.13.3.2 PLX Technology, Inc. I/O CAM Registers Register 10-88. 308h I/O CAM_0 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 7:4 I/O Base Mirror copy of Ports 0 and 8 I/O Base value. 11:8 Reserved 15:12 I/O Limit Mirror copy of Ports 0 and 8 I/O Limit value. Type Serial EEPROM Default 1h R/W Yes Fh 1h R/W Yes 0h Serial EEPROM Default Bit(s) PR EL IM IN AR Y Register 10-89. 30Ah I/O CAM_1 (Only Ports 0 and 8) Description 3:0 Reserved 7:4 I/O Base Mirror copy of Port 1 I/O Base value. 11:8 Reserved 15:12 I/O Limit Mirror copy of Port 1 I/O Limit value. Type R/W 1h Yes Fh 1h R/W Yes 0h Type Serial EEPROM Default Register 10-90. 30Ch I/O CAM_2 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 7:4 Reserved 11:8 Reserved 15:12 Reserved 1h 0h 1h 0h Register 10-91. 30Eh I/O CAM_3 (Only Ports 0 and 8) Bit(s) Description Type Serial EEPROM Default 3:0 Reserved 1h 7:4 Reserved 0h 11:8 Reserved 1h 15:12 Reserved 0h 168 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 CAM Routing Registers Register 10-92. 318h I/O CAM_8 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 7:4 I/O Base Mirror copy of Port 8 I/O Base value. 11:8 Reserved 15:12 I/O Limit Mirror copy of Port 8 I/O Limit value. Type Serial EEPROM Default 1h R/W Yes 0h 1h R/W Yes 0h Bit(s) PR EL IM IN AR Y Register 10-93. 31Ah I/O CAM_9 (Only Ports 0 and 8) Description 3:0 Reserved 7:4 I/O Base Mirror copy of Port 9 I/O Base value. 11:8 Reserved 15:12 I/O Limit Mirror copy of Port 9 I/O Limit value. Type R/W Serial EEPROM Default 1h Yes Fh 1h R/W Yes 0h Type Serial EEPROM Default Register 10-94. 31Ch I/O CAM_10 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 7:4 I/O Base Mirror copy of Port 10 I/O Base value. 11:8 Reserved 15:12 I/O Limit Mirror copy of Port 10 I/O Limit value. R/W 1h Yes Fh 1h R/W Yes 0h Type Serial EEPROM Default Register 10-95. 31Eh I/O CAM_11 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 7:4 I/O Base Mirror copy of Port 11 I/O Base value. 11:8 Reserved 15:12 I/O Limit Mirror copy of Port 11 I/O Limit value. 1h R/W Yes Fh 1h R/W PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 0h 169 PEX 8524 Port Registers 10.13.3.3 PLX Technology, Inc. AMCAM (Address-Mapping CAM) Registers AMCAM registers contain mirror images of the corresponding port Memory Base and Memory Limit, Prefetchable Base and Prefetchable Limit, and Prefetchable Base Upper and Prefetchable Limit Upper registers of the PEX 8524 PCI-to-PCI bridges. Register 10-96. 348h AMCAM_0 Memory Limit and Base (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 15:4 Memory Base Mirror copy of Port 0 Memory Base value. 19:16 Reserved 31:20 Memory Limit Mirror copy of Port 0 Memory Limit value. Type Serial EEPROM Default 0h R/W Yes FFFh 0h PR EL IM IN AR Y R/W Yes 000h Register 10-97. 34Ch AMCAM_0 Prefetchable Memory Limit and Base[31:0] (Only Ports 0 and 8) Bit(s) Description Type Serial EEPROM Default 3:0 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 15:4 Prefetchable Memory Base AMCAM_0 Prefetchable Memory Base. R/W Yes FFFh 19:16 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 31:20 Prefetchable Memory Limit AMCAM_0 Prefetchable Memory Limit. R/W Yes 000h Register 10-98. 350h AMCAM_0 Prefetchable Memory Base[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Base[63:32] AMCAM_0 Prefetchable Memory Base[63:32]. Type Serial EEPROM Default R/W Yes FFFF_FFF Fh Register 10-99. 354h AMCAM_0 Prefetchable Memory Limit[63:32] (Only Ports 0 and 8) Bit(s) 31:0 170 Description Prefetchable Memory Limit[63:32] AMCAM_0 Prefetchable Memory Limit[63:32]. Type Serial EEPROM Default R/W Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 CAM Routing Registers Register 10-100. 358h AMCAM_1 Memory Limit and Base (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 15:4 Memory Base Mirror copy of Port 1 Memory Base value. 19:16 Reserved 31:20 Memory Limit Mirror copy of Port 1 Memory Limit value. Type Serial EEPROM Default 0h R/W Yes FFFh 0h R/W Yes 000h Register 10-101. 35Ch AMCAM_1 Prefetchable Memory Limit and Base[31:0] (Only Ports 0 and 8) Description Type Serial EEPROM Default PR EL IM IN AR Y Bit(s) 3:0 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 15:4 Prefetchable Memory Base AMCAM_1 Prefetchable Memory Base. R/W Yes FFFh 19:16 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 31:20 Prefetchable Memory Limit AMCAM_1 Prefetchable Memory Limit. R/W Yes 000h Register 10-102. 360h AMCAM_1 Prefetchable Memory Base[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Base[63:32] AMCAM_1 Prefetchable Memory Base[63:32]. Type Serial EEPROM Default R/W Yes FFFF_FFF Fh Register 10-103. 364h AMCAM_1 Prefetchable Memory Limit[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Limit[63:32] AMCAM_1 Prefetchable Memory Limit[63:32]. Type Serial EEPROM Default R/W Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 171 PEX 8524 Port Registers PLX Technology, Inc. Register 10-104. 368h AMCAM_2 Memory Limit and Base (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 15:4 Memory Base Mirror copy of Port 2 Memory Base value. 19:16 Reserved 31:20 Memory Limit Mirror copy of Port 2 Memory Limit value. Type Serial EEPROM Default 0h R/W Yes FFFh 0h R/W Yes 000h Register 10-105. 36Ch AMCAM_2 Prefetchable Memory Limit and Base[31:0] (Only Ports 0 and 8) Description Type Serial EEPROM Default PR EL IM IN AR Y Bit(s) 3:0 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 15:4 Prefetchable Memory Base AMCAM_2 Prefetchable Memory Base. R/W Yes FFFh 19:16 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 31:20 Prefetchable Memory Limit AMCAM_2 Prefetchable Memory Limit. R/W Yes 000h Register 10-106. 370h AMCAM_2 Prefetchable Memory Base[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Base[63:32] AMCAM_2 Prefetchable Memory Base[63:32]. Type Serial EEPROM Default R/W Yes FFFF_FFFFh Register 10-107. 374h AMCAM_2 Prefetchable Memory Limit[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Limit[63:32] AMCAM_2 Prefetchable Memory Limit[63:32]. Type Serial EEPROM Default R/W Yes 0-0h Register 10-108. 378h AMCAM_3 Memory Limit and Base (Only Ports 0 and 8) Bit(s) 3:0 172 Description Reserved Type Serial EEPROM Default 0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 CAM Routing Registers Register 10-108. 378h AMCAM_3 Memory Limit and Base (Only Ports 0 and 8) Bit(s) Description 15:4 Memory Base Mirror copy of Port 3 Memory Base value. 19:16 Reserved 31:20 Memory Limit Mirror copy of Port 3 Memory Limit value. Type Serial EEPROM Default R/W Yes FFFh 0h R/W Yes 000h Register 10-109. 37Ch AMCAM 3 Prefetchable Memory Limit and Base[31:0] (Only Ports 0 and 8) Bit(s) Description Type Serial EEPROM Default Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 15:4 Prefetchable Memory Base AMCAM_3 Prefetchable Memory Base. R/W Yes FFFh 19:16 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 31:20 Prefetchable Memory Limit AMCAM_3 Prefetchable Memory Limit. R/W Yes 000h PR EL IM IN AR Y 3:0 Register 10-110. 380h AMCAM 3 Prefetchable Memory Base[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Base[63:32] AMCAM_3 Prefetchable Memory Base[63:32]. Type Serial EEPROM Default R/W Yes FFFF_FFFFh Register 10-111. 384h AMCAM 3 Prefetchable Memory Limit[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Limit[63:32] AMCAM_3 Prefetchable Memory Limit[63:32]. Type Serial EEPROM Default R/W Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 173 PEX 8524 Port Registers PLX Technology, Inc. Register 10-112. 3C8h AMCAM 8 Memory Limit and Base (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 15:4 Memory Base Mirror copy of Port 8 Memory Base value. Type Serial EEPROM Default 0h 19:16 Reserved 31:20 Memory Limit Mirror copy of Port 8 Memory Limit value. R/W Yes FFFh 0h R/W Yes 000h Register 10-113. 3CCh AMCAM 8 Prefetchable Memory Limit and Base[31:0] Bit(s) PR EL IM IN AR Y (Only Ports 0 and 8) Description Type Serial EEPROM Default 3:0 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 15:4 Prefetchable Memory Base AMCAM_8 Prefetchable Memory Base. R/W Yes FFFh 19:16 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 31:20 Prefetchable Memory Limit AMCAM_8 Prefetchable Memory Limit. R/W Yes 000h Register 10-114. 3D0h AMCAM 8 Prefetchable Memory Base[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Base[63:32] AMCAM_8 Prefetchable Memory Base[63:32]. Type Serial EEPROM Default R/W Yes FFFF_FFFFh Register 10-115. 3D4h AMCAM 8 Prefetchable Memory Limit[63:32] (Only Ports 0 and 8) Bit(s) 31:0 174 Description Prefetchable Memory Limit[63:32] AMCAM_8 Prefetchable Memory Limit[63:32]. Type Serial EEPROM Default R/W Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 CAM Routing Registers Register 10-116. 3D8h AMCAM 9 Memory Limit and Base (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 15:4 Memory Base Mirror copy of Port 9 Memory Base value. 19:16 Reserved 31:20 Memory Limit Mirror copy of Port 9 Memory Limit value. Type Serial EEPROM Default 0h R/W Yes FFFh 0h R/W Yes 000h Register 10-117. 3DCh AMCAM 9 Prefetchable Memory Limit and Base[31:0] (Only Ports 0 and 8) Description PR EL IM IN AR Y Bit(s) Type Serial EEPROM Default 3:0 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 15:4 Prefetchable Memory Base AMCAM_9 Prefetchable Memory Base. R/W Yes FFFh 19:16 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 31:20 Prefetchable Memory Limit AMCAM_9 Prefetchable Memory Limit. R/W Yes 000h Register 10-118. 3E0h AMCAM 9 Prefetchable Memory Base[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Base[63:32] AMCAM_9 Prefetchable Memory Base[63:32]. Type Serial EEPROM Default R/W Yes FFFF_FFFFh Register 10-119. 3E4h AMCAM 9 Prefetchable Memory Limit[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Limit[63:32] AMCAM_9 Prefetchable Memory Limit[63:32]. Type Serial EEPROM Default R/W Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 175 PEX 8524 Port Registers PLX Technology, Inc. Register 10-120. 3E8h AMCAM 10 Memory Limit and Base (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 15:4 Memory Base Mirror copy of Port 10 Memory Base value. 19:16 Reserved 31:20 Memory Limit Mirror copy of Port 10 Memory Limit value. Type Serial EEPROM Default 0h R/W Yes FFFh 0h R/W Yes 000h Register 10-121. 3ECh AMCAM 10 Prefetchable Limit and Memory Base[31:0] (Only Ports 0 and 8) Description Type Serial EEPROM Default PR EL IM IN AR Y Bit(s) 3:0 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 15:4 Prefetchable Memory Base AMCAM_10 Prefetchable Memory Base. R/W Yes FFFh 19:16 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 31:20 Prefetchable Memory Limit AMCAM_10 Prefetchable Memory Limit. R/W Yes 000h Register 10-122. 3F0h AMCAM 10 Prefetchable Memory Base[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Base[63:32] AMCAM_10 Prefetchable Memory Base[63:32]. Type Serial EEPROM Default R/W Yes FFFF_FFFFh Register 10-123. 3F4h AMCAM 10 Prefetchable Memory Limit[63:32] (Only Ports 0 and 8) Bit(s) 31:0 176 Description Prefetchable Memory Limit[63:32] AMCAM_10 Prefetchable Memory Limit[63:32]. Type Serial EEPROM Default R/W Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 CAM Routing Registers Register 10-124. 3F8h AMCAM 11 Memory Limit and Base (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 15:4 Memory Base Mirror copy of Port 11 Memory Base value. 19:16 Reserved 31:20 Memory Limit Mirror copy of Port 11 Memory Limit value. Type Serial EEPROM Default 0h R/W Yes FFFh 0h R/W Yes 000h Register 10-125. 3FCh AMCAM 11 Prefetchable Limit and Memory Base[31:0] (Only Ports 0 and 8) Description Type Serial EEPROM Default PR EL IM IN AR Y Bit(s) 3:0 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 15:4 Prefetchable Memory Base AMCAM_11 Prefetchable Memory Base. R/W Yes FFFh 19:16 Addressing Support 1h = 64-bit addressing supported. RO Yes 1h 31:20 Prefetchable Memory Limit AMCAM_11 Prefetchable Memory Limit. R/W Yes 000h Register 10-126. 400h AMCAM 11 Prefetchable Memory Base[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Base[63:32] AMCAM_11 Prefetchable Memory Base[63:32]. Type Serial EEPROM Default R/W Yes FFFF_FFFFh Register 10-127. 404h AMCAM 11 Prefetchable Memory Limit[63:32] (Only Ports 0 and 8) Bit(s) 31:0 Description Prefetchable Memory Limit[63:32] AMCAM_11 Prefetchable Memory Limit[63:32]. Type Serial EEPROM Default R/W Yes 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 177 PEX 8524 Port Registers 10.13.4 PLX Technology, Inc. TIC Control Registers Register 10-128. 660h TIC Control (Only Ports 0 and 8) Description Type Serial EEPROM Default 1:0 TIC Control Peer configuration access; When set to 1, configuration transactions (Type 0/1) coming upstream from a Downstream port are allowed to enter the device and all the Type 1 headers of the Downstream ports in the switch are accessible. In this mode, the Upstream Port Type 1 Header space is not accessible from the Downstream port. Bit 1 disables Unsupported Requests to access to the Reserved space. Bit 0 enables Configuration Transactions from the Downstream port. R/W Yes 0h 31:2 TIC Control Factory use only. R/W Yes 0-0h PR EL IM IN AR Y Bit(s) Register 10-129. 668h TIC Port Enable (Only Ports 0 and 8) Bit(s) 31:0 178 Description TIC_UNP_Status Factory use only. Type Serial EEPROM Default R/W Yes FFFF_FFFFh PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 10.13.5 I/O Base and Limit Upper 16 Bits Registers I/O Base and Limit Upper 16 Bits Registers Register 10-130. 680h I/OCAM_0 for Port 0 (Only Port 0) Bit(s) Description Type Serial EEPROM Default 15:0 I/OCAM Base[31:16] I/O Base Upper 16 bits. R/W Yes FFFFh 31:16 I/OCAM Limit[31:16] I/O Limit Upper 16 bits. R/W Yes 0000h Type Serial EEPROM Default Register 10-131. 684h I/OCAM_1 for Port 1 (Only Port 0) Bit(s) Description I/OCAM Base[31:16] I/O Base Upper 16 bits. R/W Yes FFFFh 31:16 I/OCAM Limit[31:16] I/O Limit Upper 16 bits. R/W Yes 0000h Type Serial EEPROM Default PR EL IM IN AR Y 15:0 Register 10-132. 688h I/OCAM_2 for Port 2 (Only Port 0) Bit(s) Description 15:0 I/OCAM Base[31:16] I/O Base Upper 16 bits. R/W Yes FFFFh 31:16 I/OCAM Limit[31:16] I/O Limit Upper 16 bits. R/W Yes 0000h Type Serial EEPROM Default Register 10-133. 68Ch I/OCAM_3 for Port 3 (Only Port 0) Bit(s) Description 15:0 I/OCAM Base[31:16] I/O Base Upper 16 bits. R/W Yes FFFFh 31:16 I/OCAM Limit[31:16] I/O Limit Upper 16 bits. R/W Yes 0000h Type Serial EEPROM Default Register 10-134. 6A0h I/OCAM_8 for Port 8 (Only Port 8) Bit(s) Description 15:0 I/OCAM Base[31:16] I/O Base Upper 16 bits. R/W Yes FFFFh 31:16 I/OCAM Limit[31:16] I/O Limit Upper 16 bits. R/W Yes 0000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 179 PEX 8524 Port Registers PLX Technology, Inc. Register 10-135. 6A4h I/OCAM_9 for Port 9 (Only Port 8) Bit(s) Description Type Serial EEPROM Default 15:0 I/OCAM Base[31:16] I/O Base Upper 16 bits. R/W Yes FFFFh 31:16 I/OCAM Limit[31:16] I/O Limit Upper 16 bits. R/W Yes 0000h Type Serial EEPROM Default R/W Yes FFFFh R/W Yes 0000h Type Serial EEPROM Default Register 10-136. 6A8h I/OCAM_10 for Port 10 (Only Port 8) Bit(s) Description I/OCAM Base[31:16] I/O Base Upper 16 bits. 31:16 I/OCAM Limit[31:16] I/O Limit Upper 16 bits. PR EL IM IN AR Y 15:0 Register 10-137. 6ACh I/OCAM_11 for Port 11 (Only Port 8) Bit(s) Description 15:0 I/OCAM Base[31:16] I/O Base Upper 16 bits. R/W Yes FFFFh 31:16 I/OCAM Limit[31:16] I/O Limit Upper 16 bits. R/W Yes 0000h 180 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 10.13.6 Base Address Registers (BARs) Base Address Registers (BARs) The registers delineated in Table 10-15 contain a shadow copy of the two Type 1 Configuration Base Address registers for each port. Table 10-15. PLX-Specific Base Address Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6C0h BAR_1 for Port 0 6C4h BAR_0 for Port 1 6C8h BAR_1 for Port 1 6CCh BAR_0 for Port 2 6D0h BAR_1 for Port 2 6D4h BAR_0 for Port 3 6D8h BAR_1 for Port 3 6DCh PR EL IM IN AR Y BAR_0 for Port 0 Reserved 6E0h - 6FCh BAR_0 for Port 8 (Only Port 8) 700h BAR_1 for Port 8 704h BAR_0 for Port 9 708h BAR_1 for Port 9 70Ch BAR_0 for Port 10 710h BAR_1 for Port 10 714h BAR_0 for Port 11 718h BAR_1 for Port 11 71Ch Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 720h ... 73Ch 181 PEX 8524 Port Registers PLX Technology, Inc. Register 10-138. 6C0h BAR_0 for Port 0 (Only Port 0) Type Serial EEPROM Default 0 Memory Space Indicator 0b = Memory BAR 1b = I/O BAR Reads 0b, and ignores Writes. RO Yes 0b 2:1 Memory Mapping_0 Range Memory Mapping for Port 0. 00b = 32 bits 10b = 64 bits 01b, 11b = Reserved R/W Yes 00b 3 Prefetchable 0b = Not Prefetchable 1b = Prefetchable Reads 0b, and ignores Writes. RO Yes 0b Description PR EL IM IN AR Y Bit(s) 15:4 Reserved 31:16 Base Address_0 Shadow copy of Base Address 0 for Port 0. Where BAR_0[15:0] = Reserved. R/W 000h Yes 0000h Register 10-139. 6C4h BAR_1 for Port 0 (Only Port 0) Bit(s) 31:0 182 Description Base Address_1[63:32] When Port 0 BAR_0[2:1] = 10b, becomes a Shadow copy of Port 0 Base Address_1[63:32]. Type Serial EEPROM Default R/W Yes 0000_0000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Base Address Registers (BARs) Register 10-140. 6C8h BAR_0 for Port 1 (Only Port 0) Type Serial EEPROM Default 0 Memory Space Indicator 0b = Memory BAR 1b = I/O BAR Reads 0b, and ignores Writes. RO Yes 0b 2:1 Memory Mapping_1 Range Memory Mapping for Port 1. 00b = 32 bits 10b = 64 bits 01b, 11b = Reserved R/W Yes 00b RO Yes 0b Bit(s) 0b = Not Prefetchable 1b = Prefetchable Reads 0b, and ignores Writes. PR EL IM IN AR Y 3 Description 15:4 Reserved 31:16 Shadow copy of Base Address 0 for Port 1. Where BAR_0[15:0] = Reserved. 000h R/W Yes 0000h Type Serial EEPROM Default R/W Yes 0000_0000h Register 10-141. 6CCh BAR_1 for Port 1 (Only Port 0) Bit(s) 31:0 Description Base Address_1[63:32] When Port 1 BAR_0[2:1] = 10b, becomes a Shadow copy of Port 1 Base Address_1[63:32]. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 183 PEX 8524 Port Registers PLX Technology, Inc. Register 10-142. 6D0h BAR_0 for Port 2 (Only Port 0) Type Serial EEPROM Default 0 Memory Space Indicator 0b = Memory BAR 1b = I/O BAR Reads 0b, and ignores Writes. RO Yes 0b 2:1 Memory Mapping_2 Range Memory Mapping for Port 2 00b = 32 bits 10b = 64 bits 01b, 11b = Reserved R/W Yes 00b 3 Prefetchable 0b = Not Prefetchable 1b = Prefetchable Reads 0b, and ignores Writes. RO Yes 0b Description PR EL IM IN AR Y Bit(s) 15:4 Reserved 31:16 Base Address_0 Shadow copy of Base Address 0 for Port 2. Where BAR_0[15:0] = Reserved. 000h R/W Yes 0000h Type Serial EEPROM Default R/W Yes 0000_0000 h Register 10-143. 6D4h BAR_1 for Port 2 (Only Port 0) Bit(s) 31:0 184 Description Base Address_1[63:32] When Port 2 BAR_0[2:1] = 10b, becomes a Shadow copy of Port 2 Base Address_1[63:32]. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Base Address Registers (BARs) Register 10-144. 6D8h BAR_0 for Port 3 (Only Port 0) Type Serial EEPROM Default 0 Memory Space Indicator 0b = Memory BAR 1b = I/O BAR Reads 0b, and ignores Writes. RO Yes 0b 2:1 Memory Mapping_3 Range Memory Mapping for Port 3 00b = 32 bits 10b = 64 bits 01b, 11b = Reserved R/W Yes 00b 3 Prefetchable 0b = Not Prefetchable 1b = Prefetchable Reads 0b, and ignores Writes. RO Yes 0b Description PR EL IM IN AR Y Bit(s) 15:4 Reserved 31:16 Base Address_0 Shadow copy of Base Address 0 for Port 3. Where BAR_0[15:0] = Reserved. 000h R/W Yes 0000h Type Serial EEPROM Default R/W Yes 0000_0000 h Type Serial EEPROM Default 0 Memory Space Indicator 0b = Memory BAR 1b = I/O BAR Reads 0b, and ignores Writes. RO Yes 0b 2:1 Memory Mapping_8 Range Memory Mapping for Port 8 00b = 32 bits 10b = 64 bits 01b, 11b = Reserved R/W Yes 00b Register 10-145. 6DCh BAR_1 for Port 3 (Only Port 0) Bit(s) 31:0 Description Base Address_1[63:32] When Port 3 BAR_0[2:1] = 10b, becomes a Shadow copy of Port 3 Base Address_1[63:32]. Register 10-146. 700h BAR_0 for Port 8 (Only Port 8) Bit(s) Description PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 185 PEX 8524 Port Registers PLX Technology, Inc. Register 10-146. 700h BAR_0 for Port 8 (Only Port 8) Bit(s) 3 Description Type Serial EEPROM Default RO Yes 0b Prefetchable0b = Not Prefetchable 1b = Prefetchable Reads 0b, and ignores Writes. 15:4 Reserved 000h 31:16 Base Address_0 Shadow copy of Base Address 0 for Port 8. Where BAR_0[15:0] = Reserved. R/W Yes 0000h Register 10-147. 704h BAR_1 for Port 8 (Only Port 8) Description 31:0 Base Address_1[63:32] When Port 8 BAR_0[2:1] = 10b, becomes a Shadow copy of Port 8 Base Address_1[63:32]. Type PR EL IM IN AR Y Bit(s) R/W Serial EEPROM Default Yes 0000_0000h Register 10-148. 708h BAR_0 for Port 9 (Only Port 8) Type Serial EEPROM Default 0 Memory Space Indicator 0b = Memory BAR 1b = I/O BAR Reads 0b, and ignores Writes RO Yes 0b 2:1 Memory Mapping_9 Range Memory Mapping for Port 9 00b = 32 bits 10b = 64 bits 01b, 11b = Reserved R/W Yes 00b Prefetchable0b = Not Prefetchable 1b = Prefetchable Reads 0b, and ignores Writes RO Yes 0b Bit(s) 3 Description 15:4 Reserved 000h 31:16 Base Address_0 Shadow copy of Base Address 0 for Port 9. Where BAR_0[15:0] = Reserved. R/W Yes 0000h Type Serial EEPROM Default R/W Yes 0-0h Register 10-149. 70Ch BAR_1 for Port 9 (Only Port 8) Bit(s) 31:0 186 Description Base Address_1[63:32] When Port 9 BAR_0[2:1] = 10b, becomes a Shadow copy of Port 9 Base Address_1[63:32]. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Base Address Registers (BARs) Register 10-150. 710h BAR_0 for Port 10 (Only Port 8) Type Serial EEPROM Default 0 Memory Space Indicator 0b = Memory BAR 1b = I/O BAR Reads 0b, and ignores Writes. RO Yes 0b 2:1 Memory Mapping_10 Range Memory Mapping for Port 10 00b = 32 bits 10b = 64 bits 01b, 11b = Reserved R/W Yes 00b 3 Prefetchable 0b = Not Prefetchable 1b = Prefetchable Reads 0b, and ignores Writes RO Yes 0b Description PR EL IM IN AR Y Bit(s) 15:4 Reserved 31:16 Base Address_0 Shadow copy of Base Address 0 for Port 10. Where BAR_0[15:0] = Reserved. 000h R/W Yes 0000h Type Serial EEPROM Default R/W Yes 0-0h Register 10-151. 714h BAR_1 for Port 10 (Only Port 8) Bit(s) 31:0 Description Base Address_1[63:32] When Port 10 BAR_0[2:1] = 10b, becomes a Shadow copy of Port 10 Base Address_1[63:32]. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 187 PEX 8524 Port Registers PLX Technology, Inc. Register 10-152. 718h BAR_0 for Port 11 (Only Port 8) Type Serial EEPROM Default 0 Memory Space Indicator 0b = Memory BAR 1b = I/O BAR Reads 0b, and ignores Writes. RO Yes 0b 2:1 Memory Mapping_11 Range Memory Mapping for Port 11 00b = 32 bits 10b = 64 bits 01b, 11b = Reserved R/W Yes 00b 3 Prefetchable 0b = Not Prefetchable 1b = Prefetchable Reads 0b, and ignores Writes. RO Yes 0b Description PR EL IM IN AR Y Bit(s) 15:4 Reserved 31:16 Base Address_0 Shadow copy of Base Address 0 for Port 11. Where BAR_0[15:0] = Reserved. 000h R/W Yes 0000h Type Serial EEPROM Default R/W Yes 0-0h Register 10-153. 71Ch BAR_1 for Port 11 (Only Port 8) Bit(s) 31:0 188 Description Base Address_1[63:32] When Port 11 BAR_0[2:1] = 10b, becomes a Shadow copy of Port 11 Base Address_1[63:32]. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 10.13.7 Table 10-16. Shadow Virtual Channel (VC) Capability Registers Shadow Virtual Channel (VC) Capability Registers Shadow Virtual Channel (VC) Capability Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 740h VC1 Port 0 Capability 744h VC0 Port 1 Capability 748h VC1 Port 1 Capability 74Ch VC0 Port 2 Capability 750h VC1 Port 2 Capability 754h VC0 Port 3 Capability 758h VC1 Port 3 Capability 75Ch PR EL IM IN AR Y VC0 Port 0 Capability Reserved 760h - 77Ch VC0 Port 8 Capability 780h VC1 Port 8 Capability 784h VC0 Port 9 Capability 788h VC1 Port 9 Capability 78Ch VC0 Port 10 Capability 790h VC1 Port 10 Capability 794h VC0 Port 11 Capability 798h VC1 Port 11 Capability 79Ch Reserved 7A0h - 83Ch Port 0 VC Capability_1 840h Port 1 VC Capability_1 844h Port 2 VC Capability_1 848h Port 3 VC Capability_1 84Ch Reserved 850h - 85Ch Port 8 VC Capability_1 860h Port 9 VC Capability_1 864h Port 10 VC Capability_1 868h Port 11 VC Capability_1 86Ch Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 870h - 9F0h 189 PEX 8524 Port Registers PLX Technology, Inc. Register 10-154. 740h VC0 Port 0 Capability (Only Port 0) Type Serial EEPROM Default TC_VC0_0 Map[0] Traffic-Class VC0 Port 0 Map[0] = 1b Reads 1b, and ignores Writes. RO Yes 1b 7:1 TC_VC0_0 Map[7:1] Traffic-Class VC0 Port 0 Map[7:1]. R/W Yes 7Fh 23:8 Reserved Bit(s) 24 30:25 31 000h VC0_0 ID Virtual Channel 0 Port 0 ID. R/W Yes Reserved 0b 00h VC0_0 Enable Virtual Channel 0 Port 0 Enable. RO Yes 1b Type Serial EEPROM Default PR EL IM IN AR Y 0 Description Register 10-155. 744h VC1 Port 0 Capability (Only Port 0) Bit(s) 0 Description Reserved 7:1 TC_VC1_0 Map[7:1] Traffic-Class VC1 Port 0 Map[7:1]. 23:8 Reserved 24 30:25 31 190 VC1_0 ID Virtual Channel 1 Port 0 ID. Reserved VC1_0 Enable Virtual Channel 1 Port 0 Enable. R/W R/W R/W 0b Yes 00h 000h Yes 0b 000h Yes 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Shadow Virtual Channel (VC) Capability Registers Register 10-156. 748h VC0 Port 1 Capability (Only Port 0) Type Serial EEPROM Default TC_VC0_1 Map[0] Traffic-Class VC0 Port 1 Map[0] = 1b Reads 1b, and ignores Writes. RO Yes 1b 7:1 TC_VC0_1 Map[7:1] Traffic-Class VC0 Port 1 Map[7:1]. R/W Yes 7Fh 23:8 Reserved Bit(s) 24 30:25 31 000h VC0_1 ID Virtual Channel 0 Port 1 ID. R/W Yes Reserved 0b 000h VC0_1 Enable Virtual Channel 0 Port 1 Enable. PR EL IM IN AR Y 0 Description RO Yes 1b Type Serial EEPROM Default Register 10-157. 74Ch VC1 Port 1 Capability (Only Port 0) Bit(s) 0 Description Reserved 7:1 TC_VC1_1 Map[7:1] Traffic-Class VC1 Port 1 Map[7:1]. 23:8 Reserved 24 30:25 31 VC1_1 ID Virtual Channel 1 Port 1 ID. Reserved VC1_1 Enable Virtual Channel 1 Port 1 Enable. 0b R/W Yes 00h 000h R/W Yes 0b 000h R/W Yes 0b Type Serial EEPROM Default TC_VC0_2 Map[0] Traffic-Class VC0 Port 2 Map[0] = 1b. Reads 1b, and ignores Writes. RO Yes 1b TC_VC0_2 Map[7:1] Traffic-Class VC0 Port 2 Map[7:1]. R/W Yes 7Fh Register 10-158. 750h VC0 Port 2 Capability (Only Port 0) Bit(s) 0 7:1 23:8 24 30:25 31 Description Reserved VC0_2 ID Virtual Channel 0 Port 2 ID. 000h R/W Yes Reserved VC0_2 Enable Virtual Channel 0 Port 2 Enable. 0b 000h RO PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 1b 191 PEX 8524 Port Registers PLX Technology, Inc. Register 10-159. 754h VC1 Port 2 Capability (Only Port 0) Bit(s) 0 Description 23:8 Reserved R/W Yes 00h 000h VC1_2 ID Virtual Channel 1 Port 2 ID. R/W Yes Reserved 0b 000h VC1_2 Enable Virtual Channel 1 Port 2 Enable. R/W Yes 0b Type Serial EEPROM Default TC_VC0_3 Map[0] Traffic-Class VC0 Port 3 Map[0] = 1b. Reads 1b, and ignores Writes. RO Yes 1b 7:1 TC_VC0_3 Map[7:1] Traffic-Class VC0 Port 3 Map[7:1]. R/W Yes 7Fh 23:8 Reserved PR EL IM IN AR Y 31 Default 0b TC_VC1_2 Map[7:1] Traffic-Class VC1 Port 2 Map[7:1]. 30:25 Serial EEPROM Reserved 7:1 24 Type Register 10-160. 758h VC0 Port 3 Capability (Only Port 0) Bit(s) 0 24 30:25 31 Description VC0_3 ID Virtual Channel 0 Port 3 ID. Reserved R/W VC0_3 Enable Virtual Channel 0 Port 3 Enable. 000h Yes 0b 000h RO Yes 1b Type Serial EEPROM Default Register 10-161. 75Ch VC1 Port 3 Capability (Only Port 0) Bit(s) 0 Description Reserved 0b 7:1 TC_VC1_3 Map[7:1] Traffic-Class VC1 Port 3 Map[7:1]. 23:8 Reserved 24 30:25 31 192 R/W Yes 00h 000h VC1_3 ID Virtual Channel 1 Port 3 ID. R/W Yes Reserved 0b 000h VC1_3 Enable Virtual Channel 1 Port 3 Enable. R/W Yes 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Shadow Virtual Channel (VC) Capability Registers Register 10-162. 780h VC0 Port 8 Capability (Only Port 8) Type Serial EEPROM Default TC_VC0_8 Map[0] Traffic-Class VC0 Port 8 Map[0] = 1b Reads 1b, and ignores Writes. RO Yes 1b 7:1 TC_VC0_8 Map[7:1] Traffic-Class VC0 Port 8 Map[7:1]. R/W Yes 7Fh 23:8 Reserved Bit(s) 24 30:25 31 000h VC0_8 ID Virtual Channel 0 Port 8 ID. R/W Yes Reserved 0b 000h VC0_8 Enable Virtual Channel 0 Port 8 Enable. PR EL IM IN AR Y 0 Description RO Yes 1b Type Serial EEPROM Default Register 10-163. 784h VC1 Port 8 Capability (Only Port 8) Bit(s) 0 Description Reserved 7:1 TC_VC1_8 Map[7:1] Traffic-Class VC1 Ports 0 and 8 Map[7:1]. 23:8 Reserved 24 30:25 31 VC1_8 ID Virtual Channel 1 Port 8 ID. Reserved VC1_8 Enable Virtual Channel 1 Port 8 Enable. 0b R/W Yes 00h 000h R/W Yes 0b 000h R/W Yes 0b Type Serial EEPROM Default TC_VC0_9 Map[0] Traffic-Class VC0 Port 9 Map[0] = 1b Reads 1b, and ignores Writes. RO Yes 1b TC_VC0_9 Map[7:1] Traffic-Class VC0 Port 9 Map[7:1]. R/W Yes 7Fh Register 10-164. 788h VC0 Port 9 Capability (Only Port 8) Bit(s) 0 7:1 23:8 24 30:25 31 Description Reserved VC0_9 ID Virtual Channel 0 Port 9 ID. 000h R/W Yes Reserved VC0_9 Enable Virtual Channel 0 Port 9 Enable. 0b 000h RO PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 1b 193 PEX 8524 Port Registers PLX Technology, Inc. Register 10-165. 78Ch VC1 Port 9 Capability (Only Port 8) Bit(s) 0 Description 23:8 Reserved R/W Yes 00h 000h VC1_9 ID Virtual Channel 1 Port 9 ID. R/W Yes Reserved 0b 000h VC1_9 Enable Virtual Channel 1 Port 9 Enable. R/W Yes 0b Type Serial EEPROM Default TC_VC0_10 Map[0] Traffic-Class VC0 Port 10 Map[0] = 1b Reads 1b, and ignores Writes. RO Yes 1b 7:1 TC_VC0_10 Map[7:1] Traffic-Class VC0 Port 10 Map[7:1]. R/W Yes 7Fh 23:8 Reserved PR EL IM IN AR Y 31 Default 0b TC_VC1_9 Map[7:1] Traffic-Class VC1 Port 9 Map[7:1]. 30:25 Serial EEPROM Reserved 7:1 24 Type Register 10-166. 790h VC0 Port 10 Capability (Only Port 8) Bit(s) 0 24 30:25 31 Description VC0_10 ID Virtual Channel 0 Port 10 ID. Reserved R/W VC0_10 Enable Virtual Channel 0 Port 10 Enable. 000h Yes 0b 000h RO Yes 1b Type Serial EEPROM Default Register 10-167. 794h VC1 Port 10 Capability (Only Port 8) Bit(s) 0 Description Reserved 0b 7:1 TC_VC1_10 Map[7:1] Traffic-Class VC1 Port 10 Map[7:1]. 23:8 Reserved 24 30:25 31 194 R/W Yes 00h 000h VC1_10 ID Virtual Channel 1 Port 10 ID. R/W Yes Reserved 0b 000h VC1_10 Enable Virtual Channel 1 Port 10 Enable. R/W Yes 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Shadow Virtual Channel (VC) Capability Registers Register 10-168. 798h VC0 Port 11 Capability (Only Port 8) Type Serial EEPROM Default TC_VC0_11 Map[0] Traffic-Class VC0 Port 11 Map[0] = 1b Reads 1b, and ignores Writes. RO Yes 1b 7:1 TC_VC0_11 Map[7:1] Traffic-Class VC0 Port 11 Map[7:1]. R/W Yes 7Fh 23:8 Reserved Bit(s) 24 30:25 31 000h VC0_11 ID Virtual Channel 0 Port 11 ID. R/W Yes Reserved 0b 000h VC0_11 Enable Virtual Channel 0 Port 11 Enable. PR EL IM IN AR Y 0 Description RO Yes 1b Type Serial EEPROM Default Register 10-169. 79Ch VC1 Port 11 Capability (Only Port 8) Bit(s) 0 Description Reserved 7:1 TC_VC1_11 Map[7:1] Traffic-Class VC1 Port 11 Map[7:1]. 23:8 Reserved 24 30:25 31 VC1_11 ID Virtual Channel 1 Port 11 ID. Reserved VC1_11 Enable Virtual Channel 1 Port 11 Enable. 0b R/W Yes 00h 000h R/W Yes 0b 000h R/W PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 0b 195 PEX 8524 Port Registers 10.13.8 PLX Technology, Inc. Shadow Port Virtual Channel Capability_1 Registers Register 10-170. 840h Port 0 VC Capability_1 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 6:4 LOW-PRI-VC Count Low-priority Virtual Channel count. 31:7 Reserved Type Serial EEPROM Default 0h R/W Yes 000b 0-0h Register 10-171. 844h Port 1 VC Capability_1 (Only Ports 0 and 8) Description Type PR EL IM IN AR Y Bit(s) 3:0 Reserved 6:4 LOW-PRI-VC Count Low-priority Virtual Channel count. 31:7 Reserved R/W Serial EEPROM Default 0h Yes 000b 0-0h Register 10-172. 848h Port 2 VC Capability_1 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 6:4 LOW-PRI-VC Count Low-priority Virtual Channel count. 31:7 Reserved Type R/W Serial EEPROM Default 0h Yes 000b 0-0h Register 10-173. 84Ch Port 3 VC Capability_1 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 6:4 LOW-PRI-VC Count Low-priority Virtual Channel count. 31:7 Reserved Type Serial EEPROM Default 0h R/W Yes 000b 0-0h Register 10-174. 860h Port 8 VC Capability_1 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 6:4 LOW-PRI-VC Count Low-priority Virtual Channel count. 31:7 Reserved 196 Type Serial EEPROM Default 0h R/W Yes 000b 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Shadow Port Virtual Channel Capability_1 Registers Register 10-175. 864h Port 9 VC Capability_1 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 6:4 LOW-PRI-VC Count Low-priority Virtual Channel count. 31:7 Reserved Type Serial EEPROM Default 0h R/W Yes 000b 0-0h Register 10-176. 868h Port 10 VC Capability_1 (Only Ports 0 and 8) Bit(s) Description Reserved 6:4 LOW-PRI-VC Count Low-priority Virtual Channel count. 31:7 Reserved Serial EEPROM Default 0h PR EL IM IN AR Y 3:0 Type R/W Yes 000b 0-0h Register 10-177. 86Ch Port 11 VC Capability_1 (Only Ports 0 and 8) Bit(s) Description 3:0 Reserved 6:4 LOW-PRI-VC Count Low-priority Virtual Channel count. 31:7 Reserved Type Serial EEPROM Default 0h R/W PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 000b 0-0h 197 PEX 8524 Port Registers 10.13.9 Table 10-17. PLX Technology, Inc. Ingress Credit Handler (INCH) Registers Ingress Credit Handler Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9F4h Reserved 9F8h INCH Mode 9FCh INCH Threshold Port 0 VC0 Posted A00h INCH Threshold Port 0 VC0 Non-Posted A04h INCH Threshold Port 0 VC0 Completion A08h INCH Threshold Port 0 VC1 Posted A0Ch INCH Threshold Port 0 VC1 Non-Posted A10h INCH Threshold Port 0 VC1 Completion A14h PR EL IM IN AR Y INCH FC Update Pending Timer INCH Threshold Port 1 VC0 Posted A18h INCH Threshold Port 1 VC0 Non-Posted A1Ch INCH Threshold Port 1 VC0 Completion A20h INCH Threshold Port 1 VC1 Posted A24h INCH Threshold Port 1 VC1 Non-Posted A28h INCH Threshold Port 1 VC1 Completion A2Ch INCH Threshold Port 2 VC0 Posted A30h INCH Threshold Port 2 VC0 Non-Posted A34h INCH Threshold Port 2 VC0 Completion A38h INCH Threshold Port 2 VC1 Posted A3Ch INCH Threshold Port 2 VC1 Non-Posted A40h INCH Threshold Port 2 VC1 Completion A44h INCH Threshold Port 3 VC0 Posted A48h INCH Threshold Port 3 VC0 Non-Posted A4Ch INCH Threshold Port 3 VC0 Completion A50h INCH Threshold Port 3 VC1 Posted A54h INCH Threshold Port 3 VC1 Non-Posted A58h INCH Threshold Port 3 VC1 Completion A5Ch Reserved 198 AC0h - B7Ch PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Ingress Credit Handler (INCH) Registers Register 10-178. 9F4h INCH FC Update Pending Timer (Only Ports 0 and 8) Descriptiona Bit(s) Type Serial EEPROM Default 7:0 Port_0 Update Timer Update pending timer for Port 0. R/W Yes 00h 15:8 Port_1 Update Timer Update pending timer for Port 1. R/W Yes 00h 23:16 Port_2 Update Timer Update pending timer for Port 2. R/W Yes 00h 31:24 Port_3 Update Timer Update pending timer for Port 3. R/W Yes 00h PR EL IM IN AR Y a.Timers mentioned in Register 10-178 are duplicated in Station 1, Port 0 for Ports[11-8]. Register 10-179. 9FCh INCH Mode (Only Ports 0 and 8) Bit(s) Description Type Serial EEPROM Default RO Yes FFh 7:0 Maximum Mode Enable Factory use only. 15:8 Reserved 19:16 Extra R/W Bits R/W Yes 0h 23:20 Pending Timer Source Pending timer register - uses EEPROM values. R/W Yes 0h 31:24 Reserved 0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 00h 199 PEX 8524 Port Registers 10.13.9.1 PLX Technology, Inc. INCH Threshold Port Virtual Channel Register (Ports 0 and 8 Only) There are six Ingress Credit Handler (INCH) Threshold Port VC registers which are duplicated for each port. These registers represent the maximum number of payload credits allocated per port, virtual channel, and type. The register names and address/location are delineated in Table 10-17. The following registers describe the data that applies to these registers. Register 10-180. A00h, A18h INCH Threshold Port n VC0 Posted (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Bit(s) Description Reserved 8:3 Payload Payload = 00_1011b. 13:9 Header Header = 0_0101b. 31:14 Reserved Serial EEPROM Default 000b R/W PR EL IM IN AR Y 2:0 Type Yes 14Bh 0-0h Register 10-181. A04h, A1Ch INCH Threshold Port n VC0 Non-Posted (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Bit(s) Description 8:0 Payload Payload = 0_0000_1001b. 13:9 Header Header = 0_1001b. 31:14 Reserved Type Serial EEPROM Default R/W Yes 1209h 0-0h Register 10-182. A08h, A20h INCH Threshold Port n VC0 Completion (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Bit(s) Description 2:0 Reserved 8:3 Payload Payload = 00_1011b. 13:9 Header Header = 0_0101b. 31:14 Reserved 200 Type Serial EEPROM Default 000b R/W Yes 14Bh 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Ingress Credit Handler (INCH) Registers Register 10-183. A0Ch, A24h INCH Threshold Port n VC1 Posted (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Bit(s) Description 2:0 Reserved 8:3 Payload Payload = 00_0010b. 13:9 Header Header = 0_0001b. 31:14 Reserved Type Serial EEPROM Default 000b R/W Yes 042h 0-0h Register 10-184. A10h, A28h INCH Threshold Port n VC1 Non-Posted (where n = 0 Bit(s) PR EL IM IN AR Y through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Description 8:0 Payload Payload = 0_0000_0001b. 13:9 Header Header = 0_0001b. 31:14 Reserved Type Serial EEPROM Default R/W Yes 0201h 0-0h Register 10-185. A14h, A2Ch INCH Threshold Port n VC1 Completion (where n = 0 through 1 for Station 0 ports, and n = 8 through 11 for Station 1 ports) Bit(s) Description 2:0 Reserved 8:3 Payload Payload = 00_0010b. 13:9 Header Header = 0_0001b. 31:14 Reserved Type Serial EEPROM Default 000b R/W PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 042h 0-0h 201 PEX 8524 Port Registers 10.13.10 Table 10-18. PLX Technology, Inc. Egress Credit Handler (EGCH) Registers Egress Credit Handler Register Map (Only Ports 0 and 8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved B80h Reserved B84h Reserved B88h Reserved B8Ch - B94h B98h Reserved B9Ch Reserved BA0h - BEFh PR EL IM IN AR Y Reserved 202 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PLX-Specific Relaxed Ordering Mode Register 10.13.11 Table 10-19. PLX-Specific Relaxed Ordering Mode Register Performance Tuning Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BF0h Reserved BF4h Reserved BF8h PLX-Specific Relaxed Ordering Mode BFCh Register 10-186. BFCh PLX-Specific Relaxed Ordering Mode (Only Ports 0, 8, and NT Link Interface) Type Serial EEPROM Default 7:0 ENABLE_RLX_ORDERING Port_0 Enables PLX-Specific Relaxed Ordering mode on Port 0 when [7:0] = 1h, the corresponding Traffic Class for that port TC[7:0] is enabled. R/W Yes 00h 15:8 ENABLE_RLX_ORDERING Port_1 Enables PLX-Specific Relaxed Ordering mode on Port 1 when [15:8] = 1h, the corresponding Traffic Class for that port TC[7:0] is enabled. R/W Yes 00h 23:16 ENABLE_RLX_ORDERING Port_2 Enables PLX-Specific Relaxed Ordering mode on Port 2 When [23:16] = 1h, the corresponding Traffic Class for that port TC[7:0] is enabled. R/W Yes 00h 31:24 ENABLE_RLX_ORDERING Port_3 Enables PLX-Specific Relaxed Ordering mode on Port 3 When [31:24] = 1h, the corresponding Traffic Class for that port TC[7:0] is enabled. R/W Yes 00h PR EL IM IN AR Y Description Bit(s) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 203 PEX 8524 Port Registers 10.13.12 Table 10-20. PLX Technology, Inc. Internal Credit Handler (ITCH) VC&T Threshold Registers PEX 8524 Internal Credit Handler (ITCH) VC&T Threshold Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ITCH VC&T Threshold_1 C00h ITCH VC&T Threshold_2 C04h ITCH VC&T Threshold_3 C08h PR EL IM IN AR Y The threshold (Packet Count) units are equivalent to 8 beats, where each beat can be up to 20 Bytes. Therefore, a programmed value of 1 represents 160 Bytes, 2 is 320 Bytes, and so forth. The entire TLP (header, payload, and ECRC, if any) is used to determine a total byte size, and the total byte size is divided by 20 and rounded up to the nearest integer to ascertain the number of beats. Every 8 beats counts as 1 threshold unit. The Upper Packet Count is the high threshold. If more units than the programmed upper count are queued, then no further packets of that type can be scheduled across the internal fabric. Note: Previously scheduled packets arrive in their entirety, completely unaffected by the cut-off signal. The Lower Packet Count is the low threshold. After cutting off a VC&T due to the high threshold, when the count returns below the low threshold, then that VC&T is again turned on. The upper and lower counts must be different, and the upper number must be at least two units larger than the lower number. 204 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Internal Credit Handler (ITCH) VC&T Threshold Registers Register 10-187. C00h ITCH VC&T Threshold_1 (Only Ports 0 and 8) Bit(s) Description Type Serial EEPROM Default 7:0 VC0 Posted Upper Packet Count VC0 posted upper packet beat limit. R/W Yes FFh 15:8 VC0 Posted Lower Packet Count VC0 posted lower packet beat limit. R/W Yes 7Fh 23:16 VC0 Non-Posted Upper Packet Count VC0 non-posted upper packet beat limit. R/W Yes FFh 31:24 VC0 Non-Posted Lower Packet Count VC0 non-posted lower packet beat limit. R/W Yes 7Fh Type Serial EEPROM Default Bit(s) PR EL IM IN AR Y Register 10-188. C04h ITCH VC&T Threshold_2 (Only Ports 0 and 8) Description 7:0 VC0 Completion Upper Packet Count VC0 completion upper packet beat limit. R/W Yes FFh 15:8 VC0 Completion Lower Packet Count VC0 completion lower packet beat limit. R/W Yes 7Fh 23:16 VC1 Posted Upper Packet Count VC1 posted upper packet beat limit. R/W Yes FFh 31:24 VC1 Posted Lower Packet Count VC1 posted lower packet beat limit. R/W Yes 7Fh Type Serial EEPROM Default Register 10-189. C08h ITCH VC&T Threshold_3 (Only Ports 0 and 8) Bit(s) Description 7:0 VC1 Completion Upper Packet Count VC1 non-posted upper packet beat limit. R/W Yes FFh 15:8 VC1 Completion Lower Packet Count VC1 non-posted lower packet beat limit. R/W Yes 7Fh 23:16 VC1 Posted Upper Packet Count VC1 completion upper packet beat limit. R/W Yes FFh 31:24 VC1 Posted Lower Packet Count VC1 completion lower packet beat limit. R/W Yes 7Fh PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 205 PEX 8524 Port Registers 10.14 PLX Technology, Inc. Non-Transparent Registers Offsets C3Ch to FB0h are Reserved if the PEX 8524 is configured in T mode. (Otherwise, refer to Section 14.16, "PEX 8524 Non-Transparent Bridging-Specific Registers.") 10.15 Advanced Error Reporting Capability Registers (All Ports) Table 10-21. PLX-Specific Error Check/Debug and Physical Layer Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FB4h Uncorrectable Error Status FB8h Uncorrectable Error Mask FBCh Uncorrectable Error Severity FC0h Correctable Error Status FC4h Correctable Error Mask FC8h Advanced Error Capabilities and Control FCCh Header Log_0 FD0h Header Log_1 FD4h Header Log_2 FD8h Header Log_3 FDCh PR EL IM IN AR Y Advanced Error Reporting Enhanced Capability Header Reserved FE0h - FFFh Register 10-190. FB4h Advanced Error Reporting Enhanced Capability Header (All Ports) Bit(s) Description Type Serial EEPROM Default 15:0 PCI Express Extended Capability ID RO Yes 0001h 19:16 Capability Version RO Yes 1h 31:20 Next Capability Offset RO Yes 138h 206 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Advanced Error Reporting Capability Registers (All Ports) Register 10-191. FB8h Uncorrectable Error Status (All Ports) Bit(s) 0 3:1 4 11:5 Description Training Error Status 0b = No error detected 1b = Error detected Type Serial EEPROM Default R/W1CS Yes 0b Reserved 000b Data Link Protocol Error Status 0b = No error detected 1b = Error detected R/W1CS Yes Reserved 0b 0000_000b Poisoned TLP Status 0b = No error detected 1b = Error detected R/W1CS 13 Reserved R/W1CS 14 Reserved 15 Completer Abort Status 0b = No error detected 1b = Error detected R/W1CS Yes 0b 16 Reserved R/W1CS Yes 0b 17 Receiver Overflow Status 0b = No error detected 1b = Error detected R/W1CS Yes 0b 18 Malformed TLP Status 0b = No error detected 1b = Error detected R/W1CS Yes 0b 19 ECRC Error Status 0b = No error detected 1b = Error detected R/W1CS Yes 0b 20 Unsupported Request Error Status 0b = No error detected 1b = Error detected R/W1CS Yes 0b 31:21 PR EL IM IN AR Y 12 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 0b Yes 0b 0b 0-0h 207 PEX 8524 Port Registers PLX Technology, Inc. Register 10-192. FBCh Uncorrectable Error Mask (All Ports) Bit(s) 0 3:1 4 11:5 Training Error Mask 0b = No mask is set 1b = Error reporting, first error update, and header logging are masked for this error Type Serial EEPROM Default R/WS Yes 0b Reserved 000b Data Link Protocol Error Mask 0b = No mask is set 1b = Error reporting, first error update, and header logging are masked for this error R/WS Yes Reserved 0b 0000_000b R/WS Yes 13 Reserved R/WS Yes 14 Reserved 15 Completer Abort Mask 0b = No mask is set 1b = Error reporting, first error update, and header logging are masked for this error R/WS Yes 0b 16 Reserved R/WS Yes 0b 17 Receiver Overflow Mask 0b = No mask is set 1b = Error reporting, first error update, and header logging are masked for this error R/WS Yes 0b 18 Malformed TLP Mask 0b = No mask is set 1b = Error reporting, first error update, and header logging are masked for this error R/WS Yes 0b 19 ECRC Error Mask 0b = No mask is set 1b = Error reporting, first error update, and header logging are masked for this error R/WS Yes 0b 20 Unsupported Request Error Mask 0b = No mask is set 1b = Error reporting, first error update, and header logging are masked for this error R/WS Yes 0b Reserved PR EL IM IN AR Y 12 Poisoned TLP Mask 0b = No mask is set 1b = Error reporting, first error update, and header logging are masked for this error 31:21 208 Description 0b 0b 0b 0-0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Advanced Error Reporting Capability Registers (All Ports) Register 10-193. FC0h Uncorrectable Error Severity (All Ports) Bit(s) 0 3:1 4 11:5 Description Training Error Severity 0b = Error reported as non-fatal 1b = Error reported as fatal Type Serial EEPROM Default R/WS Yes 1b Reserved 000b Data Link Protocol Error Severity 0b = Error reported as non-fatal 1b = Error reported as fatal R/WS Yes Reserved 1b 0-0b Poisoned TLP Severity 0b = Error reported as non-fatal 1b = Error reported as fatal R/WS 13 Reserved R/WS 14 Reserved 15 Completer Abort Severity 0b = Error reported as non-fatal 1b = Error reported as fatal R/WS Yes 0b 16 Reserved R/WS Yes 0b 17 Receiver Overflow Severity 0b = Error reported as non-fatal 1b = Error reported as fatal R/WS Yes 1b 18 Malformed TLP Severity 0b = Error reported as non-fatal 1b = Error reported as fatal R/WS Yes 1b 19 ECRC Error Severity 0b = Error reported as non-fatal 1b = Error reported as fatal R/WS Yes 0b 20 Unsupported Request Error Severity 0b = Error reported as non-fatal 1b = Error reported as fatal R/WS Yes 0b 31:21 PR EL IM IN AR Y 12 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 0b Yes 1b 0b 0-0h 209 PEX 8524 Port Registers PLX Technology, Inc. Register 10-194. FC4h Correctable Error Status (All Ports) Bit(s) 0 5:1 Description Receive Error Status 0b = No error detected 1b = Error detected Type Serial EEPROM Default R/W1CS Yes 0b Reserved 0-0b R/W1CS Yes 0b 7 Bad DLLP Status 0b = No error detected 1b = Error detected R/W1CS Yes 0b 8 Replay-Number Rollover Status 0b = No error detected 1b = Error detected R/W1CS Yes 0b 11:9 12 31:13 Reserved PR EL IM IN AR Y 6 Bad TLP Status 0b = No error detected 1b = Error detected Replay-Timer Timeout Status 0b = No error detected 1b = Error detected Reserved R/W1CS 000b Yes 0b 0-0h Register 10-195. FC8h Correctable Error Mask (All Ports) Bit(s) 0 5:1 Description Receive Error Mask 0b = Error reporting not masked 1b = Error reporting masked Reserved Type Serial EEPROM Default R/W1CS Yes 0b 0-0b 6 Bad TLP Mask 0b = Error reporting not masked 1b = Error reporting masked R/W1CS Yes 0b 7 Bad DLLP Mask 0b = Error reporting not masked 1b = Error reporting masked R/W1CS Yes 0b 8 Replay-Number Rollover Mask 0b = Error reporting not masked 1b = Error reporting masked R/W1CS Yes 0b 12 Replay-Timer Timeout Mask 0b = Error reporting not masked 1b = Error reporting masked R/W1CS Yes 0b 11:9 Reserved 000b 31:13 Reserved 0-0h 210 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Advanced Error Reporting Capability Registers (All Ports) Register 10-196. FCCh Advanced Error Capabilities and Control (All Ports) Description Type Serial EEPROM Default 4:0 First Error Pointer Identifies the bit position of the first error reported in the Uncorrectable Error Status register ROS Yes 1_1111b 5 ECRC Generation Capable 0b = ECRC generation not supported 1b = ECRC generation supported, but must be enabled RO Yes 1b 6 ECRC Generation Enable 0b = ECRC generation disabled 1b = ECRC generation enabled R/WS Yes 0b 7 ECRC Check Capable 0b = ECRC checking not supported 1b = ECRC checking supported, but must be enabled RO Yes 1b 8 ECRC Check Enable 0b = ECRC checking disabled 1b = ECRC checking enabled R/WS Yes 0b 31:9 Reserved PR EL IM IN AR Y Bit(s) 0-0h Register 10-197. FD0h Header Log_0 (All Ports) Bit(s) 31:0 Description TLP HEADER_0 TLP header associated with error. Type Serial EEPROM Default ROS Yes 0-0h Type Serial EEPROM Default ROS Yes 0-0h Type Serial EEPROM Default ROS Yes 0-0h Type Serial EEPROM Default ROS Yes 0-0h Register 10-198. FD4h Header Log_1 (All Ports) Bit(s) 31:0 Description TLP HEADER_1 TLP header associated with error. Register 10-199. FD8h Header Log_2 (All Ports) Bit(s) 31:0 Description TLP HEADER_2 TLP header associated with error. Register 10-200. FDCh Header Log_3 (All Ports) Bit(s) 31:0 Description TLP HEADER_3 TLP header associated with error. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 211 PLX Technology, Inc. PR EL IM IN AR Y PEX 8524 Port Registers 212 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 11 11.1 Non-Transparent (NT) Bridging Introduction The following are key elements of the PEX 8524 NT bridging: * Device Type Identification * Non-Transparent-Port (NT Port) Reset * Scratchpad Registers * Doorbell Registers * Address Translation 11.1.1 Device Type Identification Devices identify themselves by way of the standard CSR header Class Code register. A transparent PCI-to-PCI bridge identifies itself as a Class Code 060400h. An NT bridge identifies itself as "other" 068000h, with a Type 0 Header. This identification is consistent with the use of other non-transparent bridges available in the industry. PCI Express Capabilities registers include a Device Type field. In this register, a transparent bridge/ switch port identifies itself as an upstream or Downstream port while an NT bridge/switch NT port identifies itself as a PCI Express endpoint. 11.1.2 Non-Transparent-Port (NT Port) Reset The section discusses Non-Transparent mode exceptions and enhancements to T mode PCI Express (standard) reset behavior. 11.1.2.1 Fundamental Reset (PEX_PERST#) PEX_PERST# resets all PEX 8524 states, including NT port states. All Sticky bits and Configuration registers in virtual and link spaces are initialized to default values by this reset. 11.1.2.2 Intelligent Adapter Mode NT Port Reset In Intelligent Adapter mode, when a Hot Reset is received by the transparent-side Upstream port, the PEX 8524 propagates the reset to all transparent Downstream ports to reset them, resets the internal switch fabric and NT Port Virtual Interface states. There is no reset propagation to the NT port and its link-side remains intact. The PEX 8524 supports an option which allows these Hot Reset conditions at its transparent Upstream port to be masked (disabled) by setting the Port 0 Configuration register bit in offset 1DCh[20]. When the NT Port Link Interface receives a Hot Reset, the NT Port Link Interface registers are reset. This reset type does not reset the transparent ports or NT Port Virtual Interface. Instead, when the NT Port Link Interface receives a Hot Reset (or enters DL_Down condition) the PEX_NT_RESET# signal ball is set low for 1 ms. The system can use this signal to trigger a reset of the entire local subsystem (transparent side). When software writes to the PEX 8524 transparent side Upstream port Bridge Control register Secondary Bus Reset bit, the resulting secondary-bus reset is (as above) propagated to all PEX 8524 transparent Downstream ports, and the port states and NT Port Virtual Interface states are reset. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 213 Non-Transparent (NT) Bridging 11.1.2.3 PLX Technology, Inc. Dual-Host Mode NT Port Reset Dual-Host mode reset behavior is the same as Intelligent Adapter mode, with the following exception - in Dual-Host mode, a Hot Reset received from the Active host as seen at the PEX 8524 transparent Upstream port (or DL-Down condition) does not reset the transparent ports, the internal switch-fabric nor the NT Port Virtual Interface. The queues' internal operation and Downstream ports remain intact, allowing the Backup Host to take over (per Dual-Host mode section). There is no reset propagation onto the NT port. 11.1.2.4 Reset Propagation Reset propagation, during a Hot Reset or by way of the Bridge Control register Secondary Bus Reset mechanism is limited to transparent Downstream ports. In an NT bridge, this reset cannot be propagated across the bridge (across the NT port). (Refer to Chapter 5, "Reset and Initialization," for details regarding PEX 8524 T mode reset behavior.) Scratchpad Registers PR EL IM IN AR Y 11.1.3 Scratchpad registers are readable and writable from both sides of the NT bridge, providing a generic means for inter-host communications. A block of eight registers are provided, accessible in Memory or I/O space from the NT Port Virtual and Link Interfaces. These registers pass control and status information between Virtual Interface and Link Interface devices or can be generic R/W registers. Writing or reading Scratchpad registers does not cause interrupt assertion - Doorbell registers are used for this purpose. 11.1.4 Doorbell Registers Doorbell registers are used to transmit interrupts from one side of the NT bridge to the other. The following section describes a typical set of Doorbell Control registers. A 16-bit software-controlled Interrupt Request register and associated 16-bit Mask register is implemented for the NT Port Virtual and Link Interfaces. These registers can be accessed from the Virtual and Link Interfaces in Memory or I/O space. The Doorbell mechanisms consist of the following: * Set Virtual Interface IRQ register * Clear Virtual Interface IRQ register * Set Virtual Interface IRQ Mask register * Clear Virtual Interface IRQ Mask register * Set Link Interface IRQ register * Clear Link Interface IRQ register * Set Link Interface IRQ Mask register * Clear Link Interface IRQ Mask register An Interrupt is asserted on the Virtual Interface when one or more of the Set Virtual Interface IRQ register bits are set and their corresponding mask bits are cleared to 0. The interrupt is asserted if this condition exists. The Link Interface works identically. The interrupt is removed when all bits originally set are masked or cleared. In a PCI Express switch, the interrupt state transitions from setting to clearing or vice-versa result in packets being transmitted upstream on the appropriate side of the bridge when INTx is enabled. Standard PCI Express capability structures allow these interrupts to be configured as INTx or MSI. When MSI are enabled, packets are transmitted only when interrupts transition from Clear IRQ to Set IRQ. 214 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 BAR Setup Registers Internally, the Set IRQ and Clear IRQ registers are the same register. One location is used to set bits and the other is used to clear bits. The status can be read from either register. Internally, the Set/Clear Mask registers are the same register. The PEX 8524 Virtual Interrupts are also disabled/removed when the NT Port Physical Layer DL_Down condition exists. 11.1.5 BAR Setup Registers All NT Port Virtual Interface and Link Interface BARs include programmable window sizes, with the exception of BAR0 and BAR1 (on both interfaces), which provide Memory and/or I/O-mapped access to the CSRs. The BAR Setup registers are used to program the window size of each BAR. A detailed description of the NT Port Virtual Interface and Link Interface BARs follows. 11.1.5.1 NT Port Virtual Interface Table 11-1 delineates the NT Port Virtual Interface BARs. NT Port Virtual Interface BARs PR EL IM IN AR Y Table 11-1. BAR Description BAR0 Reserved. All PEX 8524 port-configuration registers are mapped into Memory space using transparent Upstream port Type 1 space BAR0 and BAR1 registers. The Local Host, connected to the transparent ports, can use the transparent Upstream port BARs to access PEX 8524 port-configuration register. BAR1 BAR1 is reserved. BAR2 Configured by NT Port Virtual Interface BAR2 Setup register. BAR2 is always a 32-bit BAR and uses Direct Address Translation. BAR3 Configured by NT Port Virtual Interface BAR3 Setup register. BAR3 is always a 32-bit BAR and uses Lookup Table-based Address Translation described in Section 11.1.6.2, "Lookup Table-Based Address Translation." BAR4 Configured by NT Port Virtual Interface BAR4 Setup register. BAR4 can be implemented as a 32-bit BAR or lower half of a 64-bit BAR by combining it with BAR5. BAR4 uses Direct Address Translation. BAR5 Enabled only when BAR4 is configured as a 64-bit BAR. It holds the upper 32-bit base address of the 64-bit memory aperture. The NT Port Virtual Interface BAR4 Setup register defines the size. BAR5 is not implemented as a 32-bit only BAR. BAR5 uses Direct Address Translation. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 215 Non-Transparent (NT) Bridging 11.1.5.2 PLX Technology, Inc. NT Port Link Interface Table 11-2 delineates the NT Port Link Interface BARs. Table 11-2. NT Port Link Interface BARs BAR BAR0 Maps all PEX 8524 port configuration registers into System Host Memory Space. BAR0 is always enabled. BAR1 Maps only NT Port Virtual Interface and Link Interface Configuration registers into System Host I/O space. BARs can be disabled (enabled by default) by Configuration BAR Setup register. BAR2 Configured by BAR2 Setup register. BAR2 can be implemented as a 32-bit BAR or lower half of a 64-bit BAR by combining it with BAR3. BAR2 uses Direct Address Translation. BAR3 Enabled only when BAR2 is configured as a 64-bit BAR. It holds the upper 32-bit base address of the 64-bit memory aperture. The BAR3 Setup register defines the size. BAR3 is not implemented as a 32-bit only BAR. BAR3 uses Direct Address Translation. BAR4 Configured by BAR4 Setup register. This BAR can be implemented as a 32-bit BAR or lower half of a 64-bit BAR by combining it with BAR5. BAR4 uses Direct Address Translation. BAR5 Enabled only when BAR4 is configured as a 64-bit BAR. It holds the upper 32-bit base address of the 64-bit memory aperture. The NT Port Link Interface BAR5 Setup register defines the size. BAR5 is not implemented as a 32-bit only BAR. BAR5 uses Direct Address Translation. PR EL IM IN AR Y 11.1.5.3 Description BAR Limit Registers The Base Address register (BAR) address range size is a power of two (BARs can be assigned only Memory resources in "power of two" granularity). A Limit register is used to reduce the size of the address range. If a Limit register is implemented, the address range extends from the Base register to the Limit register, instead of to the Base register plus an offset of 2N - 1, where N is the number of bits in the offset as defined by the Setup register. The NT port forwards the transaction when the transaction address falls within the range of the BAR lower address limit value to the BAR Limit register value. If the transaction address is outside this range, NT Port reports an "Unsupported Request" and discards the transaction. 216 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Address Translation Figure 11-1. Limit Register Application Source Address Map Target Address Map Translated Base Base 11.1.6 Limit Accesses within the window but above the limit do not pass through the bridge PR EL IM IN AR Y Decode W indow Address Translation The transparent bridge uses Base and Limit registers in I/O space, non-prefetchable Memory space, and prefetchable Memory space to map transactions in the downstream direction across the bridge. All downstream devices must be mapped in contiguous address regions, such that a single aperture in each space is sufficient. Upstream mapping is done by way of inverse decode, relative to the same registers. A transparent bridge does not translate the addresses of forwarded transactions/packets. Address domain is unique per host. If a transaction originates in one host domain and targets a device in another host domain, it must travel through the NT port. If the NT port does not process address translation, the transaction travels to an untargeted device on a second host domain, or is rejected by the NT Port Upstream Bridge. Transactions crossing the address domain are required to be address-translated by the NT Port before transmitting the transaction to the target host domain. The NT bridge uses the standard set of BARs in its Type 0 CSR header to define apertures into the Memory space on the other side of the bridge. BARs define resource apertures that allow transaction forwarding to the opposite (other side) interface. There are two sets of BARs - one on the link side and one on the virtual side. BARs contain a setup and address translation register. * The BAR setup register enables/disables the BAR and defines the aperture size and type. Certain BARs contain a Limit register, which is used to restrict its aperture size to less than a power of two. BAR Setup registers must be programmed prior to allowing configuration software to assign a resource for these BARs. * Address translation registers must be programmed before generating traffic across the NT port. This programming is typically done by information downloaded from the serial EEPROM or by software. The PEX 8524 NT Port Virtual Interface supports two types of address translation: * Direct Address Translation * Lookup Table-Based Address Translation The PEX 8524 NT Port Link Interface supports only Direct Address Translation. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 217 Non-Transparent (NT) Bridging 11.1.6.1 PLX Technology, Inc. Direct Address Translation The primary function of the BAR Setup register is to define a mask which splits the address into an upper "base" field and a lower "offset" field. Translation then consists of replacing, under the maskable portion of the Setup register, the address base bits with the corresponding Address Translation register bits. The device(s) on the originating-host domain can communicate to a single device or multiple devices mapped to consecutive Memory Address space on the target host-domain by using the Direct Address Translation mechanism. Figure 11-3 illustrates the entire address map, claimed by the NT port, mapped into the single target device. Figure 11-4 illustrates the entire address map claimed by NT port mapped into multiple target devices. Those multiple devices must be in continuous memory range. Figure 11-2. Target Address Map PR EL IM IN AR Y Source Address Map Base Direct Address Translation Contents of Base Translation Register Base + Offset Translated Base + Offset Figure 11-3. NT-Port Address Map 20 MB NT Port Mapped into Single Target Device Target Address Map 52 MB 800 MB 832 MB 218 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Address Translation Figure 11-4. NT Port Mapped into Multiple Target Devices NT-Port Address Map Target Address Map 20 MB 800 MB 52 MB 808 MB 816 MB 824 MB 832 MB Device 1 address map Device 2 address map Device 3 address map Device 4 address map PR EL IM IN AR Y Address Translation Example Assume the following: 1. NT Port Virtual Interface BAR2 claims 128 KB Memory space. 2. Configuration software assigns 5F000000h address value to NT Port Virtual Interface BAR2 and it is within the transparent Upstream port Memory window. 3. Device driver software programs BAR2 address translation register to 27540000h. The PEX 8524 receive a transaction to NT Port Virtual Interface with address 5F000080h. The received transaction address is attaining the NT Port Virtual Interface BAR2. The PEX 8524 claims the transaction and executes the address translation described in Figure 11-5. Figure 11-5. Address Translation Example BAR2 Address Translation register 31 Received TLP Address 0 31 27540000h 31 5F000080h 0 17 16 0 31 0 17 16 2754h 0000h 5F00h 0080h Base Offset Base Offset Split Address into: 1. Base - Software programmable portion of BAR 2. Offset - Software Read-Only portion of BAR Drop TLP Address Base 31 17 16 0 2754h 0080h Base Offset 31 0 27540080h Translated Address with Base and Offset Address after Address Translation Note: Nibble boundary-aligned hex address, bar_addr_xlation_reg[31:16], is 0010_0111_0101_0100b (2754h). PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 219 Non-Transparent (NT) Bridging 11.1.6.2 PLX Technology, Inc. Lookup Table-Based Address Translation On the NT Port Virtual Interface, BAR3 uses a special lookup table-based address translation for transactions that fall inside its window. The NT Port Virtual Interface BAR3 setup register defines the lookup table (LUT) entry/page size. The NT Port Virtual Interface BAR3 size is determined by multiplying page size by 64. This BAR3 Setup register defines a mask which splits transaction address into upper and lower/offset fields. The upper field is further divided into two portions - the upper portion is termed "Base Address" and lower portion is termed "Lookup Table Index." The index field location of the received TLP address varies based on the page size selection. Table 11-3 defines the LUT entry/page size, corresponding BAR size, and bit position of individual fields in the received transaction address. PR EL IM IN AR Y Figure 11-6 describes the Lookup Table-Based Address Translation scheme. The received transaction address is divided into three pieces based on the BAR Setup register. Base Address and LUT Index field are compared against the BAR. If the transaction address attains the BAR, The PEX 8524 uses the LUT Index to select the LUT Entry. It replaces the base address and the LUT Index with the selected Lookup Table Entry value, if the selected Lookup Table Entry is valid. Otherwise, the NT Port Virtual Interface returns "Unsupported Request" error condition. The PEX 8524 passes the received transaction address offset into translated address offset without modification. Applications can use the Lookup Table-Based Address transaction, when the target device's address range is scattered over 32-bit Memory space. The NT Port Lookup table descriptions are discussed in Section 14.16.2, "Lookup Table-Based Address Translation Registers." Table 11-3. 220 Received Transaction-Address Breakdown Page Size (Bytes) Window Size (Bytes) Base Address (Bits) LUT Index (Bits) Offset (Bits) 4K 256K [31:18] [17:12] [11:0] 8K 512K [31:19] [18:13] [12:0] 16K 1M [31:20] [19:14] [13:0] 32K 2M [31:21] [20:15] [14:0] 64K 4M [31:22] [21:16] [15:0] 128K 8M [31:23] [22:17] [16:0] 256K 16M [31:24] [23:18] [17:0] 512K 32M [31:25] [24:19] [18:0] 1M 64M [31:26] [25:20] [19:0] 2M 128M [31:27] [26:21] [20:0] 4M 256M [31:28] [27:22] [21:0] 8M 12M [31:29] [28:23] [22:0] 16M 1G [31:30] [29:24] [23:0] 32M 2G 31 [30:25] [24:0] PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Requester ID Translation Figure 11-6. Lookup Table-Based Address Translation Translated Base Lookup Table 3Fh Translated Base Addr 3Fh Translated Base Addr 3Eh 31 20 19 14 13 Base Index O ffset 0 31 14 13 Translated Base O ffset 0 . . . Translated Base Addr [index] . . Translated Base Addr 03h 11.2 PR EL IM IN AR Y Translated Base Addr 02h 01h Translated Base Addr 01h 00h Translated Base Addr 00h Requester ID Translation Configuration, Message, and Completion transactions are ID-routed instead of address-routed. Of these, the NT port forwards only the completion transaction between the two host domains. PCI Express Switches and Bridges use the Requester ID [defined in completion Transaction Layer Packet (TLP) header] to route these packets. The Requester ID consists of the following: * Requester's PCI Bus Number * Device Number * Function Number The Completer ID consists of the following: * Completer's PCI Bus Number * Device Number * Function Number Note: The PCI Bus Number is unique for each host domain. The Memory Request TLP header format is illustrated in Figure 11-7, and the Completion TLP Header format is illustrated in Figure 11-8. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 221 Non-Transparent (NT) Bridging Figure 11-7. PLX Technology, Inc. Memory Request TLP Header Format Byte 0 7 Byte 0-3 6 5 4 3 R Fmtx1 Byte 1 2 1 0 Type Byte 4-7 7 6 R 5 4 3 Byte 2 2 TC 1 0 R 7 6 TD EP Byte 12-15 Address[31:0] Figure 11-8. Attr 2 1 0 7 6 R 5 4 3 2 1 0 Length Last DW BE 1st DW BE R Completion TLP Header Format Byte 0 7 6 5 R Fmt 4 3 Byte 1 2 1 0 7 6 5 4 3 Byte 2 2 1 0 7 6 5 4 Byte 3 3 2 1 PR EL IM IN AR Y Byte 4-7 3 Tag Address[63:32] Byte 8-11 4 Requester ID Byte 8-11 Byte 0-3 5 Byte 3 Type R TC Completer ID R TD EP Attr 7 R Completer BC Requester ID 0 Tag 6 5 4 3 2 1 0 Length Byte Count R Lower Address Transaction Sequence To implement a transaction sequence: 1. Requester inserts ID information into the Memory Read TLP that it generates on the initiating-host domain. 2. Switches and bridges between transaction initiator and PEX 8524 NT port route this Memory Read TLP based on address. 3. NT port replaces the Memory Read TLP Requester ID with its ID and it conducts the address translation before it forwards this Requester ID translated TLP to the target-host domain, because the NT port is the transaction initiator in the target host domain. 4. Switches and bridges between PEX 8524 NT port and target device route this Memory Read TLP, based on address. 5. When target device generates the completion TLP, it copies the Memory Read TLP Requester ID into the corresponding completion TLP Requester ID field and inserts its ID into the TLP Completer ID field. 6. Switches and bridges between target device and PEX 8524 NT port routes the completion TLP, based on Requester ID information. 7. NT port restores the original requester Requester ID value from the Configuration register and it implements another Requester ID and Completer ID translation for the completion TLP before it forwards the completion TLP to requester-host domain. 8. Switches and bridges between PEX 8524 NT port and requester routes the Completion TLP based on Requester ID. 9. Requester accepts the Completion TLP and processes it. 222 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 11.2.1 Transaction Originating in Local Host Domain Transaction Originating in Local Host Domain The translation of outgoing requests from the NT Port Virtual Interface to NT Port Link Interface uses an 8-entry LUT as discussed in Section 14.16.4, "NT Port Virtual Interface Send LUT Entry Registers." Each LUT entry supports all outgoing requests and any number of outstanding requests made by a single device or function. If a device uses phantom Function Numbers to increase the maximum number of outstanding transactions, then each phantom function consumes a LUT entry. The LUT must be configured, by a serial EEPROM or local firmware, before it is possible to transmit requests to the system domain, which provides a measure of security/protection. When a memory request arrives at the NT Port Virtual Interface, the packet Requester ID is associated with this LUT. If it attains one of the enabled LUT entries, the corresponding entry address (TxIndex) is inserted into the Function Number field of the packet's Requester ID. Conversely, if it misses, an Unsupported Request completion is returned. PR EL IM IN AR Y At the same time, the contents of the NT Port Link Interface Bus Number and Device Number Capture registers (the values last used during the last CSR write to the port) are copied into the Bus Number and Device Number fields of the packet Requester ID. Figure 11-9. Requester ID Translation for Request Originating in Local Domain Requester ID in Outgoing Request Device Number Capture Register ReqDev No [4:0] ReqFun No [2:0] Translation of an Outgoing Request at originating non-transparent bridge function Source CapDev DevNo FunNo Tx Translation of an Incoming Completion back at originating non-transparent bridge function ReqFun No [2:0] LUT Look up Requester ID based on TxIndex in packet BusNo BusNo DevNo DevNo BusNo DevNo FunNo FunNo 8 entries ReqDev No [4:0] BusNo FunNo FunNo Index TxIndex ReqBusNo [7:0] DevNo DevNo TxIndex Translated Requester ID in System Domain Source CapBus No BusNo BusNo 8 entries Bus Number Capture Register ReqBusNo [7:0] LUT If {BusNo, DevNo,FunNo} hit in LUT, use TxIndex; else return UR FunNo Restored Requester ID in Completion in Requester's Local Domain PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 223 Non-Transparent (NT) Bridging PLX Technology, Inc. A completion, with translated Requester ID, returned from the system domain to the PEX 8524, is recognized when its Requester ID Bus and Device Numbers match the NT Port Link Interface captured Bus and Device Numbers. When the original Requester ID is restored, the following occurs: 1. TxIndex is retrieved from the Function Number field of the completion TLP Requester ID. 2. TxIndex is used to look up the same 8-entry LUT, to restore the original Requester ID. 3. If the selected entry is valid, the restored Requester ID is placed into the completion TLP Requester field; otherwise, an unexpected completion is returned. 4. Completion TLP Completer ID field is replaced by the NT Port Virtual Interface captured Bus, Device, and Function Numbers. 5. Translated Completion TLP is forwarded to the original requester in the local domain. System Host Domain Transaction Originating PR EL IM IN AR Y 11.2.2 Transactions originating in System Host domain use a second LUT, with 32 entries as illustrated in Figure 11-10. This data structure supports up to 32 devices (elsewhere in the system domain) that are transmitting requests through the associated NT Switch port. Because the Function Number is not used in the LUT association, a separate LUT entry is not required for each requesting or phantom function device. The LUT must be configured before transmitting requests through the NT Switch port. This requester registration process, which cannot be accomplished by a peer, is an effective security and protection mechanism. When a request is received from system domain and routed to the NT port, its Requester ID is again translated - Bus and Device Number, but not Function Number. The received memory request TLP Requester ID is associated with this LUT, and the address (RxIndex) of the corresponding matching entry is substituted into the Device Number field of the memory request TLP Requester ID field. If no match is found, or the matched entry is not enabled, the request receives a UR response. If a match is found, and matched entry is enabled, the PEX 8524 internal virtual PCI Bus Number is copied into the Bus Number field of the packet Requester ID. The translated memory request TLP is address-translated and forwarded into the Local domain. The PEX 8524 internal virtual PCI Bus Number is sufficient to route the completion from the completer back to the NT port in the completer's domain, because the NT switch port is the only possible requester on the switch internal virtual bus. Elsewhere in the PCI Express hierarchy, the Bus Number is sufficient to route the completion back into the switch containing the NT port. The inverse translation occurs when a completion passes through the NT bridge from local domain to system domain. The RxIndex is retrieved from the Device Number field of received completion TLP Requester ID header field, and used to look up the 32-entry LUT. The Completion TLP Requester ID. Bus Number and Device Number fields are replaced by the decoded LUT entry Bus Number and Device Number value if the entry is valid; otherwise, an unexpected completion is returned. The Completion TLP Completer ID is replaced by the NT Port Link Interface captured Bus Number, captured Device Number and Function Number value before forwarding the completion TLP to the system domain. 224 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 NT Port Power Management Handling Figure 11-10. Requester ID Translation for Request Originating in System Domain Requester ID in Incoming Request from Host or Device in System Domain ReqBusNo [7:0] ReqDev No [4:0] LUT If {BusNo, DevNo} hit in CAM, use RxIndex; else return UR ReqFun No [2:0] {BusNo, DevNo} BusNo BusNo DevNo DevNo 32 entries Translation of an Incoming Request at target non-transparent bridge function RxIndex BusNo DevNo Translated Requester ID in Target's Local Domain Host Switch VirtBusNo [7:0] RxIndex FunNo [2:0] PR EL IM IN AR Y RxIndex LUT Use RxIndex to look up ReqBusNo and ReqDevNo Translation of an Outgoing Completion at target non-transparent bridge function BusNo BusNo ReqBusNo [7:0] ReqFun No [2:0] Requester ID in Outgoing Completion in System Domain BusNo 11.3 NT Port Power Management Handling 11.3.1 Active State Power Management (ASPM) 32 entries {BusNo, DevNo} ReqDev No [4:0] DevNo DevNo DevNo When NT mode is enabled in the PEX 8524 (Intelligent Adapter or Dual-Host mode), the device does not enter into active Power Management states L0s and L1 on any of its ports, although the PEX 8524 NT Link Interface Type 0 Endpoint, NT Virtual Interface Type 0 Endpoint, and transparent Type 1 ports are enabled for ASPM by programming ASPM control fields in the Link Control register. The PEX 8524 NT Link Interface Type 0 Endpoint and transparent Upstream ports do not enter L0s nor request an ASPM L1 entry on its transmit direction. Similarly, the PEX 8524 transparent Downstream ports transmit direction does not enter L0s state. If an ASPM L1 request is received on a PEX 8524 transparent Downstream port, a PM_Active_State_Nak message is transmitted downstream, irrespective of the Link control register ASPM control field value. The PEX 8524 allows all ports to receive a lane entry to L0s state, although NT mode is enabled. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 225 Non-Transparent (NT) Bridging 11.3.2 PLX Technology, Inc. PCI-PM and PME Turn Off Support When NT mode is enabled in the PEX 8524, the NT Port Link Interface Type 0 Endpoint behave as other endpoints in D3hot PCI-PM power states. Once in D3hot, the PEX 8524 NT Port Link Interface Type 0 Endpoint request PCI_PM L1 entry and finally settle in the L1 link state. Only configuration access and messages to the NT Port Link Interface Type 0 Endpoint are supported in D3hot state. NT host software can transmit PME_Turn_Off messages when it decides to turn off the main power and main reference clock. The PEX 8524 NT Link Interface Type 0 Endpoint indicates its readiness to lose power by transmitting a PME_To_Ack message towards the upstream device. The PME_To_Ack message is transmitted when there is no pending TLP currently to be transmitted in PEX 8524 NT Port Link Interface upstream direction. The port requests for L2/L3 Ready state by transmitting PM_Enter_L23 DLLP to the upstream device after transmitting PME_TO_Ack TLP. It settles into the L3 link state when the main power and reference clock is removed by the power controller. 11.3.3 PR EL IM IN AR Y When PME_Turn_Off message is received on the PEX 8524 transparent Upstream port, it broadcasts this message to all PEX 8524 downstream devices including the NT Port Virtual Interface Type 0 Endpoint. Once PME_To_Ack message is received from all downstream devices and from the PEX 8524 NT Port Virtual Interface Type 0 Endpoint, the PEX 8524 transparent Upstream port transmits an aggregated PME_TO_Ack message to the upstream component after it finishes transmitting all pending TLP to the upstream component. When the NT mode is enabled, the PEX 8524 transparent Downstream ports allow the attached devices to enter the PCI-PM-compatible L1 state. The PEX 8524 NT Port Virtual Interface Type 0 Endpoint never enters the PCI-PM L1 state. Message Generation The PEX 8524 NT Port Link Interface Type 0 Endpoint never generates PM_PME messages. The PEX 8524 NT Port Virtual Interface Type 0 Endpoint never receives Set_Slot_Power_Limit messages and never generates PM_PME messages. 11.4 NT Hot Plug Support The transparent Downstream ports of the PEX 8524, with NT mode enabled, behave in the same way when NT mode is disabled. The PEX 8524 NT Port Virtual Interface Type 0 Endpoint never receives Hot Plug messages and it never generates Hot Plug messages. The PEX 8524 NT Port Link Interface Type 0 Endpoint generates and receives Hot Plug messages which an Endpoint (or Switch Upstream Port) receives/generates. The PEX 8524 NT Port Link Interface Type 0 Endpoint and transparent Upstream port implements Hot Plug client features. Attention Button Present Device, Attention Indicator Present Device and Power Indicator Present Device registers and their functionality implemented on PEX 8524 NT Port Link Interface Type 0 Endpoint and the PEX 8524 Upstream port. The PEX 8524 NT Port Virtual Interface Type 0 Endpoint does not implement Hot Plug Control nor Hot Plug Client functionality, because it is an Endpoint device not connected to Physical Link. 226 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Figure 11-11. NT Hot Plug Support Intelligent Adapter Mode Hot Plug View Local Host PCI Bus upstream port number register (port 0) NT port number register (port 2) Hot-Plug Client Upstream Port0 (T) Virtual PCI Bus PR EL IM IN AR Y Virtual Side NT Bridge NT Port2 Downstream Port 1 Hot-Plug Controller Type0 Type1 Idle Type0 Hot-Plug Client Downstream Port 3 Downstream Port 15 Hot-Plug Controller Hot-Plug Controller Hot-Plug Device Hot-Plug Device Link Side NT Bridge Hot-Plug Device Downstream Device Downstream Device Downstream Device Hot-Plug Controller System Host PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 227 Non-Transparent (NT) Bridging Figure 11-12. PLX Technology, Inc. Dual-Host Mode Hot Plug View Active Host PCI Bus upstream port number register (port 0) NT port number register (port 2) Hot-Plug Client Upstream Port0 (T) Virtual PCI Bus Virtual Side NT Bridge PR EL IM IN AR Y NT Port2 Downstream Port 1 Hot-Plug Controller Type0 Type1 Idle Type0 Hot-Plug Device Downstream Port 3 Downstream Port 15 Hot-Plug Controller Hot-Plug Controller Hot-Plug Device Hot-Plug Device Link Side NT Bridge Hot-Plug Device Downstream Device Downstream Device Downstream Device Hot-Plug Controller Back up Host 11.4.1 Hot Plug Sequence during Host-Failover Hot Plugging the complete Active Host domain into Backup Host is similar to Hot Plugging the end point device into Downstream port of a Switch or Root Port. If the Backup Host is dead, it is not a problem. If the Active Host is dead, the Backup Host first completes the Hot Plug insertion sequence before it starts the failover sequence. Active host can service none or a portion of the Hot Plug sequence on transparent Downstream port and dies before servicing the remaining sequence. Downstream port Hot Plug controller module previously transmitted an interrupt for the next Hot Plug sequence to the failed transparent Upstream port and it did not receive service from failed active host. The Backup Host disables the "MSI and INTX interrupt generation" before it starts the failover sequence. After the Backup Host finishes the failover sequence, it enables the "MSI and/or INTX interrupt generation" for the transparent Downstream port. This interrupt generation re-enabling generates Interrupt Assertion messages (or MSI Interrupt) to the selfpromoted Backup (Active) Host. This self-promoted Backup (Active) Host continues the remaining Hot Plug insertion/removal sequence remaining from the failed active host. 228 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 12 12.1 Non-Transparent Bridging Software Architecture Introduction This chapter focuses on system configuration and data transfer through the NT port. the PEX 8524 supports two types of NT modes: * Intelligent Adapter * Dual-Host The NT Port and NT-mode type are described in Chapter 11, "Non-Transparent (NT) Bridging." The PEX 8524 NT feature and mode (Intelligent Adapter or Dual-Host) are enabled using card-level Strapping balls. The PEX 8524 require software support for the following: * System Configuration * Data transfer through NT port * Quality of Service (QoS) management in a switch * Performance tuning in a switch * Interrupt Service routine * Hot Plug routine * Power Management routine * Error Handling routine 12.2 System Configuration The PCI Express Configuration model supports two configuration space access mechanisms: * PCI-compatible configuration * PCI Express-enhanced configuration The PCI-compatible mechanism supports 100% binary compatibility with the PCI r2.3 or later operating systems and corresponding bus enumeration and configuration software. The PCI Express-enhanced mechanism is provided to increase the size of available configuration space and optimize access mechanisms. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 229 Non-Transparent Bridging Software Architecture 12.2.1 PLX Technology, Inc. PEX 8524 Intelligent Adapter Mode Configuration Figure 12-1 describes a sample system view with PEX 8524 NT Intelligent Adapter mode enabled. Figure 12-1. Sample System Configuration with Non-Transparent PEX 8524 The PEX 8524 transparent ports are a PCI-to-PCI bridge, and the PEX 8524 NT port is two Type 0 Endpoint devices connected back-to-back. PCI Express devices must include an assigned unique ID (Bus, Device, and Function Numbers). Each PEX 8524 transparent port includes its own 4-KB PCI Express configuration registers and NT Port includes 8 KB configuration space - 4 KB for NT Port Virtual Interface Type 0 Endpoint and another 4 KB for NT Port Link Interface Type 0 Endpoint. At power-up, one of PEX 8524 ports are selected as an Upstream port and one of PEX 8524 Downstream ports are selected as an NT port, using card-level Strapping balls or a serial EEPROM. PR EL IM IN AR Y The BIOS running in Local Host configures PEX 8524 Upstream ports, Downstream ports, and NT Port Virtual Interface Type 0 Endpoint. The BIOS running in System Host configures NT Port Link Interface Type 0 Endpoint. Local Host-connected Root Complex initiates Type 0 Configuration cycle to configure only PEX 8524 Upstream ports and initiates Type 1 Configuration cycles to configure the PCI Express hierarchy behind the PEX 8524 Upstream port, including the PEX 8524 NT Port Virtual Interface Type 0 Endpoint. Local Host is not allowed to configure the NT Port Link Interface Type 0 Endpoint using Type 0/Type 1 Configuration cycles. System Host-connected Root Complex initiates Type 0 Configuration cycle to configure only PEX 8524 NT Port Link Interface Type 0 Endpoint. If this Root Complex initiates Type 1 Configuration cycles, it is rejected by NT Port Link Interface Type 0 Endpoint as an Unsupported Request (UR) error. 230 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PEX 8524 Intelligent Adapter Mode Configuration NT Port Virtual and Link Interface Type 0 Endpoint BARs 2 through 5 are disabled by default. Each BAR includes a corresponding BAR Setup register. This BAR Setup register controls the corresponding BAR, in the following manner: * Enables/disables BAR * Programs BAR size * Maps BAR group into 32- or 64-bit Address space * Maps BAR into Prefetchable or Non-Prefetchable Memory space Refer Section 11.1.5, "BAR Setup Registers," for a detailed description of BARs and BAR Setup registers. PR EL IM IN AR Y Use a serial EEPROM to enable the necessary BARs for inter-host-domain traffic by default; otherwise, System software/BIOS and Device Driver software must work together to enable the NT Port Type 0 Endpoint BARs before assigning resources to the BARs. The PEX 8524 implements the following two configuration register bits to take advantage of software layer resource assignment for the NT port. The NT port includes Debug Control register Link Interface Access Enable and Virtual Interface Access Enable device-specific Configuration register bits, mapped to PEX 8524 Port 0, at offset 1DCh[29:28], respectively. By default, the Virtual Interface Access Enable configuration bit is set to 1, and the Link Interface Access Enable configuration bit is set to 0. The serial EEPROM overrides these default values. If the Virtual Interface Access Enable configuration bit is 0, NT Port Virtual Interface Type 0 Endpoint returns "Configuration Retry Status (CRS)" response (completion with CRS status) for the received Configuration cycle request from Local Host. Otherwise, it accesses the corresponding Configuration registers. If the Link Interface Access Enable configuration bit is 0, NT Port Link Interface Type 0 Endpoint returns "Configuration Retry Status (CRS)" response (completion with CRS status) for the received Configuration cycle request from System Host. Otherwise, it accesses the corresponding Configuration registers. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 231 Non-Transparent Bridging Software Architecture 12.2.2 PLX Technology, Inc. Sample PEX 8524 Configuration Steps The PEX 8524 can be configured using a serial EEPROM or software. To configure the PEX 8524: 1. Select PEX 8524 operating mode. a. Use STRAP_MODE_SEL[1:0] balls to select PEX 8524 operating mode. (Refer to Table 3-6: PEX 8524 Strapping Signals - 24 Balls for the operating mode encoding values.) b. Serial EEPROM is used to override the Strapping ball selection. 2. Select port configuration. a. Select STRAP_STN0_PORTCFG[4:0] for PEX 8524 Station 0 port configuration, and STRAP_STN1_ PORTCFG[3:0] for PEX 8524 Station1 port configuration. (Refer to Table 4-1: PEX 8524 Port Configurations for the Strapping ball encoded values.) b. Serial EEPROM is used to override the Strapping ball selection. PR EL IM IN AR Y 3. Select Upstream port. a. STRAP_UPSTRM_PORT_SEL[3:0] selects one of PEX 8524 ports as an Upstream port. b. Serial EEPROM is used to override the Strapping ball selection. 4. NT Port selection a. STRAP_NT_UPSTRM_PORT_SEL[3:0] selects one of the PEX 8524 Downstream ports as an NT port. b. Serial EEPROM is used to override the Strapping ball selection. 5. Power-up the system. 6. Software enumeration directives. a. Locating Root Port devices and Root complex integrated Endpoint devices within a Root Complex are implementation-specific. b. Root Complex is allowed more than one Root Port. c. PCI Express hierarchy starts from Root Complex Root Port. d. Local Host BIOS and System Host BIOS scans the device presence behind Root Port, using Type 0 Configuration cycle. e. BIOS reads key configuration registers (for example, Header Type, Class Code, PCI Express Device/Port Type field, and so forth) to locate the Device Type and Header Type. f. PEX 8524 NT Port Link Interface Type 0 Endpoint responds to the configuration access with CRS, as its "Link Interface Access Enable" is disabled by default. g. System Host connected Root Complex later Retries this Configuration cycle to PEX 8524 NT Port Link Interface Type 0 Endpoint. h. PEX 8524 NT Port Link Interface Type 0 Endpoint continues to Retry the Configuration request until it comprehends that "Link Interface Access Enable" is enabled. i. PEX 8524 Upstream port accesses the corresponding Configuration registers and returns a successful completion. j. BIOS detects a PCI-to-PCI bridge device behind Local Host connected Root Complex and programs the PEX 8524 Upstream port Primary Bus Number, Secondary Bus Number, and Subordinate Bus Number registers. k. BIOS commences scanning devices behind the PEX 8524 Upstream port, using Type 1 Configuration cycle. 232 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Sample PEX 8524 Configuration Steps l. m. PR EL IM IN AR Y n. If the received Type 1 Configuration cycle Bus Number is equal to the PEX 8524 Upstream port secondary Bus Number register value, and the Type 1 Configuration cycle Device Number is equal to the Downstream port number or NT Port number, PEX 8524 accesses the corresponding port configuration register. (Downstream ports "port number" and NT Port "port number" is equal to Device Number on PEX 8524 Internal PCI Bus. NT Port Virtual Interface Type 0 Endpoint Device Number is NT Port "port number" and NT Port Link Interface Type 0 Endpoint Device Number is the Device Number assigned by the upstream device.) If BIOS locates a PCI-to-PCI device (Downstream port) on PEX 8524 internal PCI Bus, it commences the depth-first device scan behind PEX 8524 Downstream port by programming PEX 8524 Downstream port's Primary Bus Number, Secondary Bus Number, and Subordinate Bus Number registers. PEX 8524 Upstream port routes received Type 1 Configuration cycle to a PEX 8524 Downstream port if the received Type 1 Configuration cycle Bus Number is greater than the PEX 8524 Upstream port secondary Bus Number and less than or equal to PEX 8524 Upstream port subordinate Bus Number, as well as within the PEX 8524 Downstream port secondary Bus Number and subordinate Bus Number window. If the received Type 1 Configuration cycle Bus Number is equal to PEX 8524 Downstream port secondary Bus Number, the PEX 8524 downstream converts this Type 1 Configuration access to a Type 0 Configuration access, if the Type 1 configuration cycle Device Number is 0. If the Type 1 configuration cycle Device Number is non-zero, the PEX 8524 Downstream port returns Unsupported Request (UR) error. If the received Type 1 Configuration cycle Bus Number is greater than the PEX 8524 Downstream port secondary Bus Number and less than or equal to the PEX 8524 Downstream port subordinate Bus Number, the PEX 8524 Downstream port forwards this Type 1 Configuration cycle to the downstream device unmodified. If BIOS locates an NT Port Virtual Interface Type 0 Endpoint of the PEX 8524 internal PCI Bus, it stops scanning behind the NT port, because it is an Endpoint and the PCI Express Hierarchy ends in an Endpoint. After locating all devices within the PCI Express hierarchy, BIOS commences resource assignment (for example, Memory, I/O, and/or Interrupt resource). If the application is not using a serial EEPROM, System software/BIOS requires modification to implement the following: o. p. q. r. s. - Assign a Memory, I/O, and/or Interrupt resource to the PEX 8524 Upstream port BAR0 (Memory BAR) or PEX 8524 NT Port Virtual Interface BAR1 (I/O BAR) before assigning Memory resources to PEX 8524 NT Port Virtual Interface Type 0 Endpoint BAR2 to BAR5 - Use Memory/I/O-Mapped cycle (refer to Section 14.2, "Register Access," for details) to program the PEX 8524 NT Port Virtual Interface Type 0 Endpoint BAR Setup register t. u. v. w. x. - Assign a resource to the PEX 8524 NT Port Virtual Interface Type 0 Endpoint Use Memory/I/O-Mapped cycle to program the NT Port Link Interface Type 0 Endpoint BAR Setup register. Use Memory-Mapped cycle to enable Link Interface Access Enable Configuration bit. After enabling the PEX 8524 NT Port Link Interface Type 0 Endpoint, System Host BIOS is allowed to enumerate and assign a resource to the PEX 8524 NT Port Link Interface Type 0 Endpoint. Use a Memory/I/O-Mapped cycle to program the PEX 8524 NT Port Type 0 Endpoint Address Translation registers. (Refer to Chapter 14, "NT Port Virtual Interface Registers," and Chapter 15, "NT Port Link Interface Registers," for details.) Use Memory/I/O-Mapped cycle to program the PEX 8524 NT Port Type 0 Endpoint BAR Limit registers if application is to efficiently use the memory resource. (Refer to Chapter 14, "NT Port Virtual Interface Registers," and Chapter 15, "NT Port Link Interface Registers," for details.) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 233 Non-Transparent Bridging Software Architecture y. 12.2.3 PLX Technology, Inc. Use Memory/I/O-Mapped cycle to program the PEX 8524 NT Port Type 0 Endpoint "Send LUT Entry" and "Receive LUT Entry" registers. (Refer to Chapter 14, "NT Port Virtual Interface Registers," and Chapter 15, "NT Port Link Interface Registers," for details.) PEX 8524 Dual-Host Mode Configuration PEX 8524 NT Dual-Host mode configuration is similar to PEX 8524 NT Intelligent Adapter mode configuration, except the default values of the NT port Virtual Interface Access Enable and Link Interface Access Enable bits are set to 1. Both hosts connected to the PEX 8524 Upstream port and NT Port Link Interface Type 0 Endpoint can concurrently enumerate the devices. The PEX 8524 does not generate a CRS response in NT Dual-Host mode. 12.2.4 Host-Failover Application PR EL IM IN AR Y The host-failover application is based on the basic dual-host configuration. The active host periodically transmits heartbeat messages, by way of the switch to the Backup host, to state it remains active. When the Backup Host fails to receive heartbeat messages before the fail-detect timer expires, it starts the failover process. The Backup Host halts cross-domain traffic before it starts the failover. The Backup Host uses the Memory-Mapped access to the Configuration register to execute the failover. The Backup Host follows the ensuing procedure to take control: 1. Failover Detected: a. Backup Host detects the Active host failure condition and it starts the failover process (such as, Heartbeat Message Reception timeout). b. The Upstream port remains active in this state. 2. Upstream Port Demotion: a. PEX 8524 is not in Reset when the failover process begins. b. PEX 8524 contains a Hot Reset Disable Configuration register bit that disables reset generation due to Hot Reset and Upstream Port DL_Down condition. This CSR bit is located in Port 0 offset 1DCh[20] and is asserted by default for PEX 8524 Dual-Host mode. c. As one of the first steps in the failover process, the Backup Host demotes the Upstream port by writing 0000b into the PCI Express Capabilities register (PCI Express Endpoint) Device/Port Type field. d. Transaction Layer Ingress snoops this access and informs Event c above detection to the TLP destined transparent Upstream port. e. Event d above causes the Upstream Port Physical Layer to bring down its upstream link, which generates the Upstream port DL_Down condition. f. Event d also causes the Upstream port to change its Device/Port type field to PCI Express Endpoint, and changes the PCI Class code to other bridged devices. The transparent Upstream port becomes a PCI Express endpoint. g. Upstream Port Transaction Layer Egress module drops all outgoing packets to the upstream device when it comprehends the Upstream port DL_Down condition. h. Upstream_Port_Number_Register[3:0] and NT_Port_Number_Register[3:0] remains unchanged in this state. i. Downstream port internal modules forward/generate the packet for the upstream device which goes to the previous Upstream port and the packets are dropped by the demoted Upstream port Transaction Layer Egress module due to this DL_Down condition. j. When a Transaction Layer Ingress module receives TLPs from the demoted upstream connected device, it processes the normal Upstream port type of address decoding and forwards the packet to the destination port based on AMCAM, IOCAM, or BusNoCAM lookup. 3. NT Port (Self) Promotion as a New Upstream Port: 234 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Data Transfer through NT Port a. b. c. d. e. PR EL IM IN AR Y f. Software can disable the Master Enable, Memory Enable, I/O Enable and Interrupt Enable NT Port Virtual Interface (Even Error Message Generation Enable CSR bits), if it cannot receive traffic immediately after self-promotion. Backup Host host promotes itself as a Active host by writing 0101b into the NT Port Virtual Interface Type 0 configuration PCI Express Capabilities register (transparent Upstream port) Device/Port Type field. PEX 8524 swaps the Upstream_Port_Number_Register[3:0] and NT_Port_Number_Register[3:0] values when a Transaction Layer ingress informs Event b of this condition. PEX 8524 processes the Port transition. PEX 8524 converts demoted transparent Upstream port to NT Port and Previous NT Port to transparent Upstream port. New Upstream port retrieves previously programmed NT Port Virtual Interface Type 0 CSR values. PEX 8524 does not swap the configuration space value from previous Upstream port to new Upstream port by itself after failover. Software running in Promoted Active Host follows the ensuing procedure to bring the system into a communicating state. - Copies the previous Upstream port configuration space value to a new Upstream port configuration space value and the previous NT Port Virtual Interface Type 0 endpoint configuration space value to a new NT Port Virtual Interface Type 0 Endpoint configuration space value. - Resets the entire hierarchy and restarts the system using full software re-enumeration. 12.3 Data Transfer through NT Port The following discusses the configuration registers mainly programmed for data transfer through the NT port. To transfer data from NT Port Virtual Interface to NT Port Link Interface direction: 1. Assign memory space to NT Port Virtual Interface Type 0 Endpoint BAR registers. 2. Enable NT Port Virtual Interface Type 0 Endpoint "Memory Enable" Link Interface Access Enable CSR bit (offset 04h). 3. Enable NT Port Link Interface Type 0 Endpoint "Master Enable" CSR bit (offset 04h). 4. Program NT Port Virtual Interface Type 0 Endpoint Address Translation registers with transaction completer (target) BAR value. If application is using Lookup Table-based Address translation, it must enable the corresponding LUT Entry as well. Address translation register values can be dynamically changed by a device driver depending on where the requester is located. Before changing the Address Translation register values, the device driver must ensure that there is no outstanding request pending to the NT Port. 5. Enable and program NT Port Virtual Interface "Send LUT Entry" registers with Requesters ID (Bus, Device, and Function Numbers). "Send LUT Entry" registers values can be dynamically changed by a device driver depending on the request enabled to communicate through the PEX 8524 NT port. Before changing the "Send LUT Entry," the device driver must ensure there is no outstanding request pending for that requester. To transfer data from NT Port Link Interface to NT Port Virtual Interface direction: 1. Assign memory space to NT Port Link Interface Type 0 Endpoint BARs. 2. Enable NT Port Link Interface Type 0 Endpoint "Memory Enable" CSR bit (offset 04h). 3. Enable NT Port Virtual Interface Type 0 Endpoint "Master Enable" CSR bit (offset 04h). 4. Program NT Port Link Interface Type 0 Endpoint Address Translation registers with transaction completer (target) BAR value. Address translation register values can be dynamically changed by a PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 235 Non-Transparent Bridging Software Architecture PLX Technology, Inc. device driver depending on where the requester located the Virtual Link side. Before changing the Address translation register values, device driver must ensure there is no outstanding request pending to the NT Port. PR EL IM IN AR Y 5. Enable and program NT Port Link Interface "Receive LUT Entry" registers with Requesters Bus Number, and Device Number value. "Receive LUT Entry" registers values can be dynamically changed by a device driver depends on the request enabled to communicate through the PEX 8524 NT port. Before changing the "Receive LUT Entry," the device driver must ensure there is no outstanding request pending for that requester. 236 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 13 13.1 NT Port Interrupts Introduction NT Port Virtual and Link sides can generate INTx or MSI interrupts. INTx or MSI Interrupts can be enabled by the PCI Command register INTx Disable bit and the MSI Control register MSI enable bit. Because they are endpoints, the NT Port Virtual and Link sides cannot receive Interrupt messages; therefore, if an interrupt message is received, it is reported as an error condition. The NT Port Virtual side generates Interrupts to the Local Host/Active Host for device-specific errors reported by NT Port Egress modules or Doorbell interrupts. The NT Port Link side generates interrupts to the System/Inactive Secondary Host when device-specific errors are reported by NT Port Ingress modules. 13.2 Doorbell Interrupts By default, all interrupt sources are masked. If software processes an interrupt, it first clears the Interrupt Mask register for the interrupt source. The asserted INTx virtual wires are de-asserted, when the software clears the Event Status bit that caused the assertion. The Interrupt handler maintains two set of registers - one set for Virtual Side Type 0 Configuration Space and another set for Link Side Type 0 Configuration Space of the NT port. Further information regarding INTx and MSI Interrupts is provided in Chapter 6, "Interrupts." 13.3 Doorbell Register A 16-bit software-controlled Interrupt Request register and an associated 16-bit Mask register is implemented for each interface (Virtual and Link). These registers can be accessed from the Virtual or Link Interface of the NT port in Memory or I/O space. The doorbell mechanism consists of the following registers: * Virtual IRQ Set * Virtual IRQ Clear * Virtual IRQ Set Mask * Virtual IRQ Clear Mask * Link IRQ Set * Link IRQ Clear * Link IRQ Set Mask * Link IRQ Clear Mask PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 237 NT Port Interrupts PLX Technology, Inc. An Interrupt is asserted on the Virtual Interface when one or more of the bits in the IRQ Set/Clear register are set and corresponding mask bits are 0. The Link Interface works identically. The interrupt is de-asserted when all the asserted bits are masked or cleared. The Set/Clear registers are internally the same physical Interrupt Request register. It includes two separate DWords - one DWord is used to set bits and the other is used to clear bits. The status can be read from either register. PR EL IM IN AR Y The Set/Clear Mask registers are also internally the same register - one interface is used to set a mask bit and the other to clear a mask bit. 238 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 14 14.1 NT Port Virtual Interface Registers Introduction This chapter defines the registers for the PEX 8524 Non-Transparent (NT) Port Virtual Interface (interface) registers. The NT Port includes two sets of configuration-capability, control and status registers to support the Virtual and Link Interfaces. NT Port Virtual Interface register mapping is delineated in Table 14-1. The NT Port Link Interface registers are defined in Chapter 15, "NT Port Link Interface Registers." For additional information regarding register names and descriptions, refer to the following specifications: * PCI r2.3 * PCI Express Base 1.0a * PCI Power Mgmt. r1.1 * PCI ExpressCard 1.0a * PCI HotPlug 1.1 * PCI Standard Hot Plug r1.0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 239 NT Port Virtual Interface Registers PLX Technology, Inc. Table 14-1. NT Port Virtual Interface Type 0 Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h Configuration Header Registers ... Capability Pointer (40h) 34h ... 3Ch Next Capability Ptr (48h) Capability ID (01h) Power Management Capabilities Registers Next Capability Ptr (68h) 40h 44h Capability ID (05h) 48h ... PR EL IM IN AR Y Message Signaled Interrupt Capabilities Registers Next Capability Ptr (00h) 54h Capability ID (10h) 68h ... PCI Express Capabilities Registers Reserved 78h 7Ch - 90h NT Port Registers Next Capability Offset (FB4h) 1h 8Ch ... FFh Extended Capability ID (0003h) 100h 104h Device Serial Number Extended Capabilities Registers Reserved Next Capability Offset (148h) 1h Extended Capability ID (0004h) 108h 10Ch - 134h 138h ... Device Power-Budgeting Extended Capabilities Registers 144h Next Capability Offset (000h) 1h Extended Capability ID (0002h) 148h ... Virtual Channel Extended Capabilities Registers 1C4h 1C8h PLX-Specific Registers, PEX 8524 Non-Transparent Bridging-Specific Registers ... FB0h Next Capability Offset (138h) 1h Extended Capability ID (0001h) FB4h FB8h Advanced Error Reporting Capability Registers ... FFCh 240 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 14.2 Register Access Register Access The PEX 8524 supports four methods for accessing its NT Port registers: * PCI Express Base 1.0a Configuration Mechanism * PLX-Specific Memory-Mapped Configuration Space Access Mechanism * PLX-Specific I/O-Mapped Configuration Space Access Mechanism * PLX-Specific Cursor Mechanism 14.2.1 PCI Express Base 1.0a Configuration Mechanism PCI Express extends Configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the PCI r2.3. PCI Express Configuration space is divided into PCI r2.3-compatible Configuration space and Extended PCI Express Configuration mechanisms. PR EL IM IN AR Y The PEX 8524 decodes all Type 1 Configuration transactions received on its Upstream port. If the received Type 1 Configuration transaction Bus Number matching the PEX 8524 internal PCI Bus Number and the Device Name match the NT Port number, the PEX 8524 reads or writes to the NT Port Virtual Interface requester, as specified in the original Type 1 Configuration access. The PCI r2.3-compatible Configuration mechanism provides standard access to the first 256 bytes (the bytes at offsets 00h through FFh) of the NT Port Virtual Interface Configuration register space. The PCI Express Enhanced Configuration Access mechanism provides access to the remaining 4 KB (offsets 100h through FFFh). 14.2.1.1 PCI r2.3-Compatible Configuration Mechanism The PCI r2.3-Compatible Configuration space consists of the first 256 bytes of the NT Port Virtual Interface Configuration space (Figure ). The PCI r2.3-compatible region is accessed using the Type 1 mechanism defined in the PCI r2.3, or the PCI Express Enhanced Configuration Mechanism, PLX-Specific Memory- or I/O-Mapped access. Accesses made using either access mechanism are equivalent. Because the PCI r2.3-Compatible Configuration Mechanism is limited to the first 256 bytes of the NT Port Virtual Interface Configuration register space, one of the following must be used to access beyond byte FFh. * PCI Express Enhanced Configuration Mechanism * PLX-Specific Memory-Mapped Configuration Space Access Mechanism * PLX-Specific Cursor Mechanism The PCI r2.3-Compatible Configuration Access mechanism uses the same Request format as the PCI Express Enhanced Configuration Mechanism. For PCI-compatible Configuration Requests, the Extended Register Address field must be all zeros (0). Do not use this mechanism to access the PLX PEX 8524 Device-Specific Configuration register. 14.2.1.2 PCI Express Enhanced Configuration Mechanism The Extended PCI Express Configuration Mechanism uses a flat, root complex Memory-Mapped Address space to access device Configuration registers. In this case, the Memory address determines the Configuration register accessed and the Memory data returns the addressed register's contents. The root complex converts the Memory transaction into a Configuration transaction. The mechanism is used to access the NT Port Virtual Interface Type 0 registers: * Configuration Header Registers * Power Management Capabilities Registers * Message Signaled Interrupt Capabilities Registers * PCI Express Capabilities Registers PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 241 NT Port Virtual Interface Registers PLX Technology, Inc. * Device Serial Number Extended Capabilities Registers * Device Power-Budgeting Extended Capabilities Registers * Virtual Channel Extended Capabilities Registers * Advanced Error Reporting Capability Registers Do not use this mechanism to access the PEX 8524 device-specific registers. 14.2.2 PLX-Specific Memory-Mapped Configuration Space Access Mechanism The PLX-Specific Memory-Mapped Configuration Space Access Mechanism provides a mechanism to access the PEX 8524 port configuration registers in a single memory map, as illustrated in Figure . The registers of each port are contained within a 4-KB range. PR EL IM IN AR Y When the NT Port is enabled at Fundamental reset, the NT Port Virtual Interface and Link Interface Configuration registers are used in place of the Type 0 Configuration registers for that port. To use the PLX-Specific Memory-Mapped Configuration Space Access Mechanism, use the PCI r2.3Compatible Configuration Mechanism to program The PEX 8524 Upstream port Base Address 0 and Base Address 1 registers. After the PEX 8524 Upstream port Memory-Mapped Register Base address is set, the Upstream port registers is accessed with memory reads from and writes to the configuration space registers. The NT Port registers are accessed with Memory reads from and writes to the 4-KB range, starting at offset 64 KB for the Virtual Interface registers and offset 68 KB for the Link Interface registers. This mechanism is used to access all PEX 8524 Configuration registers. Figure 14-1. PEX 8524 Memory Map PEX 8524 Port 0 0K 4K Port 1 8K 12K Reserved 16K 32K Port 8 36K Port 9 Port 10 Port 11 40K 44K 48K Reserved 64K NT-Port Virtual Interface NT-Port Link Interface 68K 72K Reserved 128K 242 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 14.2.3 PLX-Specific I/O-Mapped Configuration Space Access Mechanism PLX-Specific I/O-Mapped Configuration Space Access Mechanism The first 256 bytes of NT Port Virtual Interface Configuration Space registers are directly accessible by I/O transaction. The NT Port Virtual Interface BAR1 register is used for I/O-mapped access. Extended Configuration Space registers are accessed by using the Cursor mechanism in I/O space. Figure 14-2. I/O-Mapped Configuration Space View 32 Bits PR EL IM IN AR Y 7 0F4h BAR1 (I/O BAR) PCI-Compatible Configuration Space 0 000h 0F8h CFGADDR 0FCh CFGDATA 31 100h Extended Configuration Space FFCh 14.2.4 PLX-Specific Cursor Mechanism In Figure 14-2, the software uses the CFGADDR register to point to the NT Port Virtual Interface or NT Port Link Interface Configuration Space registers, including the Extended Space register. Software uses CFGDATA access to read or write to the selected Configuration Space registers. Refer to Section 14.11, "Cursor Mechanism Control Registers," for the register description. 14.3 Register Descriptions The following sections detail the PEX 8524 NT Port registers, including: * Bit /field names * Description of the register's function in the PEX 8524 NT Port Virtual and Link Interfaces * Type * Initial power-on/reset value * Whether the power-on/reset value is modified by way of the PEX 8524 serial EEPROM initialization feature * Specification references PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 243 NT Port Virtual Interface Registers 14.4 PLX Technology, Inc. Configuration Header Registers Table 14-2. Type 0 Configuration Space Header Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Device ID Vendor ID 00h Status Command Bits 04h Base Class Code HEADER TYPE MASTER LATENCY TIMER 08h Cache Line Size 0Ch Base Address 0 (Reserved) 10h Base Address 1 14h Base Address 2 18h PR EL IM IN AR Y BIST Revision ID Base Address 3 1Ch Base Address 4 20h Base Address 5 24h Cardbus CIS Pointer 28h Subsystem ID Subsystem Vendor ID 2Ch Expansion ROM Base Address Reserved 30h Capability Pointer 34h Reserved Reserved Interrupt Pin 38h Interrupt Line 3Ch Register 14-1. 00h Product Identification Type Serial EEPROM Default 15:0 Vendor ID Unless overwritten by the serial EEPROM, returns the PLX PCI-SIG assigned Vendor ID, for each port. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX Vendor ID with another Vendor ID. HwInit Yes 10B5h 31:16 Device ID Unless overwritten by the serial EEPROM, the PEX 8524 returns 8524h, the PLX-assigned Device ID. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX-assigned Device ID with another Device ID. HwInit Yes 8524h Bit(s) 244 Description PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers Register 14-2. 04h Status/Command Type Serial EEPROM Default 0 I/O Access Enable 0b = PEX 8524 ignores I/O accesses on the NT port Virtual Interface. 1b = PEX 8524 accepts the I/O request received on the NT port's Virtual Interface R/W Yes 0b 1 Memory Access Enable 0b = PEX 8524 ignores memory accesses on the NT port Virtual Interface. 1b = PEX 8524 accepts the memory request received on the NT port's Virtual Interface. R/W Yes 0b 2 Bus Master Enable Controls Memory request forwarding in the upstream direction. Does not affect the forwarding of messages and Completions in the upstream direction. 0b = PEX 8524 handles memory requests received on the NT port's Link Interface as Unsupported Requests (UR), and for Non-Posted Requests PEX 8524 returns a Completion with UR completion status. 1b = PEX 8524 forwards memory requests. R/W Yes 0b 3 Special Cycle Enable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 4 Memory Write and Invalidate Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 5 VGA Palette Snoop Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 6 Parity Error Response Enable Controls Master Data Parity Error. R/W Yes 0b 7 IDSEL Stepping/Write-Cycle Control Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 8 SERR# Enable Controls the Signaled System Error bit. When 1b, enables reporting of non-fatal and fatal errors detected by the NT Port Virtual Interface to the root complex. R/W Yes 0b 9 Fast Back-to-Back Transaction Enabled Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 10 Interrupt Disable 0b = Corresponding NT Port Virtual Interface enabled to generate INTx Interrupt Messages 1b = Corresponding NT Port Virtual Interface prevented from generating INTx Interrupt Messages R/W Yes 0b Bit(s) Description 15:11 PR EL IM IN AR Y Command Bits Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 00h 245 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-2. 04h Status/Command (Cont.) Bit(s) Description Type Serial EEPROM Default Status Bits 18:16 Reserved 000b 19 Interrupt Status 0b = No INTx Interrupt pending 1b = INTx Interrupt pending internally to the corresponding NT Port Interface RO Yes 0b 20 Capabilities List Set to 1b as required by the PCI Express Base 1.0a. RO Yes 1b 21 66-MHz Capable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 22 Reserved 23 Fast Back-to-Back Transaction Enabled Set to 0b as required by the PCI Express Base 1.0a. 24 Master Data Parity Error If the Parity Error Response Enable bit = 1b, the corresponding PEX 8524 port sets Master Data Parity Error to 1b when: * NT port forwards the poisoned TLP write request from Link Interface to Virtual Interface, or * NT port receives a Completion marked poisoned on its Virtual Interface If the Parity Error Response Enable bit = 0b, the PEX 8524 never sets Master Data Parity Error. PR EL IM IN AR Y 26:25 0b DEVSEL Timing Not supported. Always set to 00b. RO No 0b R/W1C Yes 0b RO No 00b R/W1C Yes 0b 27 Target Abort Signaled Set to 1b, when the NT Port forwards a Completion with Completer Abort (CA) status from the Link Interface to the Virtual Interface. Note: No update to the advanced error reporting register. 28 Target Abort Received Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 29 Master Abort Received Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 30 Signaled System Error If the SERR# Enable bit = 1b, the corresponding NT Port Virtual Interface sets Signaled System Error to 1b when it transmits an ERR_FATAL or ERR_NONFATAL Message to its Upstream port. R/W1C Yes 0b 31 Detected Parity Error The NT Port Virtual Interface sets Detected Parity Error to 1b when it receives a Poisoned TLP, regardless of the Parity Error Response Enable bit state. R/W1C Yes 0b 246 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers Register 14-3. 08h Class Code and Revision ID Bit(s) 7:0 Description Type Serial EEPROM Default RO Yes BAh Revision ID Unless overwritten by the serial EEPROM, returns BAh, the PLX-assigned Revision ID for this version of the PEX 8524. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX Revision ID with another Revision ID. Class Code 31:8 15:8 Programming Interface Reserved as required by the PCI r2.3. 23:16 Sub-Class Code Other Bridge Devices. 31:24 Base Class Code Bridge Devices. 068000h 00h PR EL IM IN AR Y RO Yes 80h 06h Register 14-4. 0Ch Miscellaneous Bit(s) Description Type Serial EEPROM Default 7:0 Cache Line Size Implemented as a read-write field for legacy compatibility purposes and does not impact PEX 8524 functionality. R/W Yes 00h 15:8 Master Latency Timer Not Supported. Set to 00h. RO No 00h 22:16 Configuration Layout Type Type 0 Configuration Header for NT Port. RO Yes 00h 23 Function Type 0b = PEX 8524 is a single-function device RO Yes 0b BIST Not Supported RO No 00h 31:24 Register 14-5. 14h Base Address 1 Bit(s) 0 Description I/O Space Indicator I/O BAR when D0h[1:0] = 11b; otherwise, Reserved. 7:1 Reserved 31:8 I/O Base Address 256-byte size I/O space base address when D0h[1:0] = 11b; otherwise, Reserved. Type Serial EEPROM Default RO Yes 1b 0h R/W PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 0000_00h 247 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-6. 18h Base Address 2 Type Serial EEPROM Default Memory Space Indicator 0b = Memory BAR - only value supported RO Yes 0b Memory Map Type 00b = Mappable anywhere in 32-bit memory space 01b, 10b, 11b = Reserved RO Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable RO Yes 0b Bit(s) 0 2:1 3 Description Reserved 00h 31:12 Base Address Contains the software-assigned Memory space Base address: * Enabled and sized by BAR2 Setup register * Used for Memory transactions crossing the NT port * Minimum Address range requested is 4 KB * Uses direct address translation * Includes a Limit register PR EL IM IN AR Y 11:4 1 R/W Yes 0000_0h Register 14-7. 1Ch Base Address 3 NT Port Virtual Interface Memory Space Type Serial EEPROM Default Memory Space Indicator 0b = Memory BAR - only value supported RO Yes 0b Memory Map Type 00b = Mappable anywhere in 32-bit memory addressing space 01b, 10b, 11b = Not allowed RO Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable RO Yes 0b Bit(s) 0 2:1 3 Description 17:4 Reserved 31:18 Base Address 3 Contains the software-assigned Memory space Base address: * Enabled and sized by BAR3 Setup register * No Limit register * Used for Memory transactions crossing the NT port * Minimum address range requested is 256 KB * Uses LUT address translation 248 000h R/W Yes 0000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers Register 14-8. 20h Base Address 4 Type Serial EEPROM Default Memory Space Indicator 0b = Memory BAR - only value supported RO Yes 0b Memory Map Type 00b = BAR is mapped anywhere in 32-bit Memory space 10b = BAR is mapped anywhere in 64-bit Memory space 01b, 11b = Reserved RO Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable RO Yes 0b Bit(s) 0 2:1 3 Description Reserved 00h 31:12 Base Address 4 Contains the software-assigned Memory space Base address: * Enabled and sized by BAR4 Setup register * Used for Memory transactions crossing the NT port * Minimum address range requested is 4 KB * Uses direct address translation PR EL IM IN AR Y 11:4 R/W Yes 0000_0h Register 14-9. 24h Base Address 5 Bit(s) 31:0 Description Base Address NT Port Virtual Interface upper 32-bit address if BAR4/5 is implemented as a 64-bit BAR; otherwise, reserved. R/W, based on BAR5 setup register. The BAR4/5 group uses direct address translation. Contains a Limit register. Type Serial EEPROM Default R/W Yes 0-0h Register 14-10. 28h Cardbus CIS Pointer Bit(s) 31:0 Description Type Serial EEPROM Reserved Default 0-0h Register 14-11. 2Ch Subsystem ID and Subsystem Vendor ID Type Serial EEPROM Default 15:0 Subsystem Vendor ID Unless overwritten by the serial EEPROM, returns PCI-SIG assigned PLX Vendor ID, for each port. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX Vendor ID with another Vendor ID. HwInit Yes 10B5h 31:16 Subsystem ID Unless overwritten by the serial EEPROM, the PEX 8524 returns 8524h, the PLX-assigned Device ID. The PEX 8524 EEPROM register initialization capability is used to replace the PLX-assigned Device ID with another Device ID. HwInit Yes 8524h Bit(s) Description PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 249 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-12. 34h Capabilities Pointer Bit(s) Description 7:0 Capability Pointer Initial value = 40h, which is the Power Management Capabilities Registers offset. 31:8 Reserved Type Serial EEPROM Default RO Yes 40h 0000_00h Register 14-13. 3Ch Interrupt Type Serial EEPROM Default 7:0 Interrupt Line Interrupt Line Routing value communicates interrupt line routing information. Values in this register are programmed by system software and are system architecture-specific. The value is used by device drivers and operating systems. R/W Yes 00h 15:8 Interrupt Pin Read-Only field that identifies the legacy interrupt message(s) the device (or device function) uses. When values = 0h, 1h, 2h, 3h, and 4h, maps to legacy interrupt messages for INTA#, INTB#, INTC#, and INTD#, respectively. When 00h, indicates that the device does not use legacy interrupt message(s). Only values 00h or 01h are allowed in the PEX 8524. RO Yes 01h 31:16 Reserved 250 Description PR EL IM IN AR Y Bit(s) 0000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Power Management Capabilities Registers 14.5 Power Management Capabilities Registers The following sections detail NT Port Power Management registers. The register map is delineated in Table 14-3. Table 14-3. Power Management Capabilities Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Power Management Capabilities Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Next Pointer PM Control/Status Bridge Extensions Capability ID 40h Power Management Status and Control 44h Register 14-14. 40h Power Management Capabilities Description Type PR EL IM IN AR Y Bit(s) Serial EEPROM Default 7:0 Capability ID Default = 01h - only value allowed RO Yes 01h 15:8 Next Pointer Default 48h points to the MSI Capabilities registers RO Yes 48h 18:16 Version Default = 010b - only value allowed RO Yes 010b 19 PME Clock Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 20 Reserved 21 Device-Specific Initialization Default 0b indicates that Device-Specific Initialization is not required. RO Yes 0b AUX Current Default 000b indicates that the PEX 8524 does not contain Auxiliary Current requirements. RO Yes 000b 25 D1 Support Default 0b indicates that the PEX 8524 does not support D1 Power state. RO No 0b 26 D2 Support Default 0b indicates that the PEX 8524 does not support D2 Power state. RO No 0b PME Support Default 0000_0b indicates that the NT port does not forward PME messages. RO Yes 0000_0b 24:22 31:27 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 251 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-15. 44h Power Management Status and Control Bit(s) Description Type Serial EEPROM Default R/W Yes 00b Power Management Status and Control 1:0 Power State 00b = D0 11b = D3hot 01b and 10b are not supported 7:2 Reserved 12:9 14:13 15 PME Enable 0b = Disables PME generation RO Data Select R/W by Serial EEPROM mode only. Bits [12:9] select the Data and Data Scale registers. 0h = D0 power consumed 3h = D3hot power consumed 4h = D0 power dissipated 7h = D3hot power dissipated No 0b RO Yes 0h RO for hardware auto configuration. Not Supported. RO No 0h Data Scale R/W by Serial EEPROM mode only. There are four internal Data Scale register per port. Bits [12:9], Data Select, select the Data Scale register. RO Yes 00b PME Status 0b = PME is not being generated by the NT port RO No 0b PR EL IM IN AR Y 8 0h PM Control/Status Bridge Extensions 21:16 Reserved 0-0h 22 B2/B3 Support Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 23 Bus Power/Clock CNTRL Enable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b RO Yes 00h Data Data 31:24 R/W by serial EEPROM mode onlya. There are four internal Data registers per port. Bits [12:9], Data Select, select the Data register. a.With no serial EEPROM, reads return 0h for Data Scale and Data registers (for all Data Selects). 252 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 14.6 Message Signaled Interrupt Capabilities Registers Message Signaled Interrupt Capabilities Registers The Message Signaled Interrupt (MSI) Capabilities registers are defined in Chapter 10, "PEX 8524 Port Registers." The description in Table 14-4 delineates the register map used by the NT Port Virtual Interface. Table 14-4. Message Signaled Interrupt Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Message Signaled Interrupt Control NEXT CAPABILITY POINTER CAPABILITY ID 48h Lower Message Address[31:0] 4Ch Upper Message Address[63:32] 50h Message Data 54h PR EL IM IN AR Y Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 253 NT Port Virtual Interface Registers 14.7 PLX Technology, Inc. PCI Express Capabilities Registers The following sections detail the PEX 8524 PCI Express Capabilities registers. The Hot Plug capabilities, command, status and events are included in these registers. The register map is delineated in Table 14-5. Table 14-5. PCI Express Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEXT CAPABILITY POINTER PCI Express Capabilities CAPABILITY ID 68h Device Capabilities Device Status 6Ch Device Control 70h Link Capabilities Link Control PR EL IM IN AR Y Link Status 74h 78h Reserved 7Ch - 8Ch Register 14-16. 68h PCI Express Capabilities Bit(s) Description Type Serial EEPROM Default 7:0 Capability ID Set to 10h by default as required by the PCI Express Base 1.0a. RO Yes 10h 15:8 Next Capability Pointer 00h = PCI Express Capability is the last capability in the first 256-byte configuration space of the PEX 8524 NT Port Virtual Interface capability list The PEX 8524 NT Port Virtual Interface Extended Capabilities list starts at 100h. RO Yes 00h 19:16 Capability Version Set to 1h. RO Yes 1h 23:20 Device/Port Type PCI Express Endpoint device. RO Yes 0h Slot Implemented Not valid for PCI Express Endpoint devices. RO No 0b 29:25 Interrupt Message Number EEPROM only writes 0000_0b, because Base message and MSI messages are the same. RO Yes 0000_0b 31:30 Reserved 24 254 00b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 14-17. 6Ch Device Capabilities Type Serial EEPROM Default 2:0 Maximum Payload Size Supported 000b = NT Port Virtual Interface supports 128-byte maximum payload 001b = NT Port Virtual Interface supports 256-byte maximum payload No other values are supported. RO Yes 001b 4:3 Phantom Functions 00b = Phantom Functions not supported. RO Yes 00b Extended Tag Field Not Supported 0b = Maximum Tag field is 5 bits 1b = Maximum Tag field is 8 bits RO Yes 0b 8:6 Endpoint L0s Acceptable Latency RO Yes 000b 11:9 Endpoint L1 Acceptable Latency RO Yes 000b 12 Attention Button Present No Attention button present for NT Virtual Interface. RO No 0b 13 Attention Indicator Present No Attention indicator present for NT Virtual Interface. RO No 0b 14 Power Indicator Present No Power indicator present for NT Virtual Interface. RO No 0b 5 Description PR EL IM IN AR Y Bit(s) 17:15 Reserved 25:18 Captured Slot Power Limit Value For the NT Port Virtual Interface register, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the Captured Slot Limit Power Scale field. RO Yes 00h 27:26 Captured Slot Limit Power Scale For the NT Port Virtual Interface register, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the Captured Slot Power Limit Value field. 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 RO Yes 00b 31:28 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 000b 0h 255 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-18. 70h Device Status and Control Bit(s) Description Type Serial EEPROM Default Device Control Correctable Error Reporting Enabled 0b = Disables 1b = Enables NT Port to report correctable errors R/W Yes 0b 1 Non-Fatal Error Reporting Enabled 0b = Disables 1b = Enables NT Port to report non-fatal errors R/W Yes 0b 2 Fatal Error Reporting Enabled 0b = Disables 1b = Enables NT Port Virtual Interface to report fatal errors R/W Yes 0b 3 Unsupported-Request Reporting Enable 0b = Disables 1b = Enables NT Port Virtual Interface to report unsupported-request errors R/W Yes 0b 4 Relaxed Ordering Enabled Set to 0b as required by the PCI Express Base 1.0a. RO No 0b Maximum Payload Size The NT Port Virtual Interface power on/reset values are 000b to support a maximum payload size of 128 bytes. Software can change this field to configure the NT Port Virtual Interface to support other payload sizes, but it should not change this field to a value larger than that indicated by the Maximum Payload Size Supported for the Virtual Interface and Maximum Payload Size Supported for the Link Interface. (Requester and completer domains must possess the same max payload size.) R/W Yes 000b 8 Extended Tag Field Enabled Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 9 Phantom Functions Enable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 10 AUX Power PM Enable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 11 No Snoop Enable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b Maximum Read-Request Size Not Supported. Set to 000b for each port. RO No 000b 7:5 14:12 15 256 PR EL IM IN AR Y 0 Reserved 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 14-18. 70h Device Status and Control (Cont.) Type Serial EEPROM Default 16 Correctable Error Detected 1b = NT port detected a Correctable Error Set when the NT Port detects a Correctable Error, regardless of the Correctable Error Reporting Enabled bit state. R/W1C Yes 0b 17 Non-Fatal Error Detected 1b = NT Port Virtual Interface detected a Non-Fatal Error Set when the NT Port Virtual Interface detects a Non-Fatal Error, regardless of the Non-Fatal Error Reporting Enabled bit state. R/W1C Yes 0b 18 Fatal Error Detected 1b = NT Port Virtual Interface detected a Fatal Error. Set when the NT Port Virtual Interface detects a Fatal Error, regardless of the Fatal Error Reporting Enabled bit state. R/W1C Yes 0b 19 Unsupported Request Detected 1b = NT Port Virtual Interface detected an Unsupported-Request Set when the NT Port Virtual Interface detects an Unsupported-Request, regardless of the Unsupported-Request Reporting Enable bit state. R/W1C Yes 0b 20 AUX Power Detected Function not supported. Set to 0b for each port. RO No 0b 21 Transactions Pending Because the PEX 8524 NT Port is a bridging device, it does not track non-posted and completion for the corresponding non-posted transactions. Therefore, the NT Port Virtual Interface does not implement Transactions Pending. RO No 0b Bit(s) Description 31:22 Reserved PR EL IM IN AR Y Device Status 000h Register 14-19. 74h Link Capabilities Bit(s) Description Type Serial EEPROM Default 3:0 Maximum Link Speed Set to 1h for 2.5 Gbps. RO Yes 1h 9:4 Maximum Link Width Actual link width is set by signal ball strapping options Maximum Link Width for the PEX 8524 is x16 = 01_0000b. RO Yes Strap levels 11:10 Active-State Power Management Support 01b = NT Port supports the L0s link power state RO Yes 01b 14:12 L0s Exit Latency 101b = NT Port L0s Exit Latency is between 1 and 2 s RO Yes 101b 17:15 L1 Exit Latency 101b = NT Port L1 Exit Latency is between 16 and 32 s RO Yes 101b 23:18 Reserved 31:24 Port Number NT Port Number is selected by signal ball strapping options. Refer to STRAP_NT_UPSTRM_PORT_SEL[3:0] on page 17 for details. 0-0b HwInit PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes Set by strap levels 257 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-20. 78h Link Status and Control Bit(s) Description Type Serial EEPROM Default R/W Yes 00b Link Control 1:0 Active-State Link Power Management Control Not applicable to the NT Port Virtual Interface, because no external port connection exists. Reserved 3 Read Completion Boundary Not supported. Set to 0b. RO Yes 0b 4 Link Disable For NT port - Reserved. RO No 0b 5 Retrain Link For NT port - Reserved. RO No 0b 6 Common Clock Configuration Not applicable to the NT port Virtual Interface, because no external port connection exists. R/W Yes 0b 7 Extended SYNC Not applicable to the NT port Virtual Interface, because no external port connection exists. R/W Yes 0b 15:8 Reserved 0b PR EL IM IN AR Y 2 00h Link Status 19:16 Link Speed NT Port Virtual Interface, set to 1h for 2.5 Gbps RO Yes 1h 25:20 Negotiated Link Width Not applicable to the NT port Virtual Interface, because no external port connection exists. RO Yes 00_0001b 26 Training Error For endpoint devices - Reserved. RO No 0b 27 Link Training For endpoint devices - Reserved. RO No 0b 28 Slot Clock Configuration Because there is no external connection to the NT Port Virtual Interface, Slot Clock Configuration is always 0b, which indicates that the PEX 8524 uses an independent clock. HwInit Yes 0b 31:29 258 Reserved 0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Virtual Interface IRQ Doorbell Registers 14.8 Virtual Interface IRQ Doorbell Registers The following sections detail the PEX 8524 NT Port Virtual Interface Interrupt Request (IRQ) Doorbell registers. The register map is delineated in Table 14-6. Table 14-6. NT Port Virtual Interface Interrupt Request (IRQ) Doorbell Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Set Virtual Interface IRQ 90h Reserved Clear Virtual Interface IRQ 94h Reserved Set Virtual Interface IRQ Mask 98h Reserved Clear Virtual Interface IRQ Mask 9Ch Reserved Set Link Interface IRQ A0h Reserved Clear Link Interface IRQ A4h PR EL IM IN AR Y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Set Link Interface IRQ Mask A8h Reserved Clear Link Interface IRQ Mask ACh Register 14-21. 90h Set Virtual Interface IRQ Description Type Serial EEPROM Default 15:0 Set IRQ Controls the state of the Virtual Interface Interrupt Request bits. Reading returns the status of the bits. Writing a 1b to a bit in the register sets the corresponding interrupt request. When this register is non-zero, the corresponding bit is not masked, and interrupts are enabled, the Virtual Interface interrupt is asserted. Writing a 0b to any bit has no effect. R/W1S Yes 0000h 31:16 Reserved Bit(s) 0000h Register 14-22. 94h Clear Virtual Interface IRQ Bit(s) Description Type Serial EEPROM Default 15:0 Clear IRQ Controls the state of the Virtual Interface Interrupt Request bits. Reading returns the status of the bits. Writing a 1b to a bit in the register clears the corresponding interrupt request. When this register is non-zero, the corresponding bit is not masked, and interrupts are enabled, the Virtual Interface interrupt is asserted. Writing a 0b to any bit has no effect. R/W1C Yes 0000h 31:16 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0000h 259 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-23. 98h Set Virtual Interface IRQ Mask Bit(s) Description Type Serial EEPROM Default 15:0 Set IRQ Mask Virtual Interface interrupt IRQ Mask Set. Reading returns the state of the mask bits. 0b = Corresponding interrupt request bit is unmasked 1b = Corresponding interrupt request bit is masked/disabled Writing a 1b to a bit in the register sets the corresponding interrupt mask bit. Writing a 0b to any bit has no effect. R/W1S Yes FFFFh 31:16 Reserved 0000h Register 14-24. 9Ch Clear Virtual Interface IRQ Mask Type Serial EEPROM Default 15:0 Clear IRQ Mask Controls the state of the Virtual Interface Interrupt Request bits. Reading returns the status of the bits. 0b = Corresponding interrupt request bit is unmasked 1b = Corresponding interrupt request bit is masked/disabled Writing a 1b to a bit in the register clears the corresponding interrupt mask bit. Writing a 0b to any bit has no effect. R/W1C Yes FFFFh 31:16 Reserved PR EL IM IN AR Y Description Bit(s) 0000h Register 14-25. A0h Set Link Interface IRQ Description Type Serial EEPROM Default 15:0 Set IRQ Controls the state of the Link Interface Interrupt Request bits. Reading returns the status of the bits. Writing a 1b to a bit in the register sets the corresponding interrupt request. When this register is non-zero, the corresponding bit is not masked, and interrupts are enabled, the Link Interface interrupt is asserted. Writing a 0b to any bit has no effect. R/W1S Yes 0000h 31:16 Reserved Bit(s) 0000h Register 14-26. A4h Clear Link Interface IRQ Bit(s) Description 15:0 Clear IRQ Controls the state of the Link Interface Interrupt Request bits. Reading returns the status of the bits. Writing a 1b to a bit in the register clears the corresponding interrupt request. When this register is non-zero, the corresponding bit is not masked, and interrupts are enabled, the Link Interface interrupt is asserted. Writing a 0b to any bit has no effect. 31:16 Reserved 260 Type Serial EEPROM Default R/W1C Yes 0000h 0000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Virtual Interface IRQ Doorbell Registers Register 14-27. A8h Set Link Interface IRQ Mask Bit(s) Description Type Serial EEPROM Default 15:0 Set IRQ Mask Link Interface interrupt IRQ Mask Set. Reading returns the state of the IRQ mask. 0b = Corresponding interrupt request bit is unmasked 1b = Corresponding interrupt request bit is masked/disabled Writing a 1b to a bit in the register sets the corresponding interrupt mask bit. Writing a 0b to any bit has no effect. R/W1S Yes FFFFh 31:16 Reserved 0000h Register 14-28. ACh Clear Link Interface IRQ Mask Description PR EL IM IN AR Y Bit(s) 15:0 Clear IRQ Mask CLR_IRQ_MASK: Link Interface interrupt IRQ Mask Clear. Reading returns the state of the IRQ mask. 1b = Corresponding interrupt request bit is masked/disabled 0b = Corresponding interrupt request bit is unmasked Writing a 1b to a bit in the register clears the corresponding interrupt mask bit. Writing a 0b to any bit has no effect. 31:16 Reserved Type Serial EEPROM Default R/W1C Yes FFFFh PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0000h 261 NT Port Virtual Interface Registers 14.9 PLX Technology, Inc. NT Port Scratchpad (Mailbox) Registers The following sections detail the PEX 8524 NT Port Scratchpad (Mailbox) registers. The register map is delineated in Table 14-7. Table 14-7. PEX 8524 NT Port Scratchpad Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B0h NT Port Scratchpad_1 B4h NT Port Scratchpad_2 B8h NT Port Scratchpad_3 BCh NT Port Scratchpad_4 C0h NT Port Scratchpad_5 C4h PR EL IM IN AR Y NT Port Scratchpad_0 NT Port Scratchpad_6 C8h NT Port Scratchpad_7 CCh Register 14-29. B0h NT Port Scratchpad_0 Bit(s) 31:0 Description Scratchpad_0 32-bit Scratchpad_0 register. Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Register 14-30. B4h NT Port Scratchpad_1 Bit(s) 31:0 Description Scratchpad_1 32-bit Scratchpad_1 register. Register 14-31. B8h NT Port Scratchpad_2 Bit(s) 31:0 Description Scratchpad_2 32-bit Scratchpad_2 register. Register 14-32. BCh NT Port Scratchpad_3 Bit(s) 31:0 262 Description Scratchpad_3 32-bit Scratchpad_3 register. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 NT Port Scratchpad (Mailbox) Registers Register 14-33. C0h NT Port Scratchpad_4 Bit(s) 31:0 Description Scratchpad_4 32-bit Scratchpad_4 register. Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Register 14-34. C4h NT Port Scratchpad_5 Bit(s) 31:0 Description Scratchpad_5 32-bit Scratchpad_5 register. Bit(s) 31:0 PR EL IM IN AR Y Register 14-35. C8h NT Port Scratchpad_6 Description Scratchpad_6 32-bit Scratchpad_6 register. Register 14-36. CCh NT Port Scratchpad_7 Bit(s) 31:0 Description Scratchpad_7 32-bit Scratchpad_7 register. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 263 NT Port Virtual Interface Registers 14.10 PLX Technology, Inc. NT Port BAR Setup Registers The following sections detail the NT Port Configuration BAR Setup registers. The register map is delineated in Table 14-7. Table 14-8. PEX 8524 NT Port BAR Setup Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NT Port Virtual Interface Configuration BAR1 Setup D0h NT Port Virtual Interface BAR2 Setup D4h NT Port Virtual Interface BAR3 Setup D8h NT Port Virtual Interface BAR4 Setup DCh NT Port Virtual Interface BAR5 Setup E0h E4h - PR EL IM IN AR Y Reserved F4h Register 14-37. D0h NT Port Virtual Interface Configuration BAR1 Setup Bit(s) Description 1:0 I/O BAR1 Enable 11b = Enables Virtual Interface BAR1 as an I/O BAR. All other codes disable BAR1. 31:2 Reserved Type Serial EEPROM Default R/W Yes 11b 0-0h Register 14-38. D4h NT Port Virtual Interface BAR2 Setup Type Serial EEPROM Default RO No 0b BAR2 Type Select 00b = Selects 32-bit memory BAR. No other values are allowed. R/W Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable R/W Yes 0b Bit(s) 0 2:1 3 Description Type Reserved 11:4 Reserved 30:12 BAR2 Size Specifies the address range size requested by the BAR2. When a bit is 1b, the corresponding bit in the BAR2 register is a readable and writable by software. When a bit is 0b, the corresponding bit in the BAR2 register is a Read-Only bit that always returns 0 when read, and writes are ignored. R/W Yes 0000_0h BAR2 Enable 0b = BAR2 disabled 1b = BAR2 enabled RO No 0b 31 264 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 NT Port BAR Setup Registers Register 14-39. D8h NT Port Virtual Interface BAR3 Setup Bit(s) 0 15:1 Description Prefetchable 0b = Non-Prefetchable 1b = Prefetchable Type Serial EEPROM Default R/W Yes 0b Reserved 0-0h BAR3 LUT Page Size Selects the page size of the Lookup Table entry used for address translation. BAR3 size is determined by multiplying page size by 64 (number of LUT entries). When the BAR3 LUT Page Size Extension bit is 0b, the encodings are as follows: 0h = Disables BAR3 5h = 4 KB 6h = 8 KB 19:16 7h = 16 KB 8h = 32 KB 9h = 64 KB Bh = 256 KB PR EL IM IN AR Y 1h to 4h = Reserved Ah = 128 KB Ch = 512 KB Dh = 1 MB Eh = 2 MB R/W Yes 0h R/W Yes 0b Fh = 4 MB When the BAR3 LUT Page Size Extension bit is 1b, the encodings are as follows: 0h = 8 MB 1h = 16 MB 2h = 32 MB 3h to Fh = Reserved 20 31:21 BAR3 LUT Page Size Extension Allows selection of larger page sizes when programming Page Size[19:16]. 0b = Page sizes 4 KB through 4 MB are available in the Page Size[19:16] 1b = Page sizes 8 MB through 32 MB are available in the Page Size[19:16] Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 000h 265 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-40. DCh NT Port Virtual Interface BAR4 Setup Type Serial EEPROM Default Type Reserved RO No 0b BAR4 Type Select 00b = Selects 32-bit memory BAR 10b = Selects 64-bit memory BAR R/W Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable R/W Yes 0b Bit(s) 0 2:1 3 Description Reserved 30:12 BAR4 Size Specifies the address range size requested by the BAR4. When a bit is 1b, the corresponding bit in the BAR4 register is a readable and writable bit. When a bit is 0b, the corresponding bit in the BAR4 register is a Read-Only bit that always returns 0 when read, and writes are ignored. R/W Yes 0000_0h BAR4 Enable 0b = BAR4 and BAR5 disabled 1b = BAR4 enabled RO No 0b Description Type Serial EEPROM Default BAR5 Size Specifies the address range size requested by the BAR4/5 in 64-bit mode. When a bit is 1b, the corresponding bit in the BAR5 register is a readable and writable bit. When a bit is 0b, the corresponding bit in the BAR5 register is a Read-Only bit that always returns 0 when reads and writes are ignored. Reserved if BAR4/5 is configured as a 32-bit BAR. R/W Yes 0-0h BAR5 Enable 0b = BAR5 disabled 1b = BAR5 enabled RO No 0b 31 00h PR EL IM IN AR Y 11:4 Register 14-41. E0h NT Port Virtual Interface BAR5 Setup Bit(s) 30:0 31 266 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 14.11 Cursor Mechanism Control Registers Cursor Mechanism Control Registers The following section details the NT Port Cursor Mechanism Control registers. The register map for the Virtual and Link Interfaces is delineated in Table 14-7. Table 14-9. NT Port Cursor Mechanism Control Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Configuration Address Window F8h Configuration Data Window FCh Register 14-42. F8h Configuration Address Window Description PR EL IM IN AR Y Bit(s) 15:0 Reserved 25:16 Offset Register Offset. 30:26 Reserved 31 Interface Select 0b = Access to NTPort Virtual Interface Type 0 Configuration Space register 1b = Access to NTPort Link Interface Type 0 Configuration Space register. Type Serial EEPROM Default 0000h R/W Yes 000h 0h R/W Yes 0b Type Serial EEPROM Default R/W Yes 0-0h Register 14-43. FCh Configuration Data Window Bit(s) 31:0 Description Data Window Software selects a register by writing into the NT Port Configuration Address Window, then reads or writes to that register using this register. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 267 NT Port Virtual Interface Registers 14.12 PLX Technology, Inc. Device Serial Number Extended Capabilities Registers The NT Port Device Serial Number Extended Capabilities registers are the same as the PEX 8524 Transparent port registers as defined in Chapter 10, "PEX 8524 Port Registers," on page 127. The register map is delineated in Table 14-10 and applies to Virtual and Link Interfaces. Table 14-10. PEX 8524 Device Serial Number Extended Capabilities Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NEXT CAPABILITY OFFSET CAPABILIT Y VERSION EXTENDED CAPABILITY ID 100h Serial Number (Low) 104h Serial Number (High) 108h Device Power-Budgeting Extended Capabilities Registers PR EL IM IN AR Y 14.13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The NT Port Device Power Budgeting Extended Capabilities registers are the same as the PEX 8524 Transparent port registers as defined in Chapter 10, "PEX 8524 Port Registers," on page 128. The register map is delineated in Table 14-11 and applies to Virtual and Link Interfaces. Table 14-11. PEX 8524 Device Power Budgeting Extended Capabilities Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NEXT CAPABILITY OFFSET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPABILIT Y VERSION Reserved EXTENDED CAPABILITY ID DATA SELECT Power Data Register Reserved 268 Power Budget Capability 138h 13Ch 140h 144h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 14.14 Virtual Channel Extended Capabilities Registers Virtual Channel Extended Capabilities Registers The NT Port Virtual Channel Extended Capabilities registers are the same as the PEX 8524 Transparent port registers as defined in Chapter 10, "PEX 8524 Port Registers," on page 130. The register map is delineated in Table 14-12 and applies to Virtual and Link Interfaces. Table 14-12. PEX 8524 Virtual Channel Extended Capabilities Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPABILIT Y VERSION NEXT CAPABILITY OFFSET EXTENDED CAPABILITY ID 148h Port VC Capability 1 14Ch Port VC Capability 2 150h Port VC Status Port VC Control 158h PR EL IM IN AR Y VC0 Resource Capability VC0 Resource Control VC0 Resource Status 154h Reserved 15Ch 160h VC1 Resource Capability 164h VC1 Resource Control 168h VC1 Resource Status Reserved Reserved Virtual Channel Arbitration Table (All Ports) 16Ch 170h ... 1B4h 1B8h ... 1C4h The NT Port PLX vendor unique registers start on page 270 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 269 NT Port Virtual Interface Registers 14.15 PLX Technology, Inc. PLX-Specific Registers The PEX 8524 PLX-Specific registers are defined in Chapter 10, "PEX 8524 Port Registers," starting on page 136. The NT Port Virtual Interface registers are included in the Transparent register definitions in Chapter 10, except as delineated in Table 14-13. Table 14-13. NT Port Virtual Interface Register Map for PLX-Specific Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 "ECC Error Check Disable" on page 137 Reserved for Factory Testing 1C8h 1CCh - 1D8h "Debug Control" on page 142 PR EL IM IN AR Y Reserved Chapter 10, "PEX 8524 Port Registers" 14.16 1DCh 1E0h - 1E4h Reserved 1E8h Reserved 1ECh Reserved 1F0h 1F4h - C38h PEX 8524 Non-Transparent Bridging-Specific Registers The following registers are implemented to support the PEX 8524 Non-Transparent Bridging function. The register descriptions are organized into the following sections: * NT Port Memory Address Translation Registers - BAR Limit Registers * Lookup Table-Based Address Translation Registers * NT Port Virtual Interface Base Address Registers (BARs) and BAR Setup Registers * NT Port Virtual Interface Send LUT Entry Registers NT station contains the main copy of these registers and the transparent station contains a shadow copy of these registers. These registers are accessed by Memory-Mapped access to Port 0, Port 8, or NT port. 270 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 14.16.1 NT Port Memory Address Translation Registers - BAR Limit Registers NT Port Memory Address Translation Registers - BAR Limit Registers The NT station contains the main copy of these registers and the transparency station contains the shadow copies of these registers. Program only the main copy. The shadow register is automatically updated. The reverse is not true. Table 14-14. NT Port Memory Address Translation Registers and BAR Limit Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3Ch Reserved C40h Memory BAR_4 Address Translation[31:0] C44h Memory BAR_5 Address Translation[63:32] C48h PR EL IM IN AR Y Memory BAR_2 Address Translation[31:0] Memory BAR_2 Limit[31:0] C4Ch Reserved C50h Memory BAR_4 Limit[31:0] C54h Memory BAR_5 Limit[63:32] C58h Register 14-44. C3Ch Memory BAR_2 Address Translation[31:0] Bit(s) Description 11:0 Reserved 31:12 BAR_2 Base Translation[31:12] Translation base address if BAR_2 is enabled. Type Serial EEPROM Default 0-0h R/W Yes 0-0h Type Serial EEPROM Default Register 14-45. C44h Memory BAR_4 Address Translation[31:0] Bit(s) Description 11:0 Reserved 0-0h 31:12 BAR_4 Base Translation[31:12] Translation base address if BAR_4 is enabled. R/W Yes 0-0h Type Serial EEPROM Default RO Yes 0-0h Register 14-46. C48h Memory BAR_5 Address Translation[63:32] Bit(s) 31:0 Description BAR_5 Base Translation[63:32] Translation base address if BAR_5 is enabled. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 271 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-47. C4Ch Memory BAR_2 Limit[31:0] Bit(s) Description 11:0 Reserved 31:12 BAR_2 Limit[31:0] Contains the upper limit of the memory window defined in the BAR_2 Setup register. If the limit is greater than the size of the window, it is ignored. Type Serial EEPROM Default 0-0h R/W Yes 000h Type Serial EEPROM Default Register 14-48. C54h Memory BAR_4 Limit[31:0] Bit(s) Description Reserved 0-0h 31:12 BAR_4 Limit[31:0] Contains the upper limit of the memory window defined in the BAR_4 Setup register. If the limit is greater than the size of the window, it is ignored. PR EL IM IN AR Y 11:0 R/W Yes 0-0h Type Serial EEPROM Default RO Yes 0-0h Register 14-49. C58h Memory BAR_5 Limit[63:32] Bit(s) 31:0 272 Description BAR_5 Limit[63:32] Contains the upper limit of the memory window defined in the BAR_5 Setup register. If the limit is greater than the size of the window, it is ignored. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 14.16.2 Lookup Table-Based Address Translation Registers Lookup Table-Based Address Translation Registers There are 64 Base-Translation Lookup Table (LUT) Entry registers to support the LUT-based address translation. The Non-Transparent Station contains the main copy of the registers, and the Transparent Station contains the shadow copy of these registers. These registers are accessed using Port 0, Port 8 and NT Port Virtual Interface Memory-Mapped or Cursor mechanism. Table 14-15 lists the registers and Address locations. The register description that follows defines the bit definitions that apply to all 64 registers. The NT station contains the main copy of these registers and the transparency station contains the shadow copies of these registers. Program only the main copy. The shadow register is automatically updated. The reverse is not true. Table 14-15. Base-Translation Lookup Table Entry_n Register Location Lookup Table Entry ADDR Location Lookup Table Entry ADDR Location C5Ch 0 C60h 1 C64h C6Ch 4 C70h 5 Lookup Table Entry ADDR Location Lookup Table Entry 2 C68h 3 C74h 6 C78h 7 PR EL IM IN AR Y ADDR Location C7Ch 8 C80h 9 C84h 10 C88h 11 C8Ch 12 C90h 13 C94h 14 C98h 15 C9Ch 17 CA0h 17 CA4h 18 CA8h 19 CACh 20 CB0h 21 CB4h 22 CB8h 23 CBCh 24 CC0h 25 CC4h 26 CC8h 27 CCCh 28 CD0h 29 CD4h 30 CD8h 31 CDCh 32 CE0h 33 CE4h 34 CE8h 35 CECh 36 CF0h 37 CF4h 38 CF8h 39 CFCh 40 D00h 41 D04h 42 D08h 43 D0Ch 44 D10h 45 D14h 46 D18h 47 D1Ch 48 D20h 49 D24h 50 D28h 51 D2Ch 52 D30h 53 D34h 54 D38h 55 D3Ch 56 D40h 57 D44h 58 D48h 59 D4Ch 60 D50h 61 D54h 62 D58h 63 Register 14-50. C5Ch - D58h Base-Translation Lookup Table Entry_n (where n = 0 through 63) Bit(s) 0 2:1 Description Entry Status 0b = Invalid 1b = Valid Type Serial EEPROM Default R/WS Yes 0b Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 00b 273 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-50. C5Ch - D58h Base-Translation Lookup Table Entry_n (where n = 0 through 63) Bit(s) 3 Description Prefetchable 0b = Non-Prefetchable 1b = Prefetchable Reserved 31:12 Base Translation Base Translation address value. Serial EEPROM Default R/W Yes 0b 00h R/W Yes 0-0h PR EL IM IN AR Y 11:4 Type 274 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 14.16.3 NT Port Virtual Interface Base Address Registers (BARs) and BAR Setup Registers NT Port Virtual Interface Base Address Registers (BARs) and BAR Setup Registers The registers in this section are shadow copies, and only valid for Port 0 and Port 8. If corresponding Port 0 or Port 8 is an NT port, the register is in Virtual Interface Configuration space. Modifying these registers is not recommended. Table 14-16. NT Port Virtual Interface Base Address Registers (BARs) and BAR Setup Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NT Port Link Interface Shadow Copy Registers D5Ch - D64h D68h BAR_1 D6Ch BAR_2 D70h BAR_3 D74h BAR_4 D78h BAR_5 D7Ch BAR_1 Setup D80h BAR_2 Setup D84h BAR_3 Setup D88h BAR_4 Setup D8Ch BAR_5 Setup D90h PR EL IM IN AR Y BAR_0 = Reserved Register 14-51. D5Ch NT Link Interface VC0 (Shadow Copy) Type Serial EEPROM Default TCVC_Map Always mapped to Virtual Channel 0. RO Yes 1b 7:1 TCVC_Map Mapped to Virtual Channel 0 by default. Software can change this field during enumeration or when quiescing the traffic to the traffic class. R/W Yes 7Fh 23:8 Reserved Bit(s) 0 24 30:25 31 Description VC_ID Virtual channel identification number. Reserved VC_Enable Virtual Channel 0 enable. RsvdP RO RsvdP Yes RsvdP RO PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0b RsvdP Yes 1b 275 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-52. D60h NT Link Interface VC1 (Shadow Copy) Bit(s) 0 7:1 23:8 Reserved 31 Default RsvdP No RsvdP R/W Yes 00h RsvdP Yes RsvdP R/W Yes 1b RsvdP Yes RsvdP R/W Yes 0b Type Serial EEPROM Default RsvdP No RsvdP RO Yes 0h RsvdP No RsvdP VC_ID Virtual channel identification number. Reserved VC_Enable Virtual Channel 1 enable. PR EL IM IN AR Y 30:25 Serial EEPROM Reserved TCVC_Map Mapped to Virtual Channel 1 by default. Software can change this field during enumeration or when quiescing the traffic to the traffic class. 24 Type Description Register 14-53. D64h NT Link Interface VC Capability 1 (Shadow Copy) Bit(s) Description 3:0 Reserved 6:4 LowPriVC_Count Indicates the number of Virtual Channels mapped to the low-priority group. 31:7 Reserved Register 14-54. D6Ch BAR_1 (14h Shadow Copy) Description Type Serial EEPROM Default I/O Space Indicator 256 bytes of I/O space base address if D0h[1:0] = 11b; otherwise, reserved. RO Yes 1b Bit(s) 0 7:1 Reserved 31:8 I/O Base Address Base Address of 256 bytes in I/O space when D0h[1:0] = 11b; otherwise, reserved. 276 R/W 0h Yes 0000_00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 NT Port Virtual Interface Base Address Registers (BARs) and BAR Setup Registers Register 14-55. D70h BAR_2 (18h Shadow Copy) Type Serial EEPROM Default Memory Space Indicator 0b = Memory BAR - only value supported RO Yes 0b Memory Map Type 00b = BAR is mapped anywhere in 32-bit Memory space 01b, 10b, 11b = Reserved RO Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable RO Yes 0b Bit(s) 0 2:1 3 Description Reserved 00h 31:12 Base Address 2 Contains the software-assigned Memory Space Base Address: * Enabled and sized by BAR2 Setup register * Used for Memory transactions crossing the NT port * Minimum address range requested is 4 KB * Uses direct address translation PR EL IM IN AR Y 11:4 R/W Yes 0000_0h Type Serial EEPROM Default Memory Space Indicator 0b = Memory BAR - only value supported RO Yes 0b Memory Map Type 00b = BAR is mapped anywhere in 32-bit Memory Addressing space 01b, 10b, 11b = Not allowed RO Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable RO Yes 0b Register 14-56. D74h BAR_3 (1Ch Shadow Copy) Bit(s) 0 2:1 3 Description 17:4 Reserved 31:18 Base Address 3 Contains the software-assigned Memory Space Base Address: * Enabled and sized by BAR3 Setup register * No Limit register * Used for Memory transactions crossing the NT port * Minimum address range requested is 256 KB * Uses LUT address translation 000h R/W PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 0000h 277 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-57. D78h BAR_4 (20h Shadow Copy) Type Serial EEPROM Default Memory Space Indicator 0b = Memory BAR - only value supported RO Yes 0b Memory Map Type 00b = Mappable anywhere in 32-bit Memory space 10b = Mappable anywhere in 64-bit Memory space 01b, 11b = Reserved RO Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable RO Yes 0b Bit(s) 0 2:1 3 Description Reserved 00h 31:12 Base Address 4 Contains the software-assigned Memory Space Base Address: * Enabled and sized by BAR4 Setup register * Used for Memory transactions crossing the NT port * Minimum address range requested is 4 KB * Uses direct address translation PR EL IM IN AR Y 11:4 R/W Yes 0000_0h Type Serial EEPROM Default R/W Yes 0-0h Register 14-58. D7Ch BAR_5 (24h Shadow Copy) Bit(s) 31:0 278 Description Base Address 5 NT Port Virtual Interface upper 32-bit address if BAR4/5 is implemented as a 64-bit BAR; otherwise, reserved. R/W, based on BAR5 setup register. The BAR4/5 group uses direct address translation. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 NT Port Virtual Interface Base Address Registers (BARs) and BAR Setup Registers Register 14-59. D80h BAR_1 Setup (D0h Shadow Copy) Bit(s) Description 1:0 I/O BAR1 Enable 11b = Enables Virtual Interface BAR1 as an I/O BAR All other codes disable BAR1. 31:2 Reserved Type Serial EEPROM Default R/W Yes 11b 0-0h Register 14-60. D84h BAR_2 Setup (D4h Shadow Copy) Type Serial EEPROM Default RO No 0b BAR2 Type Select 00b = Selects 32-bit memory BAR No other values are allowed. R/W Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable R/W Yes 0b Bit(s) 2:1 3 Type Reserved PR EL IM IN AR Y 0 Description 11:4 Reserved 30:12 Size Specifies address range size requested by the BAR2. When 0b, the corresponding bit in the BAR2 register is a Read-Only bit that always returns 0 when read, and writes are ignored. When 1b, the corresponding bit in the BAR2 register is a readable and writable by software. R/W Yes 0000_0h BAR2 Enable 0b = BAR2 disabled 1b = BAR2 enabled RO No 0b 31 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 279 NT Port Virtual Interface Registers PLX Technology, Inc. Register 14-61. D88h BAR_3 Setup (D8h Shadow Copy) Bit(s) 0 15:1 Description Prefetchable 0b = Non-Prefetchable 1b = Prefetchable Type Serial EEPROM Default R/W Yes 0b Reserved 0-0h LUT Page Size Selects the page size of the Lookup Table entry used for address translation. BAR3 size is determined by multiplying page size by 64 (number of LUT entries). When the BAR3 LUT Page Size Extension bit is 0b, the encodings are as follows: 0h = Disables BAR3 5h = 4 KB 6h = 8 KB 19:16 7h = 16 KB 8h = 32 KB 9h = 64 KB Bh = 256 KB PR EL IM IN AR Y 1h to 4h = Reserved Ah = 128 KB Ch = 512 KB Dh = 1 MB Eh = 2 MB R/W Yes 0h R/W Yes 0b Fh = 4 MB When the BAR3 LUT Page Size Extension bit is 1b, the encodings are as follows: 0h = 8 MB 1h = 16 MB 2h = 32 MB 3h to Fh = Reserved 20 31:21 280 LUT Page Size Extension Allows selection of larger page sizes when programming Page Size[19:16]. 0b = Page sizes 4 KB through 4 MB are available in Page Size[19:16] 1b = Page sizes 8 through 32 MB are available in Page Size[19:16] Reserved 000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 NT Port Virtual Interface Base Address Registers (BARs) and BAR Setup Registers Register 14-62. D8Ch BAR_4 Setup (DCh Shadow Copy) Type Serial EEPROM Default Type Reserved RO No 0b BAR4 Type Select 00b = Selects 32-bit memory BAR 10b = Selects 64-bit memory BAR R/W Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable R/W Yes 0b Bit(s) 0 2:1 3 Description Reserved 30:12 Size Specifies the address range size requested by the BAR4. When a bit is 0b, the corresponding bit in the BAR4 register is a Read-Only bit that always returns 0 when read, and writes are ignored. When a bit is 1b, the corresponding bit in the BAR4 register is a readable and writable bit. R/W Yes 0000_0h BAR4 Enable When D8Ch[2:1] = 00b, enables BAR4; otherwise, belongs to the Size field (above). 0b = BAR4 and BAR5 disabled 1b = BAR4 enabled RO No 0b Type Serial EEPROM Default Size Specifies the address range size requested by the BAR4/5 in 64-bit mode. When a bit is 0b, the corresponding bit in the BAR5 register is a Read-Only bit that always returns 0 when reads and writes are ignored. When a bit is 1b, the corresponding bit in the BAR5 register is a readable and writable bit. Reserved if BAR4/5 is configured as a 32-bit BAR. R/W Yes 0-0h BAR5 Enable 0b = BAR5 disabled 1b = BAR5 enabled RO No 0b 31 00h PR EL IM IN AR Y 11:4 Register 14-63. D90h BAR_5 Setup (E0h Shadow Copy) Bit(s) 30:0 31 Description PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 281 NT Port Virtual Interface Registers 14.16.4 PLX Technology, Inc. NT Port Virtual Interface Send LUT Entry Registers The NT Port Virtual Interface Send (Requester ID Translation) Lookup Table (LUT) Entry registers are delineated in the following tables. Table 14-17 lists the registers and Address location. NT Port uses this register for Requester ID translation when it forwards: * Memory requests from NT Port Virtual Interface to the NT Port Link Interface, or * Completion TLP from NT Port Link Interface to the NT Port Virtual Interface The register descriptions that follow the table define the bit definitions that apply to the two register types. Table 14-17. NT Port Virtual Interface Send LUT Entry Register Location ADDR Location D94h D98h D9Ch DA0h 282 PR EL IM IN AR Y The NT station contains the main copy of these registers and the Transparency station contains the shadow copies of these registers. Program only the main copy. The shadow register is automatically updated. The reverse is not true. Lookup Table Entry ADDR Location Lookup Table Entry 0 DA4h 4 1 DA8h 5 2 DACh 6 3 DB0h 7 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 NT Port Virtual Interface Send LUT Entry Registers Register 14-64. D94h - DB0h Virtual Interface Send Lookup Table Entry_n (where n = 0 through 7) Bit(s) Description Type Serial EEPROM Default 2:0 Function Number LUT Entry_n Requester Function Number. R/W Yes 000b 7:3 Device Number LUT Entry_n Requester Device Number. R/W Yes 0000_0b 15:8 Bus Number LUT Entry_n Requester Bus Number. R/W Yes 0h 30:16 Reserved LUT Entry_n Enable 0b = Disables 1b = Enables R/W PR EL IM IN AR Y 31 0-0h Yes 0b Register 14-65. DF4h NT Port Link Interface Capture Bus and Device Number Bit(s) Description Type Serial EEPROM Default 7:0 Captured Bus Number Captured Bus Number. R/W Yes 00h 12:8 Captured Device Number Captured Device Number. R/W Yes 0000_0b 31:13 Reserved 0-0h Register 14-66. DF8h NT Port Virtual Interface Control (04h[2:0] Shadow Copy) Bit(s) Description Type Serial EEPROM Default 0 I/O Enable 0b = Disables 1b = Enables R/W Yes 0b 1 Memory Enable 0b = Disables 1b = Enables R/W Yes 0b 2 Master Enable 0b = Disables 1b = Enables R/W Yes 0b 31:3 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0-0h 283 NT Port Virtual Interface Registers 14.17 PLX Technology, Inc. Advanced Error Reporting Capability Registers The Advanced Error Reporting Capability registers for the NT Port Virtual Interface are equivalent to those defined in Chapter 10, "PEX 8524 Port Registers" starting on page 206. The registers are duplicated for the NT Port Virtual Interface, and the register map is delineated in Table 14-8. Table 14-18. PLX-Specific Error Check/Debug and Physical Layer Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FB4h Uncorrectable Error Status FB8h Uncorrectable Error Mask FBCh Uncorrectable Error Severity FC0h Correctable Error Status FC4h Correctable Error Mask FC8h Advanced Error Capabilities and Control FCCh Header Log_0 FD0h Header Log_1 FD4h Header Log_2 FD8h Header Log_3 FDCh PR EL IM IN AR Y Advanced Error Reporting Enhanced Capability Header Reserved 284 FE0h - FFCh PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 15 15.1 NT Port Link Interface Registers Introduction This chapter defines the PEX 8524 Non-Transparent (NT) Port Link Interface (interface) registers. The NT Port includes two sets of configuration-capability, control, and status registers to support the Virtual and Link Interfaces. The NT Port Link Interface register mapping is delineated in Table 15-1. The NT Port Virtual Interface registers are defined in Chapter 14, "NT Port Virtual Interface Registers." For additional information regarding register names and descriptions, refer to the following specifications: * PCI r2.3 * PCI Express Base 1.0a * PCI Power Mgmt. r1.1 * PCI ExpressCard 1.0a * PCI HotPlug 1.1 * PCI Standard Hot Plug r1.0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 285 NT Port Link Interface Registers PLX Technology, Inc. Table 15-1. NT Port Link Interface Type 0 Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h Configuration Header Registers ... Capability Pointer (40h) 34h ... 3Ch Next Capability Ptr (48h) Capability ID (01h) Power Management Capabilities PR EL IM IN AR Y Next Capability Ptr (68h) 40h 44h Capability ID (05h) 48h ... Message Signaled Interrupt Capabilities Registers Next Capability Ptr (00h) 54h Capability ID (10h) 68h ... PCI Express Capabilities Registers Reserved 80h 84h - 90h NT Port Registers Next Capability Offset (FB4h) 1h 8Ch ... FFh Extended Capability ID (0003h) 100h 104h Device Serial Number Extended Capabilities Registers Reserved Next Capability Offset (148h) 1h Extended Capability ID (0004h) 108h 10Ch - 134h 138h ... Device Power Budgeting Extended Capabilities Registers 144h Next Capability Offset (000h) 1h Extended Capability ID (0002h) 148h ... Virtual Channel Extended Capabilities Registers 1C4h PLX-Specific Registers and "Unused Registers" 1C8h ... FB0h Next Capability Offset (138h) 1h Extended Capability ID (0001h) FB4h FB8h Advanced Error Reporting Capability Registers ... FFCh 286 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 15.2 Register Access Register Access The PEX 8524 supports four methods for accessing its NT Port registers: * PCI Express Base 1.0a Configuration Mechanism * PLX-Specific Memory-Mapped Configuration Space Access Mechanism * PLX-Specific I/O-Mapped Configuration Space Access Mechanism * PLX-Specific Cursor Mechanism 15.2.1 PCI Express Base 1.0a Configuration Mechanism PCI Express extends Configuration space to 4096 bytes per device function, as compared to 256 bytes allowed by the PCI r2.3. PCI Express Configuration Space Access mechanism is divided into: * PCI r2.3-Compatible Configuration Mechanism PR EL IM IN AR Y * PCI Express Enhanced Configuration Mechanism The PCI r2.3-Compatible Configuration Mechanism provides standard access to the first 256 bytes (the bytes at offsets 00h through FFh) of the NT Port Link Interface Configuration Register space. The PCI Express Enhanced Configuration Mechanism provides access to the remaining 4 KB (offsets 100h through FFFh). The PEX 8524 decodes Type 0 Configuration transactions received on its NT Port Link Interface. The PEX 8524 reads or writes to the NT Port Link Interface register, as specified in the original Type 0 Configuration access. 15.2.1.1 PCI r2.3-Compatible Configuration Mechanism The PCI r2.3-Compatible Configuration space consists of the first 256 bytes of the NT Port Link Interface Configuration space (Figure ). The PCI r2.3-compatible region is accessed using the Type 0 mechanism defined in the PCI r2.3, PCI Express Enhanced Configuration Mechanism, PLX-Specific Memory-Mapped Configuration Space Access Mechanism, or PLX-Specific I/O-Mapped Configuration access. Accesses made using either access mechanism are equivalent. Because the PCI r2.3-Compatible Configuration mechanism is limited to the first 256 bytes of the NT Port Link Interface Configuration Register space, one of the following must be used to access beyond byte FFh: * PCI Express Enhanced Configuration Mechanism * PLX-Specific Memory-Mapped Configuration Space Access Mechanism * PLX-Specific Cursor Mechanism The PCI r2.3-Compatible Configuration Access mechanism uses the same request format as the Extended PCI Express Mechanism. For PCI-compatible Configuration requests, the Extended Register Address field must be all zeros (0). Do not use this mechanism to access the PEX 8524 Device-Specific Configuration register. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 287 NT Port Link Interface Registers 15.2.1.2 PLX Technology, Inc. PCI Express Enhanced Configuration Mechanism The Extended PCI Express configuration mechanism uses a flat, root complex Memory-Mapped address space to access Device Configuration registers. In this case, the memory address determines the configuration register accessed and memory data returns the addressed register contents. The root complex converts the Memory transaction into a Configuration transaction before transmitting this access to the downstream devices. The mechanism is used to access the NT Port Link Interface Type 0 registers: * Configuration Header Registers * Power Management Capability Registers * Message Signaled Interrupt Capabilities Registers * PCI Express Capabilities Registers * Device Serial Number Extended Capabilities Registers * Device Power Budgeting Extended Capabilities Registers PR EL IM IN AR Y * Virtual Channel Extended Capabilities Registers * Advanced Error Reporting Capability Registers 288 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 15.2.2 PLX-Specific Memory-Mapped Configuration Space Access Mechanism PLX-Specific Memory-Mapped Configuration Space Access Mechanism The PLX-Specific Memory-Mapped Configuration Space Access mechanism provides a method to access the PEX 8524 port configuration registers in a single memory map, as delineated in Figure . These Port registers are contained within a 4-KB range. When the NT Port is enabled at Fundamental reset, the NT Port Virtual and Link Interface Configuration registers are used in place of the Type 1 Configuration registers for that port. Registers of each port are contained within a 4-KB range. PR EL IM IN AR Y To utilize the PLX-Specific Memory-Mapped Configuration Space Access mechanism, use the PCI r2.3-Compatible Configuration mechanism to program the PEX 8524 NT Port Link Interface Base Address 0 register. After the NT Port Link Interface Memory-Mapped Base Address register is set, the NT Port registers are accessed with Memory reads from and writes to Configuration Space registers. The NT Port registers are accessed with Memory reads from and writes to the 4-KB range, starting at offset 64 KB for the Virtual Interface registers and offset 68 KB for Link Interface registers. Figure 15-1. PEX 8524 Memory Map PEX 8524 Port 0 0K 4K Port 1 8K 12K Reserved 16K 32K Port 8 36K Port 9 Port 10 Port 11 40K 44K 48K Reserved 64K NT-Port Virtual Interface NT-Port Link Interface 68K 72K Reserved 128K PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 289 NT Port Link Interface Registers 15.2.3 PLX Technology, Inc. PLX-Specific I/O-Mapped Configuration Space Access Mechanism The first 256 bytes of NT Port Link Interface Configuration Space registers are directly accessed by an I/O transaction. The NT Port Link Interface BAR1 register is used for I/O-Mapped access. Extended Configuration Space registers are accessed by using the Cursor mechanism in I/O space. Figure 15-2. I/O-Mapped Configuration Space View 32 Bits 0FCh CFGADDR CFGDATA 31 100h PR EL IM IN AR Y 0F8h 7 0F4h BAR1 (IO BAR) PCI-Compatible Configuration Space 0 000h Extended Configuration Space FFCh 15.2.4 PLX-Specific Cursor Mechanism In Figure 15-2, the software uses the CFGADDR register to select the NT Port Virtual Interface or NT Port Link Interface Configuration Space registers, including the Extended Configuration Space register. Software uses CFGDATA access to read or write to the selected configuration space registers. (Refer to Section 15.11, "Cursor Mechanism Control Registers," for the register description.) 15.3 Register Descriptions The following sections detail the PEX 8524 NT Port registers, including: * Bit/field names * Description of the register's function in the PEX 8524 NT Port Virtual and Link Interfaces * Type * Initial power-on/reset value * Whether the power-on/reset value is modified by way of the PEX 8524 serial EEPROM initialization feature * Specification references 290 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 15.4 Configuration Header Registers Configuration Header Registers Table 15-2. Type 0 Configuration Space Header Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Device ID Vendor ID 00h Status Bits Command Bits 04h Class Code Header Type Master Latency Timer 08h Cache Line Size 0Ch Base Address 0 10h Base Address 1 14h Base Address 2 18h PR EL IM IN AR Y BIST Revision ID Base Address 3 1Ch Base Address 4 20h Base Address 5 24h Cardbus CIS Pointer 28h Subsystem Device ID Subsystem Vendor ID 2Ch Expansion ROM Base Address Reserved 30h Capability Pointer 34h Reserved Reserved Interrupt Pin 38h Interrupt Line 3Ch Register 15-1. 00h Product Identification Type Serial EEPROM Default 15:0 Vendor ID Unless overwritten by the serial EEPROM, returns the PLX PCI-SIG assigned Vendor ID, for each port. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX Vendor ID with another Vendor ID. HwInit Yes 10B5h 31:16 Device ID Unless overwritten by the serial EEPROM, the PEX 8524 returns 8524h, the PLX-assigned Device ID. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX-assigned Device ID with another Device ID. HwInit Yes 8524h Bit(s) Description PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 291 NT Port Link Interface Registers PLX Technology, Inc. Register 15-2. 04h Status/Command Bit(s) Description Type Serial EEPROM Default Command Bits I/O Access Enable 0b = PEX 8524 ignores I/O request received on the NT Port Link Interface 1b = PEX 8524 accepts I/O requests received on the NT Port Link Interface R/W Yes 0b 1 Memory Access Enable 0b = PEX 8524 ignores Memory requests received on the NT Port Link Interface 1b = PEX 8524 accepts Memory requests received on the NT Port Link Interface R/W Yes 0b 2 Bus Master Enable Controls PEX 8524 Memory request forwarding in the upstream direction. Does not affect message and completion forwarding in the upstream direction. 0b = PEX 8524 handle Memory requests received on the NT Port Virtual Interface as Unsupported Requests (UR). For Non-Posted requests, the PEX 8524 returns a Completion with UR completion status. 1b = PEX 8524 forward Memory requests from NT Port Virtual Interface to the Link Interface. R/W Yes 0b 3 Special Cycle Enable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 4 Memory Write and Invalidate Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 5 VGA Palette Snoop Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 6 Parity Error Response Enable Controls the Master Data Parity Error. R/W Yes 0b 7 IDSEL Stepping/Write-Cycle Control Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 8 SERR# Enable Controls the Signaled System Error bit. When 1b, enables reporting of non-fatal and fatal errors detected by the NT Port Link Interface to the root complex. R/W Yes 0b 9 Fast Back-to-Back Transaction Enabled Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 10 Interrupt Disable 0b = Corresponding NT Port Link Interface is enabled to generate INTx Interrupt messages 1b = Corresponding NT Port Link Interface is prevented from generating INTx Interrupt messages R/W Yes 0b 15:11 292 PR EL IM IN AR Y 0 Reserved 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers Register 15-2. 04h Status/Command (Cont.) Bit(s) Description Type Serial EEPROM Default Status Bits 18:16 Reserved 000b 19 Interrupt Status 0b = No INTx Interrupt pending 1b = INTx Interrupt pending internally to the corresponding NT Port Interface RO Yes 0b 20 Capabilities List Set to 1b as required by the PCI Express Base 1.0a. RO Yes 1b 21 66-MHz Capable Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 22 Reserved 23 Fast Back-to-Back Transaction Enabled Set to 0b as required by the PCI Express Base 1.0a. 24 Master Data Parity Error If the Parity Error Response Enable bit = 1b, the corresponding PEX 8524 port sets this bit to 1b when the following occurs: * NT Port forwards the poisoned TLP write request from Virtual Interface to the Link Interface, or * NT Port receives a Completion marked poisoned on its Link Interface If the Parity Error Response Enable bit = 0b, the PEX 8524 never sets this bit. PR EL IM IN AR Y 26:25 0b DEVSEL Timing Not supported. Always set to 00b. RO No 0b R/W1C Yes 0b RO No 00b R/W1C Yes 0b 27 Target Abort Signaled When a memory-mapped access payload length is greater than one DW, the NT Port Link Interface sets this bit to 1b. [Also, this bit is set to 1b, when the NT Port forwards a Completion with Completer Abort (CA) status from the Virtual Interface to the Link Interface.] Note: This does not set the advanced error reporting register. 28 Target Abort Received Set to 0b. Never set to 1b. RO No 0b 29 Master Abort Received Set to 0b. Never set to 1b. RO No 0b 30 Signaled System Error If the SERR# Enable bit = 1b, the corresponding NT Port Link Interface sets this bit to 1b when it transmits an ERR_FATAL or ERR_NONFATAL message to its upstream device. R/W1C Yes 0b 31 Detected Parity Error NT Port Link Interface sets this bit to 1b when it receives a Poisoned TLP, regardless of the Parity Error Response Enable bit state. R/W1C Yes 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 293 NT Port Link Interface Registers PLX Technology, Inc. Register 15-3. 08h Class Code and Revision ID Bit(s) 7:0 Description Revision ID Unless overwritten by the serial EEPROM, returns BAh, PLX-assigned Revision ID for this version of the PEX 8524. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX Revision ID with another Revision ID. Type Serial EEPROM Default RO Yes BAh Class Code 31:8 15:8 Programming Interface Set to 00h as required by the PCI r2.3 for other bridge devices. 23:16 Sub-Class Code Other Bridge Devices. 31:24 Base Class Code Bridge Devices. 068000h 00h PR EL IM IN AR Y RO Yes 80h 06h Register 15-4. 0Ch Miscellaneous Bit(s) Description Type Serial EEPROM Default 7:0 Cache Line Size Implemented as a read-write field for legacy compatibility purposes and does not impact PEX 8524 functionality. R/W Yes 00h 15:8 Master Latency Timer Set to 00h as required by the PCI Express Base 1.0a. RO No 00h 22:16 Configuration Layout Type Type 0 Configuration Header for NT Port. RO Yes 00h 23 Function Type 0b = PEX 8524 is a single-function device RO Yes 0b BIST Not supported. RO No 00h 31:24 294 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers 1 Register 15-5. 10h Base Address 0 (for NT Port Link Interface) Type Serial EEPROM Default Memory Space Indicator When enabled, the Base Address register maps PEX 8524 port configuration registers into memory space. NT_Port Link BAR0 is configured by EEPROM and Local Host. By Default Configuration BAR setup register selects 32-bit Memory BAR0 and 32-bit I/O BAR1 for CSR Mapping. RO Yes 0b Memory Map Type 00b = PEX 8524 Configuration registers are mapped anywhere in 32-bit memory addressing space only RO Yes 00b Prefetchable Base Address register maps PEX 8524 Configuration registers into nonprefetchable memory space by default. RO Yes 0b 0 2:1 3 Description PR EL IM IN AR Y Bit(s) 16:4 Reserved 31:17 Base Address 0 Base Address of 128-KB to map the PEX 8524 Configuration space registers into memory space. 0-0h R/W Yes 0000h Register 15-6. 14h Base Address 1 Bit(s) 0 Description I/O Space Indicator 0b = Reserved 1b = Implemented as an I/O BAR 7:1 Reserved 31:8 I/O Base Address I/O space Base Address of 256-Byte size. For NT Port Link Interface, when [1:0] = 11b, this BAR is enabled. Type Serial EEPROM Default RO Yes 1b 0000_000b R/W PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 0000_00h 295 NT Port Link Interface Registers PLX Technology, Inc. Register 15-7. 18h Base Address 2 Type Serial EEPROM Default Memory Space Indicator 0b = Implemented as a Memory BAR; otherwise, reserved RO Yes 0b Memory Map Type 00b = Mappable anywhere in 32-bit memory space 10b = Mappable anywhere in 64-bit memory space 01b, 11b = Reserved RO Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable RO Yes 0b Bit(s) 0 2:1 3 Description Reserved 00h 31:12 Base Address 2 Base Address is enabled and sized by BAR2 Setup register. This BAR2/BAR3 group uses direct address translation. The minimum BAR size is programmed to 4 KB. PR EL IM IN AR Y 11:4 R/W Yes 0000_0h Description Type Serial EEPROM Default Upper Base Address NT Port Link Interface upper 32-bit address if BAR2/3 is implemented as a 64-bit BAR; otherwise, reserved. These fields are R/W, based on BAR2 and BAR3 setup register. The BAR2/3 group uses direct address translation. R/W Yes 0-0h Type Serial EEPROM Default Memory Space Indicator 0b = Implemented as a Memory BAR; otherwise, reserved RO Yes 0b Memory Map Type 00b = Mappable anywhere in 32-bit memory space 10b = Mappable anywhere in 64-bit memory space 01b, 11b = Reserved RO Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable RO Yes 0b Register 15-8. 1Ch Base Address 3 Bit(s) 31:0 Register 15-9. 20h Base Address 4 Bit(s) 0 2:1 3 Description 11:4 Reserved 31:12 Base Address 4 Base Address size is set and it is enabled by BAR4 Setup register. The BAR4/5 group uses direct address translation. The minimum BAR size is programmed to 4 KB. 296 00h R/W Yes 0000_0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Configuration Header Registers Register 15-10. 24h Base Address 5 Bit(s) Description Type Serial EEPROM Default 31:0 Base Address 5 NT Port Link Interface upper 32-bit address if BAR4/5 is implemented as a 64-bit BAR; otherwise reserved. These fields are R/W, based on BAR4 and BAR5 setup register. The BAR4/5 group uses direct address translation. R/W Yes 0-0h Register 15-11. 28h Cardbus CIS Pointer Bit(s) Type Serial EEPROM Reserved Default 0-0h PR EL IM IN AR Y 31:0 Description Register 15-12. 2Ch Subsystem ID and Subsystem Vendor ID Type Serial EEPROM Default 15:0 Subsystem Vendor ID Unless overwritten by the serial EEPROM, returns PCI-SIG assigned PLX Vendor ID, for each port. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX Vendor ID with another Vendor ID. HwInit Yes 10B5h 31:16 Subsystem ID Unless overwritten by the serial EEPROM, the PEX 8524 returns 8524h, the PLX-assigned Device ID. The PEX 8524 Serial EEPROM register initialization capability is used to replace the PLX-assigned Device ID with another Device ID. HwInit Yes 8524h Type Serial EEPROM Default RO No 1b Bit(s) Description Register 15-13. 30h Expansion ROM Base Address Bit(s) 0 Description Expansion ROM Enable 0b = Expansion ROM not enabled 1b = Expansion ROM enabled 10:1 Reserved 0-0h 31:11 Expansion ROM Base Address Expansion ROM = 2 KB minimum size. RO No 0-0h Register 15-14. 34h Capabilities Pointer Bit(s) Description 7:0 Capability Pointer Points to the Power Management Capability Registers offset. Do not change this register value (40h). 31:8 Reserved Type Serial EEPROM Default RO Yes 40h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0000_00h 297 NT Port Link Interface Registers PLX Technology, Inc. Register 15-15. 3Ch Interrupt Type Serial EEPROM Default 7:0 Interrupt Line Interrupt Line Routing Value communicates interrupt line routing information. Values in this register are programmed by system software and are system architecture-specific. The value is used by device drivers and operating systems. R/W Yes 00h 15:8 Interrupt Pin Read-Only field that identifies the legacy interrupt message(s) the device (or device function) uses. When values = 0h, 1h, 2h, 3h, and 4h, maps to legacy Interrupt messages for INTA#, INTB#, INTC#, and INTD#, respectively. When 0, indicates that the device does not use legacy Interrupt message(s). Only values 00h or 01h are allowed in the PEX 8524. RO Yes 01h 31:16 Reserved 298 Description PR EL IM IN AR Y Bit(s) 0000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Power Management Capability Registers 15.5 Power Management Capability Registers The following sections detail NT Port Power Management registers. The register map is delineated in Table 15-3. Table 15-3. Power Management Capabilities Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Power Management Capabilities Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEXT POINTER PM Control/Status Bridge Extensions CAPABILITIES ID Power Management Status and Control 40h 44h Bit(s) PR EL IM IN AR Y Register 15-16. 40h Power Management Capabilities Description Type Serial EEPROM Default 7:0 Capability ID Default = 01h - only value allowed. RO Yes 01h 15:8 Next Pointer Default 48h points to the MSI Capabilities registers. RO Yes 48h 18:16 Version Default = 010b - only value allowed. RO Yes 010b 19 PME Clock Set to 0b as required by the PCI Express Base 1.0a. RO No 0b 20 Reserved 21 Device-Specific Initialization Default 0b indicates that Device Specific Initialization is not required. RO Yes 0b AUX Current Default 000b indicates that the PEX 8524 does not contain Auxiliary Current requirements. RO Yes 000b 25 D1 Support Not Supported. Set to 0b. RO No 0b 26 D2 Support Not Supported. Set to 0b. RO No 0b PME Support Default 0000_0b indicates that the NT Port Link Interface does not forward PME messages. RO Yes 0000_0b 24:22 31:27 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0b 299 NT Port Link Interface Registers PLX Technology, Inc. Register 15-17. 44h Power Management Status and Control Bit(s) Description Type Serial EEPROM Default R/W Yes 00b Power Management Status and Control 1:0 Power State 00b = D0 01b and 10b are not supported 11b = D3hot 7:2 Reserved 12:9 14:13 15 PME Enable 0b = Disables PME generation RO Data Select R/W by Serial EEPROM mode only. Bits [12:9] select the Data and Data Scale registers. 0h = D0 power consumed 3h = D3hot power consumed 4h = D0 power dissipated 7h = D3hot power dissipated No 0b RO Yes 0h RO for hardware auto configuration. Not Supported. RO No 0h Data Scale R/W by Serial EEPROM mode only. There are four internal Data Scale register per port. Bits [12:9], Data Select, select the Data Scale register. RO Yes 00b PME Status 0b = PME is not being generated by the NT port RO No 0b PR EL IM IN AR Y 8 0h PM Control/Status Bridge Extensions 21:16 Reserved 22 B2/B3 Support Always set to 0b. 23 Bus Power/Clock CNTRL Enable Always set to 0b. 0-0h RO No 0b RO No 0b RO Yes 00h Data Data 31:24 R/W by serial EEPROM mode onlya. There are four internal Data registers per port. Bits [12:9], Data Select, select the Data register. a.With no serial EEPROM, reads return 0h for Data Scale and Data registers (for all Data Selects). 300 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 15.6 Message Signaled Interrupt Capabilities Registers Message Signaled Interrupt Capabilities Registers The Message Signaled Interrupt (MSI) Capabilities registers are defined in the Chapter 10, "PEX 8524 Port Registers." Table 15-4 delineates the register map used by the NT Port Link Interfaces. Table 15-4. Message Signaled Interrupt Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Message Signaled Interrupt Control NEXT CAPABILITY POINTER CAPABILITY ID 48h Lower Message Address[31:0] 4Ch Upper Message Address[63:32] 50h Message Data 54h PR EL IM IN AR Y Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 301 NT Port Link Interface Registers 15.7 PLX Technology, Inc. PCI Express Capabilities Registers The following sections detail the PEX 8524 PCI Express Capabilities registers. The register map is delineated in Table 15-5. Table 15-5. PCI Express Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEXT CAPABILITY POINTER PCI Express Capabilities CAPABILITY ID Device Capabilities Device Status 6Ch Device Control 70h Link Capabilities Link Status 68h 74h Link Control 78h PR EL IM IN AR Y Reserved 7Ch - 8Ch Register 15-18. 68h PCI Express Capabilities Bit(s) Description Type Serial EEPROM Default 7:0 Capability ID Set to 10h by default. RO Yes 10h 15:8 Next Capability Pointer 00h = PEX 8524 PCI Express Capability is the last capability in the first 256-byte configuration space of the NT Port Link Interface capability list. The NT Port Link Interface Capabilities list starts at 100h. RO Yes 00h 19:16 Capability Version PEX 8524 NT Port Link Interface sets these bits to 1h as required by the PCI Express Base 1.0a. RO Yes 1h 23:20 Device/Port Type Default = PCI Express Endpoint device. RO Yes 0h 24 Slot Implemented Not implemented in NT Port interface. RO No 0b 29:25 Interrupt Message Number EEPROM writes 0000_0b, because Base message and MSI messages are the same. RO Yes 0000_0b 31:30 Reserved 302 00b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 15-19. 6Ch Device Capabilities Type Serial EEPROM Default 2:0 Maximum Payload Size Supported 000b = NT Port Link Interface supports 128-byte maximum payload 001b = NT Port Link Interface supports 256-byte maximum payload No other values are supported. RO Yes 001b 4:3 Phantom Functions 00b indicates that Phantom Functions are not supported. RO Yes 00b 5 Extended Tag Field 0b = Maximum Tag field is 5 bits 1b = Maximum Tag field is 8 bits Extended Tag Field not supported. RO Yes 0b 8:6 Endpoint L0s Acceptable Latency RO Yes 000b 11:9 Endpoint L1 Acceptable Latency RO Yes 000b 12 Attention Button Present For the NT Port Link Interface, this bit, when 1b, indicates that an Attention Button is implemented on that adapter card. PEX 8524 EEPROM register initialization capability is used to change this value to 0b, indicating that an Attention Button is not present on an adapter card for which PEX 8524 is providing the system interface. HwInit Yes 1b 13 Attention Indicator Present For the NT Port Link Interface, this bit, when 1b, indicates that an Attention Indicator is implemented on the adapter card. The PEX 8524 EEPROM register initialization capability is used to change this value to 0b, indicating an Attention Indicator is not present on an adapter card for which PEX 8524 is providing the system interface. HwInit Yes 1b 14 Power Indicator Present For the NT Port Link Interface, this bit, when 1b, indicates that a Power Indicator is implemented on the adapter card The PEX 8524 EEPROM register initialization capability is used to change this value to 0b, indicating that a Power Indicator is not present on an adapter card for which PEX 8524 is providing the system interface. HwInit Yes 1b Description PR EL IM IN AR Y Bit(s) 17:15 Reserved 000b 25:18 Captured Slot Power Limit Value For the NT Port Link Interface, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the Captured Slot Limit Power Scale field. RO Yes 00h 27:26 Captured Slot Limit Power Scale For the NT Port Link Interface, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the Captured Slot Power Limit Value field. 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 RO Yes 00b 31:28 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0h 303 NT Port Link Interface Registers PLX Technology, Inc. Register 15-20. 70h Device Status and Control Bit(s) Description Type Serial EEPROM Default Device Control Correctable Error Reporting Enable 0b = Disables 1b = Enables NT Port Link Interface to report correctable errors R/W Yes 0b 1 Non-Fatal Error Reporting Enable 0b = Disables 1b = Enables NT Port Link Interface to report non-fatal errors R/W Yes 0b 2 Fatal Error Reporting Enable 0b = Disables 1b = Enables NT Port Link Interface to report fatal errors R/W Yes 0b 3 Unsupported-Request Reporting Enable 0b = Disables 1b = Enables NT Port Link Interface to report unsupported-request errors as an error message with a programmed uncorrectable error severity R/W Yes 0b 4 Unsupported-Request Reporting Enable Not supported. Set to 0b. RO No 0b Maximum Payload Size NT Port Link Interface power on/reset values for this field is 000b to support a maximum payload size of 128 bytes. Software can change this field to configure the NT Port Link Interface ports to support other payload sizes, but it should not change this field to a value larger than that indicated by the Maximum Payload Size supported for the Link Interface and Maximum Payload Size for the Virtual Interface. (the requester and completer domains must possess the same max payload size) Note: Software to halt transactions through NT port before changing this field. R/W Yes 000b 8 Extended Tag Field Enabled Not supported. Set to 0b for each port. RO No 0b 9 Phantom Functions Enable Not supported. Set to 0b for each port. RO No 0b 10 AUX Power PM Enable Not supported. Set to 0b for each port. RO No 0b 11 No Snoop Enable Not supported. Set to 0b for each port. RO No 0b 14:12 Maximum Read-Request Size Not supported. Set to 0b for each port. RO No 000b 7:5 15 304 PR EL IM IN AR Y 0 Reserved 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 15-20. 70h Device Status and Control (Cont.) Type Serial EEPROM Default 16 Correctable Error Detected 1b = NT Port Link Interface detected a Correctable Error Set when the NT Port Link Interface detects a Correctable Error, regardless of the Correctable Error Reporting Enable bit state. R/W1C Yes 0b 17 Non-Fatal Error Detected 1b = NT Port Link Interface detected a Non-Fatal Error Set when the NT Port Link Interface detects a Non-Fatal Error, regardless of the Non-Fatal Error Reporting Enable bit state. R/W1C Yes 0b 18 Fatal Error Detected 1b = NT Port Link Interface detected a Fatal Error Set when the NT Port Link Interface detects a Fatal Error, regardless of the Fatal Error Reporting Enable bit state. R/W1C Yes 0b 19 Unsupported Request Detected 1b = NT Port Link Interface detected an Unsupported-Request Set when the NT Port Link Interface detects an Unsupported-Request, regardless of the Unsupported-Request Reporting Enable bit state. R/W1C Yes 0b 20 AUX Power Detected Not supported. Set to 0b for each port. RO No 0b 21 Transactions Pending Because PEX 8524 NT ports are a bridging device, they do not track non-posted and Completion for the corresponding non-posted transactions. Therefore, the NT Port Link Interface does not implement this bit. RO No 0b Bit(s) Description 31:22 Reserved PR EL IM IN AR Y Device Status PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 000h 305 NT Port Link Interface Registers PLX Technology, Inc. Register 15-21. 74h Link Capabilities Bit(s) Description Type Serial EEPROM Default Maximum Link Speed Set to 1h for 2.5 Gbps. RO Yes 1h 9:4 Maximum Link Width Actual link width is set by signal ball strapping options Maximum Link Width for PEX 8524 is x16 = 01_0000b. RO Yes Strap levels 11:10 Active-State Power Management Support 01b = NT Port Link Interface supports the L0s link power state RO Yes 01b 14:12 L0s Exit Latency 101b = NT Port Link Interface L0s Exit Latency is between 1 and 2 s RO Yes 101b 17:15 L1 Exit Latency 101b = NT Port Link Interface L1 Exit Latency is between 16 and 32 s RO Yes 101b 23:18 Reserved PR EL IM IN AR Y 3:0 0-0b Port Number Port number is set by signal ball strapping options: 31:24 HwInit Yes STRAP_STN0_PORTCFG[4:0] - Port numbers 0, 1 STRAP_STN1_ PORTCFG[3:0] - Port numbers 8, 9, 10, 11 Set by strap levels Register 15-22. 78h Link Status and Control Bit(s) Description Type Serial EEPROM Default R/W Yes 00b Link Control 1:0 306 Active-State Link Power Management Control 00b = Disables L0s Link Interface Entry for NT Port 01b = Enables L0s Entry 10b and 11b are not allowed. 2 Reserved 3 Read Completion Boundary Not supported. Set to 0b for each port. 0b RO Yes 0b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 PCI Express Capabilities Registers Register 15-22. 78h Link Status and Control (Cont.) Bit(s) Description Type Serial EEPROM Default Link Disable Reserved for NT Port Link Interface. RO No 0b 5 Retrain Link Reserved for NT Port Link Interface. RO No 0b 6 Common Clock Configuration When set to: 0b = Corresponding PEX 8524 port and the device at the other end of the corresponding port PCI Express link are operating with an asynchronous reference clock 1b = Corresponding PEX 8524 port and the device at the other end of the corresponding port PCI Express link are operating with a distributed common reference clock R/W Yes 0b 7 Extended SYNC Set to 1b causes the corresponding PEX 8524 port to transmit: 1. 4,096 FTS ordered sets in the L0s state, and followed by a single SKP-ordered set prior to entering the L0 state. 2. Transmission of 1,024 TS1 ordered sets in the Recovery state. R/W Yes 0b 15:8 Reserved PR EL IM IN AR Y 4 00h Link Status 19:16 Link Speed NT Port Link Interface set to 1h for 2.5 Gbps. RO Yes 1h 25:20 Negotiated Link Width Indicates the negotiated width of the PCI Express link: 00_0001b = x1 00_0010b = x2 00_0100b = x4 00_1000b = x8All other values are not supported. RO Yes 00_0001b 26 Training Error Reserved for NT Port Link Interface. RO No 0b 27 Link Training Reserved for NT Port Link Interface. RO No 0b 28 Slot Clock Configuration Upstream port or NT Port Link Interface is set, but not both: 0b = Indicates that the PEX 8524 uses an independent clock 1b = Indicates that the PEX 8524 uses the same physical reference clock that the platform provides on the connector HwInit Yes 0b 31:29 Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 0h 307 NT Port Link Interface Registers 15.8 PLX Technology, Inc. NT Port Link Interface Interrupt Request (IRQ) Doorbell Registers The register map and detail for the PEX 8524 NT Port Interrupt Control (Doorbell) register is discussed in Section 14.8, "Virtual Interface IRQ Doorbell Registers." 15.9 NT Port Scratchpad (Mailbox) Registers PR EL IM IN AR Y The register map and detail for the PEX 8524 NT Port Scratchpad (Mailbox) register is discussed in Section 14.9, "NT Port Scratchpad (Mailbox) Registers." 308 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 15.10 NT Port BAR Setup Registers NT Port BAR Setup Registers The following sections detail the NT Port BAR Setup registers. The register map is delineated in Table 15-6. Table 15-6. PEX 8524 NT Port BAR Setup Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E4h BAR2 Setup E8h BAR3 Setup ECh BAR4 Setup F0h BAR5 Setup F4h PR EL IM IN AR Y Configuration BAR Setup Register 15-23. E4h Configuration BAR Setup Bit(s) Description 1:0 BAR0 Type Select 00b = 32-bit memory BAR0 11b = BAR0 is a 32-bit memory BAR and BAR1 is an I/O BAR All other codes disable BAR1 implementation 31:2 Reserved Type Serial EEPROM Default R/W Yes 11b 0-0h Register 15-24. E8h BAR2 Setup Type Serial EEPROM Default RO No 0b BAR2 Type Select 00b = BAR2 implemented as a 32-bit BAR 10b = BAR2/3 implemented as a 64-bit BAR R/W Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable R/W Yes 0b Bit(s) 0 2:1 3 Description Type Reserved 11:4 Reserved 30:12 BAR2 Size Specifies address range size requested by BAR2. When a bit is 1b, the corresponding bit in the BAR2 register is a readable and writable by software. When a bit is 0b, the corresponding bit in the BAR2 register is a Read-Only bit that always returns 0 when read, and writes are ignored. R/W Yes 0000_0h BAR2 Enable 0b = BAR2 disabled when bits [2:1] = 00b; otherwise, enabled R/W Yes 0b 31 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 309 NT Port Link Interface Registers PLX Technology, Inc. Register 15-25. ECh BAR3 Setup Bit(s) Description Type Serial EEPROM Default 30:0 BAR3 Size Specifies the address range size requested by BAR2/3 in 64-bit mode. When 1b, the corresponding bit in the BAR3 register is a readable and writable bit. When 0b, the corresponding bit in the BAR3 register is a Read-Only bit that always returns 0 when reads and writes are ignored. Reserved if BAR2/3 is configured as a 32-bit BAR. R/W Yes 0-0h BAR3 Enable 0b = BAR3 disabled 1b = BAR2/3 enabled as 64-bit memory R/W Yes 0b Type Serial EEPROM Default RO No 0b BAR4 Type Select 00b = BAR4 implemented as a 32-bit BAR 10b = BAR4/5 implemented as a 64-bit BAR R/W Yes 00b Prefetchable 0b = Non-Prefetchable 1b = Prefetchable R/W Yes 0b 31 Bit(s) 0 2:1 3 PR EL IM IN AR Y Register 15-26. F0h BAR4 Setup Description Type Reserved 11:4 Reserved 30:12 BAR4 Size Specifies address range size requested by the BAR4. When 0b, the corresponding bit in the BAR4 register is a Read-Only bit that always returns 0 when read, and writes are ignored. When a bit is 1b, the corresponding bit in the BAR4 register is a readable and writable bit. R/W Yes 0000_0h BAR4 Enable 0b = BAR4 disabled when bits [2:1] = 00b; otherwise, enabled R/W Yes 0b 31 00h Register 15-27. F4h BAR5 Setup Bit(s) Description Type Serial EEPROM Default 30:0 BAR5 Data Specifies address range requested size by the BAR4/5 in 64-bit mode. When 0b, the corresponding bit in the BAR5 register is a Read-Only bit that always returns 0 when read and writes are ignored. When 1b, the corresponding bit in the BAR5 register is a readable and writable bit. Reserved if BAR4/5 is configured as a 32-bit BAR. R/W Yes 0-0h BAR5 Enable 0b = BAR5 disabled 1b = BAR4/5 enabled as 64-bit memory R/W Yes 0b 31 310 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 15.11 Cursor Mechanism Control Registers Cursor Mechanism Control Registers The following section discusses the NT Port Cursor Mechanism Control registers. The register map for the Virtual and Link Interfaces is delineated in Table 15-7. Table 15-7. Cursor Mechanism Control Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Configuration Address Window F8h Configuration Data Window FCh Register 15-28. F8h Configuration Address Window Description PR EL IM IN AR Y Bit(s) 15:0 Reserved 25:16 Offset Register Offset 30:26 Reserved 31 Interface Select 0b = Access to NT Port Link Interface Type 0 Configuration Space register 1b = Access to NT Port Virtual Interface Type 0 Configuration Space register Type Serial EEPROM Default 0000h R/W Yes 000h 0h R/W Yes 0b Type Serial EEPROM Default R/W Yes 0-0h Register 15-29. FCh Configuration Data Window Bit(s) 31:0 Description Data Window Software selects a register by writing into the Register Address window, then reads or writes to that register using this Data window. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 311 NT Port Link Interface Registers 15.12 PLX Technology, Inc. Device Serial Number Extended Capabilities Registers The NT Port Link Interface Device Serial Number Extended Capabilities registers are the same as the PEX 8524 Transparent port registers defined in Chapter 10, "PEX 8524 Port Registers." The register map is delineated in Table 15-8 and applies to the Virtual and Link Interfaces. Table 15-8. PEX 8524 Device Serial Number Extended Capabilities Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NEXT CAPABILITY OFFSET CAPABILIT Y VERSION EXTENDED CAPABILITY ID 100h Serial Number (Low) 104h Serial Number (High) 108h Device Power Budgeting Extended Capabilities Registers PR EL IM IN AR Y 15.13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The NT Port Link Interface Device Power Budgeting Extended Capabilities registers are the same as the PEX 8524 Transparent port registers defined in Chapter 10, "PEX 8524 Port Registers" on page 128. The register map is delineated in Table 15-9 and applies to the Virtual and Link Interfaces. Table 15-9. PEX 8524 Device Power Budgeting Extended Capabilities Register Map (All Ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NEXT CAPABILITY OFFSET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPABILIT Y VERSION Reserved EXTENDED CAPABILITY ID Data Select Power Data Reserved 312 Power Budget Capability 138h 13Ch 140h 144h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 15.14 Virtual Channel Extended Capabilities Registers Virtual Channel Extended Capabilities Registers The NT Port Link Interface Virtual Channel Extended Capabilities registers are the same as the PEX 8524 Transparent port registers defined in Chapter 10, "PEX 8524 Port Registers" on page 130. The register map is delineated in Table 15-10 and applies to the Virtual and Link Interfaces. Table 15-10. PEX 8524 Link Interface Virtual Channel Extended Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Capability Version NEXT CAPABILITY OFFSET Extended Capability ID 148h Port VC Capability 1 14Ch Port VC Capability 2 150h Port VC Status Port VC Control 158h PR EL IM IN AR Y VC0 Resource Capability VC0 Resource Control VC0 Resource Status 154h Reserved 15Ch 160h VC1 Resource Capability 164h VC1 Resource Control 168h VC1 Resource Status Reserved Reserved Virtual Channel Arbitration Table (All Ports) PEX 8524 Port PLX Vendor-Unique registers PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 16Ch 170h ... 1B4h 1B8h ... 1C4h 1C8h 313 NT Port Link Interface Registers 15.15 PLX Technology, Inc. PLX-Specific Registers The PEX 8524 PLX-Specific registers are defined in Chapter 10, "PEX 8524 Port Registers." The NT Port Link Interface registers are included in the Transparent register definitions in Chapter 10, except as delineated in Table 15-11. 15.15.1 Table 15-11. Error Checking and Debug Registers PLX-Specific Error Check/Debug and Physical Layer Register Map (Portsa) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Error Status 1CCh Error Mask 1D0h Reserved 1D4h - 1E4h PR EL IM IN AR Y TEC NT Port Link Interface Control and Status 1E0h Reserved for Transparent ports 1E8h - 1ECh Reserved 1F0h Reserved 1F4h ACK Transmission Latency Limit 1F8h a.Some registers are port-specific, some are station-specific, and some are device-specific. Register 15-30. 1CCh Error Status Description Type Serial EEPROM Default Error Handler Completion FIFO Overflow Status Implemented for each Port 0b = No overflow detected 1b = Completion FIFO Overflow detected whenever 4-deep completion FIFO for ingress, or 2-deep completion FIFO for egress overflows R/W1CS Yes 0b RsvdP No RsvdP 11 Credit Update Timeout Status No useful credit update to make forward progress for 512 ms or 1s (disabled by default) Implemented for each Port. 0b = No credit-update timeout detected 1b = Credit Update Timeout completed R/W1CS Yes 0b 12 INCH Underrun Error Ingress Credit Underrun. Implemented for each Port. 0b = No error detected 1b = Credit underrun error detected R/W1CS Yes 0b RsvdP No RsvdP Bit(s) 0 10:1 31:13 314 Reserved Reserved PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Error Checking and Debug Registers Register 15-31. 1D0h Error Mask Type Serial EEPROM Default Error Handler Completion FIFO Overflow Status Masked Implemented for each Port. 0b = No affect on reporting activity 1b = Error Handler Completion FIFO Overflow Status bit is masked/disabled R/WS Yes 1b Reserved RsvdP No RsvdP 11 Credit Update Timeout Status Masked Implemented for each Port. 0b = No affect on reporting activity 1b = Credit Update Timeout Status bit is masked/disabled R/WS Yes 1b 12 INCH Underrun Error Masked Implemented for each Port. 0b = No affect on reporting activity 1b = INCH Underrun Error bit is masked/disabled R/WS Yes 1b Reserved RsvdP No RsvdP Type Serial EEPROM Default 0 10:1 31:13 Description PR EL IM IN AR Y Bit(s) Register 15-32. 1E4h TEC NT Port Link Interface Control and Status Bit(s) Description 0 Egress Credit Update Timer Enable 0b = Disables Egress Credit Update Timer 1b = Enables Egress Credit Update Timer R/W Yes 0b 1 Egress Credit Timeout Value 0b = Minimum 512 ms (Max 768 ms) 1b = Minimum 1,024 ms (Max 1,280 ms) R/W Yes 0b 2 TEC Debug Factory Testing Only. R/W Yes 0b 15:3 Reserved 19:16 VCNT Encountered Timeout 0h = VC0 Posted 1h = VC0 Non-Posted 2h = VC0 Completion 3h = VC1 Posted 4h = VC1 Non-Posted 5h = VC1 Completion 31:20 Reserved 0-0h RO PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Yes 0h 000h 315 NT Port Link Interface Registers PLX Technology, Inc. Register 15-33. 1F8h ACK Transmission Latency Limit Bit(s) Description Type Serial EEPROM Default R/W Yes FFh R/W Yes 00h ACK Transmission Latency Limit Value based on the programmed link width encoding, when PL_PORT_DATA is active: Link Width Decimal Hex x1 255 FFh x2 217 D9h x4 118 76h x8 107 6Bh PR EL IM IN AR Y 7:0 15:8 HPC Test Bits Factory Testing bits - must be 00h. 31:16 Reserved 316 Register Value 0000h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 15.15.2 NT Port Link Interface Physical Layer Registers NT Port Link Interface Physical Layer Registers The PEX 8524 NT Port Link Interface Physical Layer registers are defined in Chapter 10, "Physical Layer Registers" on page 148. The NT Port Link Interface register map is delineated in Table 15-12. The references and hyperlinks are to Chapter 10, "PEX 8524 Port Registers." Table 15-12. PLX-Specific Error Check/Debug and Physical Layer Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Test Pattern_0 210h Test Pattern_1 214h Test Pattern_2 218h Test Pattern_3 21Ch Physical Layer Status Physical Layer Control 224h Physical Layer Test 228h Physical Layer 22Ch Physical Layer Port Command 230h Skip-Ordered Set Interval 234h Quad SerDes[0-3] Diagnostics Data 238h Quad SerDes[4-7] Diagnostics Data 23Ch Quad SerDes[8-11] Diagnostics Data 240h Quad SerDes[12-15] Diagnostics Data 244h SerDes Nominal Current Select 248h SerDes Driver Current Level_1 24Ch SerDes Driver Current Level_2 250h SerDes Driver Equalization Level Select_1 254h SerDes Driver Equalization Level Select_2 258h PR EL IM IN AR Y Port Configuration Reserved 15.15.3 220h 25Ch - BECh PLX-Specific Relaxed Ordering Mode Register The PLX-Specific Relaxed Ordering Mode register is delineated in Table 15-13. The reference and hyperlink is to Chapter 10, "PEX 8524 Port Registers." Table 15-13. PLX-Specific Relaxed Ordering Mode Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BF0h Reserved BF4h Reserved BF8h PLX-Specific Relaxed Ordering Mode BFCh PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 317 NT Port Link Interface Registers 15.15.4 PLX Technology, Inc. NT Port Link Interface Memory Address Translation and Limit BAR Registers The NT station contains the main copy of these registers and the transparency station the shadow copy of these registers. Program only the main copy. The shadow register is automatically updated. The reverse is not true. Table 15-14. NT Port Memory Address Translation and Limit BAR Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3Ch Memory BAR_3 Address Translation[63:32] C40h Memory BAR_4 Address Translation[31:0] C44h Memory BAR_5 Address Translation[63:32] C48h Memory BAR_2 Limit[31:0] C4Ch Memory BAR_3 Limit[63:32] C50h Memory BAR_4 Limit[31:0] C54h Memory BAR_5 Limit[63:32] C58h PR EL IM IN AR Y Memory BAR_2 Address Translation[31:0] Register 15-34. C3Ch Memory BAR_2 Address Translation[31:0] Bit(s) Description 11:0 Reserved 31:12 BAR_2 Base Translation[31:12] NT Port Link Interface base address translation register if BAR_2 enabled Type Serial EEPROM Default 0-0h R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Register 15-35. C40h Memory BAR_3 Address Translation[63:32] Bit(s) 31:0 318 Description BAR_2/3 Base Translation[63:32] NT Port Link Interface base address translation register extension when BAR2 TYPE SELECT = 10b PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 NT Port Link Interface Memory Address Translation and Limit BAR Registers Register 15-36. C44h Memory BAR_4 Address Translation[31:0] Bit(s) Description 11:0 Reserved 31:12 BAR_4 Base Translation[31:12] NT Port Link Interface base address translation register if BAR_4 enabled Type Serial EEPROM Default 0-0h R/W Yes 0-0h Type Serial EEPROM Default R/W Yes 0-0h Type Serial EEPROM Default Register 15-37. C48h Memory BAR_5 Address Translation[63:32] Bit(s) BAR_4/5 Base Translation[63:32] NT Port Link Interface base address translation register extension when BAR4 TYPE SELECT = 10b. PR EL IM IN AR Y 31:0 Description Register 15-38. C4Ch Memory BAR_2 Limit[31:0] Bit(s) Description 11:0 Reserved 31:12 BAR_2 Limit[31:0] Contains the upper limit of the memory window defined in the BAR_2 Setup register. If the limit is greater than the size of the window, it is ignored. 0-0h R/W Yes 000h Description Type Serial EEPROM Default BAR_2/3 Limit[63:32] NT Port Link Interface = contains the upper limit of the memory window defined in BAR_3 Setup register, when BAR2 TYPE SELECT = 10b, and BAR3 ENABLE = 1. If the limit is greater than the size of the window, it is ignored. R/W Yes 0-0h Register 15-39. C50h Memory BAR_3 Limit[63:32] Bit(s) 31:0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 319 NT Port Link Interface Registers PLX Technology, Inc. Register 15-40. C54h Memory BAR_4 Limit[31:0] Bit(s) Description 11:0 Reserved 31:12 BAR_4 Limit[31:0] Contains the upper limit of the memory window defined in the BAR_4 Setup register. If the limit is greater than the size of the window, it is ignored. Type Serial EEPROM Default 0-0h R/W Yes 0-0h Type Serial EEPROM Default Yes 0-0h Register 15-41. C58h Memory BAR_5 Limit[63:32] 31:0 320 Description BAR_4/5 Limit[63:32] Contains the upper limit of the memory window defined in the BAR_5 Setup register. If the limit is greater than the size of the window, it is ignored. PR EL IM IN AR Y Bit(s) R/W PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 NT Port Link Interface Receive LUT Entry Registers 15.15.5 NT Port Link Interface Receive LUT Entry Registers The Link Interface Receive (Requester ID Translation) Lookup Table (LUT) Entry registers are delineated in the following tables. NT Port uses this register for Requester ID translation when it forwards the TLP requester from NT Port Link Interface to Virtual Interface. It also uses this register when it forwards a completion TLP from NT Port Virtual Interface to the Link Interface. Table 15-15 lists the registers and address location. The register descriptions that follow the table defines the bit definitions that apply to the registers. The NT station contains the main copy of these registers and the transparency station contains the shadow copies of these registers. Program only the main copy. The shadow register is automatically updated. The reverse is not true. Table 15-15. Link Interface Receive LUT Entry Register Location Lookup Table Entry (n_m) ADDR Location Lookup Table Entry (n_m) DB4h 0_1 DD4h 16_17 2_3 DD8h 18_19 4_5 DDCh 20_21 6_7 DE0h 22_23 8_9 DE4h 24_25 10_11 DE8h 26_27 12_13 DECh 28_29 14_15 DF0h 30_31 DB8h DBCh DC0h DC4h DC8h DCCh DD0h PR EL IM IN AR Y ADDR Location Register 15-42. DB4h - DF0h Link Interface Receive LUT Entry_n_m (where n_m = 0_1 through 30_31) Bit(s) 0 Description LUT Entry_n Enable 0b = Disables 1b = Enables Type Serial EEPROM Default R/W Yes 0b 2:1 Reserved 7:3 LUT Entry_n Device Number R/W Yes 0000_0b 15:8 LUT Entry_n Bus Number R/W Yes 00h LUT Entry_m Enable 0b = Disables 1b = Enables R/W Yes 0b 16 00b 18:17 Reserved 00b 23:19 LUT Entry_m Device Number R/W Yes 0000_0b 31:24 LUT Entry_m Bus Number R/W Yes 00h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 321 NT Port Link Interface Registers 15.16 PLX Technology, Inc. Advanced Error Reporting Capability Registers PR EL IM IN AR Y The Advanced Error Reporting Capability registers for the NT Port Link Interface are equivalent to those defined in Chapter 10, "PEX 8524 Port Registers." 322 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 16 Test and Debug 16.1 Physical Layer Loop-Back Operation 16.1.1 Overview Physical layer loop-back functions are used to test SerDes in the PEX 8524, connections between devices, SerDes of external devices, and certain PEX 8524 and external digital logic. The PEX 8524 supports five types of loop-back operations: * Internal Loop-Back - Connects SerDes serial Tx output to serial Rx input. The PRBS generator is used to create a pseudo-random data pattern that is transmitted and returned to the PRBS checker. * Analog Loop-Back Master - Depends on an external device or dumb connection (such as a cable) to loop back the transmitted data to the PEX 8524. If an external device is used, it must not include its elastic buffer in the Loop-Back data path because no SKP-ordered sets are transmitted. Use the PRBS generator and checker to create and check the data pattern. * Digital Loop-Back Master - As with the Analog Loop-Back Master mode, this method depends upon an external device to loop back the transmitted data. This method is best utilized with an external device that includes at least its elastic buffer in the Loop-Back data path. The PEX 8524 provides user-definable data pattern generators and checkers that insert the SKP-ordered set at the proper intervals. * Analog Loop-Back Slave -The PEX 8524 enters Analog Loop-Back Slave mode when an external device transmits training sets with the Loop-Back TCB set and the Physical Layer Test register Analog Loop-Back Enable bit (register 228h, bit 4) is set. The received data is looped back from the SerDes 10-bit receive interface to the 10-bit transmit interface. All digital logic is excluded from the Loop-Back data path. * Digital Loop-Back Slave - The PEX 8524 enters Digital Loop-Back Slave mode when an external device transmits training sets with the Loop-Back TCB set and the Analog Loop-Back Enable bit is clear. In this mode, the data is looped back at an 8-bit level, which includes the PEX 8524 elastic buffer, 8b/10b decoder, and 8b/10b encoder in the Loop-Back data path. 16.1.1.1 Loop-Back Test Modes The PEX 8524 supports all Loop-Back modes described in the PCI Express Base 1.0a. To establish a PEX 8524 port as a Loop-Back master, the serial EEPROM is used to write 1b to the appropriate Physical Layer Port Command register bit. This enables the selected port to set its Port Loop-Back Training Control bit (TCB) in the training sets during the Configuration.Linkwidth.Start state. Once a port is established as a Loop-Back master, the corresponding Physical Layer Port Command register (register 230h) Port Loop-Back Master ready status bit is set. Depending on the capability of the Loop-Back slave, the PRBS generator or Bit-Pattern generator is used to create a bit stream that is checked by appropriate checking logic. When the PEX 8524 is established as a Loop-Back slave, it can operate as an Analog or Digital (default) Far-End device. * Analog Loop-Back mode is selected by setting the Physical Layer Test register Analog LoopBack Enable bit [4] to 1b. When in Analog Loop-Back mode, the received data is looped back from the 10-bit received data to the 10-bit transmit data. * When Digital Loop-Back mode is selected (power-on default), the data is looped back from the 8-bit decoded received data to the 8-bit transmit data path. This loop-back point allows the elastic buffer 8b/10b decoder, and 8b/10b encoder to be included in the test data path. Digital Loop-Back mode requires that SKP-ordered sets are included in the data stream. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 323 Test and Debug 16.1.2 PLX Technology, Inc. Internal Loop-Back Figure 16-1 illustrates the Loop-Back data path when Internal Loop-Back mode is enabled. The only items in the data path are the serializer and de-serializer. Loop-Back mode is used when the SerDes BIST (Built-In Self-Test) is enabled. Figure 16-1. Internal Loop-Back (Analog near End) Data Path PEX 8524 PRBS G en Rx Pad PRBS Chk PR EL IM IN AR Y Tx Pad SerDes BIST is intended to be overlapped with the serial EEPROM load operation. To achieve this overlap, the Physical Layer Test register SerDes BIST Enable bit (register 228h, bit 7) is written early in the serial EEPROM load operation. After the SerDes BIST Enable bit is set, SerDes is placed in Loop-Back mode and the PRBS generator is started. The BIST is run for 512 s; if an error is detected on a SerDes, the BIST_ERROR ball associated with the station that includes the SerDes in error is asserted. While the SerDes BIST is in progress, the PRBS test data is present on the external TxP and TxN balls. The Tx Pad TxN signals must have an AC-coupled, 50-Ohm termination to ground. The continuing Serial EEPROM register load leaves no effect on the SerDes BIST. 324 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 16.1.3 Analog Loop-Back Master Analog Loop-Back Master Analog Loop-Back mode is normally used for Analog Far-End testing (Figure 16-2); however, it can also be used to re-create the previously described BIST by looping back the data with a cable. Looping back with a cable (Figure 16-3) includes the internal bond, external balls, any card trace, and connectors in the test data path. Figure 16-2. Analog Far-End Loop-Back PCI-E Loop-Back Slave Device PEX 8524 Rx Pad PRBS Gen Rx Pad PRBS Chk PR EL IM IN AR Y Tx Pad Tx Pad PCI-E = PCI Express Figure 16-3. Cable Loop-Back PEX 8524 Tx Pad PRBS Gen Rx Pad PRBS Chk To cause a PEX 8524 port to request to become a Loop-Back master, the following must be accomplished: 1. After the link is up, a Configuration write to the appropriate Physical Layer Port Command register (register 230h) loop-back command bit causes the port to transition from the L0 state to Recovery, then to the Loop-Back state: - If a cable is used for a loop-back, the port transitions from the Configuration state to the Loop-Back state. Connect this cable only after the upstream link is up and configuration writes are possible. - If the cable is connected before the upstream device is able to set the Analog Loop-Back Enable bit, the link with the cable can reach the L0 state and not go to the Loop-Back state. - Cable length is limited only by the PCI Express drivers and cable properties. 2. After the port is in the Loop-Back state, the corresponding Physical Layer Port Command register Port Loop-Back Master ready status bit is set: - At this time, the PRBS engine is enabled by setting the PRBS Enable bit (register 228h, bits [19:16]) associated with the SerDes assigned to the port under test. - The returned PRBS data is checked by the PRBS checker. Errors are logged in the Test Diagnostic register (registers 238h through 244h) that corresponds to the SerDes quad being tested. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 325 Test and Debug 16.1.4 PLX Technology, Inc. Digital Loop-Back Master The only difference between the Analog and Digital Loop-Back Master modes is that the external device is assumed to possess certain digital logic in the Loop-Back data path. Because this includes the elastic buffer, SKP-ordered sets must be included in the test data pattern. For the PEX 8524, this precludes PRBS engine use. Figure 16-4. Digital Far-End Loop-Back PCI-E Loop-Back Slave Device EBuffer PEX 8524 Rx Pad UTP Tx Rx Pad UTP Chk PR EL IM IN AR Y Tx Pad Tx Pad The PEX 8524 provides the User Data Pattern (registers 210h through 21Ch) transmitter for digital far-end loop-back testing. the following must be accomplished: 1. After the Loop-Back Master mode is established, Configuration writes are used to fill the Test Data Pattern registers. The corresponding Physical Layer Test register Test Pattern Enable bit is set; this starts the transmission of the user data pattern on all lanes: - If the Enable by Port bit is also set, the test pattern is transmitted on all corresponding port lanes, regardless of width. - If the Enable by Port bit is clear, then the test pattern is transmitted only on corresponding SerDes quad lanes. 2. SKP-ordered sets are inserted at the interval determined by the value in the SKP Interval register (default value is 1180 symbol times) at the nearest data pattern boundary. The Test Pattern checker ignores SKP-ordered sets returned by the Loop-Back slave, because the number of SKP symbols received are different from the number transmitted. 3. All other data is compared to the data transmitted and errors are logged in the Test Diagnostic registers. 326 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 16.1.5 Analog Loop-Back Slave Analog Loop-Back Slave The PEX 8524 becomes an Analog Loop-Back slave (Figure 16-5) if it receives training sets with the Loop-Back TCB set while the Physical Layer Test register Analog Loop-Back Enable bit (register 228h, bit 4) is set. While an Analog Loop-Back slave, the PEX 8524 only includes the de-serializer and serializer in the Loop-Back data path. The Loop-Back master must provide the test data pattern and data pattern checking. It is unnecessary for the Loop-Back master to include SKP-ordered sets in the data pattern. Figure 16-5. Analog Loop-Back Slave Mode PCI-E Loop-Back Master Device PEX 8524 Rx Pad Data Gen Rx Pad Data Chk PR EL IM IN AR Y Tx Pad Tx Pad PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 327 Test and Debug 16.1.6 PLX Technology, Inc. Digital Loop-Back Slave The PEX 8524 becomes a Digital Loop-Back slave (Figure 16-6) if it receives training sets with the Loop-Back TCB set while the Physical Layer Test register Analog Loop-Back Enable bit is clear. When a PEX 8524 port is a Digital Loop-Back slave, it includes the elastic buffer and 8b/10b decoder and encoder in the Loop-Back data path. The Loop-Back master must provide the test data pattern and data pattern checker. Additionally, the master must transmit valid 8b/10b symbols, for the Loop-Back data from the slave to be valid. The Loop-Back master must also transmit SKP-ordered sets with the data pattern. The data checker must make provisions for the PEX 8524 to return more or fewer SKP symbols than it received. Figure 16-6. Digital Loop-Back Slave Mode PCI-E Loop-Back Master Device PR EL IM IN AR Y PEX 8524 8b/10b Dec 8b/10b Enc 16.1.7 EBuffer Rx Pad Tx Pad Data Tx Tx Pad Rx Pad Data Chk Using the Diagnostic Registers There are four diagnostic registers per station, one for each serdes quad. The contents of the Diagnostic registers (registers 238h through 244h) reflect the performance of the SerDes selected by the Physical Layer Test register PRBS Association SerDes Select bits. For example, if SerDes Select is equal to 10b, the information in diagnostic register 0 is for SerDes 2 in quad 0. The PRBS Association SerDes Select bits must be setup before the test is started. 16.2 Pseudo-Random and Bit-Pattern Generation Each SerDes quad contains an associated PRBS generator and checker. The PRBS generator is based on a 7-bit Linear Feedback Shift register (LFSR) which can generate up to (27 - 1) unique patterns. The PRBS logic is assigned to a SerDes in the quad by manipulating the Physical Layer Test[9:8] bits in each station. The PRBS bit stream is used for internal SerDes or analog far-end loop-back testing. The PEX 8524 also provides a method of creating a repeating user-defined bit pattern. Each of the four 32-bit Test Pattern registers are loaded with a 32-bit data pattern. After a port is established as a Loop-Back master, the Test Pattern Enable bit associated with that port or SerDes quad is set to 1b. The PEX 8524 proceeds to transmit the data pattern on all lanes starting with byte_0 of the Test Pattern_0 register, and continuing in sequence through the byte_3 of the Test Pattern_3 register. SKP-ordered sets are inserted at the proper intervals, which makes this method appropriate for Digital Far-End Loop-Back testing. The received pattern is checked/compared for errors. The errors are logged and retrieved by reading the Quad SerDes[0-3] Diagnostics Data through Quad SerDes[12-15] Diagnostics Data registers. 328 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 16.3 JTAG Interface JTAG Interface The PEX 8524 provides a JTAG Boundary Scan interface, which is utilized to debug card connectivity for each ball. 16.3.1 IEEE 1149.1 and 1149.6 Test Access Port The IEEE 1149.1 Test Access Port (TAP), commonly called the JTAG (Joint Test Action Group) debug port, is an architectural standard described in the IEEE Standard 1149.1-1990. The IEEE Standard 1149.6-2003 defines extensions to 1149.1 to support PCI Express SerDes testing. These standards describe methods for accessing internal chip facilities, using a four- or five-signal interface. The JTAG debug port, originally designed to support scan-based card testing, is enhanced to support the attachment of debug tools. The enhancements, which comply with IEEE Standard 1149.1b-1994 Specifications for Vendor-Specific Extensions, are compatible with standard JTAG hardware for boundary-scan system testing. PR EL IM IN AR Y * JTAG Signals - JTAG debug port implements the four required JTAG signals - JTAG_TCK, JTAG_TDI, JTAG_TDO, JTAG_TMS - and optional JTAG_TRST# signal * Clock Requirements - The JTAG_TCK signal frequency ranges from DC to 10 MHz * JTAG Reset Requirements - Section 16.3.4, "JTAG Reset Input Signal JTAG_TRST#" PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 329 Test and Debug 16.3.2 PLX Technology, Inc. JTAG Instructions The JTAG debug port provides the IEEE Standard 1149.1-1990 EXTEST, SAMPLE/PRELOAD, BYPASS, and IDCODE instructions. IEEE Standard 1149.6-2003 EXTEST_PULSE and EXTEST_TRAIN instructions are also supported. PRIVATE instructions are for PLX use only. Invalid instructions behave as BYPASS instructions. Table 16-1 lists the JTAG instructions, along with their input codes. Table 16-1. JTAG Instructions Input Code EXTEST 00000b IDCODE 00001b SAMPLE/PRELOAD 00010b BYPASS 11111b Comments IEEE Standard 1149.1-1990 PR EL IM IN AR Y Instruction EXTEST_PULSE 00011b EXTEST_TRAIN 00100b IEEE Standard 1149.6-2003 00101b 00110b 00111b 01000b 01001b PRIVATE a 01010b 01011b 01100b 01101b 01110b 01111b a. Warning: Non-PLX use of PRIVATE instructions can cause a component to operate in a hazardous manner. The PEX 8524 returns the IDCODE values listed in Table 16-2. Table 16-2. 330 PEX 8524 JTAG IDCODE Values PEX 8524 Version Part Number PLX Manufacturer Identity Least Significant Bit Bits 0001b TBD 001_1100_1101 1 Hex 1h 8524h 1CDh 1h Decimal 1 8524 461 1 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 16.3.3 JTAG Boundary Scan Boundary JTAG Boundary Scan Boundary Scan Description Language (BSDL), IEEE 1149.1b-1994, is a supplement to IEEE Standard 1149.11990 and IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture. BSDL, a subset of the IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL), allows a rigorous description of testability features in components which comply with the standard. It is used by automated test pattern generation tools for package interconnect tests and Electronic Design Automation (EDA) tools for synthesized test logic and verification. BSDL supports robust extensions that can be used for internal test generation and to write software for hardware debug and diagnostics. The primary components of BSDL include the logical port description, physical ball map, instruction set, and boundary register description. The logical port description assigns symbolic names to the chip balls. Each ball includes a logical type of in, out, in out, buffer, or linkage that defines the logical direction of signal flow. PR EL IM IN AR Y The physical ball map correlates the chip logical ports to the physical balls of a specific package. A BSDL description can include several physical ball maps, and maps are provided with a unique name. Instruction set statements describe the bit patterns that must be shifted into the Instruction register to place the chip in the various test modes defined by the standard. Instruction set statements also support descriptions of instructions that are unique to the chip. The boundary register description lists each cell or shift stage of the Boundary register. Each cell contains a unique number, the cell numbered 0 is the closest to the Test Data Out (JTAG_TDO) ball and the cell with the highest number is closest to the Test Data In (JTAG_TDI) ball. Each cell contains additional information, including: * Cell type * Logical port associated with the cell * Logical function of the cell * Safe value * Control cell number * Disable value * Result value PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 331 Test and Debug 16.3.4 PLX Technology, Inc. JTAG Reset Input Signal JTAG_TRST# The JTAG_TRST# input ball is the asynchronous JTAG logic reset. When JTAG_TRST# is set low, it causes the PEX 8524 TAP controllers to initialize. In addition, when the TAP controller is initialized, it selects the PEX 8524 normal logic path (core-to-I/O). It is recommended to take the following into consideration when implementing the asynchronous JTAG logic reset on a card: * If JTAG functionality is required, consider one of the following: - JTAG_TRST# input signal to use a low-to-high transition once during PEX 8524 boot-up, along with the system PEX_PERST# signal - Hold the JTAG_TMS ball high while clocking the JTAG_TCK ball five times * If JTAG functionality is not required, the JTAG_TRST# signal must be directly connected to VSS to hold the JTAG controller inactive Lane-Good Status LEDs PR EL IM IN AR Y 16.4 The PEX 8524 provides Lane-Good outputs that can directly drive external common anode LED modules to indicate the presence and link-up state of each lane. The PEX 8524 provides PEX_LANE_GOOD[7:0]# and PEX_LANE_GOOD[31:16]# outputs. These outputs are used to determine which SerDes are active, and also provide the visual indication of the final negotiated link width. 332 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 17 17.1 Hot Plug Support Hot Plug Purpose and Capability Hot Plug capability allows card insertion and extraction from a running system without adversely affecting the system. Card insertion or extraction is accomplished for faulty card repair or system reconfiguration without system down time. Hot Plug capability allows systems to isolate faulty cards in the event of a failure. The PEX 8524 contains one Hot Plug controller per port. Each Hot Plug controller is compliant with the PCI Standard Hot Plug r1.0. 17.1.1 Hot Plug Controller Capabilities * Insertion and removal of PCI Express cards without removing system power * Hot Plug controller * Card-present and MRL (Manually operated Retention Latch) sensor signals supported * Power Indicator and Attention Indicator output signals controlled * Attention button switch monitored * Power fault detection and Faulty card isolation * Power switch for controlling downstream device power * Generates PME (Power Management Event) for a Hot Plug event in a sleeping system (D3hot) * Presence detect is accomplished through an in-band SerDes receiver detect mechanism or by using the HP_PRSNT[3:0]# or HP_PRSNT[11:8]# signals PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 333 Hot Plug Support 17.1.2 PLX Technology, Inc. Hot Plug Port External Signals The PEX 8524 Hot Plug controllers contain nine Hot Plug signals, delineated in Table 17-1. Actual signal-to-ball mapping is delineated in Table 3-4, "PEX 8524 Hot Plug Signals - 72Balls," on page 14. Table 17-1. Hot Plug Signals HP_ATNLED# HP_BUTTON# HP_CLKEN# HP_MRL# Type Description Output Hot Plug Attention LED Outputs Per Port Active-Low Slot Control Logic output used to drive the Attention Indicator. Output is set low to illuminate indicator, as follows: High/Off = Normal Operation Low/On = Slot Operational Problem Blinking = Slot is identified at the user's request Blinking Frequency = 2.0 Hz, 50% Duty cycle Hot Plug Attention Button Input Per Port Active-Low Slot Control Logic input, directly connected to the Attention Button which is pressed by the user to request Hot Plug operations. Implemented on the switch or downstream device. PR EL IM IN AR Y Signal Name Input Output Input Reference Clock Enable Output Per Port Hot Plug Manually Operated Retention Latch Sensor Inputs Per Port Active-Low Slot Control Logic and Power Controller input directly connected to the MRL sensor: High = Card is not available or not properly seated in slot Low = Card is properly seated in slot HP_PERST# Output HP_PRSNT# Input Combination of Hot Plug PRSNT1# and PRSNT2# Inputs Per Port Active-Low input, connected to external logic that outputs PRSNT1# and PRSNT2# directly from the slot's PRSNT1# and PRSNT2# signals. HP_PWREN# Output Active-Low Hot Plug Power Enable Output Per Port Slot Control Logic output that controls the slot power state. When this signal is low, power is enabled to the slot. HP_PWRFLT# Input Hot Plug Power Fault Input Per Port Active-Low input indicating that the power controller for the slot detected a power fault on one or more supply rails. HP_PWRLED# 334 Output Active-Low Reset Output Per Port Hot Plug Power LED Output Per Port Active-Low Slot Control Logic output used to drive the Power Indicator: Message generated High/Off = Slot is powered off. Card insertion or removal is permitted. Low/On = Card insertion or removal is not permitted. Blinking = Slot is in the process of powering up or down. Blinking Frequency = 2.0 Hz, 50% Duty cycle. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 17.2 PCI Express Capabilities Registers PCI Express Capabilities Registers The Hot Plug configuration, capabilities, command, status and events are included in the PEX 8524 PCI Express Capabilities registers. The applicable register map is delineated in Table 17-2. Table 17-2. PCI Express Capabilities Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slot Capabilities Slot Status 17.3 7Ch Slot Control 80h Hot Plug Interrupts PR EL IM IN AR Y HPC supports Hot Plug interrupt generation on the following events: * Attention button pressed * Power fault detected * MRL sensor changed * Presence detect changed * Command complete set Depending on the Downstream port power state, a Hot Plug event can generate a system interrupt or PME. When the PEX 8524 Downstream port is in the D0 power state, Hot Plug events generate a system interrupt; when not in the D0 state, a PME interrupt is generated on Hot Plug events. The Command Completed bit does not generate a PME interrupt. When the system is in Sleep mode, Hot Plug operation causes a wakeup of the system using PME logic. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 335 Hot Plug Support 17.4 PLX Technology, Inc. Hot Plug Card Insertion and Removal Process The card insertion procedure supported by the PEX 8524 is delineated in Table 17-3. The card removal procedure is delineated in Table 17-4. Table 17-3. Hot Plug Card Insertion Process Operator Lock the MRL (manually operated retention latch) Press Attention Button Power Indicator blinks Power Indicator ON 336 1. 2. 3. 4. Presence Detect State bit is set. Presence Detect Change Enable bit is set. Interrupt message generated, if enabled. Interrupt de-assertion message transmitted, if enabled. 5. 6. 7. 8. MRL Sensor Present bit = 0b. MRL Sensor Changed bit is set. Interrupt message generated, if enabled. Interrupt de-assertion message transmitted, if enabled. Software Presence Detect Change Enable bit is cleared. PR EL IM IN AR Y Place card in slot Hot Plug Controller 9. Attention Button Present bit is set. 10. Interrupt message generated, if enabled. 11. Interrupt de-assertion message transmitted, if enabled. 12. Power Indicator Control = 10b 13. Power indicator blink-message is transmitted downstream. 14. Command Complete bit is set. 15. Interrupt message generated, if enabled. 16. Interrupt de-assertion message transmitted, if enabled. 17. 18. 19. 20. Power Indicator Control = 01b After TPCC delay, Command Complete bit is set. Interrupt message generated, if enabled. Interrupt de-assertion message transmitted, if enabled. MRL Sensor Changed bit is cleared. Attention Button Present bit is cleared. Write to Power Indicator Control to blink the power LED to indicate card is being powered up. Command Complete bit is cleared. Write to Power Indicator Control bit in the Control register to turn ON power to the port. Command Complete bit is cleared. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Hot Plug Card Insertion and Removal Process Table 17-4. Hot Plug Card Removal Process Operator Hot Plug Controller 1. Attention Button Present bit is set. 2. Interrupt message generated, if enabled. 3. If the attention button is present on the downstream device, the "Attention Button" message is received, and the Attention Button Present bit is set. 4. Interrupt message generated bit is cleared. Press Attention Button Power Indicator OFF Unlock the MRL (Manually operated Retention Latch) Remove card from slot Attention Button Present bit is cleared. Write to Power Indicator Control to blink the power LED, to indicate card is being powered down. Command Complete bit is cleared. PR EL IM IN AR Y Power Indicator blinks 5. Power Indicator Control = 10b. 6. Power Indicator Blink message transmitted to downstream device. 7. Command Complete bit is set. 8. Interrupt message generated, if enabled. 9. Interrupt de-assertion message transmitted, if enabled. Software 10. 11. 12. 13. Power Indicator Control = 0b. After TPCC delay, Command Complete bit is set. Interrupt message generated, if enabled. Interrupt de-assertion message transmitted, if enabled. 14. 15. 16. 17. MRL Sensor Present bit = 1b. MRL Sensor Change Enable bit is set. Interrupt message generated, if enabled. Interrupt de-assertion message transmitted, if enabled. 18. 19. 20. 21. Presence Detect State bit is cleared. Presence Detect Change Enable bit is set. Interrupt message generated, if enabled. Interrupt de-assertion message transmitted if enabled. Write to Power Indicator Control bit in the Control register, to turn OFF power to the port. Command Complete bit is cleared. MRL Sensor Change Enable bit is cleared. Presence Detect Change Enable bit is cleared. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 337 PLX Technology, Inc. PR EL IM IN AR Y Hot Plug Support 338 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 18 18.1 Electrical Specifications PEX 8524 Power-On Sequence The PEX 8524 requires three different voltage sources: * 3.3V for I/O power and clock PLL power * 1.0 to 1.8V for SerDes transmitter common mode biasing * 1.0V for SerDes/core power VDD10, VDD10S, and VDD10A should power up first, and power down last. If sequenced properly, all supply rails should power up within 50 ms of each other. 18.2 Absolute Maximum Ratings Note: Conditions that exceed the Absolute Maximum limits may destroy the device. Table 18-1. Absolute Maximum Rating (All Voltages Referenced to VSS System Ground) Item I/O Interface Supply Voltage PLL Supply Voltage SerDes Analog Supply Voltage Symbol Absolute Maximum Rating Units VDD33 -0.5 to +4.6 V VDD33A -0.5 to +4.6 V VDD10A -0.3 to +3.0a V +3.0a V SerDes Digital Supply Voltage VDD10S -0.3 to Core (Logic) Supply Voltage VDD10 -0.3 to +3.0 V SerDes Termination Voltage VTT_PEX -0.3 to +3.0 V Input Voltage (3.3V Interface) VI -0.3 to +4.6 V Operating Case Temperature TC -20 to +75 C TSTG -55 to +150 C Storage Temperature a.The SerDes Analog and Digital power supplies must track within 0.01V of each other. Table 18-2. Logic/Control Input and Output Capacitance Item Input Ball Symbol CIN Output Ball COUT In/Out and Three-State Ball CI/O Conditions VDD33/A = 0.0 V VDD10/A/S = 0.0 V Min Typ Max Unit - 4 6 pF - 6 10 pF - 6 10 pF PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 339 Electrical Specifications PLX Technology, Inc. Table 18-3. PEX 8524 Power Dissipation* Wattage (W) Value Traffic Typical Light Maximum Typical Medium Maximum Typical High SerDes VTT (1.5V) Core VDD10 (1.0V) VDD33 (3.3V) Total 0.99 0.72 1.99 0.07 3.77 1.47 0.81 2.88 0.08 5.24 0.99 0.72 2.29 0.07 4.07 1.47 0.81 3.35 0.08 5.71 0.99 0.72 2.59 0.07 4.37 1.47 0.81 3.80 0.08 6.16 PR EL IM IN AR Y Maximum SerDes VDD10 (1.0V) * Legend for Table 18-3: 340 Light Traffic Host-Centric traffic, 75% lanes active, 50% link utilization Medium Traffic Host-Centric traffic, all lanes active, 50 to 70% link utilization Heavy Traffic Peer-to-peer, all lanes active, 80 to 90% link utilization Typical Nominal process, room temperature and nominal voltage Maximum Fast/fast process, -40C temperature and worst voltage Maximum Power/SerDes Quad 325 mW PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Thermal Characteristics 18.2.1 Thermal Characteristics The PEX 8524 requires 1 m/s of air flow and a heat sink for commercial operating temperatures (0 to 70C) in worst case usage. The recommended heat sink dimensions are illustrated in Figure 18-1. Note: Heat sink and air flow requirements for industrial operating temperatures (-40 to +85C) to be provided later. Table 18-4. Package Thermal Resistance Linear Air Flow 1 m/s 2 m/s 7.6 6.1 5.3 Comments With heat sink PR EL IM IN AR Y Static (Convection Only) Figure 18-1. PEX 8524 Copper Fin Heat Sink (38 x 38 x 12.7 mm) PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 341 Electrical Specifications 18.3 PLX Technology, Inc. Digital Interface Operating Characteristics Operating Conditions - VDD33 = 3.3V 0.3 V, VDD10 = 1.0V 0.1 V, TA = -40 to 85C, unless specified otherwise Table 18-5. Digital Logic Interface Operating Electrical Characteristics Symbol Parameter VDD33 Ranges and Limits Test Conditions Units Min Typ Max Operating Voltage (I/O) 3.0 3.3 3.6 V VDD33A Operating Voltage for PLL 3.0 3.3 3.6 V VDD10 Operating Voltage (Core) 0.9 1.0 1.1 V VDD10 1.5 1.8 V VTT_PEX SerDes Termination Voltage Average I/O Power Supply Current IDD10 Average Core Power Supply Current VDD33 = 3.6V, f = 100 MHza mA PR EL IM IN AR Y IDD33 VDD10 = 1.1V, f = 100 MHza VIL Input Low Voltage VIH Input High Voltage IIN Input Leakage Current 0V < VIN < VDD33 VOL Output Low Voltage VOH Output High Voltage mA 0.8 2.0 V V -10.0b +10.0b A ILOAD = 12 mAc VSS 0.2VDD V ILOAD = -12 mAc 0.8VDD VDD V a. The PEX_REFCLK is used to internally synthesize a 250-MHz clock for the SerDes modules and core logic. b. Current into the ball is delineated as "+". Current out of the ball is delineated as "-". c. These are CMOS technology I/O balls with TTL-compatible levels. 342 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 18.3.1 SerDes/Lane Interface DC Characteristics SerDes/Lane Interface DC Characteristics Operating Conditions - VDD33A = 3.3V 0.3 V, VDD10S = VDD10A = 1.0V 0.1 V, TA = -40 to 85C, unless specified otherwise Table 18-6. SerDes Interface DC Electrical Characteristics Symbol Parameter Test Conditions Min Typ Max Units VDD10A SerDes Analog Supply Voltagea 0.9 1.0 1.1 V VDD10S SerDes Analog Supply Voltagea 0.9 1.0 1.1 V IDDA/S Average SerDes Supply Current PEX_REFCLKb = 100 MHz mA PEX_PET Transmit Outputs Differential Peak-to-Peak Output Voltage 0.8 1.0 1.2 V VTX-DE-RATIO De-emphasis differential output voltage ratio -3.5 -7.96 dB VTX-CM-AC_P RMS AC Peak Common-mode Output Voltage 20 mV VTX-CM-DC-ACTIVE- Absolute Delta between DC Commonmode during L0 and Electrical Idle 0.0 100 mV Maximum Common mode Voltage Delta between PEX_PETn and PEX_PETp 0.0 25 mV VTX-IDLE-DIFF_P Electrical-Idle Differential-Peak Output Voltage 0.0 20 mV VTX-RCV-DETECT Amount of Voltage change allowed during Receiver Detection 600 mV 3.6 mV 90 mA 120 Ohm PR EL IM IN AR Y VTX-DIFF_P-P 0.0 Differential Output Impedance 80 Output Impedance per output and for all power states 40 Ohm RLTX-DIFF Differential Return Loss 12 dB RLTX-CM Common-mode Return Loss 6.0 dB IDLE-DELTA VTX-CM-DCLINE-DELTA VTX-DC-CM TX DC Common-mode Voltage ITX-SHORT Output Short-Circuit current ZTX-DIFF-DC ZTX-DC 0.0 VTX-OUT = 0.0V 100 PEX_PER Receive Inputs VRX-DIFF_P-P Differential Peak-to-Peak Input Voltage VRX-IDLE-DET- Idle detect threshold voltage DIFF_P-P 0.175 1.200 V 65 175 mV 150 mV VRX-CM-AC_P Receiver Common-mode voltage for AC coupling ZRX-DIFF-DC DC Differential Input Impedance 80 100 120 Ohm DC Input Impedance 40 50 60 Ohm ZRX-DC ZRX-HIGH-IMP-DC Power-Down DC Input Impedance 200k PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Ohm 343 Electrical Specifications PLX Technology, Inc. Table 18-6. SerDes Interface DC Electrical Characteristics (Cont.) Symbol Parameter Test Conditions Min Typ Max Units RLRX-DIFF Differential Return Loss 15 dB RLRX-CM Common-mode Return Loss 6.0 dB a.The SerDes Analog and Digital power supplies must track within 0.01V of each other. PR EL IM IN AR Y b.The PEX_REFCLK is used to internally synthesize a 250-MHz clock for the SerDes modules and core logic. 344 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 18.4 AC Specifications AC Specifications Operating Conditions - VDD33A = 3.3V 0.3 V, VDD10S = VDD10A = 1.0V 0.1 V, TA = -40 to 85C, unless specified otherwise Table 18-7. AC Electrical Characteristics for SerDes Interfaces Symbol Parameter Test Conditions Min Typ Max Units 399.88 400 400.12 ps -300 ppm 2.5 +300 ppm Gbits/s PEX_PET Transmit Outputs UI Unit Interval FTX-CLK Transmit Output Frequency TTX-RISE D+/D- TX Output rise time 20 to 80% 0.125 0.3 UI TTX-FALL D+/D- TX Output fall time 20 to 80% 0.125 0.3 UI Minimum idle time for transmitter TTX-IDLE-TODIFF-DATA Transmitter recovery time from Idle state to fully active transmit state 20 UI TTX-SKEW Lane-to-lane static output skew for all lanes in port/link 1.3 ns TTX-EYE 50 PR EL IM IN AR Y TTX-IDLE-MIN Transmitter Eye width UI 0.7 UI PEX_PER Receive Inputs UI TRX-SKEW TRX-IDLE-DETDIFF-ENTERTIME TRX-EYE LRX-SKEW Unit Interval 399.88 400.12 ps Lane-to-lane skew compensation capability for all lanes in port/link 20 ns Maximum time required for receiver to recognize and signal an unexpected idle on link 10 ms Receiver Eye width 400 0.4 UI Total Skew 20 ns Table 18-8. Reference Clock AC and DC Characteristics Symbol FREFCLK Parameter Min Typ Max Units Notes 1 Reference Clock Frequency 100 MHz VCM Input Common mode Voltage 0.65 V TR/TF Clock Input Rise/Fall Time VSW Differential Input Voltage Swing JCLK-REF DCREFCLK 2 ns 1.6 V 0.1 UI 60 % -300 +300 ppm 30 33 KHz 0.6 Input Jitter (Peak-to-Peak) Input Clock Duty Cycle PPM Reference Clock Tolerance FMOD Spread-Spectrum Modulation Frequency 40 50 2 Notes: 1. PEX_REFCLKp/n must be AC coupled. Use 0.01 to 0.1 F ceramic capacitors. 2. UI refers to PCI Express Transmit/Receive Unit Interval. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 345 PLX Technology, Inc. PR EL IM IN AR Y Electrical Specifications 346 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Chapter 19 Mechanical Specifications 19.1 PEX 8524 Mechanical Specifications 19.1.1 PEX 8524 Package Specifications The PEX 8524 is offered in a 35-mm square 680-pin EHBGA (Enhanced Heat-spreader BGA) package. Package specifications are delineated in Table 19-1. Unpopulated BGA balls facilitate card design and placement of card level de-coupling capacitors between VDD10, VDD10A, VDD10S, VDD33, and VSS/Ground. Table 19-1. PEX 8524 680-Ball EHBGA Package Specifications Parameter Specification Package Type Enhanced Heat-spreader Ball Grid Array Package Dimensions 35 x 35 mm (approximately 2.23 mm high) Number of Populated BGA balls TBD Number of BGA balls assigned TBD Number of unpopulated BGA balls TBD Ball matrix pattern 34 x 34 (10 x 10 center area reserved for Ground) Ball pitch 1.00 mm Ball diameter 0.60 0.15 mm Ball spacing 0.40 mm PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 347 Mechanical Specifications PEX 8524 Mechanical Drawing Figure 19-1. PEX 8524 680-Ball EHBGA Mechanical Drawing 34 4321 30o Typ 33.00 Bottom View 1.00 PR EL IM IN AR Y A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 35.00 19.1.2 PLX Technology, Inc. 1.00 33.00 0.20 (3X) Ball A1 Corner Identification 348 0.56 2.23 1.17 DIMENSIONS: Dimensions in mm; all dimensions are Nominal 35.00 30.00 4.00 45o 35.00 0.50 Heat Slug Exposed Area PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 4 N/C VSS N/C VSS STRAP_MO DE_SEL0 PEX_PERST STRAP_MO # DE_SEL1 HP_BUTTO HP_CLKEN N1# 8# HP_ATNLE HP_PWRLE D1# D8# E F G H J K VDD10 HP_PERST PEX_LANE_ PEX_LANE_ 9# GOOD7# GOOD16# PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential VSS VSS AJ AK N/C 2 N/C 1 AP N/C N/C AN VSS VSS PEX_REFCL PEX_REFCL Kn Kp VSS AM AL N/C STRAP_FA ST_BRING UP# VDD33 AH 3 VSS VDD10S VDD10S VSS VSS VSS N/C HP_CLKEN HP_BUTTO 0# N9# AG VSS N/C N/C HP_PERST HP_MRL9# 0# HP_PWRLE HP_ATNLE D0# D9# AD AF N/C HP_PRSNT HP_PWRFL 0# T9# AC AE N/C N/C HP_PWRFL HP_PRSNT T0# 9# HP_PWREN HP_PWREN 0# 9# AB 6 VDD10S VSS VSS VDD10S VDD10A VDD33A VDD10 VDD33 VDD10 VSS VDD10 PEX_PETp1 VSS PEX_PERp1 PEX_PERn1 PEX_PERn1 7 PEX_PERp1 7 VSS PEX_PETp1 7 4 5 6 PEX_PETn0 VTT_PEX0 PEX_PETn1 PEX_PETp0 VSS PEX_PERp0 PEX_PERn0 VSS VSSA_PLL VSS N/C N/C N/C N/C VDD33 VDD33 HP_ATNLE HP_PWRLE PEX_LANE_ PEX_LANE_ D0# D9# GOOD6# GOOD17# Y N/C VSS AA HP_MRL0# VDD10 HP_CLKEN HP_BUTTO PEX_LANE_ PEX_LANE_ 1# N8# GOOD4# GOOD19# HP_BUTTO HP_CLKEN PEX_LANE_ PEX_LANE_ N0# 9# GOOD5# GOOD18# V VDD10 VDD33 HP_PERST PEX_LANE_ PEX_LANE_ HP_MRL8# 1# GOOD2# GOOD21# HP_PWRLE HP_ATNLE PEX_LANE_ PEX_LANE_ D1# D8# GOOD3# GOOD20# T U W VDD33 HP_PRSNT HP_PWRFL PEX_LANE_ PEX_LANE_ 1# T8# GOOD1# GOOD22# R VDD33 VDD10 VDD33 VDD10 VSS VDD33 VDD10 VDD10 VDD10S VSS VSS STRAP_UP STRM_POR TSEL2 STRAP_UP STRM_POR TSEL3 N/C JTAG_TRST # N/C VSS VSS VSS VDD10S VSS P HP_MRL1# STRAP_UP HP_PERST STRM_POR 8# TSEL0 STRAP_UP HP_PWRFL HP_PRSNT STRM_POR T1# 8# TSEL1 N/C N/C N/C N/C N/C VSS VDD10S HP_PWREN HP_PWREN PEX_LANE_ PEX_LANE_ 1# 8# GOOD0# GOOD23# N M L VSS PEX_PERn1 6 PEX_NT_R JTAG_TCK JTAG_TDO JTAG_TMS ESET# JTAG_TDI VSS PEX_PERp1 6 D VDD10S PEX_PETp1 6 VSS VDD10S VSS N/C 5 PEX_PETn1 PEX_PETn1 VTT_PEX8 6 7 C 3 VSS N/C 2 N/C B 1 N/C 7 7 VSS VDD10S VDD10S VSS VDD10A VDD10A VSS VDD10S VDD10S VSS 8 9 10 VDD10S VSS VSS VDD10 VDD10 VSS VSS VDD10S PEX_PETp3 VSS PEX_PERp3 PEX_PERn3 PEX_PERn1 9 PEX_PERp1 9 VSS PEX_PETp1 9 8 9 10 PEX_PETn2 VTT_PEX1 PEX_PETn3 PEX_PETp2 VSS PEX_PERp2 PEX_PERn2 PEX_PERn1 8 PEX_PERp1 8 VSS PEX_PETp1 8 PEX_PETn1 PEX_PETn1 VTT_PEX9 8 9 11 11 VSS VDD10S VDD10S VSS VDD10 VDD10 VSS VDD10S VDD10S VSS 12 13 14 PEX_PERp4 PEX_PERn4 PEX_PETp2 1 VDD10S VSS VSS VDD10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD10 VSS VSS PEX_PETp5 VSS PEX_PERp5 PEX_PERn5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PEX_PERn2 1 PEX_PERp2 1 VSS 12 13 14 PEX_PETn4 VTT_PEX2 PEX_PETn5 PEX_PETp4 VSS VDD10S VDD10S PEX_PETp2 2 VDD10S PEX_PETp2 3 PEX_PETn2 PEX_PETn2 VTT_PEX11 2 3 VDD10S VSS 21 22 PEX_PETp2 4 VDD10S PEX_PETp2 5 PEX_PETn2 PEX_PETn2 VTT_PEX12 4 5 BGA680 15 Vega24AA_Pinout_050421.xls:8524 16 17 18 19 35x35 20 VSS 23 VDD10S VSS 24 25 26 PEX_PETp2 6 VDD10S PEX_PETp2 7 PEX_PETn2 PEX_PETn2 VTT_PEX13 6 7 15 VSS VDD10S VDD10S VSS VSS PEX_PERn2 2 PEX_PERp2 2 VSS VDD10S VSS VSS VDD10 VSS VSS VSS VSS VSS VSS VSS PEX_PETp7 VSS PEX_PERp7 PEX_PERn7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PEX_PERn2 3 PEX_PERp2 3 VSS UP Die VSS VSS VSS VDD10 VSS VSS 16 17 18 PEX_PETn6 VTT_PEX3 PEX_PETn7 PEX_PETp6 VSS PEX_PERp6 PEX_PERn6 VSS VSS VSS VSS VSS VSS VSS VSS VSS <= Pad 1 VDD10A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD10A VSS VDD10S 19 VSS VDD10S VDD10S VSS VDD10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD10 VSS VDD10S 20 N/C N/C VSS N/C N/C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PEX_PERn2 4 PEX_PERp2 4 VSS 21 VDD10 VDD10S VSS VSS VDD10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD10 VSS VSS 22 N/C N/C VSS N/C N/C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PEX_PERn2 5 PEX_PERp2 5 VSS 23 VSS VDD10S VDD10S VSS VDD10 VDD10A VSS VDD10S 24 N/C N/C VSS N/C N/C PEX_PERn2 6 PEX_PERp2 6 VSS 25 VDD10 VDD10S VSS VSS VDD10 VDD10 VSS VSS 26 N/C N/C VSS N/C N/C PEX_PERn2 7 PEX_PERp2 7 VSS PR EL IM IN AR Y PEX_PERn2 0 PEX_PERp2 0 VSS PEX_PETp2 0 PEX_PETn2 PEX_PETn2 VTT_PEX10 0 1 27 27 VSS VDD10S VDD10S VSS VDD10 VDD10 VSS VDD10S VDD10S VSS 28 29 30 28 N/C N/C VSS N/C N/C PEX_PERn2 8 PEX_PERp2 8 VSS PEX_PETp2 8 29 VDD10 VDD10S VSS VSS VDD10 VDD10 VSS VSS VDD10S 31 VDD10S PEX_PERn2 9 30 N/C N/C VSS N/C N/C VDD10 VDD33 VDD10 VDD33 VDD10 VSS VDD10 VDD33 VDD10 VDD33 VSS VDD10 VDD33 VDD10 VSS VDD10 VDD33 VDD10 VSS VDD33 VDD10 VSS VDD10 32 N/C PEX_LANE_ GOOD31# N/C 31 VSS VDD10S VDD10S VSS VDD10S VSS VSS VDD33 N/C 34 STRAP_TE STMODE2 STRAP_TE STMODE0 VSS PEX_PERn3 1 PEX_PERp3 1 VSS PEX_PETp3 1 HP_PWREN HP_PWREN 11# 2# HP_PRSNT HP_PWRFL 11# T2# HP_PERST HP_MRL2# 11# HP_PWRLE HP_ATNLE D11# D2# HP_CLKEN HP_BUTTO 11# N2# HP_BUTTO HP_CLKEN N10# 3# HP_ATNLE HP_PWRLE D10# D3# HP_MRL10 HP_PERST # 3# 32 N/C N/C VSS N/C N/C VSS N/C EE_CS# N/C 33 VDD10 VDD10S VSS VSS VDD10S VDD10S EE_PR# EE_SK 34 N/C N/C VSS N/C N/C VSS EE_DI EE_DO HP_BUTTO HP_CLKEN N11# 2# AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N HP_PWREN HP_PWREN 10# 3# HP_PWRFL HP_PRSNT T10# 3# M L K J H G F E D C B A HP_PRSNT HP_PWRFL 10# T3# HP_PERST HP_MRL3# 10# HP_PWRLE HP_ATNLE D10# D3# HP_CLKEN HP_BUTTO 10# N3# STRAP_TE STMODE3 STRAP_TE STMODE1 VDD10S VDD10S VSS VSS VDD10S STRAP_ST HP_PWRFL HP_PRSNT N0_PORTC T11# 2# FG4 STRAP_ST HP_MRL11 HP_PERST N0_PORTC # 2# FG2 STRAP_ST HP_ATNLE HP_PWRLE N0_PORTC D11# D2# FG0 N/C N/C PEX_LANE_ GOOD29# PEX_LANE_ GOOD30# N/C N/C PEX_LANE_ GOOD27# N/C PEX_LANE_ GOOD26# PEX_LANE_ GOOD28# N/C PEX_LANE_ GOOD25# VSS STRAP_NT _UPSTRM_ PORTSEL0 STRAP_NT _UPSTRM_ PORTSEL1 STRAP_ST N1_PORTC FG0 STRAP_ST N1_PORTC FG2 VDD33 VDD33 N/C VSS PEX_PERn3 0 PEX_PERp3 0 VSS PEX_PETp3 0 N/C STRAP_ST N0_PORTC FG3 STRAP_ST N0_PORTC FG1 33 PEX_PETn3 PEX_PETn3 VTT_PEX15 1 0 PEX_LANE_ GOOD24# STRAP_NT _UPSTRM_ PORTSEL2 STRAP_NT _UPSTRM_ PORTSEL3 STRAP_ST N1_PORTC FG1 STRAP_ST N1_PORTC FG3 VDD33 VDD33 N/C VSS VSS VSS PEX_PERp2 9 VDD10A VDD10S VDD10S VSS VSS PEX_PETp2 9 PEX_PETn2 PEX_PETn2 VTT_PEX14 8 9 19.1.3 A June, 2005 PEX 8524 Physical Layout PEX 8524 Physical Layout Figure 19-2. PEX 8524 680-Ball EHBGA Physical Layout 349 PLX Technology, Inc. PR EL IM IN AR Y Mechanical Specifications 350 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential June, 2005 Serial EEPROM Memory Map Appendix A A.1 Serial EEPROM Memory Map Serial EEPROM Memory Map Figure A-1. PEX 8524 Memory Map PEX 8524 Port 0 0K 4K Port 1 8K 12K 16K PR EL IM IN AR Y Reserved 32K Port 8 36K Port 9 Port 10 Port 11 40K 44K 48K Reserved 64K NT-Port Virtual Interface NT-Port Link Interface 68K 72K Reserved 128K PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 351 Serial EEPROM Memory Map Table A-1. PLX Technology, Inc. PEX 8524 Serial EEPROM Memory Map Port Register Loaded from Listed EEPROM Address 000h 004h 008h 00Ch 010h 014h 018h 01Ch 020h 024h 028h 02Ch 030h 034h 038h 03Ch 040h 044h 048h 04Ch 050h 054h 058h 05Ch 060h 064h 068h 06Ch 070h 352 Register Name Product Identification Status/Command Class Code and Revision ID Miscellaneous Control Base Address 0 Base Address 1 Bus Number Secondary Status Memory Base and Limit Address Prefetchable Memory Base and Limit Addressing Prefetchable Memory Upper Base Address[63:32] Prefetchable Memory Upper Limit Address[63:32] I/O Base Address[31:16] and I/O Limit Address[31:16] Capabilities Pointer Expansion ROM Base Address Bridge Control and Interrupt Signal Power Management Capabilities Power Management Status and Control Message Signaled Interrupt Control Message Address[31:0] Message Address[63:32] Message Data Reserved Reserved Reserved Reserved PCI Express Capabilities Device Capabilities Device Status and Control Station 0 Station 1 Non-Transparent Ports Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h 321h 322h 323h 324h 325h 326h 327h 328h 329h 32Ah 32Bh 32Ch 32Dh 32Eh 32Fh 330h 331h 332h 333h 334h 335h 336h 4B8h 4B9h 4BAh 4BBh 4BCh 4BDh 4BEh 4BFh 4C0h 4C1h 4C2h 4C3h 4C4h 4C5h 4C6h 4C7h 4C8h 4C9h 4CAh 4CBh 4CCh 4CDh 4CEh 4CFh 4D0h 4D1h 4D2h 4D3h 4D4h 7D2h 7D3h 7D4h 7D5h 7D6h 7D7h 7D8h 7D9h 7DAh 7DBh 7DCh 7DDh 7DEh 7DFh 7EOh 7E1h 7E2h 7E3h 7E4h 7E5h 7E6h 7E7h 7E8h 7E9h 7EAh 7EBh 7ECh 7EDh 7EEh 85Ch 85Dh 85Eh 85Fh 860h 861h 862h 863h 864h 865h 866h 867h 868h 869h 86Ah 86Bh 86Ch 86Dh 86Eh 86Fh 870h 871h 872h 873h 874h 875h 876h 877h 878h 8E6h 8E7h 8E8h 8E9h 8EAh 8EBh 8ECh 8EDh 8EEh 8EFh 8F0h 8F1h 8F2h 8F3h 8F4h 8F5h 8F6h 8F7h 8F8h 8F9h 8FAh 8FBh 8FCh 8FDh 8FEh 8FFh 900h 901h 902h 970h 971h 972h 973h 974h 975h 976h 977h 978h 979h 97Ah 97Bh 97Ch 97Dh 97Eh 97Fh 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch A68h A69h A6Ah A6Bh A6Ch A6Dh A6Eh A6Fh A70h A71h A72h A73h A74h A75h A76h A77h A78h A79h A7Ah A7Bh A7Ch A7Dh A7Eh A7Fh A80h A81h A82h A83h A84h PR EL IM IN AR Y Register Address PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Table A-1. Serial EEPROM Memory Map PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address Register Address Link Capabilities Link Status and Control Slot Capabilities Slot Status and Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Station 0 Station 1 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Non-Transparent Ports Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 01Dh 01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 02Fh 030h 031h 032h 033h 034h 035h 036h 037h 038h 039h 03Ah 337h 338h 339h 33Ah 33Bh 33Ch 33Dh 33Eh 33Fh 340h 341h 342h 343h 344h 345h 346h 347h 348h 349h 34Ah 34Bh 34Ch 34Dh 34Eh 34Fh 350h 351h 352h 353h 354h 4D5h 4D6h 4D7h 4D8h 4D9h 4DAh 4DBh 4DCh 4DDh 4DEh 4DFh 4E0h 4E1h 4E2h 4E3h 4E4h 4E5h 4E6h 4E7h 4E8h 4E9h 4EAh 4EBh 4ECh 4EDh 4EEh 4EFh 4F0h 4F1h 4F2h 7EFh 7F0h 7F1h 7F2h 7F3h 7F4h 7F5h 7F6h 7F7h 7F8h 7F9h 7FAh 7FBh 7FCh 7FDh 7FEh 7FFh 800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 879h 87Ah 87Bh 87Ch 87Dh 87Eh 87Fh 880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h 9A1h 9A2h 9A3h 9A4h 9A5h 9A6h 9A7h 9A8h 9A9h 9AAh A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h AA1h AA2h PR EL IM IN AR Y 074h 078h 07Ch 080h 084h 088h 08Ch 090h 094h 098h 09Ch 0A0h 0A4h 0A8h 0ACh 0B0h 0B4h 0B8h 0BCh 0C0h 0C4h 0C8h 0CCh 0D0h 0D4h 0D8h 0DCh 0E0h 0E4h 0E8h Register Name 353 Serial EEPROM Memory Map Table A-1. PLX Technology, Inc. PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address 0ECh 0F0h 0F4h 0F8h 0FCh 100h 104h 108h 138h 13Ch 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 168h 16Ch 1B8h 1BCh 1C0h 1C4h 1C8h 1CCh 1D0h 1D4h 354 Register Name Reserved Reserved Reserved Reserved Reserved Device Serial Number Extended Capabilities Serial Number (Low) Serial Number (High) Device Power Budgeting Extended Capabilities Data Select Power Data Power Budget Capability Virtual Channel Budgeting Extended Capabilities Port VC Capability 1 Port VC Capability 2 Port VC Status and Control VC0 Resource Capability VC0 Resource Control VC0 Resource Status VC1 Resource Capability VC1 Resource Control VC1 Resource Status VC Arbitration Table Phase 7-0 VC Arbitration Table Phase 15-8 VC Arbitration Table Phase 23-16 VC Arbitration Table Phase 31-24 ECC Error Check Disable Error Handler 32-Bit Error Status Error Handler 32-Bit Error Mask Station 0 Probe Select Station 0 Station 1 Non-Transparent Ports Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 03Bh 03Ch 03Dh 03Eh 03Fh 040h 041h 042h 04Eh 04Fh 050h 051h 052h 053h 054h 055h 056h 057h 058h 059h 05Ah 05Bh 06Eh 06Fh 070h 071h 072h 073h 074h 075h 355h 356h 357h 358h 359h 35Ah 35Bh 35Ch 368h 369h 36Ah 36Bh 36Ch 36Dh 36Eh 36Fh 370h 371h 372h 373h 374h 375h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 4F3h 4F4h 4F5h 4F6h 4F7h 4F8h 4F9h 4FAh 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 526h 527h 528h 529h 52Ah 52Bh 52Ch 52Dh 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 820h 821h 822h 823h 824h 825h 826h 827h 828h 829h 82Ah 82Bh 82Ch 82Dh 840h 841h 842h 843h 844h 845h 846h 847h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 8AAh 8ABh 8ACh 8ADh 8AEh 8AFh 8B0h 8B1h 8B2h 8B3h 8B4h 8B5h 8B6h 8B7h 8CAh 8CBh 8CCh 8CDh 8CEh 8CFh 8D0h 8D1h 921h 922h 923h 924h 925h 926h 927h 928h 934h 935h 936h 937h 938h 939h 93Ah 93Bh 93Ch 93Dh 93Eh 93Fh 940h 941h 954h 955h 956h 957h 958h 959h 95Ah 95Bh 9ABh 9ACh 9ADh 9AEh 9AFh 9B0h 9B1h 9B2h 9BEh 9BFh 9C0h 9C1h 9C2h 9C3h 9C4h 9C5h 9C6h 9C7h 9C8h 9C9h 9CAh 9CBh 9DEh 9DFh 9E0h 9E1h 9E2h 9E3h 9E4h 9E5h AA3h AA4h AA5h AA6h AA7h AA8h AA9h AAAh AB6h AB7h AB8h AB9h ABAh ABBh ABCh ABDh ABEh ABFh AC0h AC1h AC2h AC3h AD6h AD7h AD8h AD9h ADAh ADBh ADCh ADDh PR EL IM IN AR Y Register Address PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Table A-1. Serial EEPROM Memory Map PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address 1D8h 1DCh 1E0h 1E4h 1F0h 1F4h 1F8h 1FCh 200h 204h 208h 20Ch 210h 214h 218h 21Ch 220h 224h 228h 22Ch 230h 234h 238h 23Ch 240h 244h 248h 24Ch 250h 254h Register Name Station 1 Probe Select Debug Control Power Management Hot Plug User Configuration TEC Control and Status TEC Performance Counter Software Controlled Lane Status ACK Transmission Latency Limit Reserved Reserved Reserved Reserved Reserved Test Pattern_0 Test Pattern_1 Test Pattern_2 Test Pattern_3 Physical Layer Status and Control Port Configuration Physical Layer Test Physical Layer Physical Layer Port Command Skip-Ordered Set Interval Quad SerDes_0 Diagnostics Data Quad SerDes_1 Diagnostics Data Quad SerDes_2 Diagnostics Data Quad SerDes_3 Diagnostics Data SerDes Nominal Current Select SerDes Driver Current Level_1 SerDes Driver Current Level_2 SerDes Driver Equalization Level Select_1 Station 0 Station 1 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Non-Transparent Ports Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 076h 077h 078h 079h 07Ch 07Dh 07Eh 07Fh 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 390h 391h 392h 393h 396h 397h 398h - - - - - - - - - - - - - - - - - - - - - - - 52Eh 52Fh 530h 531h 534h 535h 536h 537h 538h 539h 53Ah 53Bh 53Ch 53Dh 53Eh 53Fh 540h 541h 542h 543h 544h 545h 546h 547h 548h 549h 54Ah 54Bh 54Ch 54Dh 848h 849h 84Ah 84Bh 84Eh 84Fh 850h - - - - - - - - - - - - - - - - - - - - - - - 8D2h 8D3h 8D4h 8D5h 8D8h 8D9h 8DAh - - - - - - - - - - - - - - - - - - - - - - - 95Ah 95Bh 95Eh 95Fh 962h 963h 964h - - - - - - - - - - - - - - - - - - - - - - - 9E6h 9E7h 9E8h 9E9h 9ECh 9EDh 9EEh - - - - - - - - - - - - - - - - - - - - - A04h A05h ADEh ADFh AE0h AE1h AE4h AE5h AE6h - - - - - - - - - - - - - - - - - - - - - - - PR EL IM IN AR Y Register Address 355 Serial EEPROM Memory Map Table A-1. PLX Technology, Inc. PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address 258h 25Ch 260h 264h 28Ch 290h 2C8h 2CCh 2D0h 2D4h 2E8h 2ECh 2F0h 2F4h 308h 30Ch 318h 31Ch 348h 34Ch 350h 354h 358h 35Ch 360h 364h 368h 36Ch 370h 374h 356 Register Name SerDes Driver Equalization Level Select_2 Physical Layer Miscellaneous EEPROM Status and Control EEPROM Buffer Reserved Reserved Bus Number CAM 0 Bus Number CAM 1 Bus Number CAM 2 Bus Number CAM 3 Bus Number CAM 8 Bus Number CAM 9 Bus Number CAM 10 Bus Number CAM 11 I/O CAM_1 and I/O CAM_0 I/O CAM_3 and I/O CAM_2 I/O CAM_9 and I/O CAM_8 I/O CAM_11 and I/O CAM_10 AMCAM_0 Memory Limit and Base AMCAM_0 Prefetchable Memory Limit and Base[31:0] AMCAM_0 Prefetchable Memory Base[63:32] AMCAM_0 Prefetchable Memory Limit[63:32] AMCAM_1 Memory Limit and Base AMCAM_1 Prefetchable Memory Limit and Base[31:0] AMCAM_1 Prefetchable Memory Base[63:32] AMCAM_1 Prefetchable Memory Limit[63:32] AMCAM_2 Memory Limit and Base AMCAM_2 Prefetchable Memory Limit and Base[31:0] AMCAM_2 Prefetchable Memory Base[63:32] AMCAM_2 Prefetchable Memory Limit[63:32] Station 0 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 096h 097h 098h 099h 0A3h 0A4h 0B2h 0B3h 0B4h 0B5h 0BAh 0BBh 0BCh 0BDh 0C2h 0C3h 0C6h 0C7h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0D8h 0D9h 0DAh 0DBh 0DCh 0DDh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 54Eh 54Fh 550h 551h 55Bh 55Ch 56Ah 56Bh 56Ch 56Dh 572h 573h 574h 575h 57Ah 57Bh 57Eh 57Fh 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A06h A07h A08h A09h A13h A14h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PR EL IM IN AR Y Register Address PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Table A-1. Serial EEPROM Memory Map PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address 378h 37Ch 380h 384h 3C8h 3CCh 3D0h 3D4h 3D8h 3DCh 3E0h 3E4h 3E8h 3ECh 3F0h 3F4h 3F8h 3FCh 400h 404h 660h 668h 680h 684h 688h 68Ch 690h 694h 698h 69Ch Register Name AMCAM_3 Memory Limit and Base AMCAM_3 Prefetchable Memory Limit and Base[31:0] AMCAM_3 Prefetchable Memory Base[63:32] AMCAM_3 Prefetchable Memory Limit[63:32] AMCAM_8 Memory Limit and Base AMCAM_8 Prefetchable Memory Limit and Base[31:0] AMCAM_8 Prefetchable Memory Base[63:32] AMCAM_8 Prefetchable Memory Limit[63:32] AMCAM_9 Memory Limit and Base AMCAM_9 Prefetchable Memory Limit and Base[31:0] AMCAM_9 Prefetchable Memory Base[63:32] AMCAM_9 Prefetchable Memory Limit[63:32] AMCAM_10 Memory Limit and Base AMCAM_10 Prefetchable Limit and Memory Base[31:0] AMCAM_10 Prefetchable Memory Base[63:32] AMCAM_10 Prefetchable Memory Limit[63:32] AMCAM_11 Memory Limit and Base AMCAM_11 Prefetchable Limit and Memory Base[31:0] AMCAM_11 Prefetchable Memory Base[63:32] AMCAM_11 Prefetchable Memory Limit[63:32] TIC Control TIC Port Enable I/OCAM_0[xx:xx] I/OCAM_1[xx:xx] I/OCAM_2[xx:xx] I/OCAM_3[xx:xx] Reserved Reserved Reserved Reserved Station 0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 0DEh 0DFh 0E0h 0E1h 0F2h 0F3h 0F4h 0F5h 0F6h 0F7h 0F8h 0F9h 0FAh 0FBh 0FCh 0FDh 0FEh 0FFh 100h 101h 198h 19Ah 1A0h 1A1h 1A2h 1A3h 1A4h 1A5h 1A6h 1A7h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 596h 597h 598h 599h 5AAh 5ABh 5ACh 5ADh 5AEh 5AFh 5B0h 5B1h 5B2h 5B3h 5B4h 5B5h 5B6h 5B7h 5B8h 5B9h 650h 652h 658h 659h 65Ah 65Bh 65Ch 65Dh 65Eh 65Fh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PR EL IM IN AR Y Register Address 357 Serial EEPROM Memory Map Table A-1. PLX Technology, Inc. PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address Register Address 358 I/OCAM_8[xx:xx] I/OCAM_9[xx:xx] I/OCAM_10[xx:xx] I/OCAM_11[xx:xx] Reserved Reserved Reserved Reserved BAR_0 BAR_0[63:32] BAR_1 BAR_1[63:32] BAR_2 BAR_2[63:32] BAR_3 BAR_3[63:32] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BAR_8 BAR_8[63:32] BAR_9 BAR_9[63:32] BAR_10 BAR_10[63:32] Station 0 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 1A8h 1A9h 1AAh 1ABh 1ACh 1ADh 1AEh 1AFh 1B0h 1B1h 1B2h 1B3h 1B4h 1B5h 1B6h 1B7h 1B8h 1B9h 1BAh 1BBh 1BCh 1BDh 1BEh 1BFh 1C0h 1C1h 1C2h 1C3h 1C4h 1C5h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 660h 661h 662h 663h 664h 665h 666h 667h 668h 669h 66Ah 66Bh 66Ch 66Dh 66Eh 66Fh 670h 671h 672h 673h 674h 675h 676h 677h 678h 679h 67Ah 67Bh 67Ch 67Dh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PR EL IM IN AR Y 6A0h 6A4h 6A8h 6ACh 6B0h 6B4h 6B8h 6BCh 6C0h 6C4h 6C8h 6CCh 6D0h 6D4h 6D8h 6DCh 6E0h 6E4h 6E8h 6ECh 6F0h 6F4h 6F8h 6FCh 700h 704h 708h 70Ch 710h 714h Register Name PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Table A-1. Serial EEPROM Memory Map PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address Register Address BAR_11 BAR_11[63:32] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved VC0 Port 0 Capability VC1 Port 0 Capability VC0 Port 1 Capability VC1 Port 1 Capability VC0 Port 2 Capability VC1 Port 2 Capability VC0 Port 3 Capability VC1 Port 3 Capability Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved VC0 Port 8 Capability VC1 Port 8 Capability VC0 Port 9 Capability VC1 Port 9 Capability Station 0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 1C6h 1C7h 1C8h 1C9h 1CAh 1CBh 1CCh 1CDh 1CEh 1CFh 1D0h 1D1h 1D2h 1D3h 1D4h 1D5h 1D6h 1D7h 1D8h 1D9h 1DAh 1DBh 1DCh 1DDh 1DEh 1DFh 1E0h 1E1h 1E2h 1E3h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 67Eh 67Fh 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PR EL IM IN AR Y 718h 71Ch 720h 724h 728h 72Ch 730h 734h 738h 73Ch 740h 744h 748h 74Ch 750h 754h 758h 75Ch 760h 764h 768h 76Ch 770h 774h 778h 77Ch 780h 784h 788h 78Ch Register Name 359 Serial EEPROM Memory Map Table A-1. PLX Technology, Inc. PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address Register Address 360 VC0 Port 10 Capability VC1 Port 10 Capability VC0 Port 11 Capability VC1 Port 11 Capability Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Station 0 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 1E4h 1E5h 1E6h 1E7h 1E8h 1E9h 1EAh 1EBh 1ECh 1EDh 1EEh 1EFh 1F0h 1F1h 1F2h 1F3h 1F4h 1F5h 1F6h 1F7h 1F8h 1F9h 1FAh 1FBh 1FCh 1FDh 1FEh 1FFh 200h 201h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 69Ch 69Dh 69Eh 69Fh 6A0h 6A1h 6A2h 6A3h 6A4h 6A5h 6A6h 6A7h 6A8h 6A9h 6AAh 6ABh 6ACh 6ADh 6AEh 6AFh 6B0h 6B1h 6B2h 6B3h 6B4h 6B5h 6B6h 6B7h 6B8h 6B9h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PR EL IM IN AR Y 790h 794h 798h 79Ch 7A0h 7A4h 7A8h 7ACh 7B0h 7B4h 7B8h 7BCh 7C0h 7C4h 7C8h 7CCh 7D0h 7D4h 7D8h 7DCh 7E0h 7E4h 7E8h 7ECh 7F0h 7F4h 7F8h 7FCh 800h 804h Register Name PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Table A-1. Serial EEPROM Memory Map PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address 808h 80Ch 810h 814h 818h 81Ch 820h 824h 828h 82Ch 830h 834h 838h 83Ch 840h 844h 848h 84Ch 860h 864h 868h 86Ch 9F4h 9FCh A00h A04h A08h A0Ch A10h A14h Register Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Port 0 VC Capability_1 Port 1 VC Capability_1 Port 2 VC Capability_1 Port 3 VC Capability_1 Port 8 VC Capability_1 Port 9 VC Capability_1 Port 10 VC Capability_1 Port 11 VC Capability_1 INCH FC Update Pending Timer INCH Mode INCH Threshold Port 0 VC0 Posted INCH Threshold Port 0 VC0 Non-Posted INCH Threshold Port 0 VC0 Completion INCH Threshold Port 0 VC1 Posted INCH Threshold Port 0 VC1 Non-Posted INCH Threshold Port 0 VC1 Completion Station 0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 218h 219h 21Ah 21Bh 27Dh 27Fh 280h 281h 282h 283h 284h 285h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 6BAh 6BBh 6BCh 6BDh 6BEh 6BFh 6C0h 6C1h 6C2h 6C3h 6C4h 6C5h 6C6h 6C7h 6C8h 6C9h 6CAh 6CBh 6D0h 6D1h 6D2h 6D3h 735h 737h 738h 739h 73Ah 73Bh 73Ch 73Dh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PR EL IM IN AR Y Register Address 361 Serial EEPROM Memory Map Table A-1. PLX Technology, Inc. PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address A18h A1Ch A20h A24h A28h A2Ch A30h A34h A38h A3Ch A40h A44h A48h A4Ch A50h A54h A58h A5Ch B80h B84h B88h B98h B9Ch BFCh C00h C04h C08h C0Ch C10h C14h 362 Register Name INCH Threshold Port 1 VC0 Posted INCH Threshold Port 1 VC0 Non-Posted INCH Threshold Port 1 VC0 Completion INCH Threshold Port 1 VC1 Posted INCH Threshold Port 1 VC1 Non-Posted INCH Threshold Port 1 VC1 Completion INCH Threshold Port 2 VC0 Posted INCH Threshold Port 2 VC0 Non-Posted INCH Threshold Port 2 VC0 Completion INCH Threshold Port 2 VC1 Posted INCH Threshold Port 2 VC1 Non-Posted INCH Threshold Port 2 VC1 Completion INCH Threshold Port 3 VC0 Posted INCH Threshold Port 3 VC0 Non-Posted INCH Threshold Port 3 VC0 Completion INCH Threshold Port 3 VC1 Posted INCH Threshold Port 3 VC1 Non-Posted INCH Threshold Port 3 VC1 Completion EGCH Performance Counter_0 EGCH Performance Counter_1 EGCH Performance Counter_2 EGCH Performance Counter (24-Bit) EGCH Performance Control PLX-Specific Relaxed Ordering Mode ITCH VCnT Threshold_1 ITCH VCnT Threshold_2 ITCH VCnT Threshold_3 ITCH Port 0 VC0 Posted, Non-Posted Status ITCH Port 0 VC0 Completion, VC1 Posted Status ITCH Port 0 VC1 Non-Posted, Completion Status Station 0 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 2E0h 2E1h 2E2h 2E6h 2E7h 2FFh 300h 301h 302h 303h 304h 305h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 73Eh 73Fh 740h 741h 742h 743h 744h 745h 746h 747h 748h 749h 74Ah 74Bh 74Ch 74Dh 74Eh 74Fh 798h 799h 79Ah 79Eh 79Fh 7B7h 7B8h 7B9h 7BAh 7BBh 7BCh 7BDh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PR EL IM IN AR Y Register Address PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Table A-1. Serial EEPROM Memory Map PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address C18h C1Ch C20h C24h C28h C2Ch C30h C34h C38h C3Ch C40h C44h C48h C4Ch C50h C54h C58h C5Ch C60h C64h C68h C6Ch C70h C74h C78h C7Ch C80h C84h C88h C8Ch Register Name ITCH Port 1 VC0 Posted, Non-Posted Status ITCH Port 1 VC0 Completion, VC1 Posted Status ITCH Port 1 VC1 Non-Posted, Completion Status ITCH Port 2 VC0 Posted, Non-Posted Status ITCH Port 2 VC0 Completion, VC1 Posted Status ITCH Port 2 VC1 Non-Posted, Completion Status ITCH Port 3 VC0 Posted, Non-Posted Status ITCH Port 3 VC0 Completion, VC1 Posted Status ITCH Port 3 VC1 Non-Posted, Completion Status Memory BAR 2 Address Lower Memory BAR 3 Address Upper Memory BAR 4/5 Address Lower Memory BAR 4/5 Address Upper Memory BAR 2 Limit Lower Memory BAR 3 Limit Upper Memory BAR 4/5 Limit Lower Memory BAR 4/5 Limit Upper Look-up Table Entry 0 Look-up Table Entry 1 Look-up Table Entry 2 Look-up Table Entry 3 Look-up Table Entry 4 Look-up Table Entry 5 Look-up Table Entry 6 Look-up Table Entry 7 Look-up Table Entry 8 Look-up Table Entry 9 Look-up Table Entry 10 Look-up Table Entry 11 Look-up Table Entry 12 Station 0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 7BEh 7BFh 7C0h 7C1h 7C2h 7C3h 7C4h 7C5h 7C6h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9EFh 9F0h 9F1h 9F2h 9F3h 9F4h 9F5h 9F6h 9F7h 9F8h 9F9h 9FAh 9FBh 9FCh 9FDh 9FEh 9FFh A00h A01h A02h A03h - - - - - - - - - AE7h AE8h AE9h AEAh AEBh AECh AEDh AEEh AEFh AF0h AF1h AF2h AF3h AF4h AF5h AF6h AF7h AF8h AF9h AFAh AFBh PR EL IM IN AR Y Register Address 363 Serial EEPROM Memory Map Table A-1. PLX Technology, Inc. PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address Register Address 364 Look-up Table Entry 13 Look-up Table Entry 14 Look-up Table Entry 15 Look-up Table Entry 16 Look-up Table Entry 17 Look-up Table Entry 18 Look-up Table Entry 19 Look-up Table Entry 20 Look-up Table Entry 21 Look-up Table Entry 22 Look-up Table Entry 23 Look-up Table Entry 24 Look-up Table Entry 25 Look-up Table Entry 26 Look-up Table Entry 27 Look-up Table Entry 28 Look-up Table Entry 29 Look-up Table Entry 30 Look-up Table Entry 31 Look-up Table Entry 32 Look-up Table Entry 33 Look-up Table Entry 34 Look-up Table Entry 35 Look-up Table Entry 36 Look-up Table Entry 37 Look-up Table Entry 38 Look-up Table Entry 39 Look-up Table Entry 40 Look-up Table Entry 41 Look-up Table Entry 42 Station 0 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h A21h AFCh AFDh AFEh AFFh B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h PR EL IM IN AR Y C90h C94h C98h C9Ch CA0h CA4h CA8h CACh CB0h CB4h CB8h CBCh CC0h CC4h CC8h CCCh CD0h CD4h CD8h CDCh CE0h CE4h CE8h CECh CF0h CF4h CF8h CFCh D00h D04h Register Name PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Table A-1. Serial EEPROM Memory Map PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address D08h D0Ch D10h D14h D18h D1Ch D20h D24h D28h D2Ch D30h D34h D38h D3Ch D40h D44h D48h D4Ch D50h D54h D58h D5Ch D60h D64h D68h D6Ch D70h D74h D78h D7Ch Register Name Look-up Table Entry 43 Look-up Table Entry 44 Look-up Table Entry 45 Look-up Table Entry 46 Look-up Table Entry 47 Look-up Table Entry 48 Look-up Table Entry 49 Look-up Table Entry 50 Look-up Table Entry 51 Look-up Table Entry 52 Look-up Table Entry 53 Look-up Table Entry 54 Look-up Table Entry 55 Look-up Table Entry 56 Look-up Table Entry 57 Look-up Table Entry 58 Look-up Table Entry 59 Look-up Table Entry 60 Look-up Table Entry 61 Look-up Table Entry 62 Look-up Table Entry 63 VC_CapA_NT (Link) VC_CapB_NT (Link) Port_VC_Cap 1_NT (Link) Base Address 0 (Virtual) Base Address 1 (Virtual) Base Address 2 (Virtual) Base Address 3 (Virtual) Base Address 4 (Virtual) Base Address 5 (Virtual) Station 0 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A22h A23h A24h A25h A26h A27h A28h A29h A2Ah A2Bh A2Ch A2Dh A2Eh A2Fh A30h A31h A32h A33h A34h A35h A36h A37h A38h A39h A3Ah A3Bh A3Ch A3Dh A3Eh A3Fh B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h B21h B22h B23h B24h B25h B26h B27h B28h B29h B2Ah B2Bh B2Ch B2Dh B2Eh B2Fh B30h B31h B32h B33h B34h B35h B36h B37h PR EL IM IN AR Y Register Address 365 Serial EEPROM Memory Map Table A-1. PLX Technology, Inc. PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address D80h D84h D88h D8Ch D90h D94h D98h D9Ch DA0h DA4h DA8h DACh DB0h DB4h DB8h DBCh DC0h DC4h DC8h DCCh DD0h DD4h DD8h DDCh DE0h DE4h DE8h DECh DF0h DF4h 366 Register Name Configuration BAR Setup Memory BAR 2 Setup Memory BAR 3 Setup Memory BAR 4 Setup Memory BAR 5 Setup Transaction ID Translation LUT Entry 0 Transaction ID Translation LUT Entry 1 Transaction ID Translation LUT Entry 2 Transaction ID Translation LUT Entry 3 Transaction ID Translation LUT Entry 4 Transaction ID Translation LUT Entry 5 Transaction ID Translation LUT Entry 6 Transaction ID Translation LUT Entry 7 Transaction ID Translation LUT Entry 0_1 Transaction ID Translation LUT Entry 2_3 Transaction ID Translation LUT Entry 4_5 Transaction ID Translation LUT Entry 6_7 Transaction ID Translation LUT Entry 8_9 Transaction ID Translation LUT Entry 10_11 Transaction ID Translation LUT Entry 12_13 Transaction ID Translation LUT Entry 14_15 Transaction ID Translation LUT Entry 16_17 Transaction ID Translation LUT Entry 18_19 Transaction ID Translation LUT Entry 20_21 Transaction ID Translation LUT Entry 22_23 Transaction ID Translation LUT Entry 24_25 Transaction ID Translation LUT Entry 26_27 Transaction ID Translation LUT Entry 28_29 Reserved Link Interface Capture Bus/Device Number Station 0 Non-Transparent Ports Station 1 Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A40h A41h A42h A43h A44h A45h A46h A47h A48h A49h A4Ah A4Bh A4Ch A4Dh A4Eh A4Fh A50h A51h A52h A53h A54h A55h A56h A57h A58h A59h A5Ah A5Bh A5Ch A5Bh B38h B39h B3Ah B3Bh B3Ch B3Dh B3Eh B3Fh B40h B41h B42h B43h B44h B45h B46h B47h B48h B49h B4Ah B4Bh B4Ch B4Dh B4Eh B4Fh B51h B52h B53h B54h B55h B55h PR EL IM IN AR Y Register Address PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Table A-1. Serial EEPROM Memory Map PEX 8524 Serial EEPROM Memory Map (Cont.) Port Register Loaded from Listed EEPROM Address DF8h FB4h FB8h FBCh FC0h FC4h FC8h FCCh FD0h FD4h FD8h FDCh N/A Register Name NT Port Virtual Interface Control Advanced Error Reporting Enhanced Capability Header Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Error Severity Correctable Error Status Correctable Error Mask Advanced Error Capabilities and Control Header Log_0 Header Log_1 Header Log_2 Header Log_3 Refer to Table A-2 for duplicated Power Management registers that appear at this location in the EEPROM, after the previously listed registers. CRC Value Station 0 Station 1 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Non-Transparent Ports Port 0 Port 1 Port 8 Port 9 Port 10 Port 11 Link Virtual - 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h - 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h 3A1h 3A2h 3A3h - 7C7h 7C8h 7C9h 7CAh 7CBh 7CCh 7CDh 7CEh 7CFh 7D0h 7D1h - 851h 852h 853h 854h 855h 856h 857h 858h 859h 85Ah 85Bh - 8DBh 8DCh 8DDh 8DEh 8DFh 8E0h 8E1h 8E2h 8E3h 8E4h 8E5h - 965h 966h 967h 968h 969h 96Ah 96Bh 96Ch 96Dh 96Eh 96Fh A5Ch A5Dh A5Eh A5Fh A60h A61h A62h A63h A64h A65h A66h A67h B56h B57h B58h B59h B5Ah B5Bh B5Ch B5Dh B5Eh B5Fh B60h B61h PR EL IM IN AR Y Register Address BE4h 367 Serial EEPROM Memory Map Power Management Registers Additional Serial EEPROM Addresses Port Non-Transparent Link Non-Transparent Virtual 368 Serial EEPROM Address Register Address Default Value B62h 44h 0h B63h 44h 0h B64h 44h 0h B65h 44h 0h PR EL IM IN AR Y Table A-2. PLX Technology, Inc. B66h 154h 0h B67h 13Ch 0h B68h 13Ch 0h B69h 13Ch 0h B6Ah 13Ch 0h B6Bh 13Ch 0h B6Ch 13Ch 0h B6Dh 13Ch 0h B6Eh 13Ch 0h B6Fh 44h 0h B70h 44h 0h B71h 44h 0h B72h 44h 0h B73h 154h 0h B74h 13Ch 0h B75h 13Ch 0h B76h 13Ch 0h B77h 13Ch 0h B78h 13Ch 0h B79h 13Ch 0h B7Ah 13Ch 0h B7Bh 13Ch 0h PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Power Management Registers Additional Serial EEPROM Addresses (Cont.) Port Port 0 Port 1 Serial EEPROM Address Register Address Default Value B7Ch 44h 0h B7Dh 44h 0h B7Eh 44h 0h B7Fh 44h 0h B80h 154h 0h B81h 13Ch 0h B82h 13Ch 0h B83h 13Ch 0h B84h 13Ch 0h B85h 13Ch 0h B86h 13Ch 0h B87h 13Ch 0h B88h 13Ch 0h B89h 44h 0h B8Ah 44h 0h B8Bh 44h 0h B8Ch 44h 0h B8Dh 154h 0h B8Eh 13Ch 0h B8Fh 13Ch 0h B90h 13Ch 0h B91h 13Ch 0h B92h 13Ch 0h B93h 13Ch 0h B94h 13Ch 0h B95h 13Ch 0h PR EL IM IN AR Y Table A-2. Serial EEPROM Memory Map PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 369 Serial EEPROM Memory Map Power Management Registers Additional Serial EEPROM Addresses (Cont.) Port Port 8 Port 9 370 Serial EEPROM Address Register Address Default Value BB0h 44h 0h BB1h 44h 0h BB2h 44h 0h BB3h 44h 0h BB4h 154h 0h BB5h 13Ch 0h BB6h 13Ch 0h BB7h 13Ch 0h BB8h 13Ch 0h BB9h 13Ch 0h BBAh 13Ch 0h BBBh 13Ch 0h BBCh 13Ch 0h BBDh 44h 0h BBEh 44h 0h BBFh 44h 0h BC0h 44h 0h BC1h 154h 0h BC2h 13Ch 0h BC3h 13Ch 0h BC4h 13Ch 0h BC5h 13Ch 0h BC6h 13Ch 0h BC7h 13Ch 0h BC8h 13Ch 0h BC9h 13Ch 0h PR EL IM IN AR Y Table A-2. PLX Technology, Inc. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 June, 2005 Power Management Registers Additional Serial EEPROM Addresses (Cont.) Port Port 10 Port 11 Serial EEPROM Address Register Address Default Value BCAh 44h 0h BCBh 44h 0h BCCh 44h 0h BCDh 44h 0h BCEh 154h 0h BCFh 13Ch 0h BD0h 13Ch 0h BD1h 13Ch 0h BD2h 13Ch 0h BD3h 13Ch 0h BD4h 13Ch 0h BD5h 13Ch 0h BD6h 13Ch 0h BD7h 44h 0h BD8h 44h 0h BD9h 44h 0h BDAh 44h 0h BDBh 154h 0h BDCh 13Ch 0h BDDh 13Ch 0h BDEh 13Ch 0h BDFh 13Ch 0h BE0h 13Ch 0h BE1h 13Ch 0h BE2h 13Ch 0h BE3h 13Ch 0h PR EL IM IN AR Y Table A-2. Serial EEPROM Memory Map PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 371 PLX Technology, Inc. PR EL IM IN AR Y Serial EEPROM Memory Map 372 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential Appendix B B.1 General Information Product Ordering Information Contact your local PLX sales representative for ordering information. Table B-1. PEX 8524 Product Ordering Information Part Numbers PEX 8524-AA25VBI PEX 8524-AA25VBI G Description 24-Lane, 6-Port PCI Express switch 680-ball EHBGA 35 x 35 mm package 24-Lane, 6-Port PCI Express switch 680-ball EHBGA 35 x 35 mm Lead-Free ROHS Green package Note: B = Package Type I = -40 to +85C Industrial Operating Temperature range G = Lead-Free ROHS Green Packaging B.2 United States and International Representatives, and Distributors A list of PLX Technology, Inc., representatives and distributors can be found at www.plxtech.com. B.3 Technical Support PLX Technology, Inc., technical support information is listed at www.plxtech.com/support/, or call 408 774-9060 or 800 759-3735. PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 373 PLX Technology, Inc. PR EL IM IN AR Y General Information 374 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential PR EL IM IN AR Y June, 2005 PEX 8524 Versatile PCI ExpressTM Switches Data Book Copyright (c) 2005 by PLX Technology, Inc. All Rights Reserved - Version 0.99 Confidential 375 Y PR EL IM IN AR PLX Technology, Inc. 870 Maude Avenue Sunnyvale, CA 94085 1-800-759-3735 (408) 774-9060 http://www.plxtech.com E-mail: info@plxtech.com