August 2004 ASM3P2579A
rev 2.0
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document
is subject to change without notice.
Low Power Peak EMI Reducing Solution
Features
Generates an EMI optimized clocking signal at the
output.
Integrated loop filter components.
Operates with a 3.3V ±0.3V supply.
Operating current less than 6mA.
Low power CMOS design.
Input frequency range: 15MHz to 40MHz.
Generates a 1X low EMI spread spectrum clock of
the input frequency.
Spread Spectrum Enable Control.
Frequency deviation: ±1%.
Available in 6-pin TSOT-23, 8-pin SOIC and 8-pin
TSSOP packages.
Product Description
The ASM3P2579A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2579A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. The ASM3P2579A allows significant
system cost savings by reducing the number of circuit
board layers ferrite beads, shielding that are traditionally
required to pass EMI regulations.
The ASM3P2579A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all digital method.
The ASM3P2579A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
The ASM3P2579A is targeted towards all portable
devices with very low power requirements like MP3
players and digital still cameras.
Key Specifications
Description Specification
Supply voltages VDD = 3.3V ±0.3V
Frequency Range 15MHz < CLKIN < 40MHz
Cycle-to-Cycle Jitter 300 ps (maximum)
Output Duty Cycle 40/60% (worst case)
Output Rise and Fall Time 1.1 ns (maximum)
Modulation Rate Equation FIN/640
Frequency Deviation ±1%
Block Diagram
XIN
ModOUT
VSS
Frequency
Feedback
Modulation
Phase
Loop
VCO Output
PLL
VDD
Crystal
XOUT