High Performance, 3.2 GHz, 14-Output
Fanout Buffer
Data Sheet HMC7043
Rev. B Document Feedback
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FEATURES
JEDEC JESD204B support
Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz)
Very low noise floor: −155.2 dBc/Hz at 983.04 MHz
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx
frequency of 3200 MHz
JESD204B-compatible system reference (SYSREF) pulses
25 ps analog and ½ clock input cycle digital delay
independently programmable on each of 14 clock
output channels
SPI-programmable adjustable noise floor vs. power consumption
SYSREF valid interrupt to simplify JESD204B synchronization
Supports deterministic synchronization of multiple
HMC7043 devices
RFSYNCIN pin or SPI-controlled SYNC trigger for output
synchronization of JESD204B
GPIO alarm/status indicator to determine system health
Clock input to support up to 6 GHz
48-lead, 7 mm × 7 mm LFCSP package
APPLICATIONS
JESD204B clock generation
Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
Data converter clocking
Phase array reference distribution
Microwave baseband cards
GENERAL DESCRIPTION
The HMC7043 is a high performance clock buffer for the
distribution of ultralow phase noise references for high speed data
converters with either parallel or serial (JESD204B type) interfaces.
The HMC7043 is designed to meet the requirements of multicarrier
GSM and LTE base station designs, and offers a wide range of
clock management and distribution features to simplify baseband
and radio card clock tree designs.
The HMC7043 provides 14 low noise and configurable outputs
to offer flexibility in interfacing with many different components in
a base transceiver station (BTS) system, such as data converters,
local oscillators, transmit/receive modules, field programmable
gate arrays (FPGAs), and digital front-end ASICs. The HMC7043
can generate up to seven DCLK and SYSREF clock pairs per the
JESD204B interface requirements.
The system designer can generate a lower number of DCLK and
SYSREF pairs, and configure the remaining output signal paths
for independent phase and frequency. Both the DCLK and SYSREF
clock outputs can be configured to support different signaling
standards, including CML, LVDS, LVPECL, and LVCMOS, and
different bias conditions to adjust for varying board insertion losses.
One of the unique features of the HMC7043 is the independent
flexible phase management of each of the 14 channels. All
14 channels feature both frequency and phase adjustment. The
outputs can also be programmed for 50 Ω or 100 Ω internal and
external termination options.
The HMC7043 device features an RF SYNC feature that synchro-
nizes multiple HMC7043 devices deterministically, that is, ensures
that all clock outputs start with the same edge. This operation is
achieved by rephrasing the nested HMC7043 or SYSREF control
unit/divider, deterministically, and then restarting the output
dividers with this new phase.
The HMC7043 is offered in a 48-lead, 7 mm × 7 mm LFCSP
package with an exposed pad connected to ground.
FUNCTIONAL BLOCK DIAGRAM
CLKIN/
CLKIN
RFSYNCIN/
RFSYNCIN
13114-001
SDATA SPI
CONTROL
INTERFACE
SLEN SCLK
14-CLOCK
DISTRIBUTION
÷
SYSREF
CONTROL
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
÷
Figure 1.
HMC7043* PRODUCT PAGE QUICK LINKS
Last Content Update: 10/07/2017
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EVALUATION KITS
HMC7043 Evaluation Kit
DOCUMENTATION
Data Sheet
HMC7043: High Performance, 3.2 GHz, 14-Output Fanout
Buffer Data Sheet
User Guides
UG-892: Evaluating the HMC7043 High Performance, 3.2
GHz, 14-Output Fanout Buffer
TOOLS AND SIMULATIONS
HMC7043 IBIS Model
REFERENCE MATERIALS
Technical Articles
Synchronizing Sample Clocks of a Data Converter Array
DESIGN RESOURCES
HMC7043 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all HMC7043 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
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HMC7043* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
HMC7043 Evaluation Kit
DOCUMENTATION
Data Sheet
HMC7043: High Performance, 3.2 GHz, 14-Output Fanout
Buffer Data Sheet
User Guides
UG-892: Evaluating the HMC7043 High Performance, 3.2
GHz, 14-Output Fanout Buffer
TOOLS AND SIMULATIONS
HMC7043 IBIS Model
REFERENCE MATERIALS
Technical Articles
Synchronizing Sample Clocks of a Data Converter Array
DESIGN RESOURCES
HMC7043 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all HMC7043 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
HMC7043 Data Sheet
Rev. B | Page 2 of 43
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Conditions ..................................................................................... 3
Supply Current .............................................................................. 3
Digital Input/Output (I/O) Electrical Specifications ............... 4
Clock Input Path Specifications.................................................. 4
Additive Jitter and Phase Noise Characteristics ....................... 5
Clock Output Distribution Specifications ................................. 5
Clock Output Driver Characteristics ......................................... 6
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Typical Application Circuits .......................................................... 13
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Detailed Block Diagram ............................................................ 16
Clock Input Network ................................................................. 16
Clock Output Network .............................................................. 17
Typical Programming Sequence............................................... 23
Power Supply Considerations ................................................... 24
Serial Control Port ......................................................................... 27
Serial Port Interface (SPI) Control ........................................... 27
Control Registers ............................................................................ 28
Control Register Map ................................................................ 28
Control Register Map Bit Descriptions ................................... 33
Applications Information .............................................................. 41
Evaluation PCB And Schematic ............................................... 41
Outline Dimensions ....................................................................... 43
Ordering Guide .......................................................................... 43
REVISION HISTORY
7/2016Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3
5/2016—Rev. 0 to Rev. A
Changes to Table 3 ............................................................................. 4
Change to Maximum Operating Frequency Parameter, Table 7 ..... 7
Added Figure 6, Renumbered Sequentially ................................ 11
Change to Synchronization FSM/Pulse Generator
Timing Section ................................................................................. 21
Changes to Table 20 ........................................................................ 28
Change to Table 22 ......................................................................... 33
Changes to Table 28 ........................................................................ 34
Changes to Table 29 ........................................................................ 35
Change to Table 31 ......................................................................... 36
Change to Table 38 ......................................................................... 37
Changes to Table 41 ........................................................................ 39
12/2015Revision 0: Initial Version
Data Sheet HMC7043
Rev. B | Page 3 of 43
SPECIFICATIONS
VCC = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VCC and TA (−40°C to
+85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter1 Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE, VCC
VCC1_CLKDIST 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for CLK distribution
VCC2_OUT 3.135 3.3 3.465 V
3.3 V ± 5%, supply voltage for Output Channel 2 and
Output Channel 3
VCC3_OUT 3.135 3.3 3.465 V
3.3 V ± 5%, supply voltage for Output Channel 4, Output
Channel 5, Output Channel 6 and Output Channel 7
VCC4_CLKIN 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for the clock input path
VCC5_SYSREF 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for the common SYSREF divider
VCC6_OUT 3.135 3.3 3.465 V
3.3 V ± 5%, supply voltage for Output Channel 8, Output
Channel 9, Output Channel 10, and Output Channel 11
VCC7_OUT 3.135 3.3 3.465 V
3.3 V ± 5%, supply voltage for Output Channel 0, Output
Channel 1, Output Channel 12, and Output Channel 13
TEMPERATURE
Ambient Temperature Range, TA −40 +25 +85 °C
1 Maximum values are guaranteed by design and characterization.
SUPPLY CURRENT
For detailed test conditions, see Table 17 and Table 18.
Table 2
Parameter1, 2 Min Typ Max Unit Test Conditions/Comments
CURRENT CONSUMPTION3
VCC1_CLKDIST 87 125 mA
VCC2_OUT4 90 250 mA Typical value is given at TA = 25°C with two LVDS clocks at divide by 8
VCC3_OUT4 52 500 mA
Typical value is given at 25°C with two LVDS high performance clocks,
fundamental frequency of the clock input (fO), two SYSREF clocks (off)
VCC4_CLKIN 16 25 mA
Typical value is given at TA = 25°C with RF synchronization (RFSYNC) input
buffer off
VCC5_SYSREF 23 35 mA Typical value is given at TA = 25°C with internal RF SYNC path off
VCC6_OUT4 90 500 mA
Typical value is given at 25°C with two LVDS high performance clocks at
divide by 2, two SYSREF clocks (off)
VCC7_OUT4 100 500 mA
Typical value is given at 25°C with two LVDS clocks at divide by 8, two SYSREF
clocks (off)
Total Current 458 mA
1 Maximum values are guaranteed by design and characterization.
2 Currents include LVDS termination currents.
3 Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary
synchronization events.
4 Typical specification applies to a normal usage profile (Profile 1 in Table 17) but very low duty cycle currents (sync events) and some optional features are disabled.
This specification assumes output configurations as described in the test conditions/comments column.
HMC7043 Data Sheet
Rev. B | Page 4 of 43
DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUT SIGNALS (RESET, SLEN, SCLK)
Safe Input Voltage Range 0.1 +3.6 V
Input Load 0.3 pF
Input Voltage
Input Logic High 1.2 VCC V
Input Logic Low 0 0.5 V
SPI Bus Frequency 10 MHz
DIGITAL BIDIRECTIONAL SIGNALS
CONFIGURED AS INPUTS (SDATA, GPIO)
Safe Input Voltage Range −0.1 +3.6 V
Input Capacitance 0.4 pF
Input Resistance 50 GΩ
Input Voltage
Input Logic High 1.22 VCC V
Input Logic Low
0
0.24
V
Input Hysteresis 0.2 V Occurs around 0.85 V
GPIO ALARM MUXING/DELAY
Delay from Internal Alarm/Signal to
General-Purpose Output (GPO) Driver
2 ns Does not include tDGPO
DIGITAL BIDIRECTIONAL SIGNALS
CONFIFURED AS OUTPUTS (SDATA, GPIO)
CMOS Mode
Logic 1 Level 1.6 1.9 2.2 V
Logic 0 Level 0 0.1 V
Output Drive Resistance (RDRIVE) 50
Output Driver Delay (t
DGPO
)
1.5 + 42 × C
LOAD
ns
Approximately 1.5 ns + 0.69 × R
DRIVE
× C
LOAD
(CLOAD in nF)
Maximum Supported DC Current1 0.6 mA
Open-Drain Mode External 1 kΩ pull-up resistor
Logic 1 Level 3.6 V 3.6 V maximum permitted; specifications set by
external supply
Logic 0 Level
0.13
0.28
V
Against a 1 kΩ external pull-up resistor to 3.3 V
Pull-Down Impedance 60
Maximum Supported Sink Current1 5 mA
1 Guaranteed by design and characterization for long-term reliability.
CLOCK INPUT PATH SPECIFICATIONS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
CLK INPUT (CLKIN) CHARACTERISTICS
Recommended Input Power, AC-Coupled
Differential −6 +8 dBm
Single-Ended1 10 +6 dBm Noise floor degrade by 3 dB at fCLKIN = 2400 MHz
Return Loss −12 dB When terminated with 100 Ω differential
Clock Input Frequency (fCLKIN) 200 3200 MHz Fundamental mode; if <1 GHz, set the low frequency
clock input path enable bit (Register 0x0064, Bit 0)
200 6000 MHz Using clock input ÷ 2
Common-Mode Range
0.4
2.4
V
1 Guaranteed by design and characterization.
Data Sheet HMC7043
Rev. B | Page 5 of 43
ADDITIVE JITTER AND PHASE NOISE CHARACTERISTICS
Table 5.
Parameter1 Min Typ Max Unit Test Conditions/Comments
ADDITIVE JITTER
HMC7044 used as a clock source (see Figure 3)
RMS Additive Jitter <30 fs rms Clock output frequency (fCLKOUT) = 983.04 MHz, BW = 12 kHz to 20 MHz,
clock input slew rate 8 ns
<15 fs rms fCLKOUT = 2457.6 MHz, BW = 12 kHz to 20 MHz, clock input slew rate ≥ 4 ns
CLOCK OUTPUT PHASE NOISE HMC830 used as a clock source and configured to produce 983.04 MHz
at the output (see Figure 4), input slew rate > 1 V/ns
Absolute Phase Noise
Offset = 1 MHz 144.3 dBc/Hz fCLKOUT = 983.04 MHz, fCLKOUT = 983.04 MHz, divide by 1 at the output
Offset = 10 MHz 154.8 dBc/Hz fCLKOUT = 983.04 MHz, fCLKOUT = 2949.12 MHz, divide by 3 at the output
Offset = 20 MHz 155.2 dBc/Hz fCLKOUT = 983.04 MHz, fCLKOUT = 983.04 MHz, divide by 1 at the output
1 Guaranteed by design and characterization.
CLOCK OUTPUT DISTRIBUTION SPECIFICATIONS
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
CLOCK OUTPUT SKEW
CLKOUTx/CLKOUTx to SCLKOUTx/SCLKOUTx Skew
Within One Clock Output Pair
15 |ps| Same pair, same type termination and
configuration
Any CLKOUTx/CLKOUTx to Any SCLKOUTx/
SCLKOUTx 30 |ps| Any pair, same type termination and
configuration
PROPAGATION DELAY CLKIN to CLKOUTx and SCLKOUTx
1
770
820
870
ps
f
CLKIN
= 983.04 MHz, all V
CC
set to 3.3 V
CLOCK OUTPUT DIVIDER CHARACTERISTICS
12-Bit Divider Range 1 4094 1, 3, 5, and all even numbers up to 4094
SYSREF CLOCK OUTPUT DIVIDER CHARACTERISTICS
12-Bit Divider Range 1 4094 1, 3, 5, and all even numbers up to 4094;
pulse generator behavior is only
supported for divide ratios ≥ 32
CLOCK OUTPUT ANALOG FINE DELAY
Analog Fine Delay
Adjustment Range1 135 670 ps 24 delay steps, fCLKOUT = 983.04 MHz
Resolution 25 ps fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Maximum Analog Fine Delay Frequency 1600 MHz
CLOCK OUTPUT COARSE DELAY (FLIP FLOP BASED)
Coarse Delay Adjustment Range 0 17 ½ CLKIN period 17 delay steps
Coarse Delay Resolution 169.54 ps fCLKIN = 2949.12 MHz
Maximum Frequency Coarse Delay 1500 MHz
CLOCK OUTPUT COARSE DELAY (SLIP BASED)
Coarse Delay
Adjustment Range 1 to ∞ CLKIN period
Resolution 339.08 ps fCLKIN = 2949.12 MHz
Maximum Frequency Coarse Delay 1600 MHz
1 Guaranteed by design and characterization.
HMC7043 Data Sheet
Rev. B | Page 6 of 43
CLOCK OUTPUT DRIVER CHARACTERISTICS
Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
CML MODE (LOW POWER)
R
L
= 100 Ω, 9.6 mA
−3 dB Bandwidth 1950 MHz Differential output voltage = 980 mV p-p diff
Output Rise Time 175 ps fCLKOUT = 245.76 MHz, 20% to 80%
145 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 185 ps fCLKOUT = 245.76 MHz, 20% to 80%
145 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 1390 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1360 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Common-Mode Output Voltage VCC − 1.05 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
CML MODE (HIGH POWER) RL = 100 Ω, 14.5 mA
−3 dB Bandwidth 1500 MHz Differential output voltage = 1470 mV p-p diff
Output Rise Time 250 ps fCLKOUT = 245.76 MHz, 20% to 80%
165 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time
255
ps
f
CLKOUT
= 245.76 MHz, 20% to 80%
170 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 2000 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1800 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Differential Output
Voltage Magnitude 590 mV p-p diff fCLKOUT = 3200 MHz
Power 3.6 dBm diff fCLKOUT = 3200 MHz
Common-Mode Output Voltage VCC1.6 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
LVPECL MODE RL = 150 Ω, 4.8 mA
−3 dB Bandwidth 2400 MHz Differential output voltage = 1240 mV p-p diff
Output Rise Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
130 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
130
ps
f
CLKOUT
= 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 1760 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1850 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Differential Output
Voltage Magnitude 930 mV p-p diff fCLKOUT = 3200 MHz
Power 0.3 dBm diff fCLKOUT = 3200 MHz
Common-Mode Output Voltage VCC − 1.3 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
LVDS MODE (LOW POWER) 1.75 mA
Maximum Operating Frequency 1700 MHz Differential output voltage = 320 mV p-p diff
Output Rise Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
100 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
95 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle
1
47.5
50
52.5
%
f
CLKOUT
= 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 390 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
Common-Mode Output Voltage 1.1 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
Data Sheet HMC7043
Rev. B | Page 7 of 43
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS MODE (HIGH POWER) 3.5 mA
Maximum Operating Frequency 1700 MHz Differential output voltage = 600 mV p-p diff
Output Rise Time 145 ps fCLKOUT = 245.76 MHz, 20% to 80%
105 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time
145
ps
f
CLKOUT
= 245.76 MHz, 20% to 80%
100 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 750 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
730 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Common-Mode Output Voltage 1.1 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
CMOS MODE
Maximum Operating Frequency 600 MHz Single-ended output voltage = 940 mV p-p diff
Output Rise Time 425 ps fCLKOUT = 245.76 MHz, 20% to 80%
Output Fall Time
420
ps
f
CLKOUT
= 245.76 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Output Voltage
High VCC V Load current = 1 mA
VCC − 0.5 V Load current = 10 mA
Low
0.07
V
Load current = 1 mA
0.5 V Load current = 10 mA
1 Guaranteed by design and characterization.
HMC7043 Data Sheet
Rev. B | Page 8 of 43
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Rating
VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 to
Ground
0.3 V to +3.6 V
Maximum Junction Temperature 125°C
Thermal Resistance (Channel to Ground Pad) 7°C/W
Storage Temperature Range 65°C to +125°C
Operating Temperature Range 40°C to +85°C
Peak Reflow Temperature 260°C
ESD Sensitivity Level
Human Body Model (HBM) Class 1C
Charged Device Model (CDM)1 Class 4
1 Per JESD22-C101-F (CDM) standard.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet HMC7043
Rev. B | Page 9 of 43
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
SCLKOUT9
SCLKOUT9
GPIO
4SDATA
5SCLK
6SLEN
7VCC5_SYSREF
24RSV 23SCLKOUT7 22SCLKOUT7 21CLKOUT6 20CLKOUT6 19VCC3_OUT 18CLKOUT4 17CLKOUT4 16SCLKOUT5 15SCLKOUT5 14RSV 13VCC2_OUT
44 SCLKOUT13
45 SCLKOUT13
46 CLKOUT12
47 CLKOUT12
48 VCC7_OUT
43 SCLKOUT11
42 SCLKOUT11
41 CLKOUT10
40 CLKOUT10
39 VCC6_OUT
38 CLKOUT8
37 CLKOUT8
TOP VIEW
(No t t o Scal e)
HMC7043
25
CLKOUT2 26
CLKOUT2 27
SCLKOUT3 28
SCLKOUT3 29
VCC1_CLKDIST 30
LDOBYP2 31
BGAPBYP1 32
RESET 33
SCLKOUT1 34
SCLKOUT1 35
CLKOUT0 36
CLKOUT0
8RFSYNCIN
9RFSYNCIN
10 VCC4_CLKIN
11 CLKIN
12 CLKIN
NOTES
1. RSV = RESERVED PIN AND MUST BE T IED TO GROUND.
2. CO NNE CT T HE E X P OSED P AD TO A HIGH QUAL ITY RF/ DC GROUND.
13114-002
Figure 2.
Table 9. Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 CLKOUT0 O True Clock Output Channel 0. Default DCLK profile.
2 CLKOUT0 O Complementary Clock Output Channel 0. Default DCLK profile.
3
SCLKOUT1
O
True Clock Output Channel 1. Default SYSREF profile.
4 SCLKOUT1 O Complementary Clock Output Channel 1. Default SYSREF profile.
5 RESET I Device Reset Input. Active high. For normal operation, set RESET to 0.
6 BGAPBYP1 Band Gap Bypass Capacitor Connection. Connect a 4.7 µF capacitor to ground. This pin affects all
internally regulated supplies.
7 LDOBYP2 LDO Bypass 2. Connect a 4.7 µF capacitor to ground. The internal digital supply is 1.8 V. This pin is the
LDO bypass for the SYSREF section.
8 VCC1_CLKDIST P 3.3 V Supply for CLK Distribution.
9 SCLKOUT3 O True Clock Output Channel 3. Default SYSREF profile.
10 SCLKOUT3 O Complementary Clock Output Channel 3. Default SYSREF profile.
11 CLKOUT2 O True Clock Output Channel 2. Default DCLK profile.
12
CLKOUT2
O
Complementary Clock Output Channel 2. Default DCLK profile.
13 VCC2_OUT P Power Supply for Clock Group 1 (Southwest)Channel 2 and Channel 3. See the Clock Grouping,
Skew, and Crosstalk section.
14 RSV R Reserved Pin. This pin must be tied to ground.
15 SCLKOUT5 O True Clock Output Channel 5. Default SYSREF profile.
16 SCLKOUT5 O Complementary Clock Output Channel 5. Default SYSREF profile.
17 CLKOUT4 O True Clock Output Channel 4. Default DCLK profile.
18 CLKOUT4 O Complementary Clock Output Channel 4. Default DCLK profile.
19 VCC3_OUT P Power Supply for Clock Group 2 (South)Channel 4, Channel 5, Channel 6, and Channel 7. See the
Clock Grouping, Skew, and Crosstalk section.
20 CLKOUT6 O True Clock Output Channel 6. Default DCLK profile.
21 CLKOUT6 O Complementary Clock Output Channel 6. Default DCLK profile.
22 SCLKOUT7 O True Clock Output Channel 7. Default SYSREF profile.
23 SCLKOUT7 O Complementary Clock Output Channel 7. Default SYSREF profile.
24 RSV R Reserved Pin. This pin must be tied to ground.
25 CLKIN I Complementary Clock Input.
26 CLKIN I True Clock Input.
HMC7043 Data Sheet
Rev. B | Page 10 of 43
Pin No. Mnemonic Type 1 Description
27 VCC4_CLKIN P Power Supply for the Clock Input Path.
28 RFSYNCIN I True RF Synchronization Input with Deterministic Delay.
29 RFSYNCIN I Complementary RF Synchronization Input with Deterministic Delay.
30 VCC5_SYSREF P Power Supply for Common SYSREF Divider.
31 SLEN I/O SPI Latch Enable.
32 SCLK I/O SPI Clock.
33 SDATA I/O SPI Data.
34 GPIO I/O Programmable General-Purpose Input/Output.
35 SCLKOUT9 O True Clock Output Channel 9. Default SYSREF profile.
36 SCLKOUT9 O Complementary Clock Output Channel 9. Default SYSREF profile.
37 CLKOUT8 O True Clock Output Channel 8. Default DCLK profile.
38 CLKOUT8 O Complementary Clock Output Channel 8. Default DCLK profile.
39 VCC6_OUT P Power Supply for Clock Group 3 (North)Channel 8, Channel 9, Channel 10, and Channel 11. See the
Clock Grouping, Skew, and Crosstalk section.
40 CLKOUT10 O True Clock Output Channel 10. Default DCLK profile.
41
CLKOUT10
O
Complementary Clock Output Channel 10. Default DCLK profile.
42 SCLKOUT11 O True Clock Output Channel 11. Default SYSREF profile.
43 SCLKOUT11 O Complementary Clock Output Channel 11. Default SYSREF profile.
44 SCLKOUT13 O True Clock Output Channel 13. Default SYSREF profile.
45 SCLKOUT13 O Complementary Clock Output Channel 13. Default SYSREF profile.
46 CLKOUT12 O True Clock Output Channel 12. Default DCLK profile.
47 CLKOUT12 O Complementary Clock Output Channel 12. Default DCLK profile.
48 VCC7_OUT P Power Supply for Clock Group 0 (Northwest)Channel 0, Channel 1, Channel 12, and Channel 13. See
the Clock Grouping, Skew, and Crosstalk section.
EP Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.
1 O is output, I is input, P is power, R is reserved, and I/O is input/output.
Data Sheet HMC7043
Rev. B | Page 11 of 43
TYPICAL PERFORMANCE CHARACTERISTICS
–160
–150
–140
–130
–120
110
–100
110 100 1000 10000
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (kHz)
HMC7044-CLOCK S OURCE
HMC7043
13114-003
HMC7044 AS CLOCK S OURCE:
OUTPUT FREQ = 983. 04M Hz
OUTPUT P OW E R = 3.7d Bm
1MHz, –140.56dBc/ Hz
5MHz, –153.26dBc/ Hz
10MHz, –154.28dBc/ Hz
20MHz, –154.85dBc/ Hz
RMS JITTER ( 12kHz TO 20MHz) : 73.74fs
HMC7043 O UTPUT:
AT FUNDE M E N TAL MO DE
1MHz, –140.30 dBc/ Hz
5MHz, –151.02 dBc/ Hz
10MHz, –151.77 dBc/ Hz
20MHz, –151.97 dBc/ Hz
RMS JITTER = 77.01fs
Figure 3. Additive Jjitter at 983.04 MHz at Output
13114-004
–170
–160
–150
–140
–130
–120
–110
–100
110 100 1000 10000
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (kHz)
HMC830-CLOCK S OURCE
HMC7043 HMC830 AS CLOCK S OURCE:
OUTPUT FREQ = 983. 04M Hz
OUTPUT P OW E R = 4dBm
1MHz, –144.49dBc/ Hz
5MHz, –158.38dBc/ Hz
10MHz,–162.61dBc/Hz
20MHz, –164.29dBc/ Hz
HMC7043 O UTPUT:
AT FUNDE M E N TAL MO DE
1MHz, –144.31 dBc/ Hz
5MHz, –153.46 dBc/ Hz
10MHz, –154.78 dBc/ Hz
20MHz, –155.18 dBc/ Hz
Figure 4. Absolute Phase Noise Measured at 983.04 MHz at Output
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
100M 1G 3.2G
DIFFERENTIAL OUTPUT VOLTAGE (Vp-p DIFF)
FREQUENCY (Hz)
13114-206
LVPECL
CML100 HIGH
CML100 LOW
LVDS HIGH
CMOS (NOT IN
DIFFERENTIAL MODE)
Figure 5. Differential Output Power vs. Frequency over Various Modes
0
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
1.65
1.80
1.95
2.10
2.25
1.0 1.5 2.0 2.5 3.0 3.5
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
FRE Q UE NCY ( GHz)
LVPECL
CML 100 HIGH
CML 100 LOW
LVDS HIGH
13114-100
Figure 6.Differential Output Voltage vs. Frequency over Various Modes
DIFFERENTIAL OUTPUT VOLTAGE (Vp-p DIFF)
FREQUENCY (Hz)
0
0.25
0.5
0.75
1.00
1.25
1.5
1.75
2.00
100M 1G 3G
–40°C
+25°C
+85°C
13114-205
Figure 7. LVPECL Differential Output Power vs. Frequency over Various
Temperatures
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
00.4 0.8 1.2 1.6 2.0
CLKOUT0/CL KOUT0 V O LTAGE (V)
TIME (n s)
13114-007
Figure 8. Differential CLKOUT0/CLKOUT0 at 2457 MHz, LVPECL
HMC7043 Data Sheet
Rev. B | Page 12 of 43
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 1 2345678910
TIME (n s)
13114-008
CLKO UT0/ CLKO UT0 VOLTAGE (V)
Figure 9. Differential CLKOUT0/CLKOUT0 Voltage at 614.4 MHz, LVPECL
13114-009
–0.5
0
0.5
1.0
1.5
2.0
2.5
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0200 400 600 800 1000
CLOCK GROUP VALID PHASE ALARM V OLTAGE (V)
CLOCK OUP UT VOLTAGE (V)
TIME (ns)
CLKOUT0
CLKOUT2
VALID PHAS E ALARM
Figure 10. Output Channel Synchronization Before and After Rephase
13114-010
–0.5
0
0.5
1.0
1.5
2.0
2.5
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
330 335 340 345 350
CLOCK GROUPVALID PHASE ALARM V OLTAGE (V)
CLOCK OUTPUT VOLTAGE (V)
TIME (n s)
CLKOUT0
CLKOUT2
VAL I D P HAS E ALARM
Figure 11. Output Channel Synchronization Before Rephase
13114-011
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
695 700 705 710 715
CLOCK GROUP VALID PHASE ALARM V OLTAGE (V)
CLOCK OUTPUT VOLTAGE (V)
TIME (ns)
CLKOUT0
CLKOUT2 V ALI D P HAS E ALARM
–0.5
0
0.5
1.0
1.5
2.0
2.5
Figure 12. Output Channel Synchronization After Rephase
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
13114-012
10
15
20
25
30
DELAY STEP SIZ E (p s)
DELAY STEP
–40°C
+25°C
+85°C
Figure 13. Analog Delay Step Size vs. Delay Step over Temperature,
LVPECL at 983.04 MHz
13114-013
–200
–100
0
100
200
300
400
500
600
700
800
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
DELAY STEP SIZ E (p s)
DELAY STEP
FUND:FUNDAMENTAL MO DE AT 2949.12MHz
DIS: ANALO G DEL AY I S DISABLED AT 983.04MHz
FUND
DIS
–40°C
+27°C
+85°C
Figure 14. Analog Delay vs. Delay Setting over Temperature, LVPECL at
983.04 MHz
Data Sheet HMC7043
Rev. B | Page 13 of 43
TYPICAL APPLICATION CIRCUITS
100Ω
0.1µF
0.1µF
DOWNSTREAM
DEVICE
LVDS
OUTPUT
HIGH
IMPEDANCE
INPUT
HMC7043
13114-014
Figure 15. AC-Coupled LVDS Output Driver
0.1µF
0.1µF
DOWNSTREAM
DEVICE
CML
OUTPUT
HIGH
IMPEDANCE
INPUT
HMC7043
100Ω 100Ω
VCC
100Ω
13114-015
Figure 16. AC-Coupled CML (Configured High-Z) Output Driver
0.1µF
0.1µF
DOWNSTREAM
DEVICE
CML
OUTPUT
HIGH
IMPEDANCE
INPUT
HMC7043
100Ω
100Ω
VCC 100Ω
13114-016
Figure 17. AC-Coupled CML (Internal) Output Driver
0.1µF
0.1µF
SELF BIASED
REF, VCXO
INPUTS
HMC7043
13114-017
Figure 18. CLKIN/CLKIN , RFSYNCIN Input Differential Mode
100Ω DOWNSTREAM
DEVICE
LVDS
OUTPUT
HIGH
IMPEDANCE
INPUT
HMC7043
13114-018
Figure 19. DC-Coupled LVDS Output Driver
DOWNSTREAM
DEVICE
(LVPECL)
LVPECL-
COMPATIBLE
OUTPUT
HMC7043
50Ω 50Ω
50Ω
GND
13114-019
Figure 20. DC-Coupled LVPECL Output Driver
CML
OUTPUT
HMC7043
100Ω
100Ω
VCC
DOWNSTREAM
DEVICE
(CML)
13114-020
Figure 21. DC-Coupled CML (Internal) Output Driver
0.1µF
HMC7043
3.3V
DRIVER 0.1µF
13114-021
Figure 22. CLKIN, RFSYNCIN Input Single-Ended Mode
HMC7043 Data Sheet
Rev. B | Page 14 of 43
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave has a continuous and even progression of
phase with time from 0° to 360° for each cycle. Actual signals,
however, display a certain amount of variation from ideal phase
progression over time. This phenomenon is phase jitter. Although
many causes can contribute to phase jitter, one major cause is
random noise, which is characterized statistically as being
Gaussian (normal) in distribution.
This phase jitter leads to the energy of the sine wave in the
frequency domain spreading out, producing a continuous power
spectrum. This power spectrum is usually reported as a series of
values whose units are dBc/Hz at a given offset in frequency from
the sine wave (carrier). The value is a ratio (expressed in decibels)
of the power contained within a 1 Hz bandwidth with respect to
the power at the carrier frequency. For each measurement, the
offset from the carrier frequency is also given.
It is meaningful to integrate the total power contained within some
interval of offset frequencies (for example, 10 kHz to 10 MHz).
This is the integrated phase noise over that frequency offset
interval and can be readily related to the time jitter due to the
phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of analog-
to-digital converters (ADCs), digital-to-analog converters (DACs),
and RF mixers. It lowers the achievable dynamic range of the
converters and mixers, although they are affected in somewhat
different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings varies. In a square
wave, the time jitter is a displacement of the edges from their
ideal (regular) times of occurrence. In both cases, the variations in
timing from the ideal are the time jitter. Because these variations
are random in nature, the time jitter is specified in seconds root
mean square (rms) or 1 sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured.
The phase noise of any external oscillators or clock sources is
subtracted, which makes it possible to predict the degree to
which the device impacts the total system phase noise when
used in conjunction with the various oscillators and clock
sources, each of which contributes a phase noise to the total. In
many cases, the phase noise of one element dominates the
system phase noise. When there are multiple contributors to
phase noise, the total is the square root of the sum of squares of
the individual contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable to
the device or subsystem being measured. The time jitter of any
external oscillators or clock sources is subtracted, which makes
it possible to predict the degree to which the device impacts the
total system time jitter when used in conjunction with the various
oscillators and clock sources, each of which contributes a time
jitter to the total. In many cases, the time jitter of the external
oscillators and clock sources dominates the system time jitter.
Data Sheet HMC7043
Rev. B | Page 15 of 43
THEORY OF OPERATION
The HMC7043 is a high performance, clock distribution IC
designed for extending the number of clock signals across the
system with minimal noise contribution. The device can be
used for distributing the noise sensitive reference clocks for high
speed data converters with either parallel or serial (JESD204B)
interfaces, FPGAs, and local oscillators. The HMC7043 is
designed to meet the requirements of demanding base station
designs, and offers a wide range of clock management and
distribution features to simplify baseband and radio card clock
tree designs. The device provides 14 low noise and configurable
outputs to offer flexibility in distributing clocks while applying
frequency division, phase adjustment, cycle slip, and external
signal synchronization options.
The HMC7043 generates up to seven DCLK and SYSREF clock
pairs per the JESD204B interface requirements. The system
designer can generate a lower number of DCLK and SYSREF
pairs, and configure the remaining output signal paths as
DCLKs, additional SYSREFs, or other reference clocks with
independent phase and frequency adjustment. Frequency
adjustment can be accomplished by selecting the appropriate
output divider values.
One of the unique features of the HMC7043 is the independent
flexible phase management of each of the 14 channels. Using a
combination of divider slip based, digital (coarse) and analog
(fine) delay adjustments, each channel can be programmed to
have a different phase offset. The phase adjustment capability
allows the designer to offset board flight time delay variations,
match data converter sample windows, and meet JESD204B
synchronization challenges. The output signal path design of
the HMC7043 is implemented to ensure both linear phase
adjustment steps and minimal noise perturbation when phase
adjustment circuits are turned on.
The HMC7043 provides output clock signals of up to 3.2 GHz,
while having the flexibility to support input reference frequencies of
up to 6 GHz when the internal clock division blocks are turned on.
The higher frequency support enables higher bandwidth RF
designs, and allows for distribution of low noise RF phase-locked
loop (PLL) voltage controlled oscillator (VCO) outputs as well
as other critical clocks across the system.
One of the key challenges in JESD204B system design is ensuring
the synchronization of data converter frame alignment across
the system, from the FPGA or digital front end (DFE) to ADCs
and DACs through a large clock tree that may comprise multiple
clock generation and distribution ICs.
There are two input paths on the HMC7043; one is for the clock
signal that is distributed, and the other may be used as an external
synchronization signal. In typical JESD204B systems, serial data
converter interfaces, there may be a need to ensure that all clock
signals that are sent to the data converters have phases which are
controlled by an FPGA. By virtue of the RF SYNC input, the
device ensures that output signals have a deterministic phase
alignment to this synchronization input. The RF SYNC input
can also implement multiple device clock trees by nesting more
than one HMC7043 to generate an even larger clock distribution
network, while still maintaining phase alignment across the
clock tree.
Offering excellent crosstalk, frequency isolation, and spurious
performance, the device generates independent frequencies in
both single-ended and differential formats including LVPECL,
LVDS, CML, and CMOS, and different bias conditions to
offset varying board insertion losses. The outputs can also be
programmed for ac or dc coupling and 50 Ω or 100 Ω internal
and external termination options.
The HMC7043 is programmed via a 3-wire serial port interface
(SPI). The HMC7043 is offered in a 48-lead, 7 mm × 7 mm,
LFCSP package with the exposed pad to ground.
HMC7043 Data Sheet
Rev. B | Page 16 of 43
DETAILED BLOCK DIAGRAM
SYSREF TIMER
ANALOG
DELAY
CLK DISTRIBUTION PATH
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
MUX
MUX
SYNC/PULSOR
CONTROL
TO LEAF DIVIDERS
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
FUNDAMENTAL MODE
FUNDAMENTAL MODE
FUNDAMENTAL MODE
FUNDAMENTAL MODE
FUNDAMENTAL MODE
FUNDAMENTAL MODE
ANALOG
DELAY
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
ANALOG
DELAY
CLKOUT2
CLKOUT2
SCLKOUT3
SCLKOUT3
CLKOUT8
CLKOUT8
SCLKOUT9
SCLKOUT9
MUX
MUX
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
ANALOG
DELAY
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
ANALOG
DELAY
GPI
SPI
MUX
MUX
ANALOG
DELAY
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
FUNDAMENTAL MODE FUNDAMENTAL MODE
FUNDAMENTAL MODE
FUNDAMENTAL MODE
ANALOG
DELAY
CLKOUT4
CLKOUT4
SCLKOUT5
SCLKOUT5
CLKOUT10
CLKOUT10
SCLKOUT11
SCLKOUT11
MUX
MUX
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
ANALOG
DELAY
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
ANALOG
DELAY MUX
MUX
ANALOG
DELAY
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
FUNDAMENTAL MODE FUNDAMENTAL MODE
FUNDAMENTAL MODE
FUNDAMENTAL MODE
LDOs
ANALOG
DELAY
CLKOUT6
CLKOUT6
SCLKOUT7
SCLKOUT7
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
MUX
MUX
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
ANALOG
DELAY
BGABYP1 LDOBYP2
SPI
SDATASCLK SLEN
ALARM GENERATION DEVICE
CONTROL
RESETGPIO
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
ANALOG
DELAY MUX
MUX
ANALOG
DELAY
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
CLKIN
CLKIN
RFSYNCIN
RFSYNCIN
13114-022
DIVIDER
÷1, ÷2
Figure 23. Detailed Block Diagram
CLOCK INPUT NETWORK
Input Termination NetworkCommon for All Input Buffers
The two clock and RFSYNC input buffers share similar architecture
and control features. The input termination network is configurable
to 100 Ω, 200 Ω, and 2 kΩ differentially. It is typically ac-coupled
on the board, and uses the on-chip resistive divider to set the
internal common-mode voltage, VCM, to 2.1 V.
By closing the 50 Ω termination switch (see Figure 24), the network
also can serve as the termination system for an LVPECL driver.
Although the input termination network for the two clock and
RFSYNC input buffers is identical, the buffer behind the
network is different.
2.8V
4kΩ
5kΩ
50Ω
50Ω,
100Ω,
1kΩ
50Ω,
100Ω,
1kΩ
1pF
13033-045
Figure 24. On-Chip Termination Network for Clock and RFSYNC Buffers
Recommendations for Normal Use
For both buffer types, unless there are extenuating circumstances
in the application, use 100 Ω differential termination resistors
to control reflections, to use the on-chip dc bias network to set
the common mode level, and to externally ac couple the input
signals in. Do not use a receiver side dc termination of the
LVPECL signal.
Data Sheet HMC7043
Rev. B | Page 17 of 43
Single-Ended Operation
The buffers can support a single-ended signal with slightly reduced
input sensitivity and bandwidth. If driving any of the buffers
single-ended, ac couple the unused leg of the buffer to ground
at the input of the die.
Maximum Signal Swing Considerations
The internal supplies to these input buffers are supplied directly
from 3.3 V. The ESD network and parasitic diodes can generally
shunt away excess power and protect the internal circuits
(withstanding reference powers above 13 dBm). Nevertheless,
to protect from latch-up concerns, the signals on the reference
inputs must not exceed the 3.3 V internal supply. For a 2.1 V
common mode, 50 Ω single-ended source, this allows ~1200 mV
of amplitude, or 11 dBm maximum reference power.
CLOCK OUTPUT NETWORK
The HMC7043 is a high performance clock buffer, is appropriate
for JESD204B data converters, and much of the uniqueness of a
JESD204B clock generation chip relates to the array of output
channels. In this device, the output network requirements include
A large number of device clock (DCLK) and synchronization
(SYSREF) channels
Very good phase noise floor of the DCLK channels that can
be connected to critical data converter sample clock inputs
Deterministic phase alignment between all output channels
relative to one another
Fine phase control of synchronization channels with
respect to the DCLK channel
Frequency coverage to satisfy typical clock rates in systems
Skew between SYSREF and DCLK channels that is much
less than a DCLK period
Spur and crosstalk performance that does not impact
system budgets
The HMC7043 output network supports the following recom-
mended features, which are sometimes critical in user applications:
Deterministic synchronization of the output channels with
respect to an external signal (RFSYNC), which allows
multichip synchronization and clean expansion to larger
systems
Pulse generator behavior to temporarily generate a
synchronization pulse stream at a user request
The flexibility to define unused JESD204B SYSREF and
DCLK channels for other purposes
Glitchless phase control of signals relative to each other
50% duty cycle clocks with odd division ratios
Multimode output buffers with a variety of swings and
termination options
Skew between all channels is much less than a DCLK period
Adjustable performance vs. power consumption for less
sensitive clock channels
CLOCK
GATING
SYNC/PULSE GENERATOR
CONTROL
DIGITAL
DELAY AND
RETIME
DIVIDER
LEAF CONTROLLER
SYNC_FSM_STATE
SYNC REQUEST (FROM SPI OR GPI PI N)
PULSE GENERATOR REQUEST (FROM SPI OR GPI PIN)
OUT P UT CHANNEL ×14
SYSREF TIMER
RESET
RF
SYNC
CLKIN PATH
SYSREF INPUT NETWORK
QD
13114-023
Figure 25. Clock Output Network Simplified Diagram
HMC7043 Data Sheet
Rev. B | Page 18 of 43
Each of the 14 output channels are logically identical. The only
distinction between the SYSREF and DCLK channels is in the
SPI configuration, and in how they are used. Each channel
contains independent dividers, phase adjustment, and analog
delay circuits. This combination provides the ultimate flexibility,
cleanly accommodating nonJESD204B devices in the system.
In addition to the 14 output channel dividers, an internal SYSREF
timer continually operates, and the synchronization of the output
channel dividers occurs deterministically with respect to this
timer, which the user can rephased deterministically by the user
through GPI or SPI or deterministically by using the RFSYNCIN/
RFSYNCIN differential pins.
The pulse generator functionality of the JESD204B standard
involves temporarily generating SYSREF output pulses, with
appropriate phasing, to downstream devices. The centralized
SYSREF timer and the associated SYNC/pulse generator control
manage the process of enabling the intended SYSREF channels,
phasing them, and then disabling them for signal integrity and
power saving advantages.
Basic Output Divider Channel
Each of the 14 output channels are logically identical, and support
divide ratios from 1 to 4094. The supported odd divide ratios
(1, 3, or 5) have 50.0% duty cycle. The only distinction between
a SYSREF channel and a device clock channel is in the SPI
configuration and the typical usage of a given channel.
For basic functionality and phase control, each output path
consists of the following:
Dividergenerates the logic signal of the appropriate
frequency and phase
Digital phase adjustadjusts the phase of each channel in
increments of ½ clock input cycles
Retimera low noise flip flop to retime the channel,
removing any accumulated jitter
Analog fine delayprovides a number of ~25 ps delay steps
Selection muxselects the fundamental, divider, analog
delay, or an alternate path
Multimode output bufferlow noise LVDS, CML, CMOS,
or LVPECL
The digital phase adjuster and retimer launch on either clock
phase of the clock input, depending on the digital phase adjust
setpoint (Coarse Digital Delay[4:0]).
To support divider synchronization, arbitrary phase slips, and
pulse generator modes, the following blocks are included:
A clock gating stage pauses the clock for synchronization
or slip operations
An output channel leaf (×14) controller that manages slip,
synchronization, and pulse generators with information
from the SYSREF finite state machine (FSM)
Each channel has an array of control signals. Some of the
controls are described in Table 10.
System wide broadcast signals can be triggered from the SPI or
general-purpose input (GPI) port to issue a SYNC command
(to align dividers to the system internal SYSREF timer), issue a
pulse generator stream, (temporarily exporting SYSREF signals to
receivers), or to cause the dividers to slip a number of clock
input cycles to adjust their phases.
Individual dividers can be made sensitive to these events by
adjusting their slip enable, SYNC enable, and Start-Up Mode[1:0]
configuration, as described in Table 11.
When output buffers are configured in CMOS mode and phase
alignment is required among the outputs, additional multislip
delays must be issued for Channel 0, Channel 3, Channel 5,
Channel 6, Channel 9, Channel 10, and Channel 13. The value
of the delay must be as large as half of the selected divider ratio.
Note that this requirement of having additional multislip delays
is not needed when the channels are used in LVPECL, CML, or
LVDS mode.
If a channel is configured to behave as a pulse generator, to
temporarily power up and power down according to the GPI
and SPI pulse generator commands; additional controls define the
behavior outside of the pulse generator chain (see Table 12).
Each divider has an additional phase offset register that adjusts
the start phase or influences the behavior of slip events sent via
the SPI (see Table 13).
Table 14 outlines the typical configuration combinations for a
DCLK channel relative to a SYSREF synchronization channel.
Note that other combinations are possible. Synchronization of
downstream devices can be managed manually, or by using the
pulse generator functionality of the HMC7043. See the Typical
Programming Sequence section for more information about the
differences between the two methods.
Data Sheet HMC7043
Rev. B | Page 19 of 43
Table 10. Basic Divider Controls
Bit Name Description
Channel Enable Channel enable. If set to 0, the channel is disabled. If set to 1, the channel can be enabled depending on the
settings of the Start-Up Mode[1:0], Seven Pairs of 14-Channel Outputs Enable[6:0], and sleep mode bits.
12-Bit Channel Divider[11:0] Divide ratio.12-bit divide ratio, split across two words (MSB and LSB). Set to 0 if not using the channel divider
(Output Mux Selection[1:0] = 2 or 3)
High Performance Mode High performance mode. Adjusts the divider and buffer bias to improve swing/phase noise slightly at the expense of
power. The performance advantage is about 1 dB, and the current penalty depends on whether the divider is enabled.
Coarse Digital Delay[4:0] Digital delay. Adjusts the phase of the divider signal by up to 17 ½ cycles of the clock input. This circuit is
practically noiseless; however, note that a low amount of additional current is consumed.
Fine Analog Delay[4:0] Analog delay. Adjusts the delay of the divider signal in increments of ~25 ps. Set Output Mux Selection[1:0] = 1
to expose this channel. Exposing this channel causes phase noise degradation of up to 12 dB; therefore, do not use
on noise sensitive DCLK channels.
Output Mux Selection[1:0] Output mux selection. 00 = divider channel, 01 = analog delay, 10 = other channel of pair, 11 = input clock.
Fundamental mode can be generated with the divider (12-Bit Channel Divider[11:0] = 1), or via Output Mux
Selection[1:0] = 10 and 12-Bit Channel Divider[11:0] = 0. Because the divider path consumes power and degrades
phase noise slightly, the fundamental mux path is recommended, but at a cost of a deterministic skew vs. a path
that is divider-based. Such skew can be compensated for with delay (digital and analog) on the divider-based
path.
Force Mute[1] Force mute. If 1, and the channel enable is true (channel enable = 1) and Force Mute[0] = 0, the signal just
before the output buffer is asynchronously forced to Logic 0. To see the effect of this, the output buffer must
be enabled, which is dependent on the dynamic driver enable and Start-Up Mode[1:0] controls.
Table 11. Channel Features
Bit Name Description
Slip Enable Slip enable. A channel processes slip requests broadcast from the SPI or GPI (or, if multislip enable = 1, initiated
following a recognized SYNC or pulse generator startup).
SYNC Enable SYNC enable. A channel processes synchronization events broadcast from the SPI or GPI or due to SYNC/RF SYNC (via
the SYSREF FSM) to reset the phase. This signal can be safely toggled on and off to adjust SYNC sensitivity without
risking the state of the divider.
Start-Up Mode[1:0] 00 = asynchronous (normal mode). The divider starts with uncontrolled phase. It is rephased by SYNC events if SYNC
enable = 1.
11 = dynamic (pulse generator mode). The divider monitors pulse generator events broadcast from the SYSREF
controller. It is powered up just before a pulse generator chain, rephased at the start, and powered down after the
pulse generator chain. This mode is only supported for divide ratios > 31.
Table 12. Pulse Generator Mode Behavior Options
Bit Name Description
Dynamic Driver Enable Dynamic output buffer enable (pulse generator mode only).
0 = the output buffer is simply enabled/disabled with the main channel enable.
1 = the output buffer enable is controlled together with the channel divider, which allows it to dynamically power
down outside pulse generator events.
Force Mute[0] Idle at Logic 0 (pulse generator mode only).
1 = if the buffer remains on outside of the pulse generator chain, drive to Logic 0.
0 = if the buffer remains on outside of the pulse generator chain, allow the outputs to float naturally to
approximately VCM.
HMC7043 Data Sheet
Rev. B | Page 20 of 43
Table 13. Multislip Configuration
Bit Name Description
Multislip Enable Allow multislip. This bit determines whether the 12-Bit Multislip Digital Delay[11:0] parameter is used
for multislip operations. Note that a multislip operation is automatically started following a SYNC or
pulse generator initiation if multislip enable = 1.
12-Bit Multislip Digital Delay[11:0] Multislip amount. If multislip enable = 1, any slip events (caused by GPI, SPI, SYNC, or pulse generator
events) repeat the number of times set by 12-Bit Multislip Digital Delay[11:0] to adjust the phase by the
multislip amount × clock input cycles. A value of 0 is not supported if multislip enable = 1. Note that
phase slips are free from a noise and current perspective, that is, no additional power is needed and
with no noise degradation, but they take some time to occur. Each slip operation takes a number of
nanoseconds to complete, and thus the phases do not necessarily stabilize immediately. An alarm is
available for the user to indicate when all phase operations are complete.
Table 14. Typical Configuration Combinations
Bit Name DCLK Pulse Generator SYSREF Manual SYSREF NonJESD204B
12-Bit Channel Divider[11:0] Small Big Big Any
Start-Up Mode-Bit Normal Pulse generator Normal Normal
Fine Analog Delay[4:0] Off Optional Optional Off
Coarse Digital Delay[4:0] Optional Optional Optional Optional
Slip Enable
Optional
Optional
Optional
Optional
Multislip Enable Optional Off Optional Optional
High Performance Mode Optional Off Off Optional
Sync Enable On On On Optional
Dynamic Driver Enable Don’t care On Don’t care Don’t care
Force Mute[1:0] Don’t care On Don’t care Don’t care
Synchronization FSM/Pulse Generator Timing
Figure 25 show a block diagram of the interface of the SYNC/
pulse generator control to the divider channels and the internal
SYSREF timer.
The SYSREF timer counts in periods defined by SYSREF
Timer[11:0], a 12-bit setting from the SPI. The SYSREF
timer sequences the enable, reset, and startup, and disables
the downstream dividers in the event of sync or pulse generator
requests. Program the SYSREF timer count to a submultiple of
the lowest output frequency in the clock network, and never
faster than 4 MHz. To synchronize the divider channels, it is
recommended, though not required, that the SYSREF Timer[11:0]
bits be set to a related frequency that is either a factor or
multiple of other frequencies on the IC.
The pulse generator is defined with respect to the periods of
this SYSREF timer, not with respect to the output period. This
behavior of the pulse generator leads to a timing constraint that
must be considered to prevent any runt pulses from affecting
the pulse generator stream.
Figure 27 shows the start-up behavior of an example divider
that is configured as a pulse generator, with a period matching
the internal SYSREF period.
The startup of the pulse stream occurs a fixed number of clock
input cycles after the FSM transitions to the start phase. Disabling
the pulse generator stream where the logic path is forced to zero
comes from a combinational path directly from the FSM.
Because the divider has the option for nearly arbitrary phase
adjustment, the stop condition can arrive when the pulse stream
is a Logic 1 and create a runt pulse.
For phase offsets of zero to (50% − 8) clock input cycles, and at
clock input frequencies <3 GHz, this condition is met naturally
within the design. For clock input frequencies >3 GHz, it is
recommended to use digital delay or slip offsets to increase the
natural phase offset and avoid the stress conditions.
The situation is avoided by never applying phase offset more
than (50% − 8) clock input cycles to an output channel
configured as a pulse generator.
Data Sheet HMC7043
Rev. B | Page 21 of 43
CLEAR
RESET
RF_SYNC
SYNC
REQUEST
PULSE
GENERATOR
REQUEST
WAIT
STARTUP
PULSE
GENERATOR
TIMEOUT?
SYNC
SETUP PULSE
GENERATOR
SETUP
NOTIFY CHANNEL FSM
WHAT TYPE OF EVENT
IS COMING
DONE
POWER DIVI DERS/S YNC BLOCKS,
PAUSE BLO CKS , RES ET L ATCHES
REMO V E LATCH RES ET,
PREPARE TO S TART CLOCKS
START CLOCKS,
WI TH CL E AN TI M ING ,
SMALL PIPELINE DELAY
WAI T UNT IL THE NUMBER OF
PULS E GE NE RATOR CY CLES
EXPIRES
REMOVE POWER
13114-125
Figure 26. Synchronization FSM Flowchart
FSM STATE STARTUP
DIVIDER CHANNEL
FI X E D NUM BE R OF CLOCK INPUT CY CLES
FROM STATE CHANG E TO STARTUP, AND
ANY INTE NTIONAL DIGITAL/ANALOG OFFSET
IF MUT E S IG NAL ARRIVES QUICKLY
RELATIVE TO SIGNAL TRAIN,
NO RUNT PULSE
PULS E G E NERATOR = 2 DONE
FSM STATE STARTUP
DIVIDER CHANNEL
IF CONTROL IS TOO LATE
RELATIVE TO SI GNAL TRAIN,
THERE IS A RUNT PULSE
PULS E G E NERATOR = 2 DONE
13114-126
Figure 27. Start-Up Behavior of an Example Divider Configured as a Pulse Generator
HMC7043 Data Sheet
Rev. B | Page 22 of 43
Clock Grouping, Skew, and Crosstalk
Although the output channels are logically independent, for
physical reasons, they are first grouped into pairs, called clock
groups. Each clock group shares a reference, an input buffer,
and a SYNC retime flip flop originating from the clock
distribution network.
The second level of grouping is according to the supply pin. Clock
Group 1 (Channel 2 and Channel 3) is on an independent supply,
and the other supply pins are each responsible for two clock groups.
As the output channels are more tightly coupled (by sharing a
clock group or by sharing a supply pin), the skew is minimized.
However, the isolation between those channels suffers.
Table 15 shows the clock grouping by location, and Table 16
show the typical skew and isolation that can be expected and how
it scales with distance between output channels.
Isolation improves as either the aggressor or the affected
frequencies decrease. Nevertheless, for particularly important
clock channels where spurious tones must be minimized, carefully
consider their frequency and channel configurations to isolate
continuously running frequencies onto different supply domains.
Channels configured as pulse generators are normally not an
issue, because they are disabled during normal operation.
Table 15. Supply Pin Clock Grouping by Location
Supply Pin Location Clock Group Channel
VCC2_OUT Southwest 1 2
3
VCC3_OUT South 2 4
5
3 6
7
VCC6_OUT Northeast 4 8
9
5
10
11
VCC7_OUT Northwest 6 12
13
0 0
1
Table 16. Typical Skew and Isolation vs. Distance
Distance
Typical
Skew (ps)
1 GHz Isolation,
Differential (dB)
Distant Supply Group ±20 90 to 100
Closest Neighbor on
Different Supply Group
±15 70
Shared Supply ±10 60
Same Clock Group ±10 45
Data Sheet HMC7043
Rev. B | Page 23 of 43
Output Buffer Details
NORTHWEST NORTHEAST
SOUTHSOUTHWEST
VCC7_OUT
VCC2_OUT
CLKOUT12
CLKOUT12
VCC6_OUT
VCC3_OUT
RESET
BGAPBYP1
LDOBYP2
VCC1_
CLKDIST
SCLKOUT5
SCLKOUT5
CLKOUT4
CLKOUT4
CLKOUT6
CLKOUT6
SCLKOUT7
SCLKOUT7
CLKOUT0
CLKOUT0 SCLKOUT9
GPIO
SPI
VCC5_
SYSREF
VCC4_
CLKIN
SCLKOUT9
RFSYNCIN
RFSYNCIN
CLKIN
CLKIN
SCLKOUT1
SCLKOUT1
CLKOUT2
CLKOUT2
SCLKOUT3
SCLKOUT3
SCLKOUT13
SCLKOUT13
SCLKOUT11
SCLKOUT11
CLKOUT10
CLKOUT10
CLKOUT8
CLKOUT8
13114-026
Figure 28. Clock Grouping
Figure 28 shows the clock groups by supply pin location on the
package. With appropriate supply pin bypassing, the spurious
noise of the outputs is improved.
Table 15 describes how the supply pins of each of the 14 clock
channels are connected within the seven clock groups. Clock
channels that are closest to each other have the best channel to
channel skew performance, but they also have the lowest isolation
from each other. Select critical signals that require high isolation
from each other from groups with distant supply pin locations.
An example of the expected isolation and channel to channel
skew performance of the HMC7043 at 1 GHz is provided in
Table 16.
SYSREF Valid Interrupt
One of the challenges in a JESD204B system is to control and
minimize the latency from the primary system controller IC,
typically an ASIC or FPGA, to the data converters. To estimate
the correct amount of latency in the system, the designer must
know the time required for a master clock generator like the
HMC7043 to provide the correct output phases at each output
channel after receiving the synchronization request. Typically, a
period of time is required on the device to implement the
change requests on the outputs due to internal state machine
cycles, data transfers, and any propagation delays. The SYSREF
valid interrupt is a function to notify the user that the correct
output settings and phase relationships are established, allowing
the user to identify quickly that the desired SYSREF and device
clock states are presented at the outputs of the HMC7043.
The user has the flexibility to assign the SYSREF valid interrupt to
a GPO pin or to use a software flag, set via Register 0x007D, Bit 2,
which the user may poll as necessary. The flag notifies the user
when the system is configured and operating in the desired
state, or conversely when it is not ready.
TYPICAL PROGRAMMING SEQUENCE
To initialize the HMC7043 to an operational state, use the
following programming procedure:
1. Connect the HMC7043 to the rated power supplies. No
specific power supply sequencing is necessary.
2. Release the hardware reset by switching from Logic 1 to
Logic 0 when all supplies are stable.
3. Load the configuration updates (provided by Analog
Devices, Inc.) to specific registers (see Table 40).
4. Program the SYSREF timer. Set the divide ratio (a submultiple
of the lower output channel frequency). Set the pulse
generator mode configuration, for example, selecting the
level sensitivity option and the number of pulses desired.
5. Program the output channels. Set the output buffer modes
(for example, LVPECL, CML, and LVDS). Set the divide
ratio, channel start-up mode, coarse/analog delays, and
performance modes.
6. Ensure the clock input signal are provided to CLKIN.
HMC7043 Data Sheet
Rev. B | Page 24 of 43
7. Issue a software restart to reset the system and initiate
calibration. Toggle the restart dividers/FSMs bit to 1 and
then back to 0.
8. Send a sync request via the SPI (set the reseed request bit)
to align the divider phases and send any initial pulse
generator stream.
9. Wait six SYSREF periods (6 × SYSREF Timer[11:0]) to
allow the outputs to phase appropriately (~3 μs in typical
configurations).
10. Confirm that the outputs have all reached their phases by
checking that the clock outputs phases status bit = 1.
11. At this time, initialize any other devices in the system.
Configure the slave JESD204B devices in the system to
operate with the SYSREF signal outputs from the HMC7043.
The SYSREF channels from the HMC7043 can be on either
asynchronously or dynamically, and may temporarily turn
on for a pulse generator stream.
12. Slave JESD204B devices in the system must be configured
to monitor the input SYSREF signal exported from the
HMC7043. At this point, SYSREF channels from the
HMC7043 can either be on asynchronously (running) or on
dynamically (temporarily turn on for a pulse generator train).
13. When all JESD204B slaves are powered and ready, send a
pulse generator request to send out a pulse generator chain on
any SYSREF channels programmed for pulse generator mode.
The system is initialized.
For power savings and the reduction of the cross coupling of
frequencies on the HMC7043, shut down the SYSREF channels.
1. Program each JESD204B slave to ignore the SYSREF input
channel.
2. On the HMC7043, disable the individual channel enable bits
of each SYSREF channel.
To resynchronize one or more of the JESD204B slaves, use the
following procedure:
1. Set the channel enable and SYNC enable bit of the SYSREF
channel of interest.
2. To prevent an output channel from responding to a sync
request, disable the SYNC enable mask of each channel so
that it continues to run normally without a phase adjustment.
3. Issue a reseed request to phase the SYSREF channel
properly with respect to the DCLK.
4. Enable the JESD204B slave sensitivity to the SYSREF channel.
5. If the SYSREF channel is in pulse generator mode, wait at
least 20 SYSREF periods from Step 3, and issue a pulse
generator request.
POWER SUPPLY CONSIDERATIONS
The output buffers are susceptible to supply with a certain
extent. The output buffers are also susceptible to supply noise,
but to a lesser extent. A noise tone of −60 dBV at a 40 MHz
offset results in a −90 dBc tone at the output of the buffers in
CML mode and −85 dBc in LVPECL mode. This result is a
relatively flat frequency response, and these numbers are
measured differentially. Phase noise/spurs caused by supply
noise on the output buffers do not scale with output frequency.
Table 17 lists the supply network of the HMC7043 by pin, showing
the relevant functional blocks. Three different usage profiles are
defined for the network, not including the output channel
supplies, which are accounted for separately.
The values listed under Profile 0 to Profile 2 in Table 17 and
Table 18 are the typical currents of that block or feature. If a
number is not listed in a profile column, a typical profile does
not exist for that block or feature, but the user can mix and
match features outside of the profile list, and can determine
what the power consumption is going to be given the current
listings per feature.
Data Sheet HMC7043
Rev. B | Page 25 of 43
Table 17. Supply Network of the HMC7043 by Pin for VCC1_CLKDIST, VCC4_CLKIN, and VCC5_SYSREF
Circuit Block Comment Typical Current (mA)
Profile1
0 1 2
VCC1_CLKDIST
Regulator to 1.8 V, Bypassed on LDOBYP2 2 2 2 2
SYSREF Timer 1 1
GPO Driver in High Speed Mode2
Clock Input Distribution Network Minimum possible value 84 8 84 34
Sync Retiming Network Minimum possible value3 8
Subtotal for VCC1_CLKDIST 10 87 36
VCC4_CLKIN
CLKIN/CLKIN Buffer 16 16 16
CLKIN/CLKIN Path Extra current for divide by 2 7
RFSYNCIN/RFSYNCIN4 Retimer 3
RFSYNCIN/RFSYNCIN Buffer 9
Subtotal or VCC4_CLKIN 0 16 16
VCC5_SYSREF
SYSREF Input Network 11 11
SYSREF Counter Base 12 12
SYSREF Counter, SYNC Network
4
Subtotal for VCC5_SYSREF 27 0 23 0
Subtotal (Without Output Paths) 10 126 52
1 Profile 0 is sleep mode; Profile 1 is power-up defaults, SYSREF timer running and RFSYNC buffer is disabled; Profile2 is only one clock output enabled, SYSREF timer is
not running and RFSYNC buffer is disabled.
2 The current is highly dependent on rate of input/output and load of input/output traces. For heavily loaded traces, it is recommended to use a series resistance of
~100to minimize the IR drop on the internal regulator during transitions.
3 A temporary current only.
4 Transient current in synchronization mode, can be temporarily enabled when using external synchronization.
HMC7043 Data Sheet
Rev. B | Page 26 of 43
Table 18. Supply Network of the HMC7043 by Pin for the Clock Output Network
Per Output Channel Comment Typical Current (mA)
Profile1
0 1 2 3 4
Digital Regulator and Other Sources
2.5
0.5
2.5
2.5
2.5
2.5
Buffer
LVPECL Including term currents 43 43 43 43
CML100
High Power
Including term currents
31
Low Power 24
LVDS
High Power At 307 MHz 10 10
Low Power 8
CMOS
At 100 MHz, both sections
25
Channel Mux Included2
Different Power Modes Deleted 2 2 2 2
Digital Delay
Off Included2
Setpoint > 1 3 3 3
Analog Delay
Off Included2 0
Minimum Setting Glitchless mode enabled 9 9
Maximum Setting 9 9
Divider Logic
0 Not using divider path Included2 0 0
÷1 27
÷2
24
÷3 31
÷4 28
÷5 30
÷6 26
÷8 28
÷16 29 29
÷32 29
÷2044 29 29
SYNC Logic
3
4
Slip Logic3 4
Subtotal 2.5 48 87 13 89
1 Profile 0 is sleep mode; Profile 1 is fundamental mode; Profile 2 is SYSREF channel matched to fundamental mode; Profile 3 is LVDShigh power signal source from
other channel; and Profile 4 is worst case configuration for power consumption of a channel.
2 The base current consumption of the circuit (for example, mux) is included in the buffer typical current.
3 Currents only occur temporarily during a synchronization event.
Data Sheet HMC7043
Rev. B | Page 27 of 43
SERIAL CONTROL PORT
SERIAL PORT INTERFACE (SPI) CONTROL
The HMC7043 can be controlled via the SPI using 24-bit
registers and three pins: serial port enable (SLEN) serial data
input/output (SDATA), and serial clock (SCLK).
The 24-bit register, shown in Table 19, consists of the following:
1-bit read/write command
2-bit multibyte field (W1, W0)
13-bit address field (A12 to A0)
8-bit data field (D7 to D0)
Table 19. SPI Bit Map
MSB LSB
Bit 23 Bit 22 Bit 21 Bits[20:8] Bits[7:0]
R/W W1 W0 A12 to A0 D7 to D0
Typical Read Cycle
A typical read cycle is shown in Figure 29 and occurs as follows:
1. The master (host) asserts both SLEN and SDATA to
indicate a read, followed by a rising edge SCLK. The slave
(HMC7043) reads SDATA on the first rising edge of SCLK
after SLEN. Setting SDATA high initiates a read.
2. The host places the 2-bit multibyte field to be written to
low (0) on the next two falling edges of SCLK. The
HMC7043 registers the 2-bit multibyte field on the next
two rising edges of SCLK.
3. The host places the 13-bit address field (A12 to A0) MSB
first on SDATA on the next 13 falling edges of SCLK. The
HMC7043 registers the 13-bit address field (MSB first) on
SDATA over the next 13 rising edges of SCLK.
4. The host registers the 8-bit data on the next eight rising
edges of SCLK. The HMC7043 places 8-bit data (D7 to D0)
MSB first on the next eight falling edges of SCLK.
5. Deassertion of SLEN completes the register read cycle.
Typical Write Cycle
A typical write cycle is shown in Figure 30 and occurs as follows:
1. The master (host) asserts both SLEN and SDATA to
indicate a read, followed by a rising edge SCLK. The slave
(HMC7043) reads SDIO on the first rising edge of SCLK
after SLEN. Setting SDATA low initiates a write.
2. The host places the 2-bit multibyte field to be written to
low (0) on the next two falling edges of SCLK. The
HMC7043 registers the 2-bit multibyte field on the next
two rising edges of SCLK.
3. The host places the13-bit address field (A12 to A0), MSB
first, on SDATA on the next 13 falling edges of SCLK. The
HMC7043 registers the 13-bit address field (MSB first) on
SDIO over the next 13 rising edges of SCLK.
4. The host places the 8-bit data (D7 to D0) MSB first on the
next eight falling edges of SCLK. The HMC7043 register
the 8-bit data (D7 to D0) MSB first on the next eight rising
edges of SCLK.
5. The final rising edge of SCLK performs the internal data
transfer into the register file, updating the configuration of
the device.
6. Deassertion of SLEN completes the register write cycle.
SCLK 1
XREAD W1 W0 A12 A11 A0 D7 D6 D0
2 3 4 516 17 18 24
SDATA
SLEN
13114-128
Figure 29. SPI Timing Diagram, Read Operation
SCLK 1
XWRITE W1 W0 A12 A11 A0 D7 D6 D0
2 3 4 5 16 17 18 24
SDATA
SLEN
13114-129
Figure 30. SPI Timing Diagram, Write Operation
HMC7043 Data Sheet
Rev. B | Page 28 of 43
CONTROL REGISTERS
CONTROL REGISTER MAP
Table 20. Control Register Map
Address
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
Global Control
0x0000 Global soft reset
control
Reserved Soft reset 0x00
0x0001 Global request
and mode
control
Reseed
request
High performance
distribution path
Reserved Reserved Mute output
drivers
Pulse
generator
request
Restart
dividers/
FSMs
Sleep mode 0x00
0x0002 Reserved Multislip
request
Reserved 0x00
0x0003 Global enable
control
Reserved RF
reseeder
enable
Reserved SYSREF
timer
enable
Reserved Reserved 0x34
0x0004 Reserved Seven Pairs of 14-Channel Outputs Enable[6:0] 0x7F
0x0005 Global mode
and enable
control
Reserved 0x0F
0x0006 Global clear
alarms
Reserved Clear alarms 0x00
0x0007
Global
miscellaneous
control
Reserved
0x00
0x0008 Reserved (scratchpad) 0x00
0x0009
Reserved
0x00
Input Buffer
0x000A CLKIN0/CLKIN0
input buffer
control
Reserved Input Buffer Mode[3:0] Buffer enable 0x07
0x000B
CLKIN1/CLKIN1
input buffer
control
Reserved
Input Buffer Mode[3:0]
Buffer enable
0x07
GPIO/SDATA Control
0x0046 GPI control Reserved GPI Selection [2:0] GPI enable 0x00
0x0050 GPO control Reserved GPO Selection[4:0] GPO
mode
GPO enable 0x37
0x0054 SDATA control Reserved SDATA
mode
SDATA enable 0x03
SYSREF/SYNC
0x005A Pulse generator
control
Reserved Pulse Generator Mode Selection[2:0] 0x00
0x005B SYNC control Reserved SYNC
retime
Reserved SYNC invert
polarity
0x04
0x005C SYSREF timer
control
SYSREF Timer[7:0] (LSB) 0x00
0x005D Reserved SYSREF Timer[11:8](MSB) 0x01
Clock Distribution Network
0x0064 Clock input
control
Reserved Divide
by 2 on
clock
input
Low
frequency
clock input
0x00
0x0065
Analog delay
common
control
Reserved
Analog delay
low power
mode
0x00
Alarm Masks Register
0x0071
Alarm mask
control
Reserved
Sync
request
mask
Reserved
Clock
outputs
phase
status
mask
SYSREF
sync
status
mask
Reserved
0x10
Product ID Registers
0x0078 Product ID Product ID Value[7:0] (LSB)
0x0079 Product ID Value[15:8] (Mid)
0x007A Product ID Value[23:16] (MSB)
Data Sheet HMC7043
Rev. B | Page 29 of 43
Address
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
Alarm Readback Status Registers
0x007B Readback
register
Reserved Alarm signal
0x007D Alarm readback Reserved Sync
request
status
Reserved Clock
outputs
phases
status
SYSREF
sync
status
Reserved
0x007F Alarm readback Reserved
SYSREF Status Register
0x0091 SYSREF status
register
Reserved Channel
outputs
FSM busy
SYSREF FSM State[3:0] 0x00
Other Controls
0x0098
Reserved
Reserved
0x00
0x0099 Reserved Reserved 0x00
0x009D Reserved Reserved 0xAA
0x009E Reserved Reserved 0xAA
0x009F Reserved Reserved 0x55
0x00A0 Reserved Reserved 0x56
0x00A2 Reserved Reserved 0x03
0x00A3 Reserved Reserved 0x00
0x00A4 Reserved Reserved 0x00
0x00AD Reserved Reserved 0x00
0x00B5 Reserved Reserved 0x00
0x00B6 Reserved Reserved 0x00
0x00B7 Reserved Reserved 0x00
0x00B8 Reserved Reserved 0x00
Clock Distribution
0x00C8 Channel
Output 0
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xF3
0x00C9 12-Bit Channel Divider[7:0] (LSB) 0x04
0x00CA Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x00CB Reserved Fine Analog Delay[4:0] 0x00
0x00CC Reserved Coarse Digital Delay[4:0] 0x00
0x00CD 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00CE Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00CF Reserved Output Mux Selection[1:0] 0x00
0x00D0
Idle at Zero[1:0]
Dynamic
driver
enable
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
0x01
0x00D2
Channel
Output 1
control
High
performance
mode
SYNC enable
Slip enable
Reserved
Start-Up Mode[1:0]
Multislip
enable
Channel
enable
0xFD
0x00D3 12-Bit Channel Divider[7:0] (LSB) 0x00
0x00D4 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x00D5 Reserved Fine Analog Delay[4:0] 0x00
0x00D6 Reserved Coarse Digital Delay[4:0] 0x00
0x00D7 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00D8 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00D9 Reserved Output Mux Selection[1:0] 0x00
0x00DA Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
HMC7043 Data Sheet
Rev. B | Page 30 of 43
Address
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
0x00DC Channel
Output 2
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xF3
0x00DD 12-Bit Channel Divider[7:0] (LSB) 0x08
0x00DE Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x00DF Reserved Fine Analog Delay[4:0] 0x00
0x00E0 Reserved Coarse Digital Delay[4:0] 0x0
0x00E1 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00E2 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00E3 Reserved Output Mux Selection[1:0] 0x00
0x00E4 Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
0x00E6 Channel
Output 3
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xFD
0x00E7 12-Bit Channel Divider[7:0] (LSB) 0x00
0x00E8 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x00E9 Reserved Fine Analog Delay[4:0] 0x00
0x00EA Reserved Coarse Digital Delay[4:0] 0x00
0x00EB 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00EC Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00ED Reserved Output Mux Selection[1:0] 0x00
0x00EE Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
0x00F0 Channel
Output 4
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xF3
0x00F1 12-Bit Channel Divider[7:0] (LSB) 0x02
0x00F2 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x00F3 Reserved Fine Analog Delay[4:0] 0x00
0x00F4 Reserved Coarse Digital Delay[4:0] 0x00
0x00F5 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00F6 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00F7 Reserved Output Mux Selection[1:0] 0x00
0x00F8
Idle at Zero[1:0]
Dynamic
driver
enable
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
0x01
0x00FA
Channel
Output 5
control
High
performance
mode
SYNC enable
Slip enable
Reserved
Start-Up Mode[1:0]
Multislip
enable
Channel
enable
0xFD
0x00FB 12-Bit Channel Divider[7:0] (LSB) 0x00
0x00FC
Reserved
12-Bit Channel Divider[11:8] (MSB)
0x01
0x00FD Reserved Fine Analog Delay[4:0] 0x00
0x00FE
Reserved
Coarse Digital Delay[4:0]
0x00
0x00FF 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0100 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0101 Reserved Output Mux Selection[1:0] 0x00
0x0102 Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
Data Sheet HMC7043
Rev. B | Page 31 of 43
Address
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
0x0104 Channel
Output 6
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xF3
0x0105 12-Bit Channel Divider[7:0] (LSB) 0x02
0x0106 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x0107 Reserved Fine Analog Delay[4:0] 0x00
0x0108 Reserved Coarse Digital Delay[4:0] 0x00
0x0109 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x010A Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x010B Reserved Output Mux Selection[1:0] 0x00
0x010C Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
0x010E Channel
Output 7
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xFD
0x010F 12-Bit Channel Divider[7:0] (LSB) 0x00
0x0110 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x0111 Reserved Fine Analog Delay[4:0] 0x00
0x0112 Reserved Coarse Digital Delay[4:0] 0x00
0x0113 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0114 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0115 Reserved Output Mux Selection[1:0] 0x00
0x0116 Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
0x0118 Channel
Output 8
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xF3
0x0119 12-Bit Channel Divider[7:0] (LSB) 0x02
0x011A Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x011B Reserved Fine Analog Delay[4:0] 0x00
0x011C Reserved Coarse Digital Delay[4:0] 0x00
0x011D 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x011E Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x011F Reserved Output Mux Selection[1:0] 0x00
0x0120
Idle at Zero[1:0]
Dynamic
driver
enable
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
0x01
0x0122
Channel
Output 9
control
High
performance
mode
SYNC enable
Slip enable
Reserved
Start-Up Mode[1:0]
Multislip
enable
Channel
enable
0xFD
0x0123 12-Bit Channel Divider[7:0] (LSB) 0x00
0x0124
Reserved
12-Bit Channel Divider[11:8] (MSB)
0x01
0x0125 Reserved Fine Analog Delay[4:0] 0x00
0x0126
Reserved
Coarse Digital Delay[4:0]
0x00
0x0127 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0128 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0129 Reserved Output Mux Selection[1:0] 0x00
0x012A Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
HMC7043 Data Sheet
Rev. B | Page 32 of 43
Address
(Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
0x012C Channel
Output 10
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xF3
0x012D 12-Bit Channel Divider[7:0] (LSB) 0x02
0x012E Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x012F Reserved Fine Analog Delay[4:0] 0x00
0x0130 Reserved Coarse Digital Delay[4:0] 0x00
0x0131 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0132 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0133 Reserved Output Mux Selection[1:0] 0x00
0x0134 Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
0x0136 Channel
Output 11
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xFD
0x0137 12-Bit Channel Divider[7:0] (LSB) 0x00
0x0138 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x0139 Reserved Fine Analog Delay[4:0] 0x00
0x013A Reserved Coarse Digital Delay[4:0] 0x00
0x013B 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x013C Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x013D Reserved Output Mux Selection[1:0] 0x00
0x013E Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
0x0140 Channel
Output 12
control
High
performance
mode
SYNC enable Slip enable Reserved Start-Up Mode[1:0] Multislip
enable
Channel
enable
0xF3
0x0141 12-Bit Channel Divider[7:0] (LSB) 0x10
0x0142 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x0143 Reserved Fine Analog Delay[4:0] 0x00
0x0144 Reserved Coarse Digital Delay[4:0] 0x00
0x0145 12-Bit Multi-Slip Digital Delay[7:0] (LSB) 0x00
0x0146 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0147 Reserved Output Mux Selection[1:0] 0x00
0x0148
Idle at Zero[1:0]
Dynamic
driver
enable
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
0x01
0x014A
Channel
Output 13
control
High
performance
mode
SYNC enable
Slip enable
Reserved
Start-Up Mode [1:0]
Multislip
enable
Channel
enable
0xFD
0x014B 12-Bit Channel Divider[7:0] (LSB) 0x00
0x014C
Reserved
12-Bit Channel Divider[11:8] (MSB)
0x01
0x014D Reserved Fine Analog Delay[4:0] 0x00
0x014E
Reserved
Coarse Digital Delay[4:0]
0x00
0x014F 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0150 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0151 Reserved Output Mux Selection[1:0] 0x00
0x0152 Idle at Zero[1:0] Dynamic
driver
enable
Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
Data Sheet HMC7043
Rev. B | Page 33 of 43
CONTROL REGISTER MAP BIT DESCRIPTIONS
Global Control (Register 0x0000 to Register 0x0009)
Table 21. Global Soft Reset Control
Address Bits Bit Name Settings Description Access
0x0000 [7:1] Reserved Reserved RW
0
Soft reset
Resets all registers, dividers, and FSMs to default values
Table 22. Global Request and Mode Control
Address Bits Bit Name Settings Description Access
0x0001 7 Reseed request Requests the centralized resync timer and FSM to reseed any of the output
dividers that are programmed to pay attention to sync events. This signal is
rising edge sensitive, and is only acknowledged if the resync FSM has
completed all events (has finished any previous pulse generator and/or
sync events, and is in the done state (SYSREF FSM State[3:0] = 0010).
RW
6
High performance
distribution path
High performance distribution path select. The clock distribution path
has two modes.
0 Power priority.
1 Noise priority. Provides the option for better noise floors on the divided
output signals.
5 Reserved Reserved.
4 Reserved Reserved.
3 Mute output drivers Mutes the output drivers (dividers still run in the background).
2 Pulse generator request Asks for a pulse stream (see the Typical Programming Sequence section).
1 Restart dividers/FSMs Resets all dividers and FSMs. Does not affect configuration registers.
0 Sleep mode Forces shutdown. Output network, and I/O buffers are disabled.
0x0002 [7:2] Reserved Reserved. RW
1 Multislip request Requests a slip or multislip event from all divider channels that are
sensitive to slip or multislip commands. The dividers are rising edge
sensitive and take some time to process the request, after which the
phase synchronization alarm is asserted.
0 Reserved Reserved.
Table 23. Global Enable Control
Address Bits Bit Name Settings Description Access
0x0003 [7:6] Reserved Reserved RW
5 RF reseeder enable Enable RF reseed for SYSREF
[4:3] Reserved Reserved
2 SYSREF timer enable Enable internal SYSREF time reference
1 Reserved Reserved
0 Reserved Reserved
0x0004 7 Reserved Reserved RW
[6:0] Seven Pairs of 14-Channel Outputs Enable[6:0] [0] Enable Channel 0 and 1
[1]
Enable Channel 2 and 3
[2] Enable Channel 4 and 5
[3] Enable Channel 6 and 7
[4] Enable Channel 8 and 9
[5] Enable Channel 10 and 11
[6] Enable Channel 12 and 13
Table 24. Global Mode and Enable Control
Address Bits Bit Name Settings Description Access
0x0005 [7:0] Reserved Reserved RW
HMC7043 Data Sheet
Rev. B | Page 34 of 43
Table 25. Global Clear Alarms
Address Bits Bit Name Settings Description Access
0x0006 [7:1] Reserved Reserved RW
0 Clear alarms Clear latched alarms
Table 26. Global Miscellaneous Control
Address Bits Bit Name Settings Description Access
0x0007 [7:0] Reserved Reserved. RW
0x0008 [7:0] Reserved (scratchpad) Reserved. The user can write/read to this register to confirm input/outputs
to the HMC7043. This register does not affect device operation.
RW
0x0009 [7:0] Reserved Reserved. RW
Input Buffer (Register 0x000A to Register 0x000B)
Table 27. CLKIN/CLKIN and RFSYNCIN/RFSYNCIN Input Buffer Control
Address Bits Bit Name Settings Description Access
0x000A, 0x000B [7:5] Reserved Reserved RW
[4:1] Input Buffer Mode[3:0] Input buffer control
[0] Enable internal 100 Ω termination
[1] Enable ac coupling input mode
[2] Enable LVPECL input mode
[3] High-Z input enable
0 Buffer enable Enable input buffer
GPIO/SDATA Control (Register 0x0046 to Register 0x0054)
Table 28. GPI Control
Address Bits Bit Name Settings Description Access
0x0046 [7:4] Reserved Reserved RW
[3:1] GPI Selection[2:0] Select the GPI functionality, Bits[2:0]
0000 Select the GPI functionality, Bits[2:0]
0001
Reserved
0010
Put the chip into sleep mode
0011 Issue a mute
0100 Issue a pulse generator request
0101 Issue a reseed request
0110 Issue a restart request
0111 Reserved
1000 Issue a slip request
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101
Reserved.
1110 Reserved
1111 Reserved.
0
GPI enable
GPI function enable. Before changing the function of the pin, disable it first,
and then reenable it after the function change.1
1 Note that it is possible to have a GPIO delete pin configured as both an output and an input.
Data Sheet HMC7043
Rev. B | Page 35 of 43
Table 29. GPO Control
Address Bits Bit Name Settings Description Access
0x0050 7 Reserved Reserved RW
[6:2] GPO Selection[4:0] Select the GPO functionality, Bits[4:0]
00000 Alarm signal
00001 SDATA from SPI communication
00010 SYSREF sync status has not synchronized since reset
00011 Clock outputs phase status
00100 Sync request status signal
00101 Channel outputs FSM busy
00110 SYSREF FSM State 0
00111 SYSREF FSM State 1
01000 SYSREF FSM State 2
01001 SYSREF FSM State 3
01010
Force Logic 1 to GPO
01011 Force Logic 0 to GPO
01100 Reserved
01101 Reserved
01110 Reserved
01111
Reserved
10000 Reserved
10001 Reserved
10010 Reserved
10011 Reserved
10100 Reserved
10101 Reserved
10110 Reserved
10111 Reserved
11000 Reserved
11001 Pulse generator request status signal
11010 Reserved
11011
Reserved
11100 Reserved
11101 Reserved
11110 Reserved
11111 Reserved
1 GPO mode Selects the mode of GPO driver
0 Open-drain mode
1 CMOS mode
0 GPO enable GPO driver enable
Table 30. SDATA Control
Address Bits Bit Name Settings Description Access
0x0054 [7:2] Reserved Reserved RW
1 SDATA mode Selects the mode of SDATA driver
0
Open-drain mode
1 CMOS mode
0 SDATA enable SDATA driver enable
HMC7043 Data Sheet
Rev. B | Page 36 of 43
SYSREF/SYNC (Register 0x005A to Register 0x005D)
Table 31. Pulse Generator Control
Address
Bits
Bit Name
Settings
Description
Access
0x005A [7:3] Reserved Reserved. RW
[2:0] Pulse Generator
Mode
Selection[2:0]
SYSREF output enable with pulse generator.
000 Level sensitive. When the GPI is configured to issue a pulse generator
request (GPI Selection[2:0] = 100), or a pulse generator request is issued
through the SPI or as a SYNC pin-based pulse generator, run the pulse
generator. Otherwise, stop the pulse generator.
001
1 pulse.
010
2 pulses.
011 4 pulses.
100 8 pulses.
101 16 pulses.
110 16 pulses.
111 Continuous mode (50% duty cycle).
Table 32. SYNC Control
Address Bits Bit Name Settings Description Access
0x005B [7:3] Reserved Reserved RW
2 SYNC retime
0 Bypass the retime (non-deterministic SYNC event condition)
1 Retime the external SYNC (deterministic SYNC event condition)
1 Reserved Reserved
0 SYNC polarity SYNC polarity (must be 0 if not using CLKIN/CLKIN as the input)
0 Positive
1 Negative
Table 33. SYSREF Timer Control
Address Bits Bit Name Settings Description Access
0x005C [7:0] SYSREF Timer[7:0]
(LSB)
12-bit SYSREF timer setpoint LSB. This sets the internal beat frequency of
the master timer, which controls synchronization and pulse generator
events. Set the 12-bit timer to a submultiple of the lowest output SYSREF
frequency, and program it to be no faster than 4 MHz.
RW
0x005D [7:4] Reserved Reserved. RW
[3:0] SYSREF Timer[11:8]
(MSB)
12-bit SYSREF timer setpoint MSB.
Clock Distribution Network (Register 0x0064 to Register 0x0065)
Table 34. Clock Input Control
Address Bits Bit Name Settings Description Access
0x0064
[7:2]
Reserved
Reserved
RW
1 Divide by 2 on clock input Use divide by 2 on clock input path
0 Low frequency clock input Changes bias to Class A for low frequency clock input
Table 35. Analog Delay Common Control
Address Bits Bit Name Settings Description Access
0x0065 [7:1] Reserved Reserved. RW
0 Analog delay low
power mode
Analog delay is low power mode. Can save power for low settings of analog
delay, but is not glitchless between setpoints.
Data Sheet HMC7043
Rev. B | Page 37 of 43
Alarm Masks Register (Register 0x0071)
Table 36. Alarm Mask Control Register
Address Bits Bit Name Settings Description Access
0x0071 [7:5] Reserved Reserved RW
4 Sync request mask If set, allow sync request signals to generate an alarm signal
3 Reserved Reserved
2 Clock outputs phase status
mask
If set, allow clock output phases status signal to generate an alarm
signal
1 SYSREF sync status mask If set, allow SYSREF sync status signal to generate an alarm signal
0
Reserved
Reserved
Product ID Registers (Register 0x0078 to 0x007A)
Table 37. Product ID Registers
Address
Bits
Bit Name
Settings
Description
Access
0x0078 [7:0] Product ID Value[7:0] (LSB) 24-bit product ID value low R
0x0079
[7:0]
Product ID Value[15:8] (Mid)
24-bit product ID value mid
R
0x007A [7:0] Product ID Value[23:16] (MSB) 24-bit product ID value high R
Alarm Readback Status Registers (Register 0x007B to 0x007F)
Table 38. Alarm Readback Status Registers
Address Bits Bit Name Settings Description Access
0x007B [7:1] Reserved Reserved. R
0 Alarm signal Readback alarm status from SPI.
0x007D [7:5] Reserved Reserved. R
4 Sync request status Unsynchronized.
3 Reserved Reserved.
2 Clock outputs phases
status
SYSREF alarm.
0 SYSREF of the HMC7043 is not valid; that is, the phase output is not stable.
1 SYSREF of the HMC7043 is valid; that is, the phase output is stable.
1 SYSREF sync status SYSREF SYNC status alarm.
0 The HMC7043 has been synchronized with an external sync pulse or a
sync request from the SPI.
1 The HMC7043 never synchronized with an external sync pulse or a sync
request from the SPI.
0 Reserved 1 Reserved.
0x007F [7:0] Reserved Reserved. R
HMC7043 Data Sheet
Rev. B | Page 38 of 43
SYSREF Status Register (Register 0x0091)
Table 39. SYSREF Status
Address
Bits
Bit Name
Settings
Description
Access
0x0091 [7:5] Reserved Reserved. R
4 Channel outputs
FSM busy
One of clock outputs FSM requested clock, and it is running.
[3:0] SYSREF FSM
State[3:0]
Indicates the current step of the SYSREF reseed process. Note that the three
different progressions are caused by different trigger events (reseed, pulse
generator, reserved).
0000
Reset.
0010
Done.
0100 Get ready.
0101 Get ready.
0110 Get ready.
1010 Running (pulse generator).
1011 Start.
1100 Power up.
1101 Power up.
1110 Power up.
1111 Clear reset.
Bias Settings (Register 0x0096 to Register 0x00B8)
For optimum performance of the chip, Register 0x0098 to Register 0x00B8 must be programmed to a different value than their default value.
Table 40. Reserved Registers
Address Bits Bit Name Settings Description Access
0x0098 [7:0] Reserved Reserved RW
0x0099
[7:0]
Reserved
Reserved
RW
0x009D [7:0] Reserved Reserved RW
0x009E [7:0] Reserved Reserved RW
0x009F [7:0] Reserved Clock output driver low power setting (set to 0x4D instead of default value) RW
0x00A0 [7:0] Reserved Clock output driver high power setting (set to 0xDF instead of default value) RW
0x00A2 [7:0] Reserved Reserved RW
0x00A3 [7:0] Reserved Reserved RW
0x00A4 [7:0] Reserved Reserved RW
0x00AD [7:0] Reserved Reserved RW
0x00B5 [7:0] Reserved Reserved RW
0x00B6 [7:0] Reserved Reserved RW
0x00B7 [7:0] Reserved Reserved RW
0x00B8 [7:0] Reserved Reserved RW
Data Sheet HMC7043
Rev. B | Page 39 of 43
Clock Distribution (Register 0x00C8 to Register 0x0152)
The bit descriptions in Table 41 apply to all 14 channels.
Table 41. Channel 0 to Channel 13 Control
Address Bits Bit Name Settings1 Description Access
0x00C8, 0x00D2, 0x00DC,
0x00E6, 0x00F0, 0x00FA,
0x0104, 0x010E, 0x0118,
0x0122, 0x012C, 0x0136,
0x0140, 0x014A
7 High performance
mode
High performance mode. Adjusts the divider and buffer
bias to improve swing/phase noise at the expense of
power.
RW
6 SYNC enable Susceptible to SYNC event. The channel can process a
SYNC event to reset the phase.
5 Slip enable Susceptible to slip event. The channel can process a slip
request from SPI or GPI. Note that if slip enable is true,
but multislip is off, a channel slips by 1 clock input cycle
on an explicit slip request broadcast from the SPI/GPI.
4
Reserved
Reserved.
[3:2] Start-Up
Mode[1:0]
Configures the channel to normal mode with
asynchronous startup, or to a pulse generator mode with
dynamic start-up. Note that this must be set to
asynchronous mode if the channel is unused.
00 Asynchronous.
01 Reserved.
10 Reserved.
11 Dynamic.
1 Multislip enable Allow multislip operation (default = 0 for SYSREF, 1 for
DCLK).
0
Do not engage automatic multislip on channel startup.
1 Multislip events after SYNC or pulse generator request, if
the slip enable bit = 1.
0
Channel enable
Channel enable. If this bit is 0, channel is disabled.
0x00C9, 0x00D3, 0x00DD,
0x00E7, 0x00F1, 0x00FB,
0x0105, 0x010F, 0x0119,
0x0123, 0x012D, 0x0137,
0x0141, 0x014B
[7:0] 12-Bit Channel
Divider[7:0] (LSB)
12-bit channel divider setpoint LSB. The divider supports
even divide ratios from 2 to 4094. The supported odd
divide ratios are 1, 3, and 5. All even and odd divide ratios
have 50.0% duty cycle.
RW
0x00CA, 0x00D4, 0x00DE,
0x00E8, 0x00F2, 0x00FC,
0x0106, 0x0110, 0x011A,
0x0124, 0x012E, 0x0138,
0x0142, 0x014C
[7:4] Reserved Reserved. RW
[3:0] 12-Bit Channel
Divider[11:8]
(MSB)
12-bit channel divider setpoint MSB.
0x00CB, 0x00D5, 0x00DF,
0x00E9, 0x00F3, 0x00FD,
0x0107, 0x0111, 0x011B,
0x0125, 0x012F, 0x0139,
0x0143, 0x014D
[7:5] Reserved Reserved. RW
[4:0] Fine Analog
Delay[4:0]
24 fine delay steps. Step size = 25 ps. Values bigger than
23 has no effect on analog delay.
0x00CC, 0x00D6, 0x00E0,
0x00EA, 0x00F4, 0x00FE,
0x0108, 0x0112, 0x011C,
0x0126, 0x0130, 0x013A,
0x0144, 0x014E
[7:5] Reserved Reserved. RW
[4:0] Coarse Digital
Delay[4:0]
17 coarse delay steps. Step size = ½ input clock cycle. This
flip flop (FF)-based digital delay does not increase noise
level at the expense of power. Values bigger than 17 have
no effect on coarse delay.
0x00CD, 0x00D7, 0x00E1,
0x00EB, 0x00F5, 0x00FF,
0x0109, 0x0113, 0x011D,
0x0127, 0x0131, 0x013B,
0x0145, 0x014F
[7:0] 12-Bit Multislip
Digital Delay[7:0]
(LSB)
12-bit multislip digital delay amount LSB. Step size =
(delay amount: MSB + LSB) × input clock cycles. If
multislip enable bit = 1, any slip events (caused by GPI,
SPI, SYNC, or pulse generator events) repeat the number
of times set by 12-Bit Multislip Digital Delay[11:0] to
adjust the phase by step size.
RW
HMC7043 Data Sheet
Rev. B | Page 40 of 43
Address Bits Bit Name Settings1 Description Access
0x00CE, 0x00D8, 0x00E2,
0x00EC, 0x00F6, 0x0100,
0x010A, 0x0114, 0x011E,
0x0128, 0x0132, 0x013C,
0x0146, 0x0150
[7:4] Reserved Reserved. RW
[3:0]
12-Bit Multislip
Digital Delay[11:8]
(MSB)
12-bit multislip digital delay amount MSB.
0x00CF, 0x00D9, 0x00E3,
0x00ED, 0x00F7, 0x0101,
0x010B, 0x0115, 0x011F,
0x0129, 0x0133, 0x013D,
0x0147, 0x0151
[7:2] Reserved Reserved. RW
[1:0] Output Mux
Selection[1:0]
Channel output mux selection.
00
Channel divider output.
01 Analog delay output.
10 Other channel of the clock group pair.
11 Input clock (fundamental). Fundamental can also be
generated with 12-bit channel divider ratio = 1.
0x00D0, 0x00DA, 0x00E4,
0x00EE, 0x00F8, 0x0102,
0x010C, 0x0116, 0x0120,
0x012A, 0x0134, 0x013E,
0x0148, 0x0152
[7:6] Idle at Zero[1:0] Idle at Logic 0 selection (pulse generator mode only).
Force to Logic 0 or VCM.
RW
00 Normal mode (selection for DCLK).
01
Reserved.
10 Force to Logic 0.
11 Force outputs to float, goes naturally to VCM.
5 Dynamic driver
enable
Dynamic driver enable (pulse generator mode only).
0 Driver is enabled/disabled with channel enable bit.
1 Driver is dynamically disabled with pulse generator events.
[4:3]
Driver Mode[1:0]
Output driver mode selection.
00 CML mode.
01 LVPECL mode.
10 LVDS mode.
11 CMOS mode.
2 Reserved Reserved.
[1:0] Driver
Impedance[1:0]
Output driver impedance selection for CML mode.
00 Internal resistor disable.
01
Internal 100 Ω resistor enable per output pin.
10 Reserved.
11 Internal 50 Ω resistor enable per output pin.
1 X means don’t care.
Data Sheet HMC7043
Rev. B | Page 41 of 43
APPLICATIONS INFORMATION
EVALUATION PCB AND SCHEMATIC
For the circuit board in this application, use RF circuit design
techniques. Ensure that signal lines have 50 impedance.
Connect the package ground leads and exposed paddle directly
to the ground plane similar to that shown in Figure 32 and
Figure 33. Use a sufficient number of via holes to connect the
top and bottom ground planes. The evaluation circuit board is
available from Analog Devices, Inc., upon request.
The typical Pb-free reflow solder profile shown in Figure 31 is
based on JEDEC J-STD-20C.
13114-031
TEMPERATURE (°C)
217°C
RAMP UP
3°C/SECOND MAX
RAMP DOWN
6°C/SECOND MAX
TIME (Second)
60 TO 150
SECONDS
60 TO 180
SECONDS 20 TO 40
SECONDS
480 SECO NDS M AX
260 – 5/0°C
150°C TO 200°C
Figure 31. Pb-Free Reflow Solder Profile
13114-029
Figure 32. Evaluation PCB Layout, Top Side
HMC7043 Data Sheet
Rev. B | Page 42 of 43
13114-030
Figure 33. Evaluation PCB Layout, Bottom Side
Data Sheet HMC7043
Rev. B | Page 43 of 43
OUTLINE DIMENSIONS
11-20-2015-B
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NO M
0.20 REF
5.50 REF
COPLANARITY
0.08
0.31
0.25
0.19
7.10
7.00 SQ
6.90
0.90
0.85
0.80 F OR PROPER CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFIGURATIO N AND
FUNCT IO N DE S CRIPT IONS
SECTION OF THIS DATA SHEET.
0.45
0.40
0.35
0.20 MIN
5.66
5.60 SQ
5.54
48
1
13 12
24
25
36
37
PKG-000000
Figure 34. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.85 mm Package Height
(HCP-48-1)
Dimensions shown in millimeters
12-10-2015-A
NOTES:
1.
10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE
± 0.20
2. CAMBER I N COM P LIANCE W ITH EIA 481
3. MAT ERIAL: CO NDUCT IVE BLACK PO LYSTYRENE
4. MEASURED ON A PLANE 0.30 mm ABO VE T HE BOTTOM OF
THE PO CKET
5. MEASURED FROM A PLANE ON THE INSIDE BO TTOM OF
THE PO CKET TO THE TOP SURFACE OF THE CARRIER
6. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED
AS TRUE PO S ITI ON OF POCKET, NO T P OCKET HOLE
NOT E 4
NOT E 4
NOT E 5
NOT E 6 NOT E 1
NOT E 6
DETAI L A
DETAI L A
16.30
16.00
15.70
DIRECTION OF FEED
7.35
7.25
7.15
7.35
7.25
7.15
12.10
12.00
11.90
4.10
4.00
3.90
7.60
7.50
7.40
2.10
2.00
1.90
1.85
1.75
1.65
1.20
1.10
1.00
A
A
Ø 1. 5 ~ 1.6
Ø 1.5 MIN
TOP VIEW
SECT IO N A- A
R 0.25
0.25
0.35
0.30
0.25
Figure 35. LFCSP Tape and Reel Outline Dimensions
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Lead Finish MSL Rating2 Package Description Package Option Branding3
HMC7043LP7FE 40oC to +85°C NiPdAu MSL-3 48-Lead Lead Frame Chip
Scale Package [LFCSP]
HCP-48-1
XXXX
7043
HMC7043LP7FETR −40oC to +85°C NiPdAu MSL-3 48-Lead Lead Frame Chip
Scale Package [LFCSP]
HCP-48-1
XXXX
7043
EK1HMC7043LP7F 40°C to +85°C Evaluation Kit
1 E = RoHS Compliant Part.
2 The maximum peak reflow temperature is 260°C for the HMC7043LP7FE.
3 Four-digit lot number represented by XXXX.
©20152016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13114-0-7/16(B)