1
File Number 6010
DG506A, DG507A, DG509A
CMOS Analog Multiplexers
The DG506A, DG507A and DG509A are CMOS Monolithic
16-Channel/Dual 8-Channel and Dual 4-Channel Analog
Multiplexers, which can also be used as demultiplexers. An
enable input is provided. When the enable input is high, a
channel is selected by the address inputs, and when low, all
channels are off.
A channel in the ON state conducts current equally well in
both directions. In the OFF state each channel blocks
voltages up to the supply rails. The address inputs and the
enable input are TTL and CMOS compatible over the full
specified operating temperature range.
The DG506A, DG507A and DG509A are pinout compatible
with the industry standard devices.
Features
• Low Power Consumption
• TTL and CMOS-Compatible Address and Enable Inputs
• 44V Maximum Power Supply Rating
• High Latch-Up Immunity
• Break-Before-Make Switching
• Alternate Source
Applications
• Data Acquisition Systems
• Communication Systems
• Signal Multiplexing/Demultiplexing
• Audio Signal Multiplexing
Part Number Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
DG506AAK -55 to 125 28 Ld CERDIP F28.6
DG506ACJ 0to70 28LdPDIP E28.6
DG506ACY 0to70 28LdSOIC M28.3
DG507ABK -25 to 85 28 Ld CERDIP F28.6
DG507ACJ 0to70 28LdPDIP E28.6
DG507ACY 0to70 28LdSOIC M28.3
DG509ACJ 0to70 16LdPDIP E16.3
DG509ACY 0to70 16LdSOIC M16.3
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
Pinouts
DG506A (PDIP, CERDIP, SOIC)
TOP VIEW DG507A (PDIP, CERDIP, SOIC)
TOP VIEW DG509A (PDIP, SOIC)
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V+
NC
NC
S16
S15
S14
S13
S12
S11
S10
S9
GND
NC
A3
D
S8
S7
S6
S5
S3
S1
EN
A0
A1
A2
V-
S4
S2
V+
DB
NC
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
NC
NC
DA
S8A
S7A
S6A
S5A
S3A
S1A
EN
A0
A1
A2
V-
S4A
S2A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
EN
V-
S1A
S2A
S3A
DA
S4A
A1
V+
S1B
S2B
S3B
S4B
DB
GND
Data Sheet May 2001
itle
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509
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OCI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil and Design is a trademark of Intersil Americas Inc. |Copyright © Intersil Americas Inc. 2001
OBSOLETEPRODUCT
POSSIBLESUBSTITUTEPRODUCT
HI1-0506(CERDIP),DG406(PLASTIC),
HI1-0507(CERDIP),DG407(PLASTIC),
HI-0509,DG409
2
Truth Tables
DG506A
A3A2A1A0EN ON SWITCH
XXXX0 None
00001 1
00011 2
00101 3
00111 4
01001 5
01011 6
01101 7
01111 8
10001 9
10011 10
10101 11
10111 12
11001 13
11011 14
11101 15
11111 16
Logic “0” = VAL,V
ENL ≤ 0.8V, Logic “1” = VAH,V
ENH ≥ 2.4V.
DG507A
A2A1A0EN ON SWITCHES
XXX0 None
0001 1A,1B
0011 2A,2B
0101 3A,3B
0111 4A,4B
1001 5A,5B
1011 6A,6B
1101 7A,7B
1111 8A,8B
Logic “0” = VAL,V
ENL ≤0.8V, Logic “1” = VAH,V
ENH ≥2.4V.
DG509A
A1A0EN ON SWITCHES
XX0 None
001 1A,1B
011 2A,2B
101 3A,3B
111 4A,4B
A0,A
1,EN
Logic “1” = VAH ≥2.4V, Logic “0” = VAL ≤0.8V.
DG506A, DG507A, DG509A
3
Schematic Diagram
Functional Diagrams
DG506A
4 Line Binary Address Inputs
(0001)andEN=5V
Above example shows channel 2 turned ON.
DG507A
3 Line Binary Address Inputs
(000)andEN=5V
Above example shows channels 1Aand 1Bturned ON.
DG509A
2 Line Binary Address Inputs
(0 0) and EN = 1
Above example shows channels 1Aand 1Bturned ON.
S1
S3
S2
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
A0
D
ADDRESS DECODER
1OF16 ENABLE
1OF4
A1A2A3EN
S16
S1A
S3A
S2A
S4A
S5A
S6A
S7A
S8A
S1B
S2B
S3B
S4B
S5B
S6B
S7B
A0
ADDRESS DECODER
1OF8 ENABLE
1OF2
A1A2EN (ENABLE INPUT)
S8B
DA
DB
S1A
S3A
S2A
S4A
S1B
S2B
S3B
S4B
DA
DB
LOGIC TRIP
POINT REF
LOGIC INTERFACE
AND LEVEL SHIFTER
+
-
DECODER
AX
V+
TYPICAL
SWITCH
SX
DX
V+
GND
LOGIC AX
INPUT OR EN
V-
DG506A, DG507A, DG509A
4
Absolute Maximum Ratings Thermal Information
V+toV-........................................... 44V
V-toGround........................................ 25V
Digital Inputs, VS,V
D(Note1)............. (V--2V)To(V++2V)
Continuous Current, (Any Terminal Except S or D) . . . . . . . . . 30mA
ContinuousCurrent,(SorD)..........................20mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max). . . . . 40mA
Operating Conditions
Temperature Range
“A”Suffix................................-55
oCto125
oC
“B”Suffix.................................-25
oCto85
oC
“C”Suffix ................................. 0
oCto70
oC
Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
28LdCERDIPPackage............ 55 18
16LdPDIPPackage.............. 90 N/A
28LdPDIPPackage.............. 55 N/A
16LdSOICPackage.............. 100 N/A
28LdSOICPackage.............. 70 N/A
Maximum Junction Temperature
CERDIPPackage.................................175
oC
PDIPPackage...................................150
oC
Maximum Storage Temperature
“A”and“B”Suffix......................... -65
oCto150
oC
“C”Suffix ............................... -65
oCto125
oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on SX,D
X,E
N,orA
Xexceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA=25
oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified
PARAMETER TEST CONDITIONS
“A” SUFFIX “B” AND “C” SUFFIX
UNITS
(NOTE4)
MIN (NOTE3)
TYP (NOTE4)
MAX (NOTE4)
MIN (NOTE3)
TYP (NOTE4)
MAX
DYNAMIC CHARACTERISTICS
Switching Time of
Multiplexer, tTRANSITION SeeFigure1 - 0.6 1 - 0.6 - µs
Break-Before-Make
Interval, tOPEN SeeFigure3 - 0.2 - - 0.2 - µs
Enable Turn-ON Time,
tON(EN) SeeFigure2 - 1 1.5 - 1 - µs
Enable Turn-OFF Time,
tOFF(EN) SeeFigure2 - 0.4 1.0 - 0.4 - µs
OFF Isolation, OIRR VEN =0V,R
L=1kΩ,C
L=15pF,
VS=7V
RMS, f = 500kHz (Note 5) -68- -68-dB
Source OFF Capacitance,
CS(OFF) VS=0V,V
EN = 0V, f = 140kHz
DG506A, DG507A - 6 - - 6 - pF
DG509A - 5 - - 5 - pF
Drain OFF Capacitance,
CD(OFF) VD=0V,V
EN = 0V, f = 140kHz
DG506A - 45 - - 45 - pF
DG507A - 23 - - 23 - pF
DG509A - 12 - - 12 - pF
Charge Injection, Q See Figure 4
DG506A, DG507A - 6 - - 6 - pC
DG509A - 4 - - 4 - pC
DIGITAL INPUT CHARACTERISTICS
Address Input Current,
Input Voltage High, IAH VA= 2.4V -10 -0.002 - -10 -0.002 - µA
VA= 15V - 0.006 10 - 0.006 10 µA
Address Input Current
Input Voltage Low, IAL VEN =2.4V V
A= 0V -10 -0.002 - -10 -0.002 - µA
VEN = 0V -10 -0.002 - -10 -0.0002 - µA
DG506A, DG507A, DG509A
5
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG (Note 7) -15 - +15 -15 - +15 V
Drain-Source ON
Resistance, rDS(ON) SequenceEach
Switch ON
VAL =0.8V
VAH =2.4V
IS=-200µA, VD= +10V - 270 400 - 270 450 Ω
IS=-200µA, VD= -10V - 230 400 - 230 450 Ω
rDS(ON) Matching
Between Channels -10V ≤VS≤+10V - 6 - - 6 - %
Source OFF Leakage
Current, IS(OFF) VEN =0V V
S=+10V,V
D= -10V -1 0.002 1 -5 0.002 5 nA
VS=-10V,V
D= +10V -1 -0.005 1 -5 -0.005 5 nA
Drain OFF Leakage
Current, ID(OFF) VEN =0V
DG506A VS=-10V,V
D= +10V -10 0.02 10 -20 0.02 20 nA
VS=+10V,V
D= -10V -10 -0.03 10 -20 -0.03 20 nA
DG507A VS=-10V,V
D= +10V -5 0.007 5 -10 0.007 10 nA
VS=+10V,V
D= -10V -5 -0.015 5 -10 -0.015 10 nA
DG509A VS=-10V,V
D= +10V - 0.005 10 - 0.005 20 nA
VS=+10V,V
D= -10V -10 -0.008 - -20 -0.008 - nA
Drain ON Leakage Current,
ID(ON) (Note 6)
SequenceEach
Switch ON
VAL =0.8V
VAH =2.4V
DG506A VD=V
S(ALL) = +10V -10 0.03 10 -20 0.03 20 nA
VD=V
S(ALL) = -10V -10 -0.06 10 -20 -0.06 20 nA
DG507A VD=V
S(ALL) = +10V -5 0.015 5 -10 0.015 10 nA
VD=V
S(ALL) = -10V -5 -0.03 5 -10 -0.03 10 nA
DG509A VD=V
S(ALL) = +10V - 0.007 10 - 0.007 20 nA
VD=V
S(ALL) = -10V -10 -0.015 - -20 -0.015 - nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current,
I+ VEN =5.0V,V
A=0V
(Enabled) - 1.3 2.4 - 1.3 2.4 mA
Negative Supply Current,
I- -1.5 -0.7 - -1.5 -0.7 - mA
Positive Supply Current,
I+ Standby VEN =0V,V
A=0V
(Standby) - 1.3 2.4 - 1.3 2.4 mA
Negative Supply Current,
I- Standby -1.5 -0.7 - -1.5 -0.7 - mA
Electrical Specifications TA=25
oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
“A” SUFFIX “B” AND “C” SUFFIX
UNITS
(NOTE4)
MIN (NOTE3)
TYP (NOTE4)
MAX (NOTE4)
MIN (NOTE3)
TYP (NOTE4)
MAX
∆rDS ON()
rDS(ON)MAX rDS ON()MIN
–
rDS ON()AVG
-----------------------------------------------------------------------=
DG506A, DG507A, DG509A
6
Electrical Specifications TA= Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, VEN =2.4V,
Unless Otherwise Specified
PARAMETER TEST CONDITIONS
“A” SUFFIX “B” AND “C” SUFFIX
UNITSMIN (NOTE 3)
TYP MAX MIN (NOTE 3)
TYP MAX
DIGITAL INPUT CHARACTERISTICS
Address Input Current, Input
Voltage High, IAH VA=2.4V -30 - - - - - µA
VA= 15V - - 30 - - - µA
Address Input Current Input
Voltage Low, IAL VEN =2.4V V
A=0V -30 - - - - - µA
VEN =0V -30 - - - - - µA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG (Note 7) -15 - +15 - - - V
Drain-Source ON
Resistance, rDS(ON) Sequence Each
Switch ON
VAL =0.8V
VAH =2.4V
IS=-200µA, VD=+10V--500---Ω
IS=-200µA, VD= -10V - - 500 - - - Ω
Source OFF Leakage
Current, IS(OFF) VEN =0V V
S=+10V,V
D=-10V - - 50 - - - nA
VS=-10V,V
D=+10V -50 - - - - - nA
Drain OFF Leakage Current,
ID(OFF) VEN =0V
DG506A VS=-10V,V
D=+10V - - 300 - - - nA
VS=+10V,V
D= -10V -300 - - - - - nA
DG507A VS=-10V,V
D=+10V - - 200 - - - nA
VS=+10V,V
D= -10V -200 - - - - - nA
DG509A VS=-10V,V
D=+10V - - 100 - - - nA
VS=+10V,V
D= -10V -100 - - - - - nA
Drain ON Leakage Current,
ID(ON) (Note 6)
Sequence Each
Switch ON
VAL =0.8V
VAH =2.4V
DG506A VD=V
S(ALL) = +10V - - 300 - - - nA
VD=V
S(ALL) = -10V -300 - - - - - nA
DG507A VD=V
S(ALL) = +10V - - 200 - - - nA
VD=V
S(ALL) = -10V -200 - - - - - nA
DG509A VD=V
S(ALL) = +10V - - 100 - - - nA
VD=V
S(ALL) = -10V -100 - - - - - nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ VEN =5.0V,V
A=0V -3.2 - 4.5 - - - mA
Negative Supply Current, I- -3.2 - 4.5 - - - mA
Positive Standby Supply Current, I+ VEN =0V,V
A=0V -3.2 - 4.5 - - - mA
Negative Standby Supply Current, I- -3.2 - 4.5 - - - mA
NOTES:
3. Typical values are for design aid only, not guaranteed and not subject to production testing.
4. The algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet.
5. Off isolation = 20Log |VS|/|VD|, where VS= input to Off switch, and VD= output due to VS.
6. ID(ON) is leakage from driver into “ON” switch.
7. Parameter not tested. Parameter guaranteed by design or characterization.
DG506A, DG507A, DG509A
7
Test Circuits and Waveforms
FIGURE 1A. DG506A TEST CIRCUIT NOTE: Similar connections for DG509A.
FIGURE 1B. DG507A TEST CIRCUIT
FIGURE 1C. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIME
FIGURE 2A. DG506A TEST CIRCUIT NOTE: Similar connections for DG509A.
FIGURE 2B. DG507A TEST CIRCUIT
EN
A2
S2THRU S15
A1
A0
LOGIC
INPUT
50Ω
+2.4V
SWITCH
OUTPUT
35pF1MΩ
+15V
-15V
-10V
+10V
GND V-
DG506A S1
S16
D
V+
VO
A3
EN
S1A THRU S8A,
A1
A0
LOGIC
INPUT
50Ω
+2.4V
SWITCH
OUTPUT
35pF1MΩ
+15V
-15V
-10V
+10V
GND V-
DG507A S1B
S8B
DB
V+
DA
S2B, AND S7B
VO
A2
(NOTE)
3V
50%
0
VS1
0.8VS1
0
0.8VS8
VS8
SWITCH
OUTPUT
VO
TRANSITION
S1ON
S8ON
LOGIC INPUT tr< 20ns
tf< 20ns
TIME TRANSITION
TIME
EN
A2
S2THRU S16
A1
A0
EN 50Ω
SWITCH
OUTPUT
35pF1kΩ
+15V
-15V
GND V-
DG506A S1
D
V+
VO
-5V
A3
EN
A0
S1A THRU S8A,
A1
A2
EN 50Ω
SWITCH
OUTPUT
35pF1kΩ
+15V
-15V
GND V-
DG507A S1B
DB
V+
VO
-5V
DA,
S2B THRU S8B
(NOTE)
DG506A, DG507A, DG509A
8
FIGURE 2C. MEASUREMENT POINTS
FIGURE 2. ENABLE TIMES
NOTE: Similar connections for DG509A.
FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
.FIGURE 4A. DG506A TEST CIRCUIT NOTE: Similar connections for DG509A.
FIGURE 4B. DG507A TEST CIRCUIT
Test Circuits and Waveforms (Continued)
3V
50%
0V
SWITCH
OUTPUT
VO
tr< 20ns
tf<20ns
0V
VO
tON (EN) tOFF (EN)
EN 50%
0.9VO
0.1VO
EN
A1
A2
A3
LOGIC
INPUT
50Ω
+2.4V
SWITCH
OUTPUT
35pF1kΩ
+15V
-15V
GND V-
DG506A
ALL S AND DA
DB
V+
VO
DG507A
A0
+5V (VS)
(NOTE)
3V
50%
0V
SWITCH
OUTPUT
VO
tr<20ns
tf< 20ns
0V
LOGIC
tOPEN
INPUT
50%
VS
EN
A2
S1
A1
A0
1000pF
+15V
-15V
GND V-
DG506A
D
V+
VO
A3
LOGIC
INPUT
EN
A2S1A,S
1B
A1
A0
1000pF
+15V
-15V
GND V-
DG507A
DAOR DB
V+
VO
LOGIC
INPUT
(NOTE)
DG506A, DG507A, DG509A
9
FIGURE 4C. CHARGE INJECTION WAVEFORMS
FIGURE 4. CHARGE INJECTION
Test Circuits and Waveforms (Continued)
3V
EN
0
VO∆VO
∆VOis the measured voltage error due to charge injection.
The charge transfer error in Coulombs isQ = CLx∆VO.
Typical Performance Curves
FIGURE 5. rDS(ON) vs ANALOG SIGNAL VOLTAGE vs
SUPPLY VOLTAGE FIGURE 6. TYPICAL rDS(ON) VARIATION WITH TEMPERATURE
ANALOG SIGNAL VOLTAGE (V)
550
-10 -5 0 5 10 15
rDS(ON) (Ω)
500
450
400
350
300
250
200
150
100
50
0
-15
V+ = +15V, V- = -15V
V+ = +10V, V- = -10V
V+ = +12V, V- = -12V
V+=+7.5V,V-=-7.5V
TEMPERATURE (oC)
-25 0 45 70 100 125-55 20
rDS(ON) (Ω)
V+ = +15V V- = -15V
VEN =2.4V
IO=-200µA+10V SIGNALS
-10V SIGNALS
400
300
200
100
0
DG506A, DG507A, DG509A
10
Die Characteristics
DIE DIMENSIONS:
3810µm x 2770µm
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
PASSIVATION:
Type: PSG/Nitride
Thickness: PSG: 7kű1.4kÅ
Nitride: 8kű1.2kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104A/cm2
Metallization Mask Layout
DG506A
NC NC V+ D V-
S8
S7
S6
S5
S4
S3
S2
S1
GND NC A3A2A1A0EN
S16
S15
S14
S13
S12
S11
S10
S9
DG506A, DG507A, DG509A
11
Die Characteristics
DIE DIMENSIONS:
3810µm x 2770µm
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
PASSIVATION:
Type: PSG/Nitride
Thickness: PSG: 7kű1.4kÅ
Nitride: 8kű1.2kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104A/cm2
Metallization Mask Layout
DG507A
NC DBV+ DAV-
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
GND NC NC A2A1A0EN
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
DG506A, DG507A, DG509A
12
Die Characteristics
DIE DIMENSIONS:
3100µm x 2083µm
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
PASSIVATION:
Type: PSG/Nitride
Thickness: PSG: 7kű1.4kÅ
Nitride: 8kű1.2kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104A/cm2
Metallization Mask Layout
DG509A
EN A0A1GND
V+
S1B
S2B
S3B
S4B
S4A DADB
V-
S1A
S2A
S3A
DG506A, DG507A, DG509A
13
DG506A, DG507A, DG509A
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. ControllingDimensions:INCH.Incaseofconflictbetween Englishand
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensionsdo not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eBand eCare measured at the lead tips with the leads unconstrained.
eCmust be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
14
DG506A, DG507A, DG509A
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. ControllingDimensions:INCH.Incaseofconflictbetween Englishand
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensionsdo not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eBand eCare measured at the lead tips with the leads unconstrained.
eCmust be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E28.6 (JEDEC MS-001-BF ISSUE D)
28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.030 0.070 0.77 1.77 8
C 0.008 0.015 0.204 0.381 -
D 1.380 1.565 35.1 39.7 5
D1 0.005 - 0.13 - 5
E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC -
eA0.600 BSC 15.24 BSC 6
eB- 0.700 - 17.78 7
L 0.115 0.200 2.93 5.08 4
N28 289
Rev. 0 12/93
15
DG506A, DG507A, DG509A
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamferon the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
hx45
o
C
H
µ
0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0o8o0o8o-
Rev. 0 12/93
16
DG506A, DG507A, DG509A
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbolsaredefinedinthe“MOSeriesSymbolList”inSection2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusionsorgate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
hx45
o
C
H
µ
0.25(0.010) BM M
α
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMINMAXMINMAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93
17
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil isbelieved to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100,RuedelaFusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
DG506A, DG507A, DG509A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2,and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. DimensionQshallbemeasuredfromtheseatingplanetothe
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa CA-B
MD
SS
eA
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.232 - 5.92 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 1.490 - 37.85 5
E 0.500 0.610 12.70 15.49 5
e 0.100 BSC 2.54 BSC -
eA 0.600 BSC 15.24 BSC -
eA/2 0.300 BSC 7.62 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N28 288
Rev. 0 4/94
