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September 1983
Revised February 1999
MM74HC175 Quad D-Type Flip-Flop With Clear
© 1999 Fairchild Semicond uctor Corpor ation DS005319.prf www.fairchildsemi.com
MM74HC175
Quad D-Type Flip-Flop With Clear
General Descript ion
The MM74HC175 high spe ed D-type flip-flop with comple-
mentary outputs utilizes advanced silicon-gate CMOS
technology to achieve the high noise immunity and low
power consumption of standard CMOS integrated circuits,
along with the ability to drive 10 LS-TTL loads.
Information at the D inputs of the MM74HC175 is trans-
ferred to the Q and Q outputs on the positive going edge of
the clock pulse. Both true and complement outputs from
each flip flop ar e externally ava ilable. All four flip- flops are
controlled by a common clock and a common CLEAR.
Clearing is accomplished by a negative pulse at the
CLEAR inpu t. A ll fou r Q o utp uts a re cleared to a l og ical “ 0”
and all four Q outputs to a logical “1.”
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to VCC and ground.
Features
■Typical propagation delay: 15 ns
■Wide operating supply voltage range: 2–6V
■Low input curre nt: 1 µA maximum
■Low quiescent supply current: 80 µA maximum (74HC)
■High output drive current: 4 mA minimum (74HC)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering cod e.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table (Each Flip-Flop)
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant
↑ = Tra nsition from LOW-to-HIGH level
Q0 = The lev el of Q b ef ore the ind ic at ed steady-s t at e input conditions were
established
Order Number Package Number Package Description
MM74HC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs Outputs
Clear Clock D Q Q
LXXLH
H↑HH L
H↑LLH
HLXQ
0Q0
www.fairchildsemi.com 2
MM74HC175
Logic Diagram
3 www.fairchildsemi.com
MM74HC175
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute M aximum Ra tings are those valu es beyond w hich dam-
age to the device may occur.
Note 2: Unless ot herwise spe c if ied all voltage s a re referenced to groun d.
Note 3: Power Dis sipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: F or a pow er sup ply of 5V ±1 0% the worst case output vol tages (VOH, and VOL) occur for H C at 4. 5V. Th us the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V re sp ec t iv ely. (Th e VIH value at 5. 5V is 3.85V.) The worst c as e leakage c ur-
rent (IIN, ICC, and I OZ) oc c ur for CMOS at th e higher vol ta ge and so the 6. 0V values should be use d.
Supply Voltage (VCC)−0.5 to +7.0V
DC Input Voltage (VIN)−1.5 to VCC +1.5V
DC Output Voltage (VOUT)−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)±20 mA
DC Output Current, per pin (IOUT)±25 mA
DC VCC or GND Current, per pin (ICC)±50 mA
Stora ge Temperature Range (TSTG)−65°C to +150°C
Power Di ssipa tion (P D)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260 °C
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage
(VIN,VOUT)0V
CC V
Operating Temperature Range (TA)−40 +85 °C
Input Rise or Fall Times
(tr, tf)V
CC = 2.0V 1000 ns
VCC = 4.5V 500 ns
VCC = 6.0V 400 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level VIN = VIH or VIL
Output Vo ltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level VIN = VIH or VIL
Output Vo ltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maxim um Input VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
ICC Maximum Quiescent VIN = VCC or GND 6.0V 8 80 160 µA
Supply Current IOUT = 0 µA
www.fairchildsemi.com 4
MM74HC175
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Note 5: CPD determines the no load dynamic power consumption, PD=CPD V
CC2f+ICC V
CC, and the no load dynamic current consumption,
IS=CPD VCC f+ICC.
Symbol Parameter Conditions Typ Guaranteed Units
Limit
fMAX Maximum Operating 60 35 MHz
Frequency
tPHL, tPLH Maximum Propagation 15 25 ns
Delay, Clock to Q or Q
tPHL, tPLH Maximum Propagation 13 21 ns
Delay, Reset to Q or Q
tREC Minimu m Remov al 20 ns
Time , Clear to Clock
tSMinimum Setup Time, Data to Clock 20 ns
tHMinimum Hold Time, Data from Clock 0 ns
tWMinimum Pulse Width, Clock or Clear 10 16 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
fMAX Maximum Operating 2.0V 12 6 5 4 MHz
Frequency 4.5V 60 30 24 20 MHz
6.0V 70 35 28 24 MHz
tPHL, tPLH Maximum Propagation 2.0V 80 150 190 225 ns
Delay, Clock to Q or Q 4.5V 15 30 38 45 ns
6.0V 13 26 32 38 ns
tPHL, tPLH Maximum Propagation 2.0V 64 125 158 186 ns
Delay, Reset to Q or Q 4.5V 14 25 32 37 ns
6.0V 12 21 27 32 ns
tREM Minimum Removal Time 2.0V 100 125 150 ns
Clear to Clock 4.5V 20 25 30 ns
6.0V 17 21 25 ns
tSMinimum Setup Time 2.0V 100 125 150 ns
Data to Clock 4.5V 20 25 30 ns
6.0V 17 21 25 ns
tHMinimum Hold Time 2.0V 0 0 0 ns
Data from Clock 4.5V 0 0 0 ns
6.0V 0 0 0 ns
tWMinimum Pulse Width 2.0V 30 80 100 120 ns
Clear or Clock 4.5V 9 16 20 24 ns
6.0V 8 14 17 20 ns
tr, tfMaximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time 4.5V 500 500 500 ns
6.0V 400 400 400 ns
tTLH, tTHL Maximum 2.0V 30 75 95 110 ns
Output Rise and 4.5V 9 15 19 22 ns
Fall Time 6.0V 8 13 16 19 ns
CPD Power Dissipation (per package) 150 pF
Capacitance (Note 5)
CIN Maximum Input 5 10 10 10 pF
Capacitance
5 www.fairchildsemi.com
MM74HC175
Physical Dim ensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
www.fairchildsemi.com 6
MM74HC175
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC175 Quad D-Type Flip-Flop With Clear
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the labe l ing, can be re a-
sonably expected to result in a significant injury to the
user.
2. A criti cal com ponen t in any compo nent o f a l ife supp ort
device or system whose failure to perform can be rea-
sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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