LTC4282
17
Rev. B
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APPLICATIONS INFORMATION
Parallel MOSFETs share current well when their GATE-
to-SOURCE voltages are fully enhanced, however when
the MOSFETs are limiting current the offset mismatch
between gate thresholds will cause the MOSFET with the
lowest threshold to carry more current than the others.
As this MOSFET gets hot it carries even more current
since threshold voltage has a negative temperature coef-
ficient. Eventually all the load current may be carried
by a single MOSFET. For this reason, when a group of
MOSFETs are operated in parallel they only provide SOA
of a singleMOSFET.
The second current limit circuit on the LTC4282 allows a
group of parallel MOSFETs to be divided into two banks.
During current limiting the independent gate control of the
two banks divides the current evenly between them, result-
ing in twice the SOA performance of a Hot Swap controller
with a single current limit circuit. This allows the use of
smaller, less expensive MOSFETs, gives it the capability
to start up a load twice as big, or makes the design easier
with respect to SOA due to increased margins.
The two GATE driver circuits also allow the two banks of
MOSFETs to be started up in a staged manner. There are
two architectures for doing this, the first is called ‘low
stress staged start’ and the second is called ‘high stress
staged start’.
Figure4 shows an example of low stress staged start,
where the power-good signal is used to hold GATE2 off
until GATE1 has powered up the load. The start-up trickle
MOSFET M1 is a compact, inexpensive device with small
SOA and is configured for a low current limit with a GATE
capacitor to limit inrush current. When the load is fully
charged and the start-up MOSFET is fully enhanced, the
power-good signal is asserted and the second bypass
side is enabled. The second side has a high current limit
to deliver the full load current, and uses low RDS(ON), low
SOA switching regulator class MOSFETs M2 and M3. The
TIMER capacitor is selected for a short time within the
SOA of the shunt MOSFETs. This architecture minimizes
the cost of MOSFETs to achieve a given load current and
RDS(ON). However, with the brief TIMER time for current
limit, it has limited ability to ride through a load surge in
current limit, or input voltage steps, and due to the low
startup current cannot start up a resistive load such as a
heating element or incandescent lamp.
Figure7 shows an example of high stress staged start. With
high stress staged start the second bypass side is gated by
the STRESS signal from GPIO2 so that one or more low
RDS(ON), low SOA MOSFETs can be used to achieve the
required RDS(ON). The STRESS condition is defined as the
VGS of both MOSFETs being lower than 8V, or the VDS of
M1 being greater than 200mV. The bypass MOSFET(s) are
turned off whenever SOA stress is encountered, while a sin-
gle high SOA stress MOSFET is used for inrush and to ride
through transients with a long TIMER time. During inrush
the VDS of the MOSFETs is high and the GATE of the stress
MOSFET is not fully enhanced, so the GPIO2 pin is held low
to indicate STRESS, which holds the bypass MOSFET(s)
off. The stress MOSFET starts up the load alone, either
with a GATE capacitor or in current limit. When start-up is
complete and the stress MOSFET is fully enhanced (VDS
low and VGS high), the STRESS condition is removed and
the GPIO2 pin goes high to enable the bypass MOSFETs to
turn on. This architecture uses the stress MOSFET to ride
through current limiting load surges as well as input voltage
steps and can also start up a resistive load. The high SOA
stress MOSFET is more expensive than the trickle MOSFET
in the low stress staged start circuit, but may be cheaper
than two or more intermediate SOA MOSFETs used in the
parallel configuration (Figure1).
Figure9 demonstrates a single MOSFET application. The
SENSE2– pin is grounded to disable the second current
limit circuit and GATE driver so that the part behaves
the same as other single Hot Swap controllers like the
LTC4280. The GATE2 pin may be left open, or tied to the
GATE1 pin to double the GATE pull-down currents for
faster turn-off times in response to faults.
Overvoltage Fault
An overvoltage fault occurs when the OV pin rises above
the OV threshold for longer than 25µs. This shuts off
the GATE pins with 1mA currents to ground and sets the
overvoltage present and overvoltage fault bits (Bit 0) in
STATUS and FAULT_LOG registers 0x1E and 0x04. If the
voltage subsequently falls back below the threshold for
50ms, the GATE pins are allowed to turn on again unless
overvoltage auto-retry has been disabled by clearing the
OV auto-retry bit (Bit 0) in CONTROL register 0x00. If
an external resistive divider is used, the OV threshold is