EPSON SRM2A256LLMX70:85/10 256K-Bit Static RAM @ Low Supply Current @ Access Time 70ns/85ns/100ns @ 32,768 Wordsx8-bit Asynchronous m@ DESCRIPTION The SRM2A256LLMX70/85/10 is a 32,768 wordsx8-bit asynchronous, static, random access memory fabricated using an advanced CMOS technology. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. The asynchronous and static nature of the memory re- quires no external clock or refresh circuit. Input and output ports are TTL compatible and the 3-state output allows easy expansion of memory capacity. m FEATURES m@ PIN CONFIGURATION @ Wide temperature range ................. 25 to 85% (DIP/SOP2) @ Fast access time .........00 ee SRM2A256LLMX70 70Ons SRM2A256LLMX85 85ns 2 SRM2A256LLMX10 100ns 5 @ Low supply current ........00 ee LL Version 2 @ Completely static ..........0000 no clock required x @ Single power supply ...........0.0.000000.. 5V+10% s @ TTL compatible inputs and outputs @ 3-state output @ Battery back-up operation TSOP) @ Package ......... SRM2A256LLCX70/85/10 DIP-28pin (plastic) se da Hato SRM2A256LLMX70/85/10 SOP2-28pin (plastic) Au 2s 20 CS SRM2A256LLTMX70/85/10 TSOP(I)-28pin (plastic) as O25 isAor SRM2A256LLRMX70/85/10 TSOP(I)-28pin-R {plastic) We 127,-.. 16D vOs vin 3 3 SRMZA256LLTMX 5 BOs m@ BLOCK DIAGRAM Arey 2 131083 Ab 04 110101 A5 5 100 Ao A4 6 9 DAt A383 07 8 DA2 AO Al 5 A2 8 (TSOP-R1) ny 8 a | 2 | Memory Cell Array Ags 07 3 DA2 AS 2 512x64x8 A4 6 9 Dat AG a > a5 5 101 Ao AT a as 04 11001 aw O71 Aree 2 3Hios An < sae Yoo i) SRM2A256LLRMX 4 Bod Att We | 27 1601/05 Al2 5 A130 26 170 O06 Al 6 zo | 64 Column Gate ata > 3 >| n q 24 teHvos j a A1iQ 23 200cs OE Cf 22 211A10 cs Be gee m@ PIN DESCRIPTION | AQ to A14 Address Input OE Ws WE Write Enable _ wee VO Butter OE Output Enable we"Lleo= cs Chip Select 1/01 to 08 = Data Input/Output VO1 O02 03 VO4 05 06 07 08 Vop Power Supply(+5V) Vss Power Supply(0V) SEIKO EPSON CORPORATIONEPSON mM ABSOLUTE MAXIMUM RATINGS (Vsg=0V) Parameter Symbol Ratings Unit Supply voltage Vop 0.5 to 7.0 Vv Input voltage Vi 0.5* to 7.0 Vv Input/Output voltage Vio 0.5* to Vpp+0.3 Vv Power dissipation Pp 1.0 W Operating temperature Topr 25 to 85 C Storage temperature Tstg 65 to 150 C Soldering temperature and time Tsol 260C, 10s(Lead only) = * V1, Vo (Min.)= 3V when pulse width is less or equal to 50ns m@ DC RECOMMENDED OPERATING CONDITIONS (Vgg=0V, Ta=-25 to 85C) Parameter Symbol Conditions Min. Typ. Max. Unit Vv 4.5 5.0 5.5 Vv Supply voltage Vex 0 0 0 v Vin 2.2 = Vpp+0.3 Vv Input voltage Vi -0.3% 0 08 V * V_ (Min.)=3V when pulse width is less or equal to 50ns m ELECTRICAL CHARACTERISTICS @ DC Electrical characyeristics (Vpp=5V+10%, Vgg=0V, Ta=-25 to 85*C) p t Symbol Conditi SRM2A256LLMX70 | SRM2A256LL MXes | SRM2A256LLMX10 Unit arameter ympo onanions Min. |Typ.*| Max. | Min. [Typ.*|Max. | Min. |Typ. |Max. Input leakage Vu V=0 to Vpp -1; -| 1 1 }] 14-1] - 1 HA CS=V\H or WE=V Output leakage I werk IL - - - - - - p g LO or OE=Vi4 Vyo=0 to Vop 1 1 1 1 1 1 HA High level output voltage Vou loy=-1.0mMA 24) -| - |24] -] - |24] - |] - V Low level output voltage VoL lo-=2.1MA - -104)] - -|04/-)]- 104 V | CS=V | 0.5}3.0} |05/3.0] [05] 3.0 A Standby supply current pes HH m lpps1 CS2Vpp-0.2V | 1]100} - | 1 |100} - | 1 |100} pA VieViLt, Vin lopa lyo<0mA, teyo=Min. - | 45| 70 | - | 45] 70} - | 45] 70} mA Average operating current Vcv, Vv MAb tt | -|10}-]|-]10}-]-]} 10} mA DDA1 lyo=OmA, tcyc=1 Us . VieVit, Vin A Operating supply current Ippo lyo=OmA -| -| 10} -] -}]10}-}- |] 10) mM *: Typical values are measured at Ta=25C and Vpp=5.0V @ Terminal Capacitance (f=1MHz, Ta=25C) Parameter Conditions in. . Max. Unit Address Vapp=0V 8 F In Cc, V\=0V 9 F VO Vv V 10 F @ AC Electrical Characteristics O Read Cycle (Vpp=5V+10%, Vgg=0V, Ta=25 to 85C) SRM2A256LLMX70 |SRM2A256LLMXe5|SRM2A256LLMX10 Parameter Symbol Conditions Min | Max. Min. | Max. Min. | Max. Unit Read cycle time tac 70 = 85 = 100 = ns Address access time tacc *Y - 70 - 85 = 100 ns CS access time tacs - 70 - 85 - 100 ns OE access time toe - 40 - 45 - 50 ns CS output set time toiz 10 - 10 - 10 - ns CS output floating tcuz *2 = 30 = 30 = 35 ns OE output set time toiz ) = ) = ) = ns OE output floating tonz = 30 = 30 - 35 ns Output hold time tou *4 10 - 10 - 10 - nsSRM2A256LLMX70:85/10 O Write Cycle (Vpp=5V+10%, Vgs=0V, Ta=-25 to 85C) P t Symbol Conditi SRM2A256LLMX70 |SRM2A256LLMXa5|SRM2A256LLMX10 . arameter ympo onaltions Min. | Max. Min. | Max. Min. | Max. Unit Write cycle time two 70 - 85 - 100 - ns Chip select time tow 60 - 70 - 80 - ns Address valid to end of write taw 60 - 70 - 80 - ns Address setup time tas 0 - 0 - 0 - ns Write pulse width twp *1 55 - 65 - 75 - ns Address hold time twr 0 - 0 - 0 - ns Input data set time tow 30 - 35 - 40 - ns Input data hold time tou 0 - 0 - 0 - ns Write to Output floating twuz 2 - 30 - 30 - 35 ns Output Active from end to wirte | tow 5 - 5 - 5 - ns *1 Test Conditions *2 Test Conditions 1. Input pulse level : 0.6V to 2.4V 1. Input pulse level : 0.6V to 2.4V 2. tr=tf=5ns 2. tr=tt=5ns 3. Input and output timing reference levels : 1.5V 3. Input timing reference levels : 1.5V 4. Output load : CL=100pF 4. Output timing reference levels : 200mV(the level displaced from stable output voltage level) 5. Output load : CL=5pF (Includes Jig Capacitance) +5V +5V 1.8kQ 1.8kQ vo vo T CS e900 T CL = g900 CL=100pF (Includes Jig Capacitance) CL=5pF (Includes Jig Capacitance) @ Timing chart O Read Cycle*! O Write Cycle(1) (CS Control)*2 ADDRESS ADDRESS as cs OE WE Dour Dout Din Note : O Write Cycle(2) (WE Control)#*3: *4 1 During read cycle time, WE is to be "H" level. *2 During write cycle time that is controlled by Cs, Output Buffer is ADDRESS in high impedance state, whether OE level is "H" or "L" _ %3 During write cycle time that is controlled by WE, Output Buffer is cs in high impedance state if OE is "L" level. __ *%4 When I/O terminals are output mode, be careful that do not give WE the opposite signals to the I/O terminals. Dout DinEPSON @ DARA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (Vsg=0V, Ta=-25 to 85C) Parameter Symbol Conditions SAM2A256LLMX70 SAM2A256LLM X85 SRM2A2S6LLMXt0 Unit Min. | Typ." Max. | Min. | Typ.*|Max. | Min. | Typ.*|Max. Data retention supply voltage Vppr 2.0} |55 420} |55/20|] - |5.5 Vv . Vppr=3V Data retention current lbpr CS>Vpp-0.2V 25 to 85C] | 0.5) 50 | | 0.5] 50} |0.5] 50 HA Chip select data hold time tcpr Oo} - - 0 -|- |0 -|- ns Operation recovery time tr 5]/-}]-7);5 7] -]-] 5) -] - ms % : Typical values are measured at 25C Data retention timing Data hold mode 4.5V VoprR22.0V tepR iR CS>Vopr-0.2V 4.5V Vin *When retaining data in standby mode, supply voltage can be lowered within a certain range, But read or write cycle cannot be performed while the supply voltage is low. @ FUNCTIONS @ Truth Table cs OE WE DATA VO Mode lbp H 4 Xx Hi-Z Standby Ipps. Ipps1 L x L Din Write Ippa. Ippat L L H Dout Read Ippa. Ipbat L H H Hi-Z Output disable Ippa. Ippat X :"H" or "L @ Read Mode The data appear when the address is setted while holding CS="L", OE="L" and WE ="H". When OE="H", DATA I/O terminals are in high impedance state, that makes circuit design and bus control easy. @ Write Mode There are the following 3 ways of writing data into memory. (1) Hold CS="L" and WE="L", set address. (2) Hold CS="L" then set address and give "L" pulse to WE. (3) After setting addresses, give "L" pulse to both CS and WE. In above any case data on the DATA I/O terminals are put into the SRM2A256LLMX7o/85/10 when both CS and WE are in"L". Since DATA I/O terminals are high impedance when CS or OE="H", bus contention between data driver and memory outputs can be avoided. When I/O terminals are output mode, be careful that do not give the opposite signals to the I/O terminals. @ Standby Mode When GS is "L" the SRM2A256LLMX70/88/10 become in the standby mode. In this mode, data I/O terminals are Hi-Z and all inputs of addresses, WE and data can be any "H" or "L". When CS is over than Vpp-0.2V, the SRM2A256LLMX70/85/10 Is in the data retention battery back-up mode, in this case, there is a small current in the SRM2A256LLMX70/85/10 which flow through the high resistances of the memory cells.SRM2A256LLMX70:85/10 lm PACKAGE DIMENSIONS Plastic DIP-28pin (600mil)* (ayes 36.7800, (1.445388) oo fi ) 38 8 leelieeelieelieeelieeeeieeieienieliel 71 Ad (0.89) Gab S| #3 if <2 It Jos! of \ s sft ] pil cet or 2.54 0.46201 ot 15.24 = (0.1} (0.018) 45 (0.6) Unit : mm (inch) Plastic SOP2-28pin (450mil) oo, 17.884, (0.701 0.008" MOOI 0000000 8] 055 97 | B97 ) Bare 7 g} g! al 0% TUTTO TOT . 1 14 7 o88| 3 g| sg] Tomo | |r eesti 127 O45 Bi (0.03028) (0.05) (0.016%) YS ge] 1.7 (0.087) Unit : mm (inch) ; . Plastic TSOP (l)-28pin 2 71 3 INDEX E | 3 Bi S Eg =z Es FE 10 a3] ag 0.1590. es|-g 0.0069" a | | 0.5401 0.55 0.2401 (0.02338) oS | 0.008 -338% (0081) Unit : mm (inch) * : The same characteristics as SRM2A256LLMX70/85/10.EPSON Plastic TSOP (1)-28pin-R1* ~ a INDEX 2 (0.31520007) 4 Bo 8 27 max (0.05%nax) 1 0. 101 0.5 on 388 os 0.55 0.2801 r (0.022} (0.008733) 08 Unit : mm (inch) * The same characteristics as SRM2A256LLMX70/85/10. @ CARACTERISTICS CURVES Normalized Ippa-Ta Normalized IppaFrequency Normalized IbpaVop 1.0 Ta=25C READ, WRITE tr 0.9 Voo=5.0V READ, WRITE 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.6 0.0 -40 -20 0 20 40 60 80 0 2 4 6 8 10 12 14 16 18 20 5 Frequency (MHz) Ta (C) Titre, Wwe Normalized Ipps1-Ta Normalized Ipps1Vpp Normalized loH-VoH Ta=25C, Voo=5.0V Ta=25C 100 10 1.0 0.1 3.0 4.0 5.0 6.0 00.1 40 -20 0 20 40 60 80 Von (V) VoH (V) Ta (C)SRM2A256LLMX70:85/10 tacc t Normalized tacs; Ta Normalized thos Vop Normalized lo.VoL tacse C 1.3 1.25 Ta=25C Vpp=5.0V 1.2 1.15 1.1 1.05 1.0 0740-200 20 40 60 80 0.95 09 0.85 0.8 Ta (C) Vop (V) VoL(V) Normalized {hoe CL a=25C Vop=5.0V 100 200 300 400 CL (pF)