FN7282 Rev.2.01 Page 1 of 11
Feb 18, 2020
FN7282
Rev.2.01
Feb 18, 2020
EL7202, EL7212, EL7222
High Speed, Dual Channel Power MOSFET Drivers
DATASHEET
The EL7202, EL7212, EL7222 ICs are matched dual-drivers
that improve the operation of the industry standard DS0026
clock drivers. The Elantec versions are very high speed
drivers capable of delivering peak currents of 2.0 amps into
highly capacitive loads. The high speed performance is
achieved by means of a proprietary “Turbo-Driver” circuit
that speeds up input stages by tapping the wider voltage
swing at the output. Improved speed and drive capability are
enhanced by matched rise and fall delay times. These
matched delays maintain the integrity of input-to-output
pulse-widths to reduce timing errors and clock skew
problems. This improved performance is accompanied by a
10 fold reduction in supply currents over bipolar drivers, yet
without the delay time problems commonly associated with
CMOS devices. Dynamic switching losses are minimized
with non-overlapped drive techniques.
Pinouts
Features
Industry standard driver replacement
Improved response times
Matched rise and fall times
Reduced clock skew
Low output impedance
Low input capacitance
High noise immunity
Improved clocking rate
Low supply current
Wide operating voltage range
Pb-Free available (RoHS compliant)
Applications
Clock/line drivers
CCD Drivers
Ultra-sound transducer drivers
Power MOSFET drivers
Switch mode power supplies
Class D switching amplifiers
Ultrasonic and RF generators
Pulsed circuits
EL7212
(8-PIN PDIP, SO)
TOP VIEW
EL7222
(8-PIN PDIP, SO)
TOP VIEW
INVERTING
DRIVERS
COMPLEMENTARY
DRIVERS
EL7202
(8-PIN PDIP, SO)
TOP VIEW
NON-INVERTING
DRIVERS
Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047
EL7202, EL7212, EL7222
FN7282 Rev.2.01 Page 2 of 11
Feb 18, 2020
Ordering Information
Part Number PART MARKING TAPE & REEL PACKAGE PKG. DWG. #
EL7202CN (No longer available,
recommended replacement:
EL7202CSZ)
EL7202CN - 8 Ld PDIP E8.3
EL7202CSZ
(See Note)
7202CSZ - 8 Ld SOIC
(Pb-free)
M8.15E
EL7202CSZ-T7
(See Note)
7202CSZ 7” 8 Ld SOIC
(Pb-free)
M8.15E
EL7202CSZ-T13 (See Note) 7202CSZ 13” 8 Ld SOIC
(Pb-free)
M8.15E
EL7212CNZ EL7212CN Z - 8 Ld PDIP*
(Pb-free)
E8.3
EL7212CSZ
(See Note)
7212CSZ - 8 Ld SOIC
(Pb-free)
M8.15E
EL7212CSZ-T7
(See Note)
7212CSZ 7” 8 Ld SOIC
(Pb-free)
M8.15E
EL7212CSZ-T13
(See Note)
7212CSZ 13” 8 Ld SOIC
(Pb-free)
M8.15E
EL7222CSZ
(See Note)
7222CSZ - 8 Ld SOIC
(Pb-free)
M8.15E
EL7222CSZ-T7
(See Note)
7222CSZ 7” 8 Ld SOIC
(Pb-free)
M8.15E
EL7222CSZ-T13
(See Note)
7222CSZ 13” 8 Ld SOIC
(Pb-free)
M8.15E
NOTE: Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
EL7202, EL7212, EL7222
FN7282 Rev.2.01 Page 3 of 11
Feb 18, 2020
Absolute Maximum Ratings (TA = 25°C)
Supply (V+ to Gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V
Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+
Combined Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . .4A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specifi ed temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications TA = 25°C, V = 15V unless otherwise specified
parameter Description Test Conditions Min Typ Max Units
INPUT
VIH Logic “1” Input Voltage 2.4 V
IIH Logic “1” Input Current @V+ 0.1 10 µA
VIL Logic “0” Input Voltage 0.8 V
IIL Logic “0” Input Current @0V 0.1 10 µA
VHVS Input Hysteresis 0.3 V
OUTPUT
ROH Pull-Up Resistance IOUT = -100mA 3 6
ROL Pull-Down Resistance IOUT = +100mA 4 6
IPK Peak Output Current Source
Sink
2
2
A
IDC Continuous Output Current Source/Sink 100 mA
POWER SUPPLY
ISPower Supply Current Inputs High/EL7202
Inputs High/EL7212
Inputs High/EL7222
4.5
1
2.5
7.5
2.5
5.0
mA
VSOperating Voltage 4.5 15 V
AC Electrical Specifications TA = 25°C, V = 15V unless otherwise specified
parameter Description Test Conditions Min Typ Max Units
SWITCHING CHARACTERISTICS
tRRise Time CL = 500pF
CL = 1000pF
7.5
10 20
ns
tFFall Time CL = 500pF
CL = 1000pF
10
13 20
ns
tD1 Turn-On Delay Time See Timing Table 18 25 ns
tD2 Turn-Off Delay Time See Timing Table 20 25 ns
EL7202, EL7212, EL7222
FN7282 Rev.2.01 Page 4 of 11
Feb 18, 2020
Timing Table
Standard Test Configuration
Simplified Schematic
EL7202, EL7212, EL7222
FN7282 Rev.2.01 Page 5 of 11
Feb 18, 2020
Typical Performance Curves
MAX POWER/DERATING CURVES SWITCH THRESHOLD vs SUPPLY VOLTAGE
PEAK DRIVE vs SUPPLY VOLTAGEINPUT CURRENT vs VOLTAGE
QUIESCENT SUPPLY CURRENT “ON” RESISTANCE vs
SUPPLY VOLTAGE
EL7202, EL7212, EL7222
FN7282 Rev.2.01 Page 6 of 11
Feb 18, 2020
Typical Performance Curves (Continued)
AVERAGE SUPPLY CURRENT vs
VOLTAGE AND FREQUENCY
AVERAGE SUPPLY CURRENT
vs CAPACITIVE LOAD
RISE/FALL TIME vs LOAD RISE/FALL TIME vs SUPPLY VOLTAGE
PROPAGATION DELAY vs SUPPLY VOLTAGE RISE/FALL TIME vs TEMPERATURE
DELAY vs TEMPERATURE
EL7202, EL7212, EL7222
FN7282 Rev.2.01 Page 7 of 11
Feb 18, 2020
**** EL7212 model ****
* input
* | gnd
* | | Vsupply
* | | | Vout
.subckt M7212 2 3 6 7
V1 12 3 1.6
R1 13 15 1k
R2 14 15 5k
R5 11 12 100
C1 15 3 43.3 pF
D1 14 13 dmod
X1 13 11 2 3 comp1
X2 16 12 15 3 comp1
sp 6 7 16 3 spmod
sn 7 3 16 3 snmod
g1 11 0 13 0 938µ
.model dmod d
.model spmod vswitch ron3 roff2meg von1 voff1.5
.model snmod vswitch ron4 roff2meg von3 voff2
.ends M7212
.subckt comp1 out inp inm vss
e1 out vss table { (v(inp) v(inm))* 5000} (0,0) (3.2,3.2)
Rout out vss 10meg
Rinp inp vss 10meg
Rinm inm vss 10meg
.ends comp1
EL7212 Macro Model
EL7202, EL7212, EL7222
FN7282 Rev.2.01 Page 8 of 11
Feb 18, 2020
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make
sure you have the latest revision.
DATE REVISION CHANGE
Feb 18, 2020 2.01 Updated ordering information table.
Added Revision History
Replaced POD MDP0031 with E8.3 POD.
Replaced POD MDP0027 with M8.15E POD.
Updated disclaimer
EL7202, EL7212, EL7222
FN7282 Rev.2.01 Page 9 of 11
Feb 18, 2020
Package Outline Drawings
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
eA
-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE (PDIP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
EL7202, EL7212, EL7222
FN7282 Rev.2.01 Page 10 of 11
Feb 18, 2020
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27 0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A" 0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27) (0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B
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