General Description
The MAX3881 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers sin-
gle-ended PECL parallel data outputs and a differential
PECL parallel clock output for interfacing with digital
circuitry.
The MAX3881 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3881’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor.
The MAX3881 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP package.
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
Features
♦Single +3.3V Supply
♦530mW Operating Power
♦Fully Integrated Clock Recovery and Data
Retiming
♦Exceeds ANSI, ITU, and Bellcore Specifications
♦Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
♦2.488Gbps Serial to 155Mbps Parallel Conversion
♦Differential PECL Clock Output
♦Single-Ended PECL Data Outputs
♦Tolerates >2000 Consecutive Identical Digits
♦Loss-of-Lock Indicator
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
________________________________________________________________ Maxim Integrated Products 1
19-1996; Rev 1; 12/01
PART
MAX3881ECB -40°C to +85°C
TEMP. RANGE PIN-PACKAGE
64 TQFP-EP*
Ordering Information
*Exposed pad
EVALUATION KIT
AVAILABLE
Pin Configuration
VCC
PD13
VCC
GND
VCC
PD14
GND
VCC
PD11
VCC
PD12
VCC
PD15
GND
LOL
GND
SLBI+
VCC
SDI-
SDI+
VCC
PHADJ-
GND
GND
SIS
VCC
SLBI-
PHADJ+
VCC
FIL-
FIL+
GND
PCLK+
PCLK-
VCC
PD0
VCC
PD1
VCC
GND
VCC
PD2
VCC
PD3
VCC
PD4
VCC
GND
PD10
TOP VIEW
VCC
PD9
VCC
PD8
VCC
GND
VCC
PD7
VCC
PD6
VCC
PD5
VCC
GND
VCC
TQFP-EP*
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
5253 49
5051
33
34
35
36
37
48
64
2322212019 2726252418 2928 32313017
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
MAX3881
*EXPOSED PAD IS CONNECTED TO GND.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Typical Application Circuit appears at end of data sheet.
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, PECL loads = 50Ωto (VCC - 2V), TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC = +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Positive Supply Voltage (VCC)...............................-0.5V to +7.0V
Input Voltage Level (SDI+, SDI-,
SLBI+, SLBI-) ...............................(VCC - 0.5V) to (VCC + 0.5V)
Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA
Voltage at LOL, SIS, PHADJ+, PHADJ-,
FIL+, FIL- .................................................-0.5V to (VCC + 0.5V)
PECL Output Current ..........................................................50mA
Continuous Power Dissipation (TA= +85°C)
64-Pin TQFP (derate 33.3mW/°C above +85°C)............1.44W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Figure 1
Excluding PECL outputs
Figure 2
TA= 0°C to +85°C
CONDITIONS
mVp-p50 800VID
Differential Input Voltage
mA160 240ICC
Supply Current
VVCC - 0.4 VCC + 0.2VIS
Single-Ended Input Voltage
Ω50RIN
Input Termination to VCC
VCC - VCC -
1.025 0.88
UNITSMIN TYP MAXSYMBOLPARAMETER
V0.8VIL
Input Low Voltage
V2.0VIH
Input High Voltage
IOH ≤40µA V2.4 VCC
VOH
Output High Voltage
µA-10 +10Input Current
IOL ≤1mA V0.4VOL
Output Low Voltage
TA= -40°C to 0°C
V
VCC - VCC -
1.085 0.88
VOH
PECL Output High Voltage
TA= 0°C to +85°C VCC - VCC -
1.81 1.62
TA= -40°C to 0°C
V
VCC - VCC -
1.83 1.555
VOL
PECL Output Low Voltage
SERIAL DATA INPUTS (SDI±, SLBI±)
PECL OUTPUTS (PD_, PCLK±)
TTL INPUTS AND OUTPUTS (SIS, LOL)
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, PECL loads = 50Ωto (VCC - 2V), TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC = +3.3V, TA= +25°C.) (Note 1)
Note 1: AC characteristics are guaranteed by design and characterization.
Note 2: At jitter frequencies <70kHz, the jitter tolerance of the MAX3881 outperforms the ITU/Bellcore specifications.
Figure 2
100kHz to 2.5GHz
f = 10MHz
f = 70kHz (Note 2)
f = 100kHz
f = 1MHz
2.5GHz to 4.0GHz
CONDITIONS
dB
-11
Input Return Loss (SDI±, SLBI±)
ps200 450 900tCLK-Q
Parallel Clock-to-Data Output
Delay
Mbps155.52
Gbps2.488SDISerial Data Rate
Parallel Output Data Rate
-18
Bits>2,000
Tolerated Consecutive Identical
Digits
UIp-p
0.28 0.46
Jitter Tolerance
2.31 3.3
1.74 2.41
0.38 0.57
UNITSMIN TYP MAXSYMBOLPARAMETER
SDI+
SDI-
VID
(SDI+) - (SDI-) 50mVp-p MIN
800mVp-p MAX
25mV MIN
400mV MAX
Figure 1. Input Amplitude
PCLK
PD0–PD15
tCLK-Q
Figure 2. Timing Parameters
20% to 80%
Output Edge Speed 800
tR, tFps
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
4 _______________________________________________________________________________________
1
0.1
10 100 1000
JITTER TOLERANCE vs. INPUT VOLTAGE
0.3
0.2
MAX3881 toc04
INPUT VOLTAGE (mVp-p)
JITTER TOLERNCE (UIp-p)
0.5
0.4
0.7
0.8
0.6
0.9
0
SONET SPEC
JITTER FREQUENCY = 5MHz
JITTER FREQUENCY = 1MHz
10-10
10-8
10-9
10-6
10-7
10-4
10-5
10-3
8.0 8.5 9.0 9.5 10
BIT ERROR RATIO vs. INPUT VOLTAGE
MAX3881-05
INPUT VOLTAGE (mVp-p)
BIT ERROR RATIO
200
300
400
600
500
700
-50 0-25 25 50 75 100
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
MAX3881-06
TEMPERATURE (°C)
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
1.64ns/div
DATA
CLOCK
RECOVERED DATA AND CLOCK
MAX3881-01
223 - 1 PATTERN
140
150
160
170
180
190
200
-50 -25 0 25 50 75 100
SUPPLY CURRENT vs. TEMPERATURE
MAX3881-02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VCC = +3.6V
VCC = +3.0V
10.0
0.1
1,000 10,000
1.0
JITTER FREQUENCY (kHz)
INPUT JITTER (UIp-p)
10010
JITTER TOLERANCE
MAX3881 toc03
CF = 0.1µF
CF = 1.0µF
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________ 5
NAME FUNCTION
1, 15, 16, 17,
25, 33, 41,
49, 57, 62,
64
GND Ground
PIN
Pin Description
2FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
3FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
4, 7, 10, 13,
20, 22, 24,
26, 28, 30,
32, 34, 36,
38, 40, 42,
44, 46, 48,
50, 52, 54,
56, 58, 60
VCC +3.3V Supply Voltage
5PHADJ+ Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
6PHADJ- Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
8SDI+ Positive Serial Data Input. 2.488Gbps data stream.
9SDI- Negative Serial Data Input. 2.488Gbps data stream.
11 SLBI+ Positive System Loopback Input. 2.488Gbps data stream.
12 SLBI- Negative System Loopback Input. 2.488Gbps data stream.
14 SIS Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
18 PCLK+ Positive Parallel Clock PECL Output
19 PCLK- Negative Parallel Clock PECL Output
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
PD0 to PD15 Parallel Data Single-Ended PECL Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 2).
63 LOL Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩpullup resistor).
The LOL monitor is valid only when a data stream is present on the inputs to the MAX3881.
EP Exposed Pad Ground. This must be soldered to a circuit board for proper electrical and thermal performance
(see Package Information).
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
6 _______________________________________________________________________________________
Detailed Description
The MAX3881 deserializer with clock recovery converts
2.488Gbps serial data to 16-bit-wide, 155Mbps parallel
data. The device combines a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
16-bit demultiplexer, clock divider, and PECL output
buffer (Figure 3). The PLL consists of a phase/frequen-
cy detector (PFD), a loop filter, and a voltage-controlled
oscillator (VCO). The MAX3881 is designed to deliver
the best combination of jitter performance and power
dissipation by using a differential signal architecture
and low-noise design techniques. The PLL recovers the
serial clock from the serial input data stream. The
demultiplexer generates a 16-bit-wide 155Mbps paral-
lel data output.
Input Amplifier
The input amplifiers on both the main data and system
loopback accept a differential input amplitude from
50mVp-p to 800mVp-p. The bit error ratio (BER) is bet-
ter than 1 x 10-10 for input signals as small as 9.5mVp-p,
Figure 3. MAX3881 Functional Diagram
MAX3881
SDI+
AMP
PECL
LOL
50Ω
50Ω
MUX PHASE &
FREQUENCY
DETECTOR
SDI-
SLBI+
AMP
SLBI-
SIS
VCC
VCC
LOOP
FILTER VCO
16-BIT
DEMULTIPLEXER
DQ
CK
PHADJ+ PHADJ- FIL+ FIL-
CLOCK
DIVIDER
PCLK+
PCLK-
PD15
PECL
PD1
PECL
PD0
PECL
TTL
0
I
0
I
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________ 7
although the jitter tolerance performance will be
degraded. For interfacing with PECL signal levels, see
Applications Information.
Phase Detector
The phase detector in the MAX3881 produces a volt-
age proportional to the phase difference between the
incoming data and the internal clock. Because of its
feedback nature, the PLL drives the error voltage to
zero, aligning the recovered clock to the center of the
incoming data eye for retiming. The external phase
adjust pins (PHADJ+, PHADJ-) allow the user to vary
the internal phase alignment.
Frequency Detector
The digital frequency detector (FD) aids frequency
acquisition during start-up conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the in-phase and quadra-
ture VCO outputs on both edges of the data input sig-
nal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequen-
cy detector.
Loop Filter and VCO
The phase detector and frequency detector outputs are
summed into the loop filter. A 1.0µF capacitor, CF, is
required to set the PLL damping ratio.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low phase noise
and is trimmed to the correct frequency.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is included in the
MAX3881 frequency detector. A loss-of-lock condition
is signaled with a TTL low. When the PLL is frequency-
locked, LOL switches to TTL high in approximately
800ns.
Note that the LOL monitor is only valid when a data
stream is present on the inputs to the MAX3881. As a
result, LOL does not detect a loss-of-power condition
resulting from a loss of the incoming signal.
Positive Emitter-Coupled
Logic (PECL) Outputs
The MAX3881 features PECL outputs for the parallel
clock and data outputs. For proper operation, PECL
outputs should be terminated with 50Ωto (VCC - 2V). In
many cases, it is not feasible to use the 50Ωto (VCC -
2V) termination, so it may be preferable to terminate to
the Thèvenin equivalent. See application note HFAN-1,
Interfacing Between CML, PECL, and LVDS for more
details regarding the Thèvenin-equivalent PECL termi-
nation.
Design Procedure
Jitter Tolerance and Input
Sensitivity Trade-Offs
When the received data amplitude is higher than
50mVp-p, the MAX3881 provides a typical jitter toler-
ance of 0.46UIp-p at jitter frequencies greater than
10MHz. The SDH/SONET jitter tolerance specification is
0.15UIp-p, leaving a jitter allowance of 0.31UIp-p for
receiver preamplifier and postamplifier design.
The BER is better than 1 x 10-10 for input signals
greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will
be degraded, but will still be above the SDH/SONET
requirement. Trade-offs can be made between jitter tol-
erance and input voltage according to the specific
application. See the Typical Operating Characteristics
for Jitter Tolerance and BER vs. Input Voltage graphs.
Applications Information
Consecutive Identical Digits (CIDs)
The MAX3881 has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER of 1 x 10-10. The CID tolerance is
tested using a 213 - 1 pseudorandom bit stream
(PRBS), substituting a long run of zeros to simulate the
worst case. A CID tolerance of greater than 2,000 bits
is typical.
Phase Adjust
The internal clock is aligned to the center of the data
eye. For specific applications, this sampling position
can be shifted using the PHADJ inputs to optimize BER
performance. The PHADJ inputs operate with differen-
tial input voltages up to ±1.5V. A simple resistor-divider
with a bypass capacitor is sufficient to set these levels
(Figure 4). When the PHADJ inputs are not used, they
should be tied directly to VCC.
System Loopback
The MAX3881 is designed to allow system loopback
testing. The user can connect a serializer output
(MAX3891) in a transceiver directly to the SLBI+ and
SLBI- inputs of the MAX3881 for system diagnostics. To
select the SLBI± inputs, apply a TTL logic high to the
SIS pin.
Interfacing with PECL Input Levels
When interfacing with differential PECL input levels, it is
important to attenuate the signal while still maintaining
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
8 _______________________________________________________________________________________
50Ωtermination (Figure 5). AC-coupling is also
required to maintain the input common-mode level.
Exposed-Pad Package
The exposed-pad (EP), 64-pin TQFP incorporates fea-
tures that provide a very low thermal-resistance path for
heat removal from the IC. The pad is electrical ground
on the MAX3881 and must be soldered to the circuit
board for proper thermal and electrical performance.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3881 high-speed inputs and outputs.
Power-supply decoupling should be placed as close to
VCC pins as possible. To reduce feedthrough, take
care to isolate the input signals from the output signals.
Chip Information
TRANSISTOR COUNT: 2231
PROCESS: BiPolar
MAX3881
PHADJ+ (PIN 5)
PHADJ- (PIN 6)
3.3V
Figure 4. Phase-Adjust Resistor-Divider
MAX3881
50Ω
50Ω
VCC
100Ω
PECL
LEVELS
SDI+
25Ω
25Ω
0.1µF
0.1µF
SDI-
Figure 5. Interfacing with PECL Input Levels
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________ 9
MAX3866
MAX3881
PRE/POSTAMPLIFIER
OVERHEAD
TERMINATION
EXTERNAL TERMINATION REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
VCC
PHADJ- VCC
LOL
GNDFIL-
FIL+
SIS
TTL TTL
SDI+
OUT+
VCC
IN+
FIL
OUT-
LOP
TTL
SDI-
SLBI-
SLBI+
SYSTEM
LOOPBACK
PHADJ+
0.01µF
+3.3V
+3.3V
CF
1.0µF
124Ω
PCLK-
+3.3V
84.5Ω
124Ω
PCLK+
+3.3V
84.5Ω
124Ω
PD0
+3.3V
84.5Ω
124Ω
PD15
+3.3V
84.5Ω
Typical Application Circuit
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
10 ______________________________________________________________________________________
Package Information
64L, TQFP.EPS
Package Information (continued)
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
MAX3881
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
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