FAN6961 Boundary Mode PFC Controller Features Description The FAN6961 is an 8-pin, boundary-mode, PFC controller IC intended for controlling PFC preregulators. The FAN6961 provides a controlled on-time to regulate the output DC voltage and achieve natural power factor correction. The maximum on-time of the external switch is programmable to ensure safe operation during AC brownouts. An innovative multivector error amplifier is built in to provide rapid transient response and precise output voltage clamping. A builtin circuit disables the controller if the output feedback loop is opened. The startup current is lower than 20A and the operating current has been reduced to under 6mA. The supply voltage can be up to 25V, maximizing application flexibility. Boundary Mode PFC Controller Low Input Current THD Controlled On-Time PWM Zero-Current Detection Cycle-by-Cycle Current Limiting Leading-Edge Blanking instead of RC Filtering Low Startup Current: 10A Typical Low Operating Current: 4.5mA Typical Feedback Open-Loop Protection Programmable Maximum On-Time (MOT) Output Over-Voltage Clamping Protection Clamped Gate Output Voltage 16.5V Applications Electric Lamp Ballasts AC-DC Switching Mode Power Converter Open Frame Power Supplies and Power Adapters Flyback Power Converters with ZCS / ZVS Ordering Information Part Number Operating Temperature Range Package Eco Status Packing Method FAN6961SZ -40C to +125C 8-Pin, Small Outline Package (SOP) RoHS Tape & Reel FAN6961DZ -40C to +125C 8-Pin, Dual In-line Package (DIP) RoHS Tube FAN6961SY -40C to +125C 8-Pin, Small Outline Package (SOP) Green Tape & Reel For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 www.fairchildsemi.com FAN6961 --Boundary Mode PFC Controller June 2009 Figure 1. Typical Application Block Diagram FAN6961 -- Boundary Mode PFC Controller Application Diagram Figure 2. Function Block Diagram (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 www.fairchildsemi.com 2 F- Fairchild Logo Z- Plant Code X- Year Code Y- Week Code TT: Die Run Code T: Package Type (S=SOP, D=DIP) P: Z: Pb Free Y: Green Compound M: Manufacture Flow Code FAN6961 TPM Figure 3. Marking Information Pin Configuration Figure 4. VCC GATE GND ZCD 8 7 6 5 1 2 3 4 INV COMP MOT CS FAN6961 -- Boundary Mode PFC Controller Marking Information DIP and SOP Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 INV 2 COMP 3 MOT 4 CS 5 ZCD Zero Current Detection. This pin is connected to an auxiliary winding via a resistor to detect the zero crossing of the switch current. When the zero crossing is detected, a new switching cycle is started. If it is connected to GND, the device is disabled. 6 GND Ground. The power ground and signal ground. Placing a 0.1F decoupling capacitor between VCC and GND is recommended. 7 GATE Driver Output. Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is 16.5V. 8 VCC Power Supply. Driver and control circuit supply voltage. Inverting Input of the Error Amplifier. INV is connected to the converter output via a resistive divider. This pin is also used for over-voltage clamping and open-loop feedback protection. Output of the Error Amplifier. To create a precise clamping protection, a compensation network between this pin and GND is suggested. Maximum On Time. A resistor from MOT to GND is used to determine the maximum on-time of the external power MOSFET. The maximum output power of the converter is a function of the maximum on time. Current Sense. Input to the over-current protection comparator. When the sensed voltage across the sense resistor reaches the internal threshold (0.8V), the switch is turned off to activate cycle-by-cycle current limiting. (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are given with respect to GND pin. Symbol Parameter Min. Max. Unit 30 V VVCC DC Supply Voltage VHIGH Gate Driver -0.3 30.0 V VLOW Others (INV, COMP, MOT, CS) -0.3 7.0 V VZCD Input Voltage to ZCD Pin -0.3 12.0 V PD Power Dissipation TJ Operating Junction Temperature JA Thermal Resistance (Junction-to-Air) TSTG TL ESD SOP 400 DIP 800 -40 SOP 150 DIP 113 Storage Temperature Range -65 Lead Temperature (Wave Soldering or IR, 10 Seconds) +125 +150 SOP +230 DIP +260 mW C C/W C FAN6961 -- Boundary Mode PFC Controller Absolute Maximum Ratings C Human Body Model: JESD22-A114 2.5 KV Machine Model: JESD22-A115 200 V Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Min. Operating Ambient Temperature (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 -40 Typ. Max. Unit +125 C www.fairchildsemi.com 4 Unless otherwise noted, VCC=15V and TJ= -40C to 125C. Current is defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Units 24.5 V VCC Section VCC-OP Continuous Operation Voltage VCC-ON Turn-On Threshold Voltage 11.5 12.5 13.5 V VCC-OFF Turn-Off Threshold Voltage 8.5 9.5 10.5 V ICC-ST Startup Current VCC=VCC-ON - 0.16V 10 20 A ICC-OP Operating Supply Current VCC=12V, VCS=0V, CL=3nF, fSW =60KHz 4.5 6 mA 27.8 28.8 V VCC-OVP VDD Over-Voltage Protection Level 26.8 tD-VCCOVP VDD Over-Voltage Protection Debounce 30 s Error Amplifier Section VREF Reference Voltage 2.475 Gm Transconductance 125 VINVH Clamp High Feedback Voltage 2.65 VINVL Clamp Low Feedback Voltage 2.25 VOUT HIGH Output High Voltage VOZ 2.500 2.525 V mho 2.70 V 2.30 V 4.8 V Zero Duty Cycle Output Voltage 1.15 1.25 1.35 V VINV-OVP Over Voltage Protection for INV Input 2.70 2.75 2.80 V VINV-UVP Under Voltage Protection for INV Input 0.40 0.45 0.50 V VINV=2.35V, VCOMP=1.5V 10 20 VINV=1.5V, 550 800 VINV=2.65V, VCOMP=5V 10 20 0.77 0.82 ICOMP Source Current Sink Current FAN6961 -- Boundary Mode PFC Controller Electrical Characteristics A Current-Sense Section VPK Threshold Voltage for Peak Current Limit Cycle-by-Cycle Limit tPD Propagation Delay tLEB Leading-Edge Blanking Time 0.87 V 200 ns RMOT=24k, VCOMP=5V 400 500 RMOT=24k, VCOMP=VOZ+50mV 270 350 16.0 17.5 V 1.4 V ns Gate Section VZ-OUT Output Voltage Maximum (Clamp) VCC=25V 14.5 VOL Output Voltage Low VCC=15V, IO=100mA VOH Output Voltage High VCC=14V, IO=100mA tR Rising Time VCC=12V, CL=3nF, 20~80% 80 ns tF Falling Time VCC=12V, CL=3nF, 80~20% 40 ns 8 V Continued on the following page... (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 www.fairchildsemi.com 5 Unless otherwise noted, VCC=15V and TJ=-40C to 125C. Current is defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Units 1.9 2.1 2.3 V Zero Current Detection Section VZCD HYS of VZCD Input Threshold Voltage Rising Edge VZCD Increasing Threshold Voltage Hysteresis VZCD Decreasing 0.35 VZCD-HIGH Upper Clamp Voltage IZCD=3mA VZCD-LOW Lower Clamp Voltage IZCD=-1.5mA 0.3 Maximum Delay, ZCD to Output Turn-On VCOMP=5V, fSW =60KHz 100 Restart Time Output Turned Off by ZCD 300 tINHIB Inhibit Time (Maximum Switching Frequency Limit) RMOT=24k VDIS Disable Threshold Voltage tDEAD tRESTART tZCD-DIS Disable Function Debounce Time 12 V V 500 400 ns 700 s 2.8 130 RMOT=24k, VZCD=100mV V 200 s 250 800 FAN6961 -- Boundary Mode PFC Controller Electrical Characteristics mV s Maximum On Time Section VMOT tON-MAX Maximum On Time Voltage Maximum On Time Programming (Resistor Based) (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 1.25 RMOT=24k, VCS=0V, VCOMP=5V 1.30 25 1.35 V s www.fairchildsemi.com 6 3.0 2.515 2.4 I CC-OP (mA) V ref (V) 2.525 2.505 2.495 2.485 1.8 1.2 0.6 2.475 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature () 20 35 50 65 80 95 110 125 Temperature () Figure 5. VREF vs. TA Figure 6. ICC-OP vs. TA 24.60 14.0 24.52 13.4 V th-ON (V) t ON-MAX (s) 5 24.44 24.36 24.28 FAN6961 -- Boundary Mode PFC Controller Typical Performance Characteristics 12.8 12.2 11.6 24.20 -40 -25 -10 5 20 35 50 65 80 11.0 95 110 125 -40 -25 -10 5 Temperature () 35 50 65 80 95 110 125 Temperature () Figure 7. tON-MAX vs. TA Figure 8. Vth-ON vs. TA 10.5 16.0 10.1 13.6 I CC-ST (A) V th-OFF (V) 20 9.7 9.3 8.9 11.2 8.8 6.4 8.5 4.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature () 20 35 50 65 80 95 110 125 Temperature () Figure 9. Vth-OFF vs. TA (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 5 Figure 10. ICC-ST vs. TA www.fairchildsemi.com 7 18.0 1.330 17.4 V Z-OUT (V) V MOT (V) 1.350 1.310 1.290 1.270 16.8 16.2 15.6 1.250 15.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature () 5 20 35 50 65 80 Temperature () Figure 11. VMOT vs. TA Figure 12. VZ-OUT vs. TA 95 110 125 FAN6961 -- Boundary Mode PFC Controller Typical Performance Characteristics (Continued) 0.87 V PK (V) 0.85 0.83 0.81 0.79 0.77 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Figure 13. VPK vs. TA (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 www.fairchildsemi.com 8 Error Amplifier Leading-Edge Blanking (LEB) The inverting input of the error amplifier is referenced to INV. The output of the error amplifier is referenced to COMP. The non-inverting input is internally connected to a fixed 2.5V 2% voltage. The output of the error amplifier is used to determine the on-time of the PWM output and regulate the output voltage. To achieve a low input current THD, the variation of the on time within one input AC cycle should be very small. A multivector error amplifier is built in to provide fast transient response and precise output voltage clamping. A turn-on spike on CS pin appears when the power MOSFET is switched on. At the beginning of each switching pulse, the current-limit comparator is disabled for around 400ns to avoid premature termination. The gate drive output cannot be switched off during the blanking period. Conventional RC filtering is not necessary, so the propagation delay of current limit protection can be minimized. For FAN6961, connecting a capacitance, such as 1F, between COMP and GND is suggested. The error amplifier is a trans-conductance amplifier that converts voltage to current with a 125mho. The turn-on and turn-off threshold voltage is fixed internally at 12V/9.5V. This hysteresis behavior guarantees a one-shot startup with proper startup resistor and hold-up capacitor. With an ultra-low startup current of 20A, one 1M RIN is sufficient for startup under low input line voltage, 85Vrms. Power dissipation on RIN would be less than 0.1W even under high line (VAC=265Vrms) condition. Under-Voltage Lockout (UVLO) Startup Current Typical startup current is less than 20A. This ultra-low startup current allows the usage of high resistance, low-wattage startup resistor. For example, 1M/0.25W startup resistor and a 10F/25V (VCC hold-up) capacitor are recommended for an AC-to-DC power adaptor with a wide input range 85-265VAC. Output Driver With low on resistance and high current driving capability, the output driver can drive an external capacitive load larger than 3000pF. Cross conduction current has been avoided to minimize heat dissipation, improving efficiency and reliability. This output driver is internally clamped by a 16.5V Zener diode. Operating Current Operating current is typically 4.5mA. The low operating current enables a better efficiency and reduces the requirement of VCC hold-up capacitance. Zero-Current Detection (ZCD) The zero-current detection of the inductor is achieved using its auxiliary winding. When the stored energy of the inductor is fully released to output, the voltage on ZCD goes down and a new switching cycle is enabled after a ZCD trigger. The power MOSFET is always turned on with zero inductor current such that turn-on loss and noise can be minimized. The converter works in boundary-mode and peak inductor current is always exactly twice of the average current. A natural power factor correction function is achieved with the lowbandwidth, on-time modulation. An inherent maximum off time is built in to ensure proper start-up operation. This ZCD pin can be used as a synchronous input. Maximum On-Time Operation Given a fixed inductor value and maximum output power, the relationship between on-time and line voltage is: t on = 2 * L * Po Vrms 2 * (1) If the line voltage is too low or the inductor value is too high, tON is too long. To avoid extra low operating frequency and achieve brownout protection, the maximum value of tON is programmable by one resistor, RI, connected between MOT and GND. A 24k resistor RI generates corresponds to 25s maximum on time: t on(max) 25 = R I ( k ) * (s ) 24 Noise Immunity Noise on the current sense or control signal can cause significant pulse-width jitter, particularly in the boundary-mode operation. Slope compensation and built-in debounce circuit can alleviate this problem. Because the FAN6961 has a single ground pin, high sink current at the output cannot be returned separately. Good high-frequency or RF layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near to the FAN6961, and increasing the power MOSFET gate resistance improve performance. (2) The range of the maximum on-time is designed as 10 ~ 50s. Peak Current Limiting The switch current is sensed by one resistor. The signal is feed into CS pin and an input terminal of a comparator. A high voltage in CS pin terminates a switching cycle immediately and cycle-by-cycle current limit is achieved. The designed threshold of the protection point is 0.82V. (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 FAN6961 -- Boundary Mode PFC Controller Functional Description www.fairchildsemi.com 9 FAN6961 -- Boundary Mode PFC Controller Reference Circuit Figure 14. (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 Reference Circuit www.fairchildsemi.com 10 FAN6961 --Boundary Mode PFC Controller Physical Dimensions 9.83 9.00 6.67 6.096 8.255 7.61 3.683 3.20 5.08 MAX 7.62 0.33 MIN 3.60 3.00 (0.56) 2.54 0.56 0.355 0.356 0.20 1.65 1.27 9.957 7.87 7.62 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 15. 8-Lead, PDIP, JEDEC MS-001, .300 Inch Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 www.fairchildsemi.com 11 5.00 4.80 A 0.65 3.81 5 8 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M FAN6961 --Boundary Mode PFC Controller Physical Dimensions (Continued) 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45 0.25 R0.10 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8 0 0.90 0.406 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 16. 8-Lead, SOIC,JEDEC MS-012, .150 Inch Narrow Body Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 www.fairchildsemi.com 12 FAN6961 --Boundary Mode PFC Controller (c) 2009 Fairchild Semiconductor Corporation FAN6961 * Rev. 1.0.3 www.fairchildsemi.com 13