FAN6961SY - Fairchild - Datasheet.Directory

June 2009

FAN6961 • Rev. 1.0.3

FAN6961 —Boundary Mode PFC Controller

FAN6961

Boundary Mode PFC Controller

Features

 Boundary Mode PFC Controller

 Low Input Current THD

 Controlled On-Time PWM

 Zero-Current Detection

 Cycle-by-Cycle Current Limiting

 Leading-Edge Blanking instead of RC Filtering

 Low Startup Current: 10µA Typical

 Low Operating Current: 4.5mA Typical

 Feedback Open-Loop Protection

 Programmable Maximum On-Time (MOT)

 Output Over-Voltage Clamping Protection

 Clamped Gate Output Voltage 16.5V

Applications

 Electric Lamp Ballasts

 AC-DC Switching Mode Power Converter

 Open Frame Power Supplies and Power Adapters

 Flyback Power Converters with ZCS / ZVS

Description

The FAN6961 is an 8-pin, boundary-mode, PFC

controller IC intended for controlling PFC pre-

regulators. The FAN6961 provides a controlled on-time

to regulate the output DC voltage and achieve natural

power factor correction. The maximum on-time of the

external switch is programmable to ensure safe

operation during AC brownouts. An innovative multi-

vector error amplifier is built in to provide rapid transient

response and precise output voltage clamping. A built-

in circuit disables the controller if the output feedback

loop is opened. The startup current is lower than 20µA

and the operating current has been reduced to under

6mA. The supply voltage can be up to 25V, maximizing

application flexibility.

Ordering Information

Part

Number Operating

Temperature Range Package Eco Status Packing

Method

FAN6961SZ -40°C to +125°C 8-Pin, Small Outline Package (SOP) RoHS Tape & Reel

FAN6961DZ -40°C to +125°C 8-Pin, Dual In-line Package (DIP) RoHS Tube

FAN6961SY -40°C to +125°C 8-Pin, Small Outline Package (SOP) Green Tape & Reel

For Fairchild’s defini t i on of Eco St atus, pleas e visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

FAN6961 • Rev. 1.0.3 2

FAN6961 — Boundary Mode PFC Controller

Application Diagram

Figure 1. Typical Application

Block Diagram

Figure 2. Function Block Diagram

FAN6961 • Rev. 1.0.3 3

FAN6961 — Boundary Mode PFC Controller

Marking Informa ti on

Figure 3. Marking Information

Pin Configuration

1432

8765

VCC GATE

MOT

ZCD

INV COMP CS

GND

Figure 4. DIP and SOP Pin Configuration (Top View)

Pin Definitions

Pin # Name Description

1 INV

Inverting Input of the Error Amplifier. INV is connected to the converter output via a resistive

divider. This pin is also used for over-voltage clamping and open-loop feedback protection.

2 COMP

Output of the Error Amplifier. To create a precise clamping protection, a compensation

network between this pin and GND is suggested.

3 MOT

Maximum On Time. A resistor from MOT to GND is used to determine the maximum on-time of

the external power MOSFET. The maximum output power of the converter is a function of the

maximum on time.

4 CS

Current Sense. Input to the over-current protection comparator. When the sensed voltage

across the sense resistor reaches the internal threshold (0.8V), the switch is turned off to

activate cycle-by-cycle current limiting.

5 ZCD

Zero Current Detection. This pin is connected to an auxiliary winding via a resistor to detect

the zero crossing of the switch current. When the zero crossing is detected, a new switching

cycle is started. If it is connected to GND, the device is disabled.

6 GND

Ground. The power ground and signal ground. Placing a 0.1µF decoupling capacitor between

VCC and GND is recommended.

7 GATE

Driver Output. Totem-pole driver output to drive the external power MOSFET. The clamped

gate output voltage is 16.5V.

8 VCC

Power Supply. Driver and control circuit supply voltage.

F- Fairchild Logo

Z- Plant Code

X- Year Code

Y- Week Code

TT: Die Run Code

T: Package Type (S=SOP, D=DIP)

P: Z: Pb Free Y: Green Compound

M: Manufacture Flow Code

FAN6961

TPM

FAN6961 • Rev. 1.0.3 4

FAN6961 — Boundary Mode PFC Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are

given with respect to GND pin.

Symbol Parameter Min. Max. Unit

VVCC DC Supply Voltage 30 V

VHIGH Gate Driver -0.3 30.0 V

VLOW Others (INV, COMP, MOT, CS) -0.3 7.0 V

VZCD Input Voltage to ZCD Pin -0.3 12.0 V

SOP 400

PD Power Dissipation DIP 800 mW

TJ Operating Junction Temperature -40 +125 °C

SOP 150

θJA Thermal Resistance (Junction-to-Air) DIP 113 °C/W

TSTG Storage Temperature Range -65 +150 °C

SOP +230

TL Lead Temperature (Wave Soldering or IR, 10 Seconds) DIP +260 °C

Human Body Model: JESD22-A114 2.5 KV

ESD Machine Model: JESD22-A115 200 V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

TA Operating Ambient Temperature -40 +125 °C

FAN6961 • Rev. 1.0.3 5

FAN6961 — Boundary Mode PFC Controller

Electrical Characteristics

Unless otherwise noted, VCC=15V and TJ= -40°C to 125°C. Current is defined as positive into the device and

negative out of the device.

Symbol Parameter Conditions Min. Typ. Max. Units

VCC Section

VCC-OP Continuous Operation Voltage 24.5 V

VCC-ON Turn-On Threshold Voltage 11.5 12.5 13.5 V

VCC-OFF Turn-Off Threshold Voltage 8.5 9.5 10.5 V

ICC-ST Startup Current VCC=VCC-ON – 0.16V 10 20 µA

ICC-OP Operating Supply Current VCC=12V, VCS=0V,

CL=3nF, fSW=60KHz 4.5 6 mA

VCC-OVP V

DD Over-Voltage Protection Level 26.8 27.8 28.8 V

tD-VCCOVP V

DD Over-Voltage Protection Debounce 30 µs

Error Amplifier Section

VREF Reference Voltage 2.475 2.500 2.525 V

Gm Transconductance 125 μmho

VINVH Clamp High Feedback Voltage 2.65 2.70 V

VINVL Clamp Low Feedback Voltage 2.25 2.30 V

VOUT HIGH Output High Voltage 4.8 V

VOZ Zero Duty Cycle Output Voltage 1.15 1.25 1.35 V

VINV-OVP Over Voltage Protection for INV Input 2.70 2.75 2.80 V

VINV-UVP Under Voltage Protection for INV Input 0.40 0.45 0.50 V

VINV=2.35V, VCOMP=1.5V 10 20

Source Current

VINV=1.5V, 550 800

ICOMP

Sink Current VINV=2.65V, VCOMP=5V 10 20

μA

Current-Sense Section

VPK Threshold Voltage for Peak Current Limit

Cycle-by-Cycle Limit 0.77 0.82 0.87 V

tPD Propagation Delay 200 ns

RMOT=24kΩ, VCOMP=5V 400 500

tLEB Leading-Edge Blanking Time RMOT=24kΩ,

VCOMP=VOZ+50mV 270 350

ns

Gate Section

VZ-OUT Output Voltage Maximum (Clamp) VCC=25V 14.5 16.0 17.5 V

VOL Output Voltage Low VCC=15V, IO=100mA 1.4 V

VOH Output Voltage High VCC=14V, IO=100mA 8 V

tR Rising Time VCC=12V, CL=3nF,

20~80% 80 ns

tF Falling Time VCC=12V, CL=3nF,

80~20% 40 ns

Continued on the following page…

FAN6961 • Rev. 1.0.3 6

FAN6961 — Boundary Mode PFC Controller

Electrical Characteristics

Unless otherwise noted, VCC=15V and TJ=-40°C to 125°C. Current is defined as positive into the device and negative

out of the device.

Symbol Parameter Conditions Min. Typ. Max. Units

Zero Current Detection Section

VZCD Input Threshold Voltage Rising Edge VZCD Increasing 1.9 2.1 2.3 V

HYS of

VZCD Threshold Voltage Hysteresis VZCD Decreasing 0.35 V

VZCD-HIGH Upper Clamp Voltage IZCD=3mA 12 V

VZCD-LOW Lower Clamp Voltage IZCD=-1.5mA 0.3 V

tDEAD Maximum Delay, ZCD to Output Turn-On VCOMP=5V,

fSW=60KHz 100 400 ns

tRESTART Restart Time Output Turned Off by

ZCD 300 500 700 μs

tINHIB Inhibit Time (Maximum Switching

Frequency Limit) RMOT=24kΩ 2.8 μs

VDIS Disable Threshold Voltage 130 200 250 mV

tZCD-DIS Disable Function Debounce Time RMOT=24kΩ,

VZCD=100mV 800 μs

Maximum On Time Section

VMOT Maximum On Time Voltage 1.25 1.30 1.35 V

tON-MAX Maximum On Time Programming

(Resistor Based)

RMOT=24kΩ, VCS=0V,

VCOMP=5V 25 μs

FAN6961 • Rev. 1.0.3 7

FAN6961 — Boundary Mode PFC Controller

Typical Performance Characteristics

2.475

2.485

2.495

2.505

2.515

2.525

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

V

ref

(V)

0.0

0.6

1.2

1.8

2.4

3.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

I

CC-OP

(mA)

Figure 5. VREF vs. TA Figure 6. ICC-OP vs. TA

24.20

24.28

24.36

24.44

24.52

24.60

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

t

ON-MAX

(μs)

11.0

11.6

12.2

12.8

13.4

14.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

V

th-ON

(V)

Figure 7. tON-MAX vs. TA Figure 8. Vth-ON vs. TA

8.5

8.9

9.3

9.7

10.1

10.5

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

V

th-OFF

(V)

4.0

6.4

8.8

11.2

13.6

16.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

I

CC-ST

(μA)

Figure 9. Vth-OFF vs. TA Figure 10. ICC-ST vs. TA

FAN6961 • Rev. 1.0.3 8

FAN6961 — Boundary Mode PFC Controller

Typical Performance Characteristics (Continued)

1.250

1.270

1.290

1.310

1.330

1.350

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

V

MOT

(V)

15.0

15.6

16.2

16.8

17.4

18.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

V

Z-OUT

(V)

Figure 11. VMOT vs. TA Figure 12. VZ-OUT vs. TA

0.77

0.79

0.81

0.83

0.85

0.87

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

V

PK

(V)

Figure 13. VPK vs. TA

FAN6961 • Rev. 1.0.3 9

FAN6961 — Boundary Mode PFC Controller

Functional Description

Error Amplifier

The inverting input of the error amplifier is referenced to

INV. The output of the error amplifier is referenced to

COMP. The non-inverting input is internally connected

to a fixed 2.5V ± 2% voltage. The output of the error

amplifier is used to determine the on-time of the PWM

output and regulate the output voltage. To achieve a

low input current THD, the variation of the on time

within one input AC cycle should be very small. A multi-

vector error amplifier is built in to provide fast transient

response and precise output voltage clamping.

For FAN6961, connecting a capacitance, such as 1µF,

between COMP and GND is suggested. The error

amplifier is a trans-conductance amplifier that converts

voltage to current with a 125µmho.

Startup Current

Typical startup current is less than 20µA. This ultra-low

startup current allows the usage of high resistance,

low-wattage startup resistor. For example, 1MΩ/0.25W

startup resistor and a 10µF/25V (VCC hold-up) capacitor

are recommended for an AC-to-DC power adaptor with

a wide input range 85-265VAC.

Operating Current

Operating current is typically 4.5mA. The low operating

current enables a better efficiency and reduces the

requirement of VCC hold-up capacitance.

Maximum On-Time Operat i on

Given a fixed inductor value and maximum output

power, the relationship between on-time and line

voltage is:

η

•

••

=2

2

rms

o

on VPL

t (1)

If the line voltage is too low or the inductor value is too

high, tON is too long. To avoid extra low operating

frequency and achieve brownout protection, the

maximum value of tON is programmable by one resistor,

RI, connected between MOT and GND. A 24kΩ resistor

RI generates corresponds to 25µs maximum on time:

()

skRt Ion

μ

24

25

)(

(max) •Ω= (2)

The range of the maximum on-time is designed as 10 ~

50µs.

Peak Current Limit i ng

The switch current is sensed by one resistor. The

signal is feed into CS pin and an input terminal of a

comparator. A high voltage in CS pin terminates a

switching cycle immediately and cycle-by-cycle current

limit is achieved. The designed threshold of the

protection point is 0.82V.

Leading-Edge Blanking (LEB)

A turn-on spike on CS pin appears when the power

MOSFET is switched on. At the beginning of each

switching pulse, the current-limit comparator is disabled

for around 400ns to avoid premature termination. The

gate drive output cannot be switched off during the

blanking period. Conventional RC filtering is not

necessary, so the propagation delay of current limit

protection can be minimized.

Under-Voltage Lockout ( UVLO )

The turn-on and turn-off threshold voltage is fixed

internally at 12V/9.5V. This hysteresis behavior

guarantees a one-shot startup with proper startup

resistor and hold-up capacitor. With an ultra-low startup

current of 20µA, one 1MΩ R

IN is sufficient for startup

under low input line voltage, 85Vrms. Power dissipation

on RIN would be less than 0.1W even under high line

(VAC=265Vrms) condition.

Output Driver

With low on resistance and high current driving

capability, the output driver can drive an external

capacitive load larger than 3000pF. Cross conduction

current has been avoided to minimize heat dissipation,

improving efficiency and reliability. This output driver is

internally clamped by a 16.5V Zener diode.

Zero-Current Detecti on (ZCD)

The zero-current detection of the inductor is achieved

using its auxiliary winding. When the stored energy of

the inductor is fully released to output, the voltage on

ZCD goes down and a new switching cycle is enabled

after a ZCD trigger. The power MOSFET is always

turned on with zero inductor current such that turn-on

loss and noise can be minimized. The converter works

in boundary-mode and peak inductor current is always

exactly twice of the average current. A natural power

factor correction function is achieved with the low-

bandwidth, on-time modulation. An inherent maximum

off time is built in to ensure proper start-up operation.

This ZCD pin can be used as a synchronous input.

Noise Immunit y

Noise on the current sense or control signal can cause

significant pulse-width jitter, particularly in the

boundary-mode operation. Slope compensation and

built-in debounce circuit can alleviate this problem.

Because the FAN6961 has a single ground pin, high

sink current at the output cannot be returned

separately. Good high-frequency or RF layout practices

should be followed. Avoiding long PCB traces and

component leads, locating compensation and filter

components near to the FAN6961, and increasing the

power MOSFET gate resistance improve performance.

FAN6961 • Rev. 1.0.3 10

FAN6961 — Boundary Mode PFC Controller

Reference Circuit

Figure 14. Reference Circuit

FAN6961 • Rev. 1.0.3 11

FAN6961 —Boundary Mode PFC Controller

Physical Dimensions

5.08 MAX

0.33 MIN

2.54

7.62

0.56

0.355

1.65

1.27

3.683

3.20

3.60

3.00

6.67

6.096

9.83

9.00

7.62

9.957

7.87

0.356

0.20

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANCES PER

ASME Y14.5M-1994

8.255

7.61

E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.

(0.56)

Figure 15. 8-Lead, PDIP, JEDEC MS-001, .300 Inch Wide

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify

or obtain the most recent revi sion. Pac kage specif i cations do not expand the terms of Fai rchild’s worldwi de terms and condition s,

specifically the warranty t herei n, which covers Fairc hi l d products.

Always vis i t Fairchild S emiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN6961 • Rev. 1.0.3 12

FAN6961 —Boundary Mode PFC Controller

Physical Dimensions (Continued)

8°

0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

LAND PATTERN RECOMMENDATION

SEATING PLANE

0.10 C

C

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR

4

8

1

C

MBA0.25

B

5

A

5.60

0.65

1.75

1.27

6.20

5.80

3.81

4.00

3.80

5.00

4.80

(0.33)

1.27

0.51

0.33

0.25

0.10

1.75 MAX

0.25

0.19

0.36

0.50

0.25

R0.10

0.90

0.406 (1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

Figure 16. 8-Lead, SOIC,JEDEC MS-012, .150 Inch Narrow Body

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor representative to verify

or obtain the most recent revi sion. Pac kage specif i cations do not expand the terms of Fai rchild’s worldwi de terms and condition s,

specifically the warranty t herei n, which covers Fairc hi l d products.

Always vis i t Fairchild S emiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN6961 • Rev. 1.0.3 13

FAN6961 —Boundary Mode PFC Controller