CAT93C66
© 2008 SCILLC. All rights reserved 1 Doc. No. MD-1089 Rev. S
Characteristics subject to change without notice
4-Kb Microwire Serial CMOS EEPROM
FEATURES
High speed operation: 2MHz
1.8V to 5.5V supply voltage range
Selectable x8 or x16 memory organization
Sequential read
Software write protection
Power-up inadvertant write protection
Low power CMOS technology
1,000,000 Program/erase cycles
100 year data retention
Industrial and Extended temperature r anges
RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
8-pad TDFN packages
PIN CONFIGURATION
PDIP (L)
SOIC (V, X)
TSSOP (Y)
TDFN (VP2, ZD4)*
CS 1 8 VCC
SK 2 7 NC
DI 3 6 ORG
DO 4
5 GND
SOIC (W)*
NC 1 8 ORG
VCC 2 7 GND
CS 3 6 DO
SK 4
5DI
* TDFN 3x3mm (ZD4) and SOIC (W) rotated pin-out packages are
available only for Die Rev E (not recommended for new designs)
PIN FUNCTION
Pin Name Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC Power Supply
GND Ground
ORG Memory Organization
NC No Connection
DESCRIPTION
The CAT93C66 is a 4-Kb CMOS Serial EEPROM
device which is organized as either 256 registers of 16
bits (ORG pin at VCC) or 512 registers of 8 bits (ORG
pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C66
features sequential read and self-timed internal write
with auto-clear. On-chip Power-On Reset circuitry
protects the internal logic against powering up in the
wrong state.
For Ordering Information details, see page 15.
FUNCTIONAL SYMBOL
CS
SK
DI
ORG
DO
CAT93C66
V
CC
GND
Note: When the ORG pin is connected to VCC, the x16 organization
is selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull-up
device will select the x16 organization
CAT93C66
Doc. No. MD-1089 Rev. S 2 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS(1)
Parameters Ratings Units
Storage Temperature -65 to +150 °C
Voltage on Any Pin with Respect to Ground(2) -0.5 to +6.5 V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter Min Units
NEND(4) Endurance 1,000,000 Program/ Erase Cycles
TDR Data Retention 100 Years
D.C. OPERATING CHARACTERISTICS (NEW PRODUCT, DIE REV. G)
VCC = +1.8V to +5.5V, TA=-40°C to +125°C unless otherwise spe cified.
Symbol Parameter Test Conditions Min Max Units
ICC1 Power Supply Current
(Write) fSK = 1MHz, VCC = 5.0V 1 mA
ICC2 Power Supply Current
(Read) fSK = 1MHz, VCC = 5.0V 500 µA
TA = -40°C to +85°C 2
ISB1 Power Supply Current
(Standby) (x8 Mode) VIN = GND or VCC,
CS = GND ORG = GND TA = -40°C to +125°C 4
µA
TA = -40°C to +85°C 1
ISB2 Power Supply Current
(Standby) (x16 Mode)
VIN = GND or VCC,
CS = GND ORG = Float
or VCC TA = -40°C to +125°C 2
µA
TA = -40°C to +85°C 1
ILI Input Leakage Current VIN = GND to VCC TA = -40°C to +125°C 2
µA
TA = -40°C to +85°C 1
ILO Output Leakage
Current VOUT = GND to VCC,
CS = GND TA = -40°C to +125°C 2
µA
VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V
VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 VCC + 1 V
VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V
VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V VCC x 0.7 VCC + 1 V
VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V, IOL = 2.1mA 0.4 V
VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V, IOH = -400µA 2.4 V
VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V, IOL = 1mA 0.2 V
VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V, IOH = -100µA VCC - 0.2 V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Block Mode, VCC = 5V, 25°C
CAT93C66
© 2008 SCILLC. All rights reserved 3 Doc. No. MD-1089 Rev. S
Characteristics subject to change without notice
D.C. OPERATING CHARACTERISTICS (MATURE PRODUCT, DIE REV. E – NOT RECO MMENDED FOR
NEW DESIGNS)
VCC = +1.8V to +5.5V, unless otherwise specified.
Symbol Parameter Test Conditions Min Max Units
ICC1 Power Supply Current (Write) fSK = 1MHz, VCC = 5.0V 3 mA
ICC2 Power Supply Current (Read) fSK = 1MHz, VCC = 5.0V 500 µA
ISB1 Power Supply Current
(Standby) (x8 Mode) VIN = GND or VCC, CS = GND
ORG = GND 10 µA
ISB2 Power Supply Current
(Standby) (x16 Mode) VIN = GND or VCC, CS = GND
ORG = Float or VCC 10 µA
ILI Input Leakage Current VIN = GND to VCC 1 µA
ILO Output Leakage Current VOUT = GND to VCC, CS = GND 1 µA
VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V
VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 VCC + 1 V
VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V
VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V VCC x 0.7 VCC + 1 V
VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V, IOL = 2.1mA 0.4 V
VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V, IOH = -400µA 2.4 V
VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V, IOL = 1mA 0.2 V
VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V, IOH = -100µA VCC - 0.2 V
PIN CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 5V
Symbol Test Conditions Min Typ Max Units
COUT(1) Output Capacitance (DO) VOUT = 0V 5 pF
CIN(1) Input Capacitance (CS, SK, DI, ORG) VIN = 0V 5 pF
Note:
(1) These paramete rs are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
CAT93C66
Doc. No. MD-1089 Rev. S 4 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
A.C. CHARACTERISTICS(1) (NEW PRODUCT, DIE REV. G)
VCC = +1.8V to +5.5V, TA = -40°C to +125°C, unless otherwise specified.
Limits
Symbol Parameter Min Max
Units
tCSS CS Setup Time 50 ns
tCSH CS Hold Time 0 ns
tDIS DI Setup Time 100 ns
tDIH DI Hold Time 100 ns
tPD1 Output Delay to 1 0.25 µs
tPD0 Output Delay to 0 0.25 µs
tHZ(2) Output Delay to High-Z 100 ns
tEW Program/Erase Pulse Width 5 ms
tCSMIN Minimum CS Low Time 0.25 µs
tSKHI Minimum SK High Time 0.25 µs
tSKLOW Minimum SK Low Time 0.25 µs
tSV Output Delay to Status Valid 0.25 µs
SKMAX Maximum Clock Frequency DC 2000 kHz
A.C. CHARACTERISTICS (1) (MATURE PRODUCT, DIE REV E – NOT RECOMMENDED FOR NEW DESIGN)
Limits
VCC = 1.8V - 5.5V VCC = 2.5V - 5.5V VCC = 4.5V - 5.5V
Symbol Parameter Min Max Min Max Min Max Units
tCSS CS Setup Time 200 100 50 ns
tCSH CS Hold Time 0 0 0 ns
tDIS DI Setup Time 400 200 100 ns
tDIH DI Hold Time 400 200 100 ns
tPD1 Output Delay to 1 1 0.5 0.25 µs
tPD0 Output Delay to 0 1 0.5 0.25 µs
tHZ(2) Output Delay to High-Z 400 200 100 ns
tEW Program/Erase Pulse Width 10 10 10 ms
tCSMIN Minimum CS Low Time 1 0.5 0.25 µs
tSKHI Minimum SK High Time 1 0.5 0.25 µs
tSKLOW Minimum SK Low Time 1 0.5 0.25 µs
tSV Output Delay to Status Valid 1 0.5 0.25 µs
SKMAX Maximum Clock Frequency DC 250 DC 500 DC 1000 kHz
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
CAT93C66
© 2008 SCILLC. All rights reserved 5 Doc. No. MD-1089 Rev. S
Characteristics subject to change without notice
POWER-UP TIMING(1) (2)
Symbol Parameter Max Units
tPUR Power-up to Read Operation 1 ms
tPUW Power-up to Write Operation 1 ms
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
A.C. TEST CONDITIONS
Input Rise and Fall Times ≤ 50 ns
Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V
Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V
Input Pulse Voltages 0.2VCC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V
Timing Reference Voltages 0.5VCC 1.8V ≤ VCC ≤ 4.5V
Output Load Current Source IOLmax/IOHmax; CL=100pF
DEVICE OPERATION
The CAT93C66 is a 4096-bit nonvolatile memory
intended for use with industry standard micropro–
cessors. The CAT93C66 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 11-bit instructions control the reading, writing and
erase operations of the device. When organized as X8,
seven 12-bit instructions control the reading, writing and
erase operations of the device. The CAT93C66 operates
on a single power supply and will generate on chip, the
high voltage req uired during any write operation.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The serial communication protocol follows the timing
shown in Figure 1.
The ready/busy status can be determined after the start
of internal write cycle by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessar y,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state
on the rising edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in
applications where the DI pin and the DO pin are to be
tied together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2-bit (or 4-bit) opcode, 8-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The instruction format is shown in
Instruction Set table.
INSTRUCTION SET
Address Data
Instruction Start
Bit Opcode x8 x16 x8 x16 Comments
READ 1 10 A8-A0 A7-A0
Read Address AN – A0
ERASE 1 11 A8-A0 A7-A0
Clear Address AN – A0
WRITE 1 01 A8-A0 A7-A0 D7-D0 D15-D0 Write Address AN – A0
EWEN 1 00 11XXXXXXX 11XXXXXX
Write Enable
EWDS 1 00 00XXXXXXX 00XXXXXX
Write Disable
ERAL 1 00 10XXXXXXX 10XXXXXX
Clear All Addresses
WRAL 1 00 01XXXXXXX 01XXXXXX D7-D0 D15-D0 Write All Addresses
CAT93C66
Doc. No. MD-1089 Rev. S 6 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C66
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data
bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (tPD0 or tPD1).
For the CAT93C66, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will auto-
matically increment to the next address and shift out
the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues
to toggle, the device will keep incrementing to the next
address automatically until it reaches to the end of the
address space, then loops back to address 0. In the
sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 2.
Erase/Write Enable and Disable
The CAT93C66 po wers up in th e write di sable st ate. An y
writing after power-up or after an EWDS (erase/write
disable) ins truction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C66 write and erase instruc tions, and w ill preve nt
any accidental writing or clearing of the device. Data can
be read normally from the device regardless of the write
enable/disable status. The EWEN and EWDS
instructions timing is shown in Figure 3.
Figure 1. Sychronous Data Timing
Figure 2. READ Instruction Timing
SK
CS
DI
DO HIGH-Z
11 0
ANAN–1 A0
Dummy 0 D15 . . . D0
or
D7 . . .D0
Address + 1
D15 . . .D0
or
D7 . . .D0
Address + 2
D15 . . .D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Don't Ca re
t
PD0
SK
DI
CS
D
O
tDIS tPD0,tPD1 tCSMIN
tCSS
tDIS tDIH
tSKHI tCSH
VALID VALID
DATA VALID
tSKLOW
CAT93C66
© 2008 SCILLC. All rights reserved 7 Doc. No. MD-1089 Rev. S
Characteristics subject to change without notice
Write
After receiving a WRITE command (Figure 4), address
and the data, the CS (Chip Select) pin must be
deselected for a minimum of tCSMIN. The falling edge of
CS will start the self clocking clear and data store cycle
of the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C66 can be determined by
selecting the device and polling the DO pin. Since this
device features Auto-Clear before write, it is NOT
necessary to erase a memory location before it is
written into.
Erase
Upon receiving an ERASE command and address,
the CS (Chip Select) pin must be deasserted for a
minimum of tCSMIN (Figure 5). The falling edge of CS
will start the self clocking clear cycle of the selected
memory location. The clocking of the SK pin is not
necessary after the device has entered the self
clocking mode. The ready/ busy status of the
CAT93C66 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
Figure 3. EWEN/EWDS Instruction Timing
Figure 4. Write Instruction Timing
Figure 5. Erase Instruction Timing
CS
DI
STANDBY
10
0*
* ENABLE = 11
DISABLE = 00
SK
SK
CS
DI
DO
tCSMIN
STANDBY
HIGH-Z
HIGH-Z
101
ANAN-1 A0DND0
BUSY
READY
STATUS
VERIFY
tSV tHZ
tEW
SK
CS
DI
DO
STANDBY
HIGH-Z
HIGH-Z
1
ANAN-1
BUSY READY
STATUS VERIFY
tSV tHZ
tEW
tCS
11
A0
CAT93C66
Doc. No. MD-1089 Rev. S 8 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
Erase All
Upon receiving an ERAL command (Figure 6), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C66 can be deter-
mined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to
a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 7). The falling edge of CS will start the
self clocking data write to all memory locations in the
device. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C66 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
Figure 6. ERAL Instruction Timing
Figure 7. WRAL Instruction Timing
SK
CS
DI
DO
STANDBY
tCS
HIGH-Z
HIGH-Z
10 1
BUSY READY
STATUS VERIFY
tSV tHZ
tEW
00
STATUS VERIFY
SK
CS
DI
DO
STANDBY
HIGH-Z
10 1
BUSY READY
tSV tHZ
tEW
tCSMIN
DND0
00
CAT93C66
© 2008 SCILLC. All rights reserved 9 Doc. No. MD-1089 Rev. S
Characteristics subject to change without notice
PACKAGE OUTLINE DRAWINGS
PDIP 8-LEAD 300MILS (L)
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VI EW
SIDE VI EW END VIEW
PIN # 1
IDENTIFICATION
SYMBOL MIN NOM MAX
A5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56
b2 1.14 1.52 1.78
c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.25
e 2.54 BSC
E1 6.10 6.35 7.11
eB 7.87 10.92
L 2.92 3.30 3.80
CAT93C66
Doc. No. MD-1089 Rev. S 10 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
SOIC 8-LEAD 150MILS (V, W)
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
E1 E
A
A1
h
θ
Lc
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
A 1.35 1.75
A1 0.10 0.25
b 0.33 0.51
c 0.19 0.25
D 4.80 5.00
E 5.80 6.20
E1 3.80 4.00
e 1.27 BSC
h 0.25 0.50
L 0.40 1.27
θ0º 8º
SYMBOL MIN NOM MAX
CAT93C66
© 2008 SCILLC. All rights reserved 11 Doc. No. MD-1089 Rev. S
Characteristics subject to change without notice
SOIC 8-LEAD 208MILS (X)
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
θ
E1
eb
SIDE VIEW
TOP VIEW
E
D
PIN#1 IDENTIFICATION
END VIEW
A1
A
Lc
SYMBOL MIN NOM MAX
A2.03
A1 0.05 0.25
b0.36 0.48
c0.19 0.25
D5.13 5.33
E7.75 8.26
E1 5.13 5.38
e 1.27 BSC
L0.51 0.76
θ0º 8º
CAT93C66
Doc. No. MD-1089 Rev. S 12 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
TSSOP 8-LEAD 4.4MM (Y )
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
A2
E1 E
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
θ1
L1 L
SYMBOL MIN NOM MAX
A1.20
A1 0.05 0.15
A2 0.80 0.90 1.05
b0.19 0.30
c0.09 0.20
D 2.90 3.00 3.10
E 6.30 6.40 6.50
E1 4.30 4.40 4.50
e 0.65 BSC
L1.00 REF
L1 0.50 0.60 0.75
θ10° 8°
CAT93C66
© 2008 SCILLC. All rights reserved 13 Doc. No. MD-1089 Rev. S
Characteristics subject to change without notice
TDFN 8-PAD 2 X 3MM (VP2)
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
PIN#1
IDENTIFICATION
E2
E
A3
eb
D
A2
TOP VIEW SIDE VIEW BOTTOM VIEW
PIN#1 INDEX AREA
FRONT VIEW
A1
A
L
D2
SYMBOL MIN NOM MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A2 0.45 0.55 0.65
A3 0.20 REF
b 0.20 0.25 0.30
D 1.90 2.00 2.10
D2 1.30 1.40 1.50
E 2.90 3.00 3.10
E2 1.20 1.30 1.40
e 050TYP
L 0.20 0.30 0.40
CAT93C66
Doc. No. MD-1089 Rev. S 14 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
TDFN 8-PAD 3 X 3MM (ZD4)
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
E2
A3
eb
A
A1
SIDE VIEW BOTTOM VIEW
E
D
TOP VIEW
PIN#1 INDEX AREA
PIN#1 ID
FRONT VIEW
A1
A
L
D2
SYMBOL MIN NOM MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.23 0.30 0.37
D 2.90 3.00 3.10
D2 2.20 — 2.50
E 2.90 3.00 3.10
E2 1.40 — 1.80
e0.65TYP
L 0.20 0.30 0.40
CAT93C66
© 2008 SCILLC. All rights reserved 15 Doc. No. MD-1089 Rev. S
Characteristics subject to change without notice
EXAMPLE OF ORDERING INFORMATION
CAT93C66, DIE REV. G (NEW PROD UCT)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT93C66VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000 units/Reel).
(4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C66XI-T2.
(5) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
CAT93C66, DIE REV. E, MATURE PROD UCT (NOT RECOMMENDED FOR NEW DESIGN)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard finish is NiPdAu.
(3) The device used in the above example is a CAT93C66VI-1.8-GT3 (SOIC green package, Industrial Temperature, 1.8 Volt to 5.5 Volt
Operating Voltage, NiPdAu finish, Tape & Reel, 3,000 units/Reel)
(4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., A YWWE.) For addi tional infor ma-
tion, please contact your ON Semiconductor Sales office.
(5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C66XI-T2.
(6) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
Prefix Device # Suffix
CAT 93C66 V I -1.8 -G T3 Rev E(4)
Operating Voltage
Blank: VCC = 2.5V to 5.5V
1.8: VCC = 1.8V to 5.5V
Company ID
Product Number
93C66
Temperature Range
I = Industrial (-40ºC to 85ºC)
A = Automotive (-40ºC to 105ºC)
E = Extended (-40º C to 125ºC)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Die Revision
93C66: E
Package
L: PDIP
V: SOIC, JEDEC
W: SOIC, JEDEC
X: SOIC, EIAJ(5)
Y: TSSOP
ZD4: T DFN (3x3mm)
Tape & Reel
T: Tape & Reel
2: 2,000 units/Reel(5)
3: 3,000 units/Reel
Prefix Device # Suffix
CAT 93C66 V I -G T3
Company ID
Product Number
93C66
Temperature Range
I = Industrial (-40ºC to +85ºC)
E = Extended (-40ºC to +125ºC)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Package
L: PDIP
V: SOIC, JEDEC
X: SOIC, EIAJ(4)
Y: TSSOP
VP2: T DFN (2x3mm) Tape & Reel
T: Tape & Reel
2: 2,000 units/Reel(4)
3: 3,000 units/Reel
CAT93C66
Doc. No. MD-1089 Rev. S 16 © 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
REVISION HISTORY
Date Rev. Comments
05/14/04 L New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT9 3C56,
CAT93C57, CAT93C66, CAT93C76 a nd CAT93C86 have been separated into singl e
data sheets
Add Die Revision ID Letter
Update Features
Update Description
Update Pin Condition
Add Functional Diagram
Update Pin Function
Update D.C. Operating Characteristics
Update Pin Capacitance
Update Instruction Set
Update Device Operation
Update Ordering Information
Update Revision History
Update Rev Number
10/13/06 M Update Features
Update Pin Configuration / Packages
Update Functional Symbol
Update Pin Functions
Update D.C. Operating Characteristics (VCC Range)
Add Package Drawings
Update Example of Ordering Information
11/17/06 N Remove "Die Rev E" from the title
Update Pin Configuration / Packages
Update Absolute Maximum Rating
Update Reliability Characteristics
Update D.C. Operating Characteristics
Added A.C. Characteristics for Die Rev G
Rearrange / Format Text and Figures
Added Example of Ordering Information for Die Rev G
12/07/06 O
Update separate DC Characteristics for Die Rev. G and Die Rev. E.
Updated Example of Ordering Information
03-Apr-07 P
Update note on page 1
Update D.C. Operating Characteristics (New Product, Die Rev. G)
Update Ordering Information – CAT93C66, Die Rev. G (New Product)
21-Aug-07 Q
Update Note on Pin Configuration
Update Package Outline Drawings
Update Example of Ordering Information
Add MD- to document number
10-Apr-08 R
Add Extended Temperature Range
Update Package Outline Drawings
24-Oct-08 S
Change logo and fine print to ON Semicondu ctor
CAT93C66
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIL LC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typ icals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended f or surgical implant into the body, or other applications
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distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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© 2008 SCILLC. All rights reserved. 17 Doc. No. MD-1089 Rev. S
Characteristics subject to change without notice
