Precision Low Cost
ISOLATION AMPLIFIER
ISO120
ISO121
Signal
Com 2
–V
S2
Gnd 2
+V
S2
Ext Osc
+V
S1
Gnd 1
–V
S1
Signal
Com 1
V
OUT
C
1L
C
1H
Sense
C
2L
C
2H
Isolation Barrier
V
IN
DESCRIPTION
The ISO120 and ISO121 are precision isolation ampli-
fiers incorporating a novel duty cycle modulation-
demodulation technique. The signal is transmitted
digitally across a 2pF differential capacitive barrier.
With digital modulation the barrier characteristics do
not affect signal integrity, which results in excellent
reliability and good high frequency transient immu-
nity across the barrier. Both the amplifier and barrier
capacitors are housed in a hermetic DIP. The ISO120
and ISO121 differ only in package size and isolation
voltage rating.
These amplifiers are easy to use. No external compo-
nents are required for 60kHz bandwidth. With the
addition of two external capacitors, precision specifi-
cations of 0.01% max nonlinearity and 150µV/°C max
VOS drift are guaranteed with 6kHz bandwidth. A
power supply range of ±4.5V to ±18V and low quies-
cent current make these amplifiers ideal for a wide
range of applications.
FEATURES
●100% TESTED FOR PARTIAL DISCHARGE
●ISO120: Rated 1500Vrms
●ISO121: Rated 3500Vrms
●HIGH IMR: 115dB at 60Hz
●USER CONTROL OF CARRIER
FREQUENCY
●LOW NONLINEARITY: ±0.01% max
●BIPOLAR OPERATION: VO = ±10V
●0.3"-WIDE 24-PIN HERMETIC DIP, ISO120
●SYNCHRONIZATION CAPABILITY
●WIDE TEMP RANGE: –55°C to +125°C
(ISO120)
APPLICATIONS
●INDUSTRIAL PROCESS CONTROL: Trans-
ducer Isolator for Thermocouples, RTDs,
Pressure Bridges, and Flow Meters, 4mA
to 20mA Loop Isolation
●GROUND LOOP ELIMINATION
●MOTOR AND SCR CONTROL
●POWER MONITORING
●ANALYTICAL MEASUREMENTS
●BIOMEDICAL MEASUREMENTS
●DATA ACQUISITION
●TEST EQUIPMENT
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1988 Burr-Brown Corporation PDS-820D Printed in U.S.A. March, 1992
SBOS158
2ISO120/121
SPECIFICATIONS
ELECTRICAL
At TA = +25°C: VS1 = VS2 = ±15V: and RL = 2kΩ, unless otherwise noted.
*Specifications same as ISO120BG, ISO121BG.
NOTE: (1) Input voltage range = ±10V for VS1, VS2 = ±4.5VDC to ±18VDC. (2) Ripple frequency is at carrier frequency. (3) Overload recovery is approximately three times
the settling time for other values of C2. (4) The SG-grade is specified –55°C to +125°C; performance of the SG in the –25°C to +85°C temperature range is the same
as the BG-grade.
ISO120BG, ISO121BG ISO120G, ISO120SG(4), ISO121G
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ISOLATION
Voltage Rated Continuous ISO120: AC 60Hz TMIN to TMAX 1500 * Vrms
DC TMIN to TMAX 2121 * VDC
ISO121: AC 60Hz TMIN to TMAX 3500 * Vrms
DC TMIN to TMAX 4950 * VDC
100% Test (AC 60Hz): ISO120 1s; Partial Discharge ≤ 5pC 2500 * Vrms
ISO121 1s; Partial Discharge ≤ 5pC 5600 * Vrms
Isolation Mode Rejection ISO 120: AC 60Hz 1500Vrms 115 * dB
DC 160 * dB
ISO121: AC60Hz 3500Vrms 115 * dB
DC 160 * dB
Barrier Impedance 1014 || 2 * Ω || pF
Leakage Current VISO = 240Vrms, 60Hz 0.18 0.5 * * µArms
GAIN(4) VO = ±10V
Nominal Gain C1 = C2 = 1000pF 1 1 V/V
Gain Error ±0.04 ±0.1 ±0.05 ±0.25 %FSR
Gain vs Temperature ±5±20 ±10 ±40 ppm/°C
Nonlinearity ±0.005 ±0.01 ±0.01 ±0.05 %FSR
Nominal Gain C1 = C2 = 0 1 1 V/V
Gain Error ±0.04 ±0.25 ±0.05 ±0.25 %FSR
Gain vs Temperature ±40 ±40 ppm/°C
Nonlinearity ±0.02 ±0.1 ±0.04 ±0.1 %FSR
INPUT OFFSET VOLTAGE(4)
Initial Offset C1 = C2 = 1000pF ±5±25 ±10 ±50 mV
vs Temperature ±100 ±150 ±150 ±400 µV/°C
Initial Offset C1 = C2 = 0 ±25 ±100 ±40 ±100 mV
vs Temperature ±250 ±500 µV/°C
Initial Offset
vs Supply ±VS1 or ±VS2 = ±4.5V to ±18V ±2±2 mV/V
Noise 44µV/√Hz
INPUT
Voltage Range(1) ±10 ±15 * * V
Resistance 200 * kΩ
OUTPUT
Voltage Range ±10 ±12.5 * * V
Current Drive ±5±15 * * mA
Capacitive Load Drive 0.1 * µF
Ripple Voltage(2) 10 * mVp-p
FREQUENCY RESPONSE
Small Signal Bandwith C1 = C2 = 0 60 * kHz
C1 = C2 = 1000pF 6 * kHz
Slew Rate 2*V/µs
Settling Time VO = ±10V
0.1% C2 = 100pF 50 * µs
0.01% C1 = C2 = 1000pF 350 * µs
Overload Recovery Time(3) 50% Output Overload, 150 * µs
C1 = C2 = 0
POWER SUPPLIES
Rated Voltage 15 * V
Voltage Range ±4.5 ±18 * * V
Quiescent Current: VS1 ±4.0 ±5.5 * * mA
VS2 ±5.0 ±6.5 * * mA
TEMPERATURE RANGE
Specification: BG and G –25 85 –25 85 °C
SG(4) –25 85 –55 125 °C
Operating –55 125 –55 125 °C
Storage –65 150 –55 150 °C
θ
JA: ISO120 40 40 °C/W
ISO121 25 25 °C/W
3ISO120/121
PACKAGE DRAWING
MODEL PACKAGE NUMBER
ISO120G 24-Pin DIP 225
ISO120BG 24-Pin DIP 225
ISO120SG 24-Pin DIP 225
ISO121G 40-Pin DIP 206
ISO121BG 40-Pin DIP 206
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM
Supply Voltage (any supply) ...............................................................18V
VIN, Sense Voltage .......................................................................... ±100V
External Oscillator Input ....................................................................±25V
Signal Common 1 to Ground 1 ........................................................... ±1V
Signal Common 2 to Ground 2 ........................................................... ±1V
Continuous Isolation Voltage: ISO120 ......................................1500Vrms
ISO121.......................................3500Vrms
VISO, dv/dt ...................................................................................... 20kV/µs
Junction Temperature...................................................................... 150°C
Storage Temperature..................................................... –65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
Output Short Duration ......................................... Continuous to Common
PACKAGE INFORMATION(1)
1/1
2/2
3/3
4/4
9/17
10/18
11/19
12/20
(1)
C
C
+V
–V
Com 2
V
Sense
Gnd 2
1H
1L
S1
S1
OUT
24/40
23/39
22/38
21/37
16/24
15/23
14/22
13/21
Gnd 1
V
Ext Osc
Com 1
–V
+V
C
C
IN
S2
S2
2L
2H
NOTE: (1) First pin number is for ISO120.
Second pin number is for ISO121.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ELECTROSTATIC
DISCHARGE SENSITIVITY
ORDERING INFORMATION
TEMPERATURE
MODEL RANGE
ISO120G –25°C to 85°C
ISO120BG –25°C to 85°C
ISO120SG –55C to 125°C
ISO121G –25°C to 85°C
ISO121BG –25°C to 85°C
4ISO120/121
TYPICAL PERFORMANCE CURVES
TA = +25°C; VS1 = VS2 = ±15V; and RL = 2kΩ, unless otherwise noted.
1
Frequency (Hz)
0
60
40
20
PSRR (dB)
PSRR vs FREQUENCY
100 10k 1M
10 1k 100k
–V
S1
, –V
S2
+V
S1
, +V
S2
54
100
Frequency (Hz)
10
1k
100
Peak Isolation Voltage
ISOLATION MODE VOLTAGE
vs FREQUENCY ISO121
10k 1M 100M
1k 100k 10M
5k
Max AC
Rating
Degraded
Performance
Max DC Rating
Typical
Performance
100
Frequency (Hz)
10
1k
100
Peak Isolation Voltage
ISOLATION MODE VOLTAGE
vs FREQUENCY ISO120
10k 1M 100M
1k 100k 10M
2.1k Max AC
Rating
Degraded
Performance
Max DC Rating
Typical
Performance
1
Frequency (Hz)
0.1µA
100mA
10mA
1mA
100µA
10µA
1µA
Leakage Current (rms)
ISOLATION LEAKAGE CURRENT
vs FREQUENCY
100 10k 1M10 1k 100k
240 Vrms
1500 Vrms
3500 Vrms
100
–3dB Frequency (Hz)
0
100nF
10nF
1000pF
C
2
BANDWIDTH vs C
2
1k 10k 100k
100
Frequency (Hz)
0.1
100
10
1
Phase Shift (degrees)
PHASE SHIFT vs C
2
1k 10k 100k
C
2
= 0
C
2
= 1000pF
5ISO120/121
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C; VS1 = VS2 = ±15V; and RL = 2kΩ, unless otherwise noted.
1
Frequency (Hz)
40
160
140
120
100
80
60
IMR (dB)
100 10k 1M10 1k 100k
IMR vs FREQUENCY
1k
Frequency (Hz)
0
10nF
1000pF
C
1
SYNCHRONIZATION RANGE at 25°C
±4Vp SINE WAVE INPUT TO EXT OSC
10k 100k 1M
C
2
≥ C
1
Typical
Free Run
Frequency
0
f
IN
(Hz)
0
–20
–40
V
OUT
/V
IN
(dB)
SIGNAL RESPONSE vs CARRIER FREQUENCY
f
C
2f
C
3f
C
0000f
c
/2 f
C
/2 f
C
/2
f
OUT
(Hz)
–20dB/dec (for comparison only)
0.1f–3dB
Normalized Frequency
0
12
10
8
6
4
2
Noise, eN (µV/ Hz)
NOISE vs SMALL SIGNAL BANDWIDTH
0.2f–3dB 0.5f–3dB f–3dB
C2 = 2C1
C2 = C1*
*C1 ≤ 5000pF
FPO
BLEED
TO EDGE
OF BOX
Output Voltage (V)
SINE RESPONSE
(f = 2kHz, C2 = 0)
Time (µs)
5000 1000
+10
0
–10
Output Voltage (V)
SINE RESPONSE
(f = 20kHz, C
2
= 0)
Time (µs)
500 100
+10
0
–10
6ISO120/121
Output Voltage (V)
STEP RESPONSE
Time (µs)
500 100
+10
0
–10
+10
0
–10
Output Voltage (V)
STEP RESPONSE
Time (µs)
2500 500
+10
0
–10
+10
0
–10
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C; VS1 = VS2 = ±15V; and RL = 2kΩ, unless otherwise noted.
THEORY OF OPERATION
The ISO120 and ISO121 isolation amplifiers comprise input
and output sections galvanically isolated by matched 1pF
capacitors built into the ceramic barrier. The input is duty-
cycle modulated and transmitted digitally across the barrier.
The output section receives the modulated signal, converts it
back to an analog voltage and removes the ripple component
inherent in the demodulation. The input and output sections
are laser-trimmed for exceptional matching of circuitry com-
mon to both input and output sections.
FREE-RUNNING MODE
An input amplifier (A1, Figure1) integrates the difference
between the input current (VIN/200kΩ) and a switched
±100µA current source. This current source is implemented
by a switchable 200µA source and a fixed 100µA current
sink. To understand the basic operation of the input section,
assume that VIN = 0. The integrator will ramp in one
direction until the comparator threshold is exceeded. The
comparator and sense amp will force the current source to
switch; the resultant signal is a triangular waveform with a
50% duty cycle. If VIN changes, the duty cycle of the
integrator will change to keep the average DC value at the
output of A1 near zero volts. This action converts the input
voltage to a duty-cycle modulated triangular waveform at
the output of A1 near zero volts. This action converts the
input voltage to a duty-cycle modulated triangular wave-
form at the output of A1 with a frequency determined by the
internal 150pF capacitor. The comparator generates a fast
rise time square wave that is simultaneously fed back to keep
A1 in charge balance and also across the barrier to a
differential sense amplifier with high common-mode rejec-
tion characteristics. The sense amplifier drives a switched
current source surrounding A2. The output stage balances
the duty-cycle modulated current against the feedback cur-
rent through the 200kΩ feedback resistor, resulting in an
average value at the Sense pin equal to VIN. The sample and
hold amplifiers in the output feedback loop serve to remove
undesired ripple voltages inherent in the demodulation process.
SYNCHRONIZED MODE
A unique feature of the ISO120 and ISO121 is the ability to
synchronize the modulator to an external signal source. This
capability is useful in eliminating trouble-some beat fre-
quencies in multi-channel systems and in rejecting AC
signals and their harmonics. To use this feature, external
capacitors are connected at C1 and C2 (Figure 1) to change
the free-running carrier frequency. An external signal is
applied to the Ext Osc pin. This signal forces the current
source to switch at the frequency of the external signal. If
VIN is zero, and the external source has a 50% duty cycle,
operation proceeds as described above, except that the switch-
ing frequency is that of the external source. If the external
signal has a duty cycle other than 50%, its average value is
not zero. At start-up, the current source does not switch until
the integrator establishes an output equal to the average DC
value of the external signal. At this point, the external signal
is able to trigger the current source, producing a triangular
waveform, symmetrical about the new DC value, at the
output of A1. For VIN = 0, this waveform has a 50% duty
cycle. As VIN varies, the waveform retains its DC offset, but
varies in duty cycle to maintain charge balance around A1.
Operation of the demodulator is the same as outlined above.
Synchronizing to a Sine
or Triangle Wave External Clock
The ideal external clock signal for the ISO120/121 is a ±4V
sine wave or ±4V, 50% duty-cycle triangle wave. The ext osc
pin of the ISO120/121 can be driven directly with a ±3V to
±5V sine or 25% to 75% duty-cycle triangle wave and the ISO
amp's internal modulator/demodulator circuitry will synchro-
nize to the signal.
Synchronizing to signals below 400kHz requires the addition
of two external capacitors to the ISO120/121. Connect one
capacitor in parallel with the internal modulator capacitor and
connect the other capacitor in parallel with the internal de-
modulator capacitor as shown in Figure 1.
7ISO120/121
f
−3dB
≈1. 2
200kΩ150 pF +C
2
()
FIGURE 1. Block Diagram.
C1, C2 ISO120/121
EXTERNAL CLOCK MODULATOR, DEMODULATOR
FREQUENCY RANGE EXTERNAL CAPACITOR
400kHz to 700kHz none
200kHz to 400kHz 500pF
100kHz to 200kHz 1000pF
50kHz to 100kHz 2200pF
20kHz to 50kHz 4700pF
10kHz to 20kHz 0.01µF
5kHz to 10kHz 0.022µF
The value of the external modulator capacitor, C1, depends on
the frequency of the external clock signal. Table I lists
recommended values.
Synchronizing to a 400kHz to 700kHz
Square-Wave External Clock
At frequencies above 400kHz, an internal clamp and filter
provides signal conditioning so that a square-wave signal can
be used to directly drive the ISO120/121. A square-wave
external clock signal can be used to directly drive the ISO120/
121 ext osc pin if: the signal is in the 400kHz to 700kHz
frequency range with a 25% to 75% duty cycle, and ±3V to
±20V level. Details of the internal clamp and filter circuitry
are shown in Figure 1.
Synchronizing to a 10% to 90%
Duty-cycle External Clock
With the addition of the signal conditioning circuit shown in
Figure 2, any 10% to 90% duty-cycle square-wave signal can
be used to drive the ISO120/121 ext osc pin. With the values
shown, the circuit can be driven by a 4Vp-p TTL signal. For
a higher or lower voltage input, increase or decrease the 1kΩ
resistor, RX, proportionally. e.g. for a ±4V square wave
(8Vp-p) RX should be increased to 2kΩ.
The value of CX used in the Figure 2 circuit depends on the
frequency of the external clock signal. Table II shows recom-
mended capacitor values.
Note: For external clock frequencies below 400kHz, external
modulator/demodulator capacitors are required on the
ISO120/121 as before.
TABLE I. Recommended ISO120/121 External Modulator/
Demodulator Capacitor Values vs External Clock
Frequency.
The value of the external demodulator capacitor, C2, depends
on the value of the external modulator capacitor. To assure
stability, C2 must be greater than 0.8 • C1. A larger value for
C2 will decrease bandwidth and improve stability:
Where:
f–3dB ≈ –3dB bandwidth of ISO amp with external C2 (Hz)
C2 = External demodulator capacitor (f)
For example, with C2 = 0.01µF, the f–3dB bandwidth of the
ISO120/121 is approximately 600Hz.
1pF
1pF
1pF
1pF
S/H
G = 1 S/H
G = 6
Sense
V
OUT
Signal
Com 2
Gnd 2 –V
S2
+V
S2
Gnd 1 –V
S1
+V
S1
Signal
Com 1
V
IN
C
1H
C
1L
C
1(1)
200kΩ150pF
A1
100µA
Sense
200µA
X
100µA
Sense
200µA
200kΩ
150pF
C
2L
C
2H
C
2(1)
X
A2
Isolation Barrier
NOTE: (1) Optional. See text.
30kΩ16kΩ
Ext
Osc
16kΩ50pF
8ISO120/121
BASIC OPERATION
Signal and Power Connections
Figure 3 shows proper power and signal connections. Each
power supply pin should be bypassed with 1µF tantalum
capacitor located as close to the amplifier as possible. All
ground connections should be run independently to a com-
mon point if possible. Signal Common on both input and
output sections provide a high-impedance point for sensing
signal ground in noisy applications. Signal Common must
have a path to ground for bias current return and should be
maintained within ±1V of Gnd. The output sense pin may be
EXTERNAL CLOCK
FREQUENCY RANGE CX
400kHz to 700kHz 30pF
200kHz to 400kHz 180pF
100kHz to 200kHz 680pF
50kHz to 100kHz 1800pF
20kHz to 50kHz 3300pF
10kHz to 20kHz 0.01µF
5kHz to 10kHz 0.022µF
10kΩ
C
X
OPA602
R
X
1µF
Sq Wave In Triangle Out
to ISO120/121
Ext Osc
1kΩ
FIGURE 2. Square Wave to Triangle Wave Signal Condi-
tioner for Driving ISO120/121 Ext Osc Pin.
TABLE II. Recommended CX Values vs Frequency for
Figure 2 Circuit.
C
1(1)
C
1H
C
1L
–V
S1
–+V
S1
+
+1µF
+1µF
+
+V
S1
Signal
Com1
Gnd1
V
IN
Guard
Ext
(2)
Osc
C
2(1)
C
2H
C
2L
–V
S2
–+V
S2
+
+1µF
Guard
1µF
+
+V
S2
Gnd 2
Signal
Com 2
R
L
V
OUT
Sense
Isolation Barrier
NOTE: (1) Optional. See text. (2) Ground if not used.
FIGURE 3. Power and Signal Connections.
connected directly to VOUT or may be connected to a remote
load to eliminate errors due to IR drops. Pins are provided
for use of external integrator capacitors. The C1H and C2H
pins are connected to the integrator summing junctions and
are therefore particularly sensitive to external pickup. This
sensitivity will most often appear as degraded IMR or PSR
performance. AC or DC currents coupled into these pins
results in VERROR = IERROR X 200kΩ at the output. Guarding
of these pins to their respective Signal Common, or C1L and
C2L is strongly recommended. For similar reasons, long
traces or physically large capacitors are not desirable. If
wound-foil capacitors are used, the outside foil should be
connected to C1L and C2L, respectively.
Optional Gain and Offset Adjustments
Rated gain accuracy and offset performance can be achieved
with no external adjustments, but the circuit of Figure 4a
may be used to provide a gain trim of ±0.5% for values
shown; greater range may be provided by increasing the size
of R1 and R2. Every 2kΩ increase in R1 will give an
additional 1% adjustment range, with R2 ≥ 2R1. If safety or
convenience dictates location of the adjustment potenti-
ometer on the other side of the barrier from the position
shown in Figure 4a, the positions of R1 and R2 may be
reversed. Gains greater than one may be obtained by using
the circuit of Figure 4b. Note that the effect of input offset
errors will be multiplied at the output in proportion to the
increase in gain. Also, the small-signal bandwidth will be
decreased in inverse proportion to the increase in gain. In
most instances, a precision gain block at the input of the
isolation amplifier will provide better overall performance.
Figure 5 shows a method for trimming VOS of the ISO120
and ISO121. This circuit may be applied to either Signal
Com (input or output) as desired for safety or convenience.
With the values shown, ±15V supplies and unity gain, the
circuit will provide ±150mV adjustment range and 0.25mV
9ISO120/121
output are not significant under these circumstances unless
the input signal contains significant components above
250kHz.
There are two ways to use these characteristics. One is to
move the carrier frequency low enough that the troublesome
signal components are attenuated to an acceptable level as
shown in Signal Response vs Carrier Frequency. This in
effect limits the bandwidth of the amplifier. The Synchroni-
zation Range performance curve shows the relationship
between carrier frequency and the value of C1. To maintain
stability, C2 must also be connected and must be equal to or
larger in value than C1. C2 may be further increased in value
for additional attenuation of the undesired signal compo-
nents and provides the additional benefit of reducing the
residual carrier ripple at the output. See the Bandwidth vs C2
performance curve.
When periodic noise from external sources such as system
clocks and DC/DC converters are a problem, ISO120 and
ISO121 can be used to reject this noise. The amplifier can be
synchronized to an external frequency source, fEXT, placing
the amplifier response curve at one of the frequency and
amplitude nulls indicated in the Signal Response vs Carrier
Frequency performance curve. For proper synchronization,
choose C1 as shown in the Synchronization Range perfor-
mance curve. Remember that C2 ≥ C1 is a necessary condi-
tion for stability of the isolation amplifier. This curve shows
the range of lock at the fundamental frequency for a 4V
sinusoidal signal source. The applications section shows the
ISO120 and ISO121 synchronized to isolation power sup-
plies, while Figure 6 shows circuitry with opto-isolation
suitable for driving the Ext Osc input from TTL levels.
FIGURE 4a. Gain Adjust.
FIGURE 4b. Gain Setting.
+V
S1
or +V
S2
Signal Com 1
or
Signal Com 2
–V
S1
or –V
S2
100kΩ1MΩ
10kΩ
FIGURE 5. VOS Adjust.
resolution with a typical trim potentiometer. The output will
have some sensitivity to power supply variations. For a
±100mV trim, power supply sensitivity is 8mV/V at the
output.
CARRIER FREQUENCY CONSIDERATIONS
As previously discussed, the ISO120 and ISO121 amplifiers
transmit the signal across the iso-barrier by a duty-cycle
modulation technique. This system works like any linear
amplifier for input signals having frequencies below one
half the carrier frequency, fC. For signal frequencies above
fC/2, the behavior becomes more complex. The Signal Re-
sponse vs Carrier Frequency performance curve describes
this behavior graphically. The upper curve illustrates the
response for input signals varying from DC to fC/2. At input
frequencies at or above fC/2, the device generates an output
signal component that varies in both amplitude and fre-
quency, as shown by the lower curve. The lower horizontal
scale shows the periodic variation in the frequency of the
output component. Note that at the carrier frequency and its
harmonics, both the frequency and amplitude of the re-
sponse go the zero. These characteristics can be exploited in
certain applications. It should be noted that when C1 is zero,
the carrier frequency is nominally 500kHz and the –3dB
point of the amplifier is 60kHz. Spurious signals at the
FIGURE 6. Synchronization with Isolated Drive Circuit for
Ext Osc Pin.
C
1
Ext Osc on
ISO120 (pin 22)
C
2
10kΩ
6
5
82
3
TTL
f
IN
2.5kΩ
200Ω
+15V+5V
f
IN
140E-6
()
C
1
= – 350pF
C
2
= 10 X C
1
, with a minimum 10nF
2.5kΩ
6N136
ISOLATION MODE VOLTAGE
Isolation mode voltage (IMV) is the voltage appearing be-
tween isolated grounds Gnd 1 and Gnd 2. IMV can induce
error at the output as indicated by the plots of IMV vs
Frequency. It should be noted that if the IMV frequency
exceeds fC/2, the output will display spurious outputs in a
manner similar to that described above, and the amplifier
response will be identical to that shown in the Signal Re-
sponse vs Carrier Frequency performance curve. This occurs
R
2
V
IN
V
OUT
R
1
Sense
R
2
R
1
200k
Gain = 1 + + R
1
( )
R
1
||
R
2
GND1
1kΩ 2kΩ
R
1
R
2
V
IN
V
OUT
GND1
Sense
10ISO120/121
because IMV-induced errors behave like input-referred error
signals. To predict the total IMR, divide the isolation voltage
by the IMR shown in IMR vs Frequency performance curve
and compute the amplifier response to this input-referred
error signal from the data given in the Signal Response vs
Carrier Frequency performance curve. Due to effects of very
high-frequency signals, typical IMV performance can be
achieved only when dV/dT of the isolation mode voltage
falls below 1000V/µs. For convenience, this is plotted in the
typical performance curves for the ISO120 and ISO121 as a
function of voltage and frequency for sinusoidal voltages.
When dV/dT exceeds 1000V/µs but falls below 20kV/µs,
performance may be degraded. At rates of change above
20kV/µs, the amplifier may be damaged, but the barrier
retains its full integrity. Lowering the power supply voltages
below ±15V may decrease the dV/dT to 500V/µs for typical
performance, but the maximum dV/dT of 20kV/µs remains
unchanged.
Leakage current is determined solely by the impedance of
the 2pF barrier capacitance and is plotted in the Isolation
Leakage Current vs Frequency curve.
ISOLATION VOLTAGE RATINGS
Because a long-term test is impractical in a manufacturing
situation, the generally accepted practice is to perform a
production test at a higher voltage for some shorter time. The
relationship between actual test voltage and the continuous
derated maximum specification is an important one. Histori-
cally, Burr-Brown has chosen a deliberately conservative
one: VTEST = (2 X ACrms continuous rating) + 1000V for 10
seconds, followed by a test at rated ACrms voltage for one
minute. This choice was appropriate for conditions where
system transients are not well defined.
Recent improvements in high-voltage stress testing have
produced a more meaningful test for determining maximum
permissible voltage ratings, and Burr-Brown has chosen to
apply this new technology in the manufacture and testing of
the ISO120 and ISO121.
Partial Discharge
When an insulation defect such as a void occurs within an
insulation system, the defect will display localized corona or
ionization during exposure to high-voltage stress. This ion-
ization requires a higher applied voltage to start the dis-
charge and lower voltage to maintain it or extinguish it once
started. The higher start voltage is known as the inception
voltage, while the extinction voltage is that level of voltage
stress at which the discharge ceases. Just as the total insula-
tion system has an inception voltage, so do the individual
voids. A voltage will build up across a void until its incep-
tion voltage is reached, at which point the void will ionize,
effectively shorting itself out. This action redistributes elec-
trical charge within the dielectric and is known as partial
discharge. If, as is the case with AC, the applied voltage
gradient across the device continues to rise, another partial
discharge cycle begins. The importance of this phenomenon
is that, if the discharge does not occur, the insulation system
retains its integrity. If the discharge begins, and is allowed
to continue, the action of the ions and electrons within the
defect will eventually degrade any organic insulation system
in which they occur. The measurement of partial discharge
is still useful in rating the devices and providing quality
control of the manufacturing process. Since the ISO120 and
ISO121 do not use organic insulation, partial discharge is
non-destructive.
The inception voltage for these voids tends to be constant, so
that the measurement of total charge being redistributed
within the dielectric is a very good indicator of the size of
the voids and their likelihood of becoming an incipient
failure. The bulk inception voltage, on the other hand, varies
with the insulation system, and the number of ionization
defects and directly establishes the absolute maximum volt-
age (transient) that can be applied across the test device
before destructive partial discharge can begin. Measuring
the bulk extinction voltage provides a lower, more conserva-
tive voltage from which to derive a safe continuous rating.
In production, measuring at a level somewhat below the
expected inception voltage and then derating by a factor
related to expectations about system transients is an
accepted practice.
Partial Discharge Testing
Not only does this test method provide far more qualitative
information about stress-withstand levels than did previous
stress tests, but it provides quantitative measurements from
which quality assurance and control measures can be based.
Tests similar to this test have been used by some manufac-
turers, such as those of high-voltage power distribution
equipment, for some time, but they employed a simple
measurement of RF noise to detect ionization. This method
was not quantitative with regard to energy of the discharge,
and was not sensitive enough for small components such as
isolation amplifiers. Now, however, manufacturers of HV
test equipment have developed means to quantify partial
discharge. VDE, the national standards group in Germany
and an acknowledged leader in high-voltage test standards,
has developed a standard test method to apply this powerful
technique. Use of partial discharge testing is an improved
method for measuring the integrity of an isolation barrier.
To accommodate poorly-defined transients, the part under
test is exposed to voltage that is 1.6 times the continuous-
rated voltage and must display ≤5pC partial discharge level
in a 100% production test.
11 ISO120/121
APPLICATIONS
The ISO120 and ISO121 isolation amplifiers are used in
three categories of applications:
1. Accurate isolation of signals from high voltage ground
potentials,
APPLICATION CIRCUITS
FIGURE 7. Eight-channel Isolated 0-20mA Loop Driver.
23
4322
21
24
912 11
10
PWS740-3
PWS740-1
T
O
T
O
6
4
0.3µF
4
5
6
3
2
1
6
31
4
0.3µF
0.3µF
PWS740-2
0.3µF
10µF
+15V +'E
20µH
1.0µF
–V
S1
To other
channels 20kΩ
20pF
1.0µF
–15V 1.0µF
R
L
≤ 600Ω
I
L
= 0-20mA
VN2222
1/4W
250Ω
0.1%
6.2V
400mW
–15V
+15V
20kΩ
ISO120
1.0µF
0-5V
System Uses:
1 - Oscillator/Driver
8 - Transformers
8 - Bridges
8 - ISO120s
8 - Transistors VN2222
8 - Zener Diodes, 6.2V, 400mW, 20%
Not all components shown.
8+V
IN
35
+15V
15
16
2. Accurate isolation of signals from severe ground noise
and,
3. Fault protection from high voltages in analog measure-
ments.
Figures 7 through 12 show a variety of Application Circuits.
12ISO120/121
FIGURE 9. Right-Leg Driven ECG Amplifier (with defibrillator protection and calibration).
2
1
+
–
23
21
24
2
3
10
11
22
0.001µF
+V
S1
8
6
10 9ISO
120
INA110
415 16
+V
S1
–V
SI
+V
S2
–V
S2
13
14
1
7
200kΩ
200kΩ
0.005 Power Resistor
120Vrms
100A
3θ Y-Connected Power Transformer
C
1
–V
S1
912
V
OUT
C
2
C
1
= 1000pF
C
2
= 1000pF
Differential input accurately senses power resistor voltage.
Two resistors protect INA110 from open power resistor.
High frequency spike reject filter has f
CO
= 400Hz.
FIGURE 8. Isolated Powerline Monitor.
15
4
7
5
6
14
+
–
37
40
38
39
1 2 21 22
18
19
20
23
24
4
3
PWS 726A
32
29
1 4
1
0.3
14 16
20kΩ
20pF
–V
S1
+V
S2
20µH
+V
S1
+V
S1
–V
S1
–V
S2
+V
S2
C
2
C
1
Calibration Signal
5.00V
0V
1/2W
300kΩ 50kΩ
1/2W
300kΩ 50kΩ
1/2W
300kΩ 180kΩ
Calibration
On
Left Arm
On
Right Arm
Calibration
Right Leg NE2H
NE2H
NE2H
(2)
500pF
500pF
200pF
7
4 3
2
–V
S1
+V
S1
–V
S1
+V
S1
–V
S1
+V
S1
+V
S1
12 0.0082
(1)
0.0082
–V
S1
9 8
10
11
13
5MΩ
1kΩ
1mV
Gain = 1000
17
ISO
121
INA102
OPA121
NOTE: (1) All capacitor values in µF unless otherwise
noted. Diodes are IN4148. (2) NE2H: Neon bulb, max
striking voltage 95V
AC
.
6
13 ISO120/121
FIGURE 10. Battery Monitor for a 600V Battery Power System.
FIGURE 11. Isolated 4-20mA Instrument Loop. (RTD shown).
21
22
23 315
11
4
e
50
=12V
9, 12 10
16
–V
24
5kΩ
+V
21
22
23 315
11
4
10kΩ
9, 12 10
16
–V
24
5kΩ
+V
10kΩ
e
49
=12V
e
2
=12V
e
1
=12V 10kΩ
10kΩ
Charge/Discharge Control
INA105
25kΩ
25kΩ
25kΩ
25kΩ
2
3
1
e
50
V = 2
+V –V
74
5
6
e
1
V = 2
Multiplexer
Control
Section
ISO
120
ISO
120
R
2
2.5kΩ
INA105 ISO
120
XTR101
R
S
150Ω
R
1
100Ω
3
5
6
47
8
10
11
0.01µF
RTD
(PT100)
1mA1mA
2mA
R
L
250Ω250Ω6
5
7
3
241
23
21
22
24 49
11 10
3
Sync
Gnd
–V
S
= –15V
on PWS740
V
OUT
+V
S
= 15V on PWS740
NOTE: Some ISO120 connections left out for clarity.
14ISO120/121
FIGURE 12. Synchronized-Multichannel Isolation System.
V
IN2
23
21
22
24
3
4
ISO
120
11
10 9
12 15
Ext Osc
0.3µF
PWS740-3
20pF
63 312
20kΩ
Gnd2
465 PWS740-2
–V
S2
+V
S2
V+V–
V
OUT2
16
V
IN1
23
21
22
24
3
4
ISO
120
11
10 9
12 15
Ext Osc
PWS740-3
20pF
63 312
20kΩ
Gnd1
465 PWS740-2
–V
S1
+V
S1
V+V–
V
OUT1
16
0.3µF
3
PWS740-1
56
4
8
V+
20µH
10µF 0.3µF 0.3µF
Up to 6
more
channels
14
14
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ISO120BG NRND CDIP SB JVA 16 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
ISO120G NRND CDIP SB JVA 16 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
ISO120SG NRND CDIP SB JVA 16 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
ISO120SGQ OBSOLETE CDIP SB JVA 16 TBD Call TI Call TI
ISO121BG ACTIVE CDIP SB JVD 16 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
ISO121G ACTIVE CDIP SB JVD 16 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 25-May-2009
Addendum-Page 1
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