ANALOG DEVICES FEATURES 18-Bit Resolution Low Nonlinearity Differential: +1/2LSB max Integral: + 1/2LSB max High Stability Differential TC: + 1Ippm/C max Integral TC: + 1/2ppm/C max Gain TC (with Reference): +4ppm/C max Fast Settling Full Scale: 40ps to +0.00019% LSB: Gus to +0.00019% Small Hermetic 32-Lead Triple DIP Package Low Cost APPLICATIONS Automatic Test Equipment Scientific Instrumentation Beam Positioners Digital Audio GENERAL DESCRIPTION The AD1139 is the first DAC offering 18-bit resolution (1 part in 262,144) and true 18-bit accuracy in a component size hybrid package. A proprietary bit switching technique provides high accuracy, speed and stability without compromising small size or low cost. The AD1139 is a complete DAC with precision internal reference, latched data inputs and a quality output voltage amplifier. The analog output voltage ranges are pin programmable to +5V, +10V, +5V and + 10V. Current output is also provided for use with external amplifiers. The internal precision 10V refer- ence has a low + 3ppm/C maximum temperature coefficient and is available for ratiometric applications. The AD1139K is a true 18-bit accurate DAC with + 1/2LSB maximum differential and integral nonlinearity. The differential and integral nonlinearity temperature stability is guaranteed at + Ippm/C maximum and + 1/2ppm/C maximum, respectively. The AD1139 settles to within + 1/2LSB at 18 bits (+ 0.00019%) in 40us for a full-scale step (10V). The glitch energy is a low 400mV x 500ns for a major carry, and wideband output noise is only 15pV. The AD1139 operates from + 15V dc and +5V dc power supplies. Digital inputs are 5V CMOS compatible with binary input coding for unipolar output ranges and offset binary coding for bipolar ranges. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implica tion or otherwise under any patent or patent rights of Analog Devices. High Accuracy, 18-Bit Digital-to-Analog Converter oe | , D139 PRODUCT HIGHLIGHTS 1. Eighteen-bit resolution with + 1/2LSB maximum differential and integral nonlinearity in a hermetic 32-lead triple DIP package. 2. Complete DAC with internal reference, stable low-noise output amplifier, latched DAC inputs, reference output and internal application resistors for programmable output voltage ranges. 3. Temperature compensated internal precision reference with +0.1% maximum initial accuracy and + 3ppm/C maximum tempco. 4. Four pin programmable output voltage ranges (+5V, + 10V, +5V, +10V) and current output available ( lmA, +0.5mA). 5. The 18-bit parallel input latch assists in microprocessor interface. 6. Accurate measurements of the DACs output are unusually simple since the AD1139 does not suffer from code dependent ground current errors. 7. True analog output remote sense capability. One Technology Way; P. O. Box $106; Norwood, MA 02062-9106 Tel: 617/329-4700 TWX: 710/394-6577 West Coast Atlantic 714/641-9391 215/643-7790 Central 214/231-5094SPECIFICATIONS typca o +25 an rtd suppies uss obervise specie OUTLINE DIMENSIONS Model AD1139J AD1139K RESOLUTION 18 Bits * Dimensions shown in inches and (mm). ACCURACY Differential Nonlinearity + 1LSB max + 1/2LSB max . (= +0,00038% max) (= +0,00019% max) orsoia.s1 SEATING PLANE Integral Nonlinearity + 1LSB max + V2LSB max $1903.84) 15.08) 0.015 10.38) (= +0.00038%max) (= +0.00019% max) f- 0.035 (0.89) Monotonicity (18 Bits) Guaranteed * n DOT INDICATES Initial Errors 1] @ 32 Unipolar Gain Error + 0.01% * Pn 1.POSTON Bipolar Gain Error +0.02% * Offset Error +0.01% * Bipolar Ofiset Error +0.01% * begst08ei STABILITY (ppm FSRPC) 1 Differential Nonlinearity + imax +0.5 typ, + 1 max Integral Nonlinearity? +0.5 max * ea Gain (Including Vrer) +4max * Offset 0.40 Unipolar Mode + Imax * (1.02) Bipolar Mode + 1 max * STABILITY (Long Term, ppm FSR?/1000 hour) Differential Nonlinearity* +0.5 * + Gein (Including Ver) * 1s * x |e "7 Bipolar Offset 2 a 0.095 (2.41) 1.079 (27.41) | Ref Output Voltage 15 * 0.105 (2.67) 1.101 (27.97) | WARMUP TIME (MINIMUM) 15 minutes * oassieen REFERENCE VOLTAGE (Vrer) oe Output Voltage (@ 5 mA max) 10V (+ 0.1% max) * " " 0.884 (22.48) Noise (BW = 0.1-10Hz) 20pV pk-pk 10,V pk-pk asieasz7 Noise (BW = 100kHz) 50p.V rms * Tempco 3ppm/C max * DYNAMIC PERFORMANCE Settling Time to 1/2LSB (@ 18 Bits) ee Voltage a Unipolar (10V Step) 40ns * ye Bipolar (20V Step) 60us * Unipolar (LSB Step) bys * ESD SENSITIVE DEVICE Bipolar (LSB Step) Sus * Slew Rate 2Vius * Current CAUTION: OBSERVE PROPER PLUG-IN POLARITY TO Full-Scale Step 10ps * PREVENT DAMAGE TO CONVERTER LSB Step Gps * Glitch Energy (Major Carry @ 20MHz Bandwidth 0-to-10V Range) 400mV (500ns Duration) * PIN DESIGNATIONS DIGITAL INPUTS (SV CMOS Compatible) yn soey * PIN} DESCRIPTION PIN | DESCRIPTION 23.5V * Unipolar Code Binary (BIN) : 1 | SIGNALGND 32 |GAINTRIM Bipolar Code Offset Binary (OBN) * 2 | BIPOLAROFFSET | 31 |REFOUT ANALOG OUTPUT 3 | lour 30 | 15V Current* imA, +0.5mA * 4 | AMPIN 29 | +15V Voltage (Pin Programmable) +5V, +10V, +5V,+10V | * 5 |20VSPAN 28 |+5V Noise (Includes Vaer) BW = 0.1-10Hz(uV pk-pk) 2xFSR 1x FSR 6 | 10V SPAN 27 | POWER GND BW = 100kHz(Unipotar) 15. rms * 7 | AMPOUT 26 |WR BW = 100kHz (Bipolar) 45yV rms * 8 | DB17 (MSB) 25 |DBO(LSB) VOLTAGE COMPLIANCE = 10mV * 9 | DB16 24 |DB1 Source Resistance 10 | 0B15 23 |DB2 Unipolar 3.3kQ * 11 | DB14 22 |DB3 Bipolar 2.85k0 12 | DB13 21 |DB4 Source Capacitance 10pF 13 |DB12 20 | DBS POWER SUPPLY REQUIREMENTS 14 |DB11 19 |DB6 +5Vde(+5%) 100p.A * + 15V de(+ 5%) +25mA, 30mA * 18 | DB10 18 |DB7 16 | DBS 17 |DB8 POWER SUPPLY REJECTION (+ 1SV dc) Gain +2.5ppm/% * Offset +0.3ppm/% * NOTES Reference Output +2.Sppm/% * *Specifications same as AD1139J. (+5Vdc) Mnitial E djustable to zero vi eee Figure 1). Diffe: <0) Nanii, ity +0.15ppm/% * 3FSR means Full Scale Range, ita %AQL, Level It ; TEMPERATURE RANGE Mer os bility toa l%AQL, sampling plan per Operating (Rated Performance) Oto + 70C * See Figure 7 for typical long-term linearity stability vs. temperature. Also, sce the Storage : -40Cto + 85C BURNIN section on page 6 for caution against preconditioning by the user. Figure 9 provides typical LSB and full-ecale settling time to within 1/2LSB PRICE at 12- to 18-bit resolutions. (1-9) $325 $450 Current Output Operation i d for input to th ing junction of an sxaplifier. (100 +) $195 $295 Specifications subject to change without aotice.INVERTER 10ka (x W2) (32) GAIN TRIM BIPOLAR (> OFFSET (31) REF OUT amp in(4 AMP OUT SIGNAL GND(1 OUTPUT @ AMPLIFIER -15V lour(3 our $ AD1139 (23) + 15V 2 10K: 10k22 (28) +5v 2ov span(5 b 5 POWER GND 10V SPAN(6 0817 (5 Lon peo sere 12-BIT 41s) ' 6-BIT 6-BIT CMOS ' 1 LATCHED| ot! 1 1 [baTcH DAC Input Vy pB12 +- 14) B14 26) WR AD1139 Functional Block Diagram ANALOG OUTPUT RANGE The AD1139 is pin programmable to provide a variety of analog outputs, either current or voltage. A unipolar output current of 0 to 1mA is available at Pin 3 and can be offset by 0.5mA (connect Pin 2 to Pin 3) for a biolar output of +0.5mA. Output voltage ranges (+5V, +10V, +5V and + 10V) are available at Pin 7 by connecting the current output (Pin 3) to the amplifier input (Pin 4) and the appropriate internal feedback resistors to the amplifier output (Pin 7) as shown in Figure 1. GAIN ADJ @ 20ki2 (20-TURN, 100ppm"C POTENTIOMETERS) 3.01k12 20ka2 +18V O= Vy + wessa , ie (Vz+6.2V 5 VOLTAGE 6 OUTPUT ? 1 POWER GROUND os17 (6 emos 2 (mss) I") wweuT a12 (43) +10V OPERATION NOTES ALL RESISTORS ARE METAL FILM RNGS OR EQUIVALENT. ALL CAPACITORS ARE POLARIZED TANTALUM. +S5VOPERATION* *ALL OTHER PIN CONNECTIONS ARE THE SAME AS SHOWN FOR UNIPOLAR OTO + 10VOPERATION. Figure 1. Output Voltage and Trim Configuration OFFSET & GAIN CALIBRATION Initial offset and gain errors can be adjusted to zero by poten- tiometers as shown in Figure 1. The offset adjust range is plus 0.03% to minus 0.02% of full scale range (wiper of potentiometer to REF OUT equals plus 0.03%). The gain adjust range is plus 0.06% to minus 0.08% of full scale range (wiper to REF OUT equals plus 0.06%). Measurement instruments used should be capable of resolving 1,V at plus full-scale for the chosen output range and within 1V of zero. Procedure: UNIPOLAR MODE 1. Apply a digital input of all Os. 2. Adjust the offset potentiometer until a 0.000000V output is obtained. 3. Apply a digital input of all 1s. 4. Adjust the gain potentiometer until plus full-scale output is obtained (see Table I for exact value). BIPOLAR MODE 1. Apply a digital input of 100..... 000. 2. Adjust the offset potentiometer until a 0.000000V output is obtained. 3. Apply a digital input of all ls. 4. Adjust the gain potentiometer until plus full-scale output is obtained (see Table I for exact value). Code 000.... 00 | Codelll... 11 Unipolar + 5V 0.000000V +4.999981V +10V_ | 0.000000V +9.999962V Code 100....00 | Codelll....11_ | Code000... .00 Bipolar +5V 0.000000V +4.999962V 5.000000V +10V_ | 0.000000V +9.999924V 10.000000V Table |. Full-Scale and Offset Calibration Voltages Symbol Parameter Requirement tps Data Setup Time 160ns min tox Data Hold Time 120ns min twr Write Pulse Width 200ns min Table Il. Timing Requirements TIMING DIAGRAM & LATCH CONTROL Timing requirements for the AD1139 are shown in Table II. The timing diagram is shown in Figure 2. The WRite line controls an 18-bit wide data input latch. This latch is transparent when the WRite line is LOW, allowing all bits to be accessed directly. When the WRite line is activated HIGH, the data present at the inputs is held in the latch and the appropriate analog voltage is seen at the output. 080-DB17 D4 DATA VALID x $4 ton aN |-__.__ Figure 2, AD1139 Timing DiagramGROUNDING & GUARDING The current from measurement ground (Pin 1) is small and independent of the digital input code to the DAC. This greatly simplifies making error free analog measurements. Connect this high quality ground to the systems or applications high quality ground. Connect the DACs power ground (Pin 27) to the system return, also connect the systems high quality ground to the system return. /t is most important that the measurement ground (Pin 1) and power ground (Pin 27) be connected externally for proper circuit operation. The current output pin (Iour, Pin 3) is sensitive to external noise sources, such as digital input lines. This pin and any components connected to this pin should be surrounded by a grounded guard as shown in Figure 3. mur ob > PINS EXTERNAL AMPLIFIER (UNIPOLAR RANGE) Figure 3. Guarding Recommendations REMOTE SENSE APPLICATION The AD1139s remote sense capability allows driving heavy loads or long cables without the usual, accompanying gain errors. By sensing at the load, as described in Figure 4, the load current will pass through the amplifiers output and the power ground, but not through the sense lines. The potential gain errors that would be induced by this load current are therefore minimized. The load should not exceed + 10mA or 2 nanofarads to insure proper operation of the AD1139s internal output amplifier. Croan + Comme Figure 4. Remote Sensing RATIOMETRIC DAC TESTING APPLICATION The AD1139s highly stable reference output can be conveniently used in the testing of other high resolution DACs. Figure 5 describes how the REF OUT (Pin 31) is used as the external reference input to a device-under-test. The gain of the device- under-test will now accurately track the AD1139s gain and eliminate reference contribution to gain error. When used as a reference DAC to test the integral and differential linearity of 14- and 16-bit DACs, the AD1139 provides a meas- urement capability with just 1/16LSB of uncertainty at 14 bits. Gain and offset errors of the device-under-test (D.U.T.) may be accounted for in software. Once zeroed, the integral linearity error can be measured as the difference between the reference DAC (AD1139) and the D.U.T. as seen at the digital voltmeter. The differential linearity error is then determined by incrementing or decrementing the D.U.T. digital input by 1LSB, and comparing the new output at the DVM with the previous output. The difference between these two measurements should be exactly one ideal LSB. The amount of disagreement from one ideal LSB is the differential linearity error. COMPUTER INTERFACE ma) Figure 5. Ratiometric DAC Testing IBM* PC INTERFACE Figure 6 illustrates a typical IBM personal computer interface which uses three 8-bit external latches and two decoder chips. The three HCT374 latches are connected to the data bus (DO through D7). The HCT138 decoder chip decodes the address bus and enables each latch, including the AD1139s internal DAC latch, to see the appropriate digital word. The HCT688 chip and the HCT 138 decoder define the I/O address space where the four latches will reside. In the Figure 6 example, they reside in the address space as shown in Table III. VO Address | SelectedLatch | Data Bits 380H Low Byte DBO-DB7 381H Mid Byte DB8-DB15 382H High Byte DB16, DB17 383H -AD1139Latch | DBO-DB17 Table lil. 18M interface Address Locations *IBM is a trademark of International Business Machines Corp.I* CONNECT TO THE PC'S +5V SUPPLY BUS PIN# 8 CONNECT TO THE AD1139'S +S5VSUPPLY' +5V +15V-15V +5V 0 0 2% ~~ P 07 (A2) D6 (A3) d DS (Aa) 9 D4 (As) ? D3 (A6) --@ p2 (A7) bo {A3) J wa (B13) 20 Low BYTE HCT374 I AD1139 ao (a3) ps | | | | | D1 {A8) -@ | | | | | | MID BYTE (10) 0815 (11) DB14 (12) 0813 DB12 HCT374 , = 0 as = 1 | +sv 1 HIGH 20 f Byte {2_ 5 Go 19 HCT374 412 la] = oa 1 ar (a30)}24 a 3 p12 = HCT138 |. 11 | 10 6 9 | +5V O- Pp - P | 8 4 = | +5V 8% 19 ) | ] 20 a3 (A28) 44 12 | 14 aa (A27) as (a26) 16 | 8 3 AB (A25) ; a7 (azay2ty HCTe88 ; | Ags (A23) = ; l 2) As (A22) 2 A1o (A21)- | 10 | 1 = AEN (A11) __J NOTE | THE PCS +5V dc LOGIC SUPPLIES SHOULD BE KEPT SEPARATE FROM THE AD1139 +5V de SUPPLY, TO KEEP LOGIC INDUCED NOISE TO A MINIMUM. Figure 6. AD1139 to IBM PC Compatible Interface LONG-TERM STABILITY VS. TEMPERATURE Adjusting the linearity of any DAC after it is installed in the application is often difficult or impossible. It is preferable to maintain some specified accuracy over the useful working life of the product (commonly 5 to 10 years). Stable linearity performance over time can, therefore, be a very important parameter for the DAC. Accelerated testing to determine the expected linearity stability over time can be accomplished by two different methods. Linearity is first measured at + 25C. The DAC is then operated at a fixed elevated temperature for an extended period of time. The DAC is then retested at + 25C, and the change in linearity error vs. time is calculated. The ARRHENIUS EQUATION (used in reliability calculations) can be used to determine what the acceleration factor is from + 25C to the elevated test tem- perature. Knowing the acceleration factor and the linearity error vs. time at the elevated temperature, one could calculate the expected long-term stability of linearity at nominal temperatures. A second test method determines how long it will take for the linearity to shift by a specific error band (we chose +2ppm for our example) at any specified temperature. The first step is to measure the linearity at a moderately elevated temperature (e.g., +85C) and then monitor how long it takes at this temperature to reach the error band limit. The second step is to perform the same test at a much higher elevated temperature (e.g., + 125C). The two resulting time vs. temperature points are then plotted on semilog paper. A line drawn through the two points allows extrapolation to the length of time expected to reach the error band (+2ppm) at other temperatures, including + 25C. -5-Figure 7 shows how long it would take for the AD 1139s linearity to drift + 2ppm (1/2LSB) at any operating temperature. The uppermost plot shows stability under storage conditions (no power), and the lower plot shows the AD1139s operating stability (under power). The operating vs. storage difference is due to the 10C temperature rise when the AD1139 is powered. 1M 300,000 (34 YEARS) 100K 87,600 (10 43,800 (S YEARS 8,760 (1 YEAR) STORAGE (NO 1K TIME - hours 720 (1 MONTH) 100 10 10 20 30 40 SO 60 70 80 90 100 110 120 130 TEMPERATURE - degrees EXPECTED TIME REQUIRED TO PRODUCE A + 2ppm LINEARITY SHIFT VS. TEST TEMPERATURE NOTE: MAX OPERATING TEMPERATURE !S + 70C Figure 7. Nonlinearity vs. Time/Temperature BURN-IN All AD1139s undergo a 168 hour, powered burn-in @125C, prior to laser trimming. This burn-in produces the optimum stability for the resistor network and eliminates infancy defects. As shown in Figure 7, exposure to elevated temperatures produces an acceleration of the normal aging process. Preconditioning/burn- in employed by the user will lead to premature linearity shifts outside of the initial guaranteed specifications. The ADI warranty will not cover DACs that exhibit this type of forced premature specification degradation. EXTERNAL AMPLIFIER FOR HIGH SPEED OR HIGH OUTPUT CURRENT The AD1139s internal output amplifier is optimized for very low noise, dc stable applications with moderate settling time. Applications requiring higher speed or more output current can use an external amplifier, such as shown in Figure 8. The AD711 settles to within 16 bits in only 6ys for a unipolar full scale step. Other amplifiers may be chosen for differing tradeoffs. The noise gain seen by the output amplifier, depends on the output voltage range selected (see Table IV). The amplifier selected must be stable at the noise gain corresponding to the output range. 10k2 Veer 2 x = = o.01pF torn | r0KR OO tv | 5 3 a~N 7 6 J HPS082-2811 4{AD711 Vour . > Shir y ye + 4 Vv 3.33k0 0 - 15v 1 O MEASUREMENT GROUND i L { 7 7 + aoe ( + 27 Figure 8. External Amplifier for High Speed Output Voltage Range | Noise Gain Oto +5V 2 Oto + 10V 3 +5V 4 +10V 7 Table lV. Noise Gain vs. Output Voltage Range SETTLING TIME The LSB step and full-scale step typical settling times, to within + 1/2LSB at 18 bits, are shown in the Specification Table. Figure 9 graphically presents the typical settling times to within + 1/2LSB at resolutions from 12 to 18 bits. ERROR ERROR BAND V/2LSB LSB STEPFOR FULL-SCALE MAJOR CARRY RANGE STEP ret oC +5 +5 * 12B 100ppm 13B 158 10ppm 16B 178 \ \. 18B +1010 +5 ERROR VS. FINAL VALUE > SETTLING TIME > NOTE LSB SETTLING TIMES SHOWN WILL ONLY BE ACHIEVED WITH CLAMPING DIODES FROM THE DACS AMP IN (PIN 4} TO GROUND PER FIGURE 1. Figure 9. Settling Time vs. Resolution