May 2001
Copyright © Alliance Semiconductor. All rights reserved.
®
AS6UA25616
2.3V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable
5/25/01; v.1.2 Alliance Semiconductor P. 1 of 9
‘Features
• AS6UA25616
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words x 16 bits
• 2.7V to 3.6V at 55 ns
• 2.3V to 2.7V at 70 ns
• Low power consumption: ACTIVE
- 114 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
• Low power consumption: STANDBY
- 72 µW max at 3.6V
-41
µW max at 2.7V
• 1.5V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
-48-ball FBGA
- 400-mil 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
256K × 16
Array
(4,194,304)
OE
CS
WE Column decoder
Row Decoder
A0
A1
A2
A3
A4
A6
A7
A8
V
CC
V
SS
A12
A5
A9
A10
A11
A14
A15
A16
A17
A13
Control circuit
I/O1–I/O8
I/O9–I/O16
UB
LB
I/O
buffer
Pin arrangement (top view)
48-CSP Ball-Grid-Array Package
123456
ALBOE A0 A1 A2 NC
BI/O9UBA3 A4 CS I/O1
C I/O10 I/O11 A5 A6 I/O2 I/O3
DV
SS I/O12 A17 A7 I/O4 VCC
EV
CC I/O13 NC A16 I/O5 VSS
F I/O15 I/O14 A14 A15 I/O6 I/O7
GI/O16NC A12A13WEI/O8
HNCA8A9A10A11NC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
A0
CS
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
44-pin 400-mil TSOP 2
21
22
A14
A13
UB
LB
I/O16
I/O15
2A3 3A2 4A1
1A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44 A6
A7
OE
A5
Selection guide
Product
VCC Range
Speed
(ns)
Power Dissipation
Min
(V)
Typ 2
(V)
Max
(V)
Operating (ICC)Standby (I
SB1)
Max (mA) Max (µA)
AS6UA25616 2.7 3.0 3.6 55 2 20
AS6UA25616 2.3 2.5 2.7 70 1 15
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AS6UA25616
Functional description
The AS6UA25616 is a low-power CMOS
4,194,304
-bit Static Random Access Memory (SRAM) device organized as 262,144 words x 16 bits.
It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55/70 ns are ideal for low-power applications. Active high and low chip enables (
CS
)
permit easy memory expansion with multiple-bank memory systems.
When
CS
is high, or UB and LB are high, the device enters standby mode: the AS6UA25616 is guaranteed not to exceed 72 µW power
consumption at 3.6V and 55 ns; 41µW at 2.7V and 70 ns. The device also returns data when VCC is reduced to 1.5V for even lower power
consumption.
A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CS
) low, and UB and/or LB low. Data on the input pins
I/O1–O16 is written on the rising edge of
WE
(write cycle 1) or
CS
(write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (
OE
), chip enable (
CS
), UB and LB low, with write enable (
WE
) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read.
LB
controls the lower bits, I/O1–I/O8, and
UB
controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.3V to 3.6V supply. Device is available in the JEDEC
standard 400-mm, TSOP 2, and 48-ball FBGA packages.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t care, L = Low, H = High.
Parameter Device Symbol Min Max Unit
Vol t age o n V CC relative to VSS VtIN –0.5 VCC + 0.5 V
Voltage on any I/O pin relative to GND VtI/O –0.5 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 oC
Temperature with VCC applied Tbias –55 +125 oC
DC output current (low) IOUT –20mA
CS WE OE LB UB
Supply
Current I/O1–I/O8 I/O9–I/O16 Mode
HXXXX
ISB High Z High Z Standby (ISB)
LXXHH
LHHXXI
CC High Z High Z Output disable (ICC)
LHL
LH
ICC
DOUT High Z
Read (ICC)HL High ZD
OUT
LL D
OUT DOUT
LLX
LH
ICC
DIN High Z
Write (ICC)HL High ZD
IN
LL D
IN DIN
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Recommended operating condition (over the operating range)
Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL)2
Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage
IOH = –1.5mA VCC = 2.7V 2.4
V
IOH = –0.5mA VCC = 2.3V 2.0
VOL Output LOW Voltage
IOL = 2.1mA VCC = 2.7V 0.4
V
IOL = 0.5mA VCC = 2.3V 0.4
VIH Input HIGH Voltage
VCC = 2.7V 2.2 VCC + 0.5
V
VCC = 2.3V 2.0 VCC + 0.3
VIL Input LOW Voltage
VCC = 2.7V –0.5 0.8
V
VCC = 2.3V –0.3 0.6
IIX Input Load Current GND < VIN < VCC –1 +1 µA
IOZ Output Load Current GND < VO < VCC; Outputs High Z –1 +1 µA
ICC
VCC Operating Supply
Current
CS = VIL, VIN = VIL
or VIH, IOUT = 0mA,
f = 0
VCC = 3.6V 2
mA
VCC = 2.7V 1
ICC1 @
1MHz
Average VCC Operating
Supply Current at 1 MHz
CS < 0.2V, VIN < 0.2V
or VIN > VCC – 0.2V,
f = 1 mS
VCC = 3.6V 8
mA
VCC = 2.7V 4
ICC2
Average VCC Operating
Supply Current
CS ≠ VIL, VIN = VIL or
VIH, f = fMax
VCC = 3.6V (55/70 ns) 40/30
mA
VCC = 2.7V (55/70) 30/25
ISB
CS Power Down Current;
TTL Inputs
CS > VIH or UB = LB
> VIH, other inputs =
VIL or VIH, f = 0
VCC = 3.6V 100 µA
ISB1
CS Power Down Current;
CMOS Inputs
CS > VCC – 0.2V or
UB = LB > VCC – 0.2V,
other inputs = 0V – VCC, f = fMax
VCC = 3.6V 20 µA
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CS, WE, OE, LB, UB VIN = 0V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF
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AS6UA25616
Read cycle (over the operating range)3,9
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CS, OE, UB, LB controlled)3,6,8,9
Parameter Symbol
–55 –70
Unit NotesMinMaxMinMax
Read cycle time tRC 55 – 70 – ns
Address access time tAA – 55 – 70 ns 3
Chip enable (CS) access time tACS – 55 – 70 ns 3
Output enable (OE) access
time tOE – 25 – 35 ns
Output hold from address
change tOH 10 – 10 – ns 5
CS low to output in low Z tCLZ 10 – 10 – ns 4, 5
CS high to output in high Z tCHZ 0 20 0 20 ns 4, 5
OE low to output in low Z tOLZ 5–5–ns 4, 5
UB/LB access time tBA – 55 – 70 ns
UB/LB low to low Z tBLZ 10 – 10 – ns 4, 5
UB/LB high to high Z tBHZ 0 20 0 20 ns 4, 5
OE high to output in high Z tOHZ 0 20 0 20 ns 4, 5
Power up time tPU 0–0–ns 4, 5
Power down time tPD – 55 – 70 ns 4, 5
Undefined/don’t careFalling inputRising input
t
OH
t
AA
t
RC
t
OH
D
OUT
Address
Data validPrevious data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACS
t
LZ
Address
OE
CS
LB, UB
D
OUT
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Write cycle (over the operating range)11
Write waveform 1 (WE controlled)10,11
Write waveform 2 (CS controlled)10,11
Parameter Symbol
–55 –70
Unit NotesMin Max Min Max
Write cycle time tWC 55 – 70 – ns
Chip enable to write end tCW 40 – 60 – ns 12
Address setup to write end tAW 40 – 60 – ns
Address setup time tAS 0–0–ns 12
Write pulse width tWP 35 – 55 – ns
Address hold from end of write tAH 0–0–ns
Data valid to write end tDW 25 – 30 – ns
Data hold time tDH 0–0–ns 4, 5
Write enable to output in high Z tWZ 0 20 0 20 ns 4, 5
Output active from write end tOW 5–5–ns 4, 5
UB/LB low to end of write tBW 35 – 55 – ns
Address
CS
LB, UB
WE
D
IN
D
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data undefined High Z
Data valid
Address
CS
LB, UB
WE
D
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
D
OUT
Data undefined
High Z High Z
t
AS
t
AW
Data valid
t
CLZ
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AS6UA25616
Data retention characteristics (over the operating range)13,5
Data retention waveform
AC test loads and waveforms
Notes
1During V
CC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions.
4t
CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6WE
is HIGH for read cycle.
7CS
and OE are LOW for read cycle.
8 Address valid prior to or coincident with CS transition LOW.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 1.5V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
Parameter Symbol Test conditions Min Max Unit
VCC for data retention VDR VCC = 1.5V
CS
≥ VCC – 0.1V or
UB = LB = > VCC – 0.1V
VIN ≥ VCC – 0.1V or
VIN ≤ 0.1V
1.5V - V
Data retention current ICCDR –8µA
Chip deselect to data retention time tCDR 0–ns
Operation recovery time tRtRC –ns
Parameters VCC = 2.7V VCC = 2.3V Unit
R1 1095 3800 Ohms
R2 1600 4000 Ohms
RTH 555 1600 Ohms
VTH 1.6 1.2V Volts
V
CC
CS
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
1.5V
V
IH
V
IH
V
DR
V
CC
R1
R2
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE (a)
V
CC
R1
R2
OUTPUT
5 pF ALL INPUT PULSES
(b)
10%
90%
10%
90%
GND
V
CC
Typ
< 5 ns
(c)
Thevenin equivalent:
OUTPUT
R
TH
V
TH
INCLUDING
JIG AND
SCOPE
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Typical DC and AC characteristics
Package diagrams and dimensions
Supply voltage (V)
1.7
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
Normalized supply current
Supply Voltage (V)
0.0
0.25
0.5
0.75
1.0
Normalized T
AA
Normalized access time
vs. supply voltagevs. supply voltage
Ambient temperature (°C)
–55 10525
0.5
1.0
0.0
1.5
2.0
2.5
Normalized I
SB2
Normalized standby current
vs. ambient temperature
V
CC
= V
CC
typ
Supply voltage (V)
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
SB
Normalized standby current
vs. supply voltage
I
SB2
Supply voltage (V)
0.10
0.50
1.0
1.5
Normalized I
CC
Normalized I
CC
vs. Cycle Time
2.2 2.7 3.2 3.7 1.7 2.2 2.7 3.2 3.7
T
A
= 25
°
C
3.0
–0.5
V
IN
= V
CC
typ
1 5 10 15
11.92.8 3.7
V
IN
= V
CC
typ
T
A
= 25
°
C
V
IN
= V
CC
typ
T
A
= 25
°
C
V
CC
= 3.6V
T
A
= 25
°
C
44-pin TSOP 2
Min
(mm)
Max
(mm)
A1.2
A10.05
A20.95 1.05
b 0.25 0.45
c 0.15 (typical)
d 20.85 21.05
e 10.06 10.26
He11.56 11.96
E 0.80 (typical)
l 0.40 0.60
d
H
e
1234567891011121314
44 43 42 41 40 39 38 37 36 35 34 33 32 31
15 16
30 29
17 18 19 20
28 27 26 25
c
l
A
1
A
2
E
44-pin TSOP 2
0–5°
21
24
22
23
e
A
b
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AS6UA25616
Minimum Typical Maximum
A–0.75–
B 6.90 7.00 7.10
B1 – 3.75 –
C 10.90 11.00 11.10
C1 – 5.25 –
D 0.30 0.35 0.40
E––1.20
E1 – 0.68 –
E2 0.22 0.25 0.27
Y––0.08
Notes
1. Bump counts: 48 (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
4. All tolerance are ±0.050 unless otherwise specified.
5. Typ: typical.
6. Y is coplanarity: 0.08 (max).
65432 1
48-ball FBGA
Bottom View Top View
A
B
C
D
E
F
G
H
Ball #A1 Ball #A1 Index
C1
A
A
B1 B
Elastomer
C
SRAM Die
Side View Detail View
Die
Die
A
E2
E
Y
0.3/Typ
E1
E
E2 D
AS6UA25616
®
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© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be
the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may
appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the
product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential
customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use
of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made
exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected
to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all
claims arising from such use.
Ordering codes
Part numbering system
Speed (ns) Ordering Code Package Type Operating Range
55/70 AS6UA25616-TC 44-pin TSOP 2 Commercial
AS6UA25616-BC 48-ball fine pitch BGA
55/70 AS6UA25616-TI 44-pin TSOP 2 Industrial
AS6UA25616-BI 48-ball fine pitch BGA
AS6UA 25616 T, B C, I
SRAM Intelliwatt™ prefix Device number
Package:
T: TSOP 2
B: CSP/BGA
Temperature range:
C: Commercial: 0° C to 70° C
IL Industrial: –40° C to 85° C
