Freescale Semiconductor, Inc. Data Sheet: Technical Data KL05P48M48SF1 Rev 4 03/2014 Kinetis KL05 32 KB Flash 48 MHz Cortex-M0+ Based Microcontroller Designed with efficiency in mind. Features a size efficient, small package, energy efficient ARM Cortex-M0+ 32-bit performance. Shares the comprehensive enablement and scalability of the Kinetis family. This product offers: * Run power consumption down to 45 A/MHz in very low power run mode * Static power consumption down to 2 A with full state retention and 4 s wakeup * Ultra-efficient Cortex-M0+ processor running up to 48MHz with industry leading throughput * Memory option is up to 32 KB Flash and 4 KB RAM * Energy-saving architecture is optimized for low power with 90 nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller Performance * 48 MHz ARM(R) Cortex(R)-M0+ core Memories and memory interfaces * Up to 32 KB program flash memory * Up to 4 KB SRAM MKL05ZxxVFK4 MKL05ZxxVLC4 MKL05ZxxVFM4 MKL05ZxxVLF4 24-pin QFN (FK) 32-pin QFN (FM) 4 x 4 x 1 Pitch 0.5 mm 5 x 5 x 1 Pitch 0.5 mm 32-pin LQFP (LC) 7 x 7 x 1.4 Pitch 0.8 mm 48-pin LQFP (LF) 7 x 7 x 1.4 Pitch 0.5 mm Human-machine interface * Low-power hardware touch sensor interface (TSI) * Up to 41 general-purpose input/output (GPIO) Communication interfaces * One 8-bit SPI module * One low power UART module * One I2C module System peripherals * Nine low-power modes to provide power optimization based on application requirements Analog Modules * COP Software watchdog * 12-bit SAR ADC * 4-channel DMA controller, supporting up to 63 request * 12-bit DAC sources * Analog comparator (CMP) containing a 6-bit DAC * Low-leakage wakeup unit and programmable reference input * SWD debug interface and Micro Trace Buffer * Bit Manipulation Engine Timers * Six channel Timer/PWM (TPM) Clocks * One 2-channel Timer/PWM module * 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator * Periodic interrupt timers * Multi-purpose clock source * 16-bit low-power timer (LPTMR) * 1 kHz LPO clock * Real time clock Operating Characteristics * Voltage range: 1.71 to 3.6 V * Flash write voltage range: 1.71 to 3.6 V * Temperature range (ambient): -40 to 105C Security and integrity modules * 80-bit unique identification number per chip Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) 2012-2014 Freescale Semiconductor, Inc. All rights reserved. Ordering Information Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MKL05Z8VFK4 8 1 22 MKL05Z16VFK4 16 2 22 MKL05Z32VFK4 32 4 22 MKL05Z8VLC4 8 1 28 MKL05Z16VLC4 16 2 28 MKL05Z32VLC4 32 4 28 MKL05Z8VFM4 8 1 28 MKL05Z16VFM4 16 2 28 MKL05Z32VFM4 32 4 28 MKL05Z16VLF4 16 2 41 MKL05Z32VLF4 32 4 41 Related Resources Type Description Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal connections. Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. Package drawing Package dimensions are provided in package drawings. 2 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Table of Contents 1 Ratings..................................................................................4 1.1 Thermal handling ratings...............................................4 1.2 Moisture handling ratings...............................................4 1.3 ESD handling ratings.....................................................4 1.4 Voltage and current operating ratings............................4 2 General.................................................................................5 2.1 AC electrical characteristics...........................................5 2.2 Nonswitching electrical specifications............................5 2.2.1 Voltage and current operating requirements......5 2.2.2 LVD and POR operating requirements..............6 2.2.3 Voltage and current operating behaviors...........7 2.2.4 Power mode transition operating behaviors.......8 2.2.5 Power consumption operating behaviors...........9 2.2.6 EMC performance..............................................15 2.2.7 Capacitance attributes.......................................16 2.3 Switching specifications.................................................16 2.3.1 Device clock specifications................................16 2.3.2 General switching specifications........................17 2.4 Thermal specifications...................................................17 2.4.1 Thermal operating requirements........................17 2.4.2 Thermal attributes..............................................17 3 Peripheral operating requirements and behaviors................18 3.1 Core modules................................................................18 3.1.1 SWD electricals .................................................18 3.2 System modules............................................................19 3.3 Clock modules...............................................................20 3.3.1 MCG specifications............................................20 3.3.2 Oscillator electrical specifications......................21 3.4 Memories and memory interfaces.................................23 3.4.1 Flash electrical specifications............................23 3.5 Security and integrity modules.......................................25 3.6 Analog............................................................................25 3.6.1 ADC electrical specifications..............................25 Kinetis KL05 32 KB Flash, Rev4 03/2014. 4 5 6 7 8 9 3.6.2 CMP and 6-bit DAC electrical specifications......28 3.6.3 12-bit DAC electrical characteristics..................30 3.7 Timers............................................................................33 3.8 Communication interfaces.............................................33 3.8.1 SPI switching specifications...............................33 3.8.2 Inter-Integrated Circuit Interface (I2C) timing.....38 3.8.3 UART.................................................................39 3.9 Human-machine interfaces (HMI)..................................39 3.9.1 TSI electrical specifications................................39 Dimensions...........................................................................40 4.1 Obtaining package dimensions......................................40 Pinout....................................................................................40 5.1 KL05 signal multiplexing and pin assignments..............40 5.2 KL05 pinouts..................................................................42 Ordering parts.......................................................................46 6.1 Determining valid orderable parts..................................46 Part identification...................................................................46 7.1 Description.....................................................................46 7.2 Format...........................................................................47 7.3 Fields.............................................................................47 7.4 Example.........................................................................47 Terminology and guidelines..................................................48 8.1 Definition: Operating requirement..................................48 8.2 Definition: Operating behavior.......................................48 8.3 Definition: Attribute........................................................48 8.4 Definition: Rating...........................................................49 8.5 Result of exceeding a rating..........................................49 8.6 Relationship between ratings and operating requirements..................................................................49 8.7 Guidelines for ratings and operating requirements........50 8.8 Definition: Typical value.................................................50 8.9 Typical value conditions.................................................51 Revision history.....................................................................52 3 Freescale Semiconductor, Inc. Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2. Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes -- 3 -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Table 3. ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105 C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage -0.3 3.8 V IDD Digital supply current -- 120 mA VIO IO pin input voltage -0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) -25 25 mA VDD - 0.3 VDD + 0.3 V ID VDDA Analog supply voltage 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. * CL=30 pF loads * Slew rate disabled * Normal drive strength 2.2 Nonswitching electrical specifications Kinetis KL05 32 KB Flash, Rev4 03/2014. 5 Freescale Semiconductor, Inc. General 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V -- VDD - VDDA VDD-to-VDDA differential voltage -0.1 0.1 V -- VSS - VSSA VSS-to-VSSA differential voltage -0.1 0.1 V -- VIH VIL Input high voltage -- * 2.7 V VDD 3.6 V 0.7 x VDD -- V * 1.7 V VDD 2.7 V 0.75 x VDD -- V Input low voltage -- * 2.7 V VDD 3.6 V -- 0.35 x VDD V * 1.7 V VDD 2.7 V -- 0.3 x VDD V 0.06 x VDD -- V -3 -- mA -- +3 VHYS Input hysteresis IICIO IO pin negative DC injection current--single pin -- 1 * VIN < VSS-0.3V (negative current injection) * VIN < VSS-0.3V (positive current injection) IICcont Notes Contiguous pin DC injection current --regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins * Negative current injection * Positive current injection -- -25 -- mA -- +25 VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 -- V -- 1. All IO pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VIO_MIN (=VSS-0.3V) and VIN is less than VIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VIO_MIN-VIN)/|IICIO|. The positive injection current limiting resistor is calculated as R=(VIN-VIO_MAX)/|IICIO|. Select the larger of these two calculated resistances. 2. Open drain outputs must be pulled to VDD. 2.2.2 LVD and POR operating requirements Table 6. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit Notes VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V -- VLVDH Falling low-voltage detect threshold -- high range (LVDV = 01) 2.48 2.56 2.64 V -- Low-voltage warning thresholds -- high range 1 Table continues on the next page... 6 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General Table 6. VDD supply LVD and POR operating requirements (continued) Symbol Min. Typ. Max. Unit VLVW1H Description * Level 1 falling (LVWV = 00) 2.62 2.70 2.78 V VLVW2H * Level 2 falling (LVWV = 01) 2.72 2.80 2.88 V VLVW3H * Level 3 falling (LVWV = 10) 2.82 2.90 2.98 V VLVW4H * Level 4 falling (LVWV = 11) 2.92 3.00 3.08 V -- 60 -- mV -- 1.54 1.60 1.66 V -- VHYSH Low-voltage inhibit reset/recover hysteresis -- high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) Notes Low-voltage warning thresholds -- low range VLVW1L * Level 1 falling (LVWV = 00) VLVW2L * Level 2 falling (LVWV = 01) VLVW3L * Level 3 falling (LVWV = 10) VLVW4L * Level 4 falling (LVWV = 11) VHYSL Low-voltage inhibit reset/recover hysteresis -- low range 1 1.74 1.80 1.86 V 1.84 1.90 1.96 V 1.94 2.00 2.06 V 2.04 2.10 2.16 V -- 40 -- mV -- VBG Bandgap voltage reference 0.97 1.00 1.03 V -- tLPO Internal low power oscillator period -- factory trimmed 900 1000 1100 s -- 1. Rising thresholds are falling threshold + hysteresis voltage 2.2.3 Voltage and current operating behaviors Table 7. Voltage and current operating behaviors Symbol VOH Description Min. Unit Output high voltage -- Normal drive pad (except RESET) * 2.7 V VDD 3.6 V, IOH = -5 mA * 1.71 V VDD 2.7 V, IOH = -1.5 mA VOH Max. 1, 2 VDD - 0.5 -- V VDD - 0.5 -- V Output high voltage -- High drive pad (except RESET_b) * 2.7 V VDD 3.6 V, IOH = -18 mA * 1.71 V VDD 2.7 V, IOH = -6 mA IOHT Output high current total for all ports VOL Output low voltage -- Normal drive pad Notes 1, 2 VDD - 0.5 -- V VDD - 0.5 -- V -- 100 mA 1 * 2.7 V VDD 3.6 V, IOL = 5 mA -- 0.5 V * 1.71 V VDD 2.7 V, IOL = 1.5 mA -- 0.5 V Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 7 Freescale Semiconductor, Inc. General Table 7. Voltage and current operating behaviors (continued) Symbol VOL Description Min. Max. Unit Notes Output low voltage -- High drive pad 1 * 2.7 V VDD 3.6 V, IOL = 18 mA -- * 1.71 V VDD 2.7 V, IOL = 6 mA 0.5 V -- 0.5 V Output low current total for all ports -- 100 mA IIN Input leakage current (per pin) for full temperature range -- 1 A 3 IIN Input leakage current (per pin) at 25 C -- 0.025 A 3 IIN Input leakage current (total all pins) for full temperature range -- 41 A 3 IOZ Hi-Z (off-state) leakage current (per pin) -- 1 A RPU Internal pullup resistors 20 50 k IOLT 4 1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS 2.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSxRUN recovery times in the following table assume this clock configuration: * CPU and system clocks = 48 MHz * Bus and flash clock = 24 MHz * FEI clock mode POR and VLLSxRUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz. Table 8. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. Min. Typ. Max. Unit -- -- 300 s -- 95 115 s * VLLS0 RUN 1 * VLLS1 RUN Table continues on the next page... 8 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General Table 8. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- 93 115 s -- 42 53 s -- 4 4.6 s -- 4 4.4 s -- 4 4.4 s * VLLS3 RUN * LLS RUN * VLPS RUN * STOP RUN 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9. Power consumption operating behaviors Symbol IDDA Description Analog supply current IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash Min. Typ. Max.1 Unit Notes -- -- See note mA 2 3 -- 4.0 4.3 mA * at 3.0 V IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code executing from flash 3 -- 4.9 5.3 mA * at 3.0 V IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code executing from flash * at 3.0 V * at 25 C 3, 4 mA -- 5.7 5.8 -- 6.0 6.2 * at 125 C IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled * at 3.0 V 3 -- 2.7 2.9 mA Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 9 Freescale Semiconductor, Inc. General Table 9. Power consumption operating behaviors (continued) Symbol Description Min. IDD_WAIT Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled * at 3.0 V IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus / flash disabled (flash doze enabled) * at 3.0 V IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code executing from flash * at 3.0 V IDD_VLPR IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code executing from flash * at 3.0 V Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code executing from flash * at 3.0 V IDD_VLPW Very low power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled * at 3.0 V IDD_STOP * at 50 C * at 70 C * at 85 C * at 105 C * at 50 C * at 70 C * at 85 C * at 105 C Unit Notes 3 -- 2.2 2.3 mA 3 -- 1.5 1.7 mA 5 -- 182 253 A 5 -- 213 284 A 4, 5 -- 243 313 A 5 -- 111 170 -- 257 277 -- 265 285 -- 278 303 -- 295 326 -- 353 412 -- 2.25 5.76 -- 4.08 8.27 -- 8.10 14.52 -- 14.18 23.78 -- 37.07 58.58 Very-low-power stop mode current * at 3.0 V * at 25 C IDD_LLS Max.1 Stop mode current * at 3.0 V * at 25 C IDD_VLPS Typ. A A A Low-leakage stop mode current * at 3.0 V Table continues on the next page... 10 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General Table 9. Power consumption operating behaviors (continued) Symbol Min. Typ. Max.1 Unit * at 25 C -- 1.72 2.01 A * at 50 C -- 2.52 3.18 * at 70 C -- 4.32 5.94 * at 85 C -- 7.18 10.00 * at 105 C -- 18.67 25.65 -- 1.16 1.36 -- 1.78 2.27 -- 3.23 4.38 -- 5.57 7.53 -- 14.80 19.74 -- 0.64 0.81 -- 1.14 1.50 -- 2.35 3.20 -- 4.37 5.80 -- 12.40 16.13 -- 0.38 0.54 -- 0.88 1.23 -- 2.10 2.95 -- 4.14 5.59 -- 12.00 15.73 Description IDD_VLLS3 Very-low-leakage stop mode 3 current * at 3.0 V * at 25 C * at 50 C * at 70 C * at 85 C * at 105 C IDD_VLLS1 Very-low-leakage stop mode 1 current * at 3.0 V * at 25C * at 50C * at 70C * at 85C * at 105C IDD_VLLS0 Very-low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0) * at 3.0 V * at 25 C * at 50 C * at 70 C * at 85 C Notes A A A * at 105 C IDD_VLLS0 Very-low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1) * at 3.0 V * at 25 C * at 50 C * at 70 C * at 85 C * at 105 C 6 -- 0.30 0.45 -- 0.79 1.12 -- 2.01 2.82 -- 4.05 5.45 -- 11.96 15.63 A 1. Data based on characterization results. Kinetis KL05 32 KB Flash, Rev4 03/2014. 11 Freescale Semiconductor, Inc. General 2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 3. MCG configured for FEI mode. 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. 6. No brownout Table 10. Low power mode peripheral adders -- typical value Symbol Description Temperature (C) Unit -40 25 50 70 85 105 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 A IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. 52 52 52 52 52 52 A IEREFSTEN4MHz External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 228 237 245 251 258 uA IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. * VLLS1 * VLLS3 * LLS * VLPS * STOP 440 490 540 560 570 580 440 490 540 560 570 580 490 490 540 560 570 680 510 560 560 560 610 680 510 560 560 560 610 680 nA ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 A IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 432 357 388 475 532 810 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. * MCGIRCLK (4 MHz internal reference clock) * OSCERCLK (4 MHz external crystal) 66 66 66 66 66 66 A 214 237 246 254 260 268 Table continues on the next page... 12 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General Table 10. Low power mode peripheral adders -- typical value (continued) Symbol ITPM Description TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. * MCGIRCLK (4 MHz internal reference clock) * OSCERCLK (4 MHz external crystal) Temperature (C) Unit -40 25 50 70 85 105 86 86 86 86 86 86 235 256 265 274 280 287 A IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. 45 45 45 45 45 45 A IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 A 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: * * * * MCG in FBE for run mode, and BLPE for VLPR mode No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFA Kinetis KL05 32 KB Flash, Rev4 03/2014. 13 Freescale Semiconductor, Inc. General Run Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 7.00E-03 6.00E-03 Current Consumption on VDD (A) 5.00E-03 4.00E-03 All Peripheral CLK Gates All Off All On 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 1 2 3 4 6 12 24 48 CLK Ratio Flash-Core Core Freq (MHz) Figure 2. Run mode supply current vs. core frequency 14 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General VLPR Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 350.00E-06 300.00E-06 Current Consumption on VDD (A) 250.00E-06 200.00E-06 All Peripheral CLK Gates All Off All On 150.00E-06 100.00E-06 50.00E-06 000.00E+00 '1-1 '1-2 1 '1-2 '1-4 2 4 CLK Ratio Flash-Core Core Freq (MHz) Figure 3. VLPR mode current vs. core frequency 2.2.6 EMC performance Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation play a significant role in EMC performance. The system designer must consult the following Freescale applications notes, available on freescale.com for advice and guidance specifically targeted at optimizing EMC performance. * AN2321: Designing for Board Level Electromagnetic Compatibility * AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers * AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers Kinetis KL05 32 KB Flash, Rev4 03/2014. 15 Freescale Semiconductor, Inc. General * AN2764: Improving the Transient Immunity Performance of MicrocontrollerBased Applications * AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems 2.2.7 Capacitance attributes Table 11. Capacitance attributes Symbol CIN Description Input capacitance Min. Max. Unit -- 7 pF Min. Max. Unit 2.3 Switching specifications 2.3.1 Device clock specifications Table 12. Device clock specifications Symbol Description Normal run mode fSYS System and core clock -- 48 MHz fBUS Bus clock -- 24 MHz fFLASH Flash clock -- 24 MHz fLPTMR LPTMR clock -- 24 MHz VLPR and VLPS modes1 fSYS System and core clock -- 4 MHz fBUS Bus clock -- 1 MHz Flash clock -- 1 MHz -- 24 MHz -- 16 MHz -- 16 MHz Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) -- 16 MHz TPM asynchronous clock -- 8 MHz UART0 asynchronous clock -- 8 MHz fFLASH clock2 fLPTMR LPTMR fERCLK External reference clock fLPTMR_ERCLK LPTMR external reference clock fosc_hi_2 fTPM fUART0 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. 16 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General 2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 13. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1 External RESET and NMI pin interrupt pulse width -- Asynchronous path 100 -- ns 2 GPIO pin interrupt pulse width -- Asynchronous path 16 -- ns 2 Port rise and fall time -- 36 ns 3 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 14. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature -40 125 C TA Ambient temperature -40 105 C 2.4.2 Thermal attributes Table 15. Thermal attributes Board type Symbol Single-layer (1S) RJA Four-layer (2s2p) RJA Description 48 LQFP 32 LQFP 32 QFN 24 QFN Thermal resistance, junction to ambient (natural convection) 82 88 97 Thermal resistance, junction to ambient (natural convection) 58 59 34 Unit Notes 110 C/W 1 42 C/W Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 17 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 15. Thermal attributes (continued) Board type Symbol Single-layer (1S) RJMA Four-layer (2s2p) Description 48 LQFP 32 LQFP 32 QFN 24 QFN Unit Notes Thermal resistance, junction to ambient (200 ft./min. air speed) 70 74 81 92 C/W RJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 52 52 28 36 C/W -- RJB Thermal resistance, junction to board 36 35 13 18 C/W 2 -- RJC Thermal resistance, junction to case 27 26 2.3 3.7 C/W 3 -- JT Thermal characterization parameter, junction to package top outside center (natural convection) 8 8 8 10 C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions--Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions--Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 SWD electricals Table 16. SWD full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V 0 25 MHz 1/J1 -- ns SWD_CLK frequency of operation * Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width Table continues on the next page... 18 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 16. SWD full voltage range electricals (continued) Symbol Description Min. Max. Unit 20 -- ns * Serial wire debug J4 SWD_CLK rise and fall times -- 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 -- ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 -- ns J11 SWD_CLK high to SWD_DIO data valid -- 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 -- ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 4. Serial wire clock input timing SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 5. Serial wire data timing Kinetis KL05 32 KB Flash, Rev4 03/2014. 19 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 17. MCG specifications Symbol Description Min. Typ. Max. Unit Notes fints_ft Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25 C -- 32.768 -- kHz fints_t Internal reference frequency (slow clock) -- user trimmed 31.25 -- 39.0625 kHz -- 0.3 0.6 %fdco 1 fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using C3[SCTRIM] and C4[SCFTRIM] fdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature -- +0.5/-0.7 3 %fdco 1, 2 fdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70 C -- 0.4 1.5 %fdco 1, 2 Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25 C -- 4 -- MHz fintf_ft Frequency deviation of internal reference clock (fast clock) over temperature and voltage -- factory trimmed at nominal VDD and 25 C -- +1/-2 3 %fintf_ft fintf_t Internal reference frequency (fast clock) -- user trimmed at nominal VDD and 25 C 3 -- 5 MHz fintf_ft floc_low Loss of external clock minimum frequency -- RANGE = 00 (3/5) x fints_t -- -- kHz floc_high Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 (16/5) x fints_t -- -- kHz 31.25 -- 39.0625 kHz 20 20.97 25 MHz 40 41.94 48 MHz -- 23.99 -- MHz -- 47.97 -- MHz 2 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS = 00) 3, 4 640 x ffll_ref Mid range (DRS = 01) 1280 x ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS = 00) 5, 6 732 x ffll_ref Mid range (DRS = 01) Table continues on the next page... 20 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 17. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes -- 180 -- ps 7 -- -- 1 ms 8 1464 x ffll_ref Jcyc_fll FLL period jitter * fVCO = 48 MHz tfll_acquire FLL target frequency acquisition time 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 Oscillator electrical specifications 3.3.2.1 Oscillator DC electrical specifications Table 18. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDOSC IDDOSC Supply current -- low-power mode (HGO=0) Notes 1 * 32 kHz -- 500 -- nA * 4 MHz -- 200 -- A * 8 MHz (RANGE=01) -- 300 -- A * 16 MHz -- 950 -- A * 24 MHz -- 1.2 -- mA * 32 MHz -- 1.5 -- mA Supply current -- high gain mode (HGO=1) 1 * 32 kHz -- 25 -- A * 4 MHz -- 400 -- A * 8 MHz (RANGE=01) -- 500 -- A * 16 MHz -- 2.5 -- mA -- 3 -- mA -- 4 -- mA Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 21 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 18. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Notes * 24 MHz * 32 MHz Cx EXTAL load capacitance -- -- -- 2, 3 Cy XTAL load capacitance -- -- -- 2, 3 RF Feedback resistor -- low-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- low-frequency, high-gain mode (HGO=1) -- 10 -- M Feedback resistor -- high-frequency, lowpower mode (HGO=0) -- -- -- M Feedback resistor -- high-frequency, high-gain mode (HGO=1) -- 1 -- M Series resistor -- low-frequency, low-power mode (HGO=0) -- -- -- k Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Series resistor -- high-frequency, low-power mode (HGO=0) -- -- -- k -- 0 -- k Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) -- VDD -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) -- VDD -- V RS 2, 4 Series resistor -- high-frequency, high-gain mode (HGO=1) 5 Vpp 1. VDD=3.3 V, Temperature =25 C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 22 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors 3.3.2.2 Symbol Oscillator frequency specifications Table 19. Oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal or resonator frequency -- lowfrequency mode (MCG_C2[RANGE]=00) 32 -- 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency -- high-frequency mode (low range) (MCG_C2[RANGE]=01) 3 -- 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 -- 32 MHz fec_extal Input clock frequency (external clock mode) -- -- 48 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) -- -- ms Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) -- -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) -- 0.6 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) -- 1 -- ms fosc_lo tcst Description Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 3.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Kinetis KL05 32 KB Flash, Rev4 03/2014. 23 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 Notes Longword Program high-voltage time -- 7.5 18 s thversscr Sector Erase high-voltage time -- 13 113 ms 1 thversall Erase All high-voltage time -- 52 452 ms 1 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications -- commands Table 21. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec1k tpgmchk Read 1s Section execution time (flash sector) -- -- 60 s 1 Program Check execution time -- -- 45 s 1 trdrsrc Read Resource execution time -- -- 30 s 1 tpgm4 Program Longword execution time -- 65 145 s tersscr Erase Flash Sector execution time -- 14 114 ms trd1all Read 1s All Blocks execution time -- -- 0.5 ms trdonce Read Once execution time -- -- 25 s Program Once execution time -- 65 -- s tersall Erase All Blocks execution time -- 61 500 ms 2 tvfykey Verify Backdoor Access Key execution time -- -- 30 s 1 tpgmonce 2 1 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 22. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 3.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation -- 2.5 6.0 mA Average current adder during high voltage flash erase operation -- 1.5 4.0 mA Reliability specifications Table 23. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash Table continues on the next page... 24 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 23. NVM reliability specifications (continued) Min. Typ.1 Max. Unit tnvmretp10k Data retention after up to 10 K cycles 5 50 -- years tnvmretp1k Data retention after up to 1 K cycles 20 100 -- years nnvmcycp Cycling endurance 10 K 50 K -- cycles Symbol Description Notes 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 C Tj 125 C. 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 3.6.1 ADC electrical specifications All ADC channels meet the 12-bit single-ended accuracy specifications. 3.6.1.1 12-bit ADC operating conditions Table 24. 12-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 -- 3.6 V VDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV 2 VSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V 3 VREFL ADC reference voltage low VSSA VSSA VSSA V 3 VADIN Input voltage VREFL -- VREFH V CADIN Input capacitance -- 4 5 pF RADIN Input series resistance -- 2 5 k * 8-bit / 10-bit / 12-bit modes Notes Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 25 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 24. 12-bit ADC operating conditions (continued) Symbol Description Conditions RAS Analog source resistance (external) 12-bit modes Min. Typ.1 Max. Unit Notes 4 fADCK < 4 MHz -- -- 5 k fADCK ADC conversion 12-bit mode clock frequency 1.0 -- 18.0 MHz Crate ADC conversion 12-bit modes rate No ADC hardware averaging 5 6 20.000 -- 818.330 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/ CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE VADIN CAS VAS RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 6. ADC input impedance equivalency diagram 26 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors 3.6.1.2 12-bit ADC electrical characteristics Table 25. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current ADC asynchronous clock source fADACK Conditions1 * ADLPC = 1, ADHSC = 0 * ADLPC = 1, ADHSC = 1 * ADLPC = 0, ADHSC = 0 Min. Typ.2 Max. Unit Notes 0.215 -- 1.7 mA 3 1.2 2.4 3.9 MHz 2.4 4.0 6.1 MHz tADACK = 1/ fADACK 3.0 5.2 7.3 MHz 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA5 * ADLPC = 0, ADHSC = 1 Sample Time TUE DNL INL EFS See Reference Manual chapter for sample times Total unadjusted error * 12-bit modes -- 4 6.8 * <12-bit modes -- 1.4 2.1 Differential nonlinearity * 12-bit modes -- 0.7 -1.1 to +1.9 * <12-bit modes -- 0.2 * 12-bit modes -- 1.0 * <12-bit modes -- 0.5 * 12-bit modes -- -4 -5.4 * <12-bit modes -- -1.4 -1.8 * 12-bit modes -- -- 0.5 Integral nonlinearity Full-scale error EQ Quantization error EIL Input leakage error -0.3 to 0.5 -2.7 to +1.9 -0.7 to +0.5 IIn x RAS LSB4 mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/C 6 Temp sensor voltage 25 C 706 716 726 mV 6 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. Kinetis KL05 32 KB Flash, Rev4 03/2014. 27 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. ADC conversion clock < 3 MHz Figure 7. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode 3.6.2 CMP and 6-bit DAC electrical specifications Table 26. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDHS Supply current, high-speed mode (EN = 1, PMODE = 1) -- -- 200 A IDDLS Supply current, low-speed mode (EN = 1, PMODE = 0) -- -- 20 A VAIN Analog input voltage VSS -- VDD V VAIO Analog input offset voltage -- -- 20 mV * CR0[HYSTCTR] = 00 -- 5 -- mV * CR0[HYSTCTR] = 01 -- 10 -- mV VH Analog comparator hysteresis1 Table continues on the next page... 28 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 26. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit * CR0[HYSTCTR] = 10 -- 20 -- mV * CR0[HYSTCTR] = 11 -- 30 -- mV VCMPOh Output high VDD - 0.5 -- -- V VCMPOl Output low -- -- 0.5 V tDHS Propagation delay, high-speed mode (EN = 1, PMODE = 1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN = 1, PMODE = 0) 80 250 600 ns Analog comparator initialization delay2 -- -- 40 s 6-bit DAC current adder (enabled) -- 7 -- A IDAC6b INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB3 DNL 6-bit DAC differential non-linearity -0.3 -- 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD - 0.7 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 CMP Hysteresis vs Vinn 90.00E-03 80.00E-03 70.00E-03 CMP Hysteresis (V) 60.00E-03 HYSTCTR Setting 50.00E-03 0 1 40.00E-03 2 3 30.00E-03 20.00E-03 10.00E-03 000.00E+00 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vinn (V) Figure 8. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Kinetis KL05 32 KB Flash, Rev4 03/2014. 29 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors CMP Hysteresis vs Vinn 180.00E-03 160.00E-03 140.00E-03 CMP Hysteresis (V) 120.00E-03 HYSTCTR Setting 100.00E-03 0 1 80.00E-03 2 3 60.00E-03 40.00E-03 20.00E-03 000.00E+00 0.1 0.4 0.7 1 -20.00E-03 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vinn (V) Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.6.3 12-bit DAC electrical characteristics 3.6.3.1 Symbol 12-bit DAC operating requirements Table 27. 12-bit DAC operating requirements Desciption Min. VDDA Supply voltage VDACR Reference voltage Max. Unit Notes 3.6 V 1.13 3.6 V 1 2 CL Output load capacitance -- 100 pF IL Output load current -- 1 mA 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. 3.6.3.2 Symbol 12-bit DAC operating behaviors Table 28. 12-bit DAC operating behaviors Description IDDA_DACL Supply current -- low-power mode Min. Typ. Max. Unit -- -- 250 A -- -- 900 A Notes P IDDA_DACH Supply current -- high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) -- low-power mode -- 100 200 s 1 tDACHP Full-scale settling time (0x080 to 0xF7F) -- high-power mode -- 15 30 s 1 Table continues on the next page... 30 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 28. 12-bit DAC operating behaviors (continued) Symbol Description tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode and high-speed mode Min. Typ. Max. Unit Notes -- 0.7 1 s 1 Vdacoutl DAC output voltage range low -- highspeed mode, no load, DAC set to 0x000 -- -- 100 mV Vdacouth DAC output voltage range high -- highspeed mode, no load, DAC set to 0xFFF VDACR -100 -- VDACR mV INL Integral non-linearity error -- high speed mode -- -- 8 LSB 2 DNL Differential non-linearity error -- VDACR > 2 V -- -- 1 LSB 3 DNL Differential non-linearity error -- VDACR = VREF_OUT -- -- 1 LSB 4 -- 0.4 0.8 %FSR 5 Gain error -- 0.1 0.6 %FSR 5 Power supply rejection ratio, VDDA 2.4 V 60 -- 90 dB TCO Temperature coefficient offset voltage -- 3.7 -- V/C TGE Temperature coefficient gain error -- 0.000421 -- %FSR/C Rop Output resistance (load = 3 k) -- -- 250 SR Slew rate -80h F7Fh 80h VOFFSET Offset error EG PSRR BW 1. 2. 3. 4. 5. 6. 6 V/s * High power (SPHP) 1.2 1.7 -- * Low power (SPLP) 0.05 0.12 -- 3dB bandwidth kHz * High power (SPHP) 550 -- -- * Low power (SPLP) 40 -- -- Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR - 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Kinetis KL05 32 KB Flash, Rev4 03/2014. 31 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 10. Typical INL error vs. digital code 32 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 -40 55 25 85 105 125 Temperature C Figure 11. Offset at half scale vs. temperature 3.7 Timers See General switching specifications. 3.8 Communication interfaces Kinetis KL05 32 KB Flash, Rev4 03/2014. 33 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.8.1 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 29. SPI master mode timing on slew rate disabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 Description Min. Max. Unit Note fperiph/2048 fperiph/2 Hz 1 2 x tperiph 2048 x tperiph ns 2 Enable lead time 1/2 -- tSPSCK -- Enable lag time 1/2 -- tSPSCK -- tperiph - 30 1024 x tperiph ns -- Data setup time (inputs) 16 -- ns -- tHI Data hold time (inputs) 0 -- ns -- 8 tv Data valid (after SPSCK edge) -- 10 ns -- 9 tHO Data hold time (outputs) 0 -- ns -- 10 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input 11 tRO Rise time output -- 25 ns -- tFO Fall time output Frequency of operation SPSCK period Clock (SPSCK) high or low time 1. For SPI0, fperiph is the bus clock (fBUS). 2. tperiph = 1/fperiph Table 30. SPI master mode timing on slew rate enabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 tHI Description Min. Max. Unit Note fperiph/2048 fperiph/2 Hz 1 2 x tperiph 2048 x tperiph ns 2 Enable lead time 1/2 -- tSPSCK -- Enable lag time 1/2 -- tSPSCK -- tperiph - 30 1024 x tperiph ns -- Data setup time (inputs) 96 -- ns -- Data hold time (inputs) 0 -- ns -- Frequency of operation SPSCK period Clock (SPSCK) high or low time Table continues on the next page... 34 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 30. SPI master mode timing on slew rate enabled pads (continued) Num. Symbol 8 tv 9 Description Min. Max. Unit Note Data valid (after SPSCK edge) -- 52 ns -- tHO Data hold time (outputs) 0 -- ns -- 10 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input 11 tRO Rise time output -- 36 ns -- tFO Fall time output 1. For SPI0, fperiph is the bus clock (fBUS). 2. tperiph = 1/fperiph SS 1 (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 11 10 11 4 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 10 5 7 MSB IN 2 BIT 6 . . . 1 LSB IN 8 MOSI (OUTPUT) MSB OUT 2 BIT 6 . . . 1 9 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 12. SPI master mode timing (CPHA = 0) Kinetis KL05 32 KB Flash, Rev4 03/2014. 35 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors SS 1 (OUTPUT) 2 3 10 11 4 10 11 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 5 6 MISO (INPUT) 7 MSB IN BIT 6 . . . 1 2 9 8 MOSI (OUTPUT) LSB IN PORT DATA MASTER MSB OUT 2 BIT 6 . . . 1 PORT DATA MASTER LSB OUT 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 13. SPI master mode timing (CPHA = 1) Table 31. SPI slave mode timing on slew rate disabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 Min. Max. Unit Note 0 fperiph/4 Hz 1 4 x tperiph -- ns 2 Enable lead time 1 -- tperiph -- Enable lag time 1 -- tperiph -- tperiph - 30 -- ns -- Data setup time (inputs) 2 -- ns -- tHI Data hold time (inputs) 7 -- ns -- 8 ta Slave access time -- tperiph ns 3 9 tdis Slave MISO disable time -- tperiph ns 4 10 tv Data valid (after SPSCK edge) -- 22 ns -- 11 tHO Data hold time (outputs) 0 -- ns -- 12 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input tRO Rise time output -- 25 ns -- tFO Fall time output 13 1. 2. 3. 4. Description Frequency of operation SPSCK period Clock (SPSCK) high or low time For SPI0, fperiph is the bus clock (fBUS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state 38 36 Freescale Semiconductor, Inc. <<CLASSIFICATION>> <<NDA MESSAGE>> Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 32. SPI slave mode timing on slew rate enabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead Enable lead time 4 tLag Enable lag time 5 tWSPSCK 6 tSU 7 Frequency of operation SPSCK period Min. Max. Unit Note 0 fperiph/4 Hz 1 4 x tperiph -- ns 2 1 -- tperiph -- 1 -- tperiph -- tperiph - 30 -- ns -- Data setup time (inputs) 2 -- ns -- tHI Data hold time (inputs) 7 -- ns -- 8 ta Slave access time -- tperiph ns 3 9 tdis Slave MISO disable time -- tperiph ns 4 10 tv Data valid (after SPSCK edge) -- 122 ns -- 11 tHO Data hold time (outputs) 0 -- ns -- 12 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input tRO Rise time output -- 36 ns -- tFO Fall time output 13 1. 2. 3. 4. Description Clock (SPSCK) high or low time For SPI0, fperiph is the bus clock (fBUS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state SS (INPUT) 2 12 13 12 13 4 SPSCK (CPOL=0) (INPUT) 5 3 SPSCK (CPOL=1) (INPUT) 5 9 8 MISO (OUTPUT) see note SLAVE MSB 6 MOSI (INPUT) 10 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined Figure 14. SPI slave mode timing (CPHA = 0) Kinetis KL05 32 KB Flash, Rev4 03/2014. 37 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 see note SLAVE 8 MSB OUT 6 MOSI (INPUT) 13 12 13 11 10 MISO (OUTPUT) 12 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . . 1 LSB IN 7 MSB IN NOTE: Not defined Figure 15. SPI slave mode timing (CPHA = 1) 3.8.2 Inter-Integrated Circuit Interface (I2C) timing Table 33. I2C timing Characteristic Symbol Standard Mode Fast Mode Minimum Maximum Minimum Maximum Unit SCL Clock Frequency fSCL 0 100 0 4001 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 -- 0.6 -- s LOW period of the SCL clock tLOW 4.7 -- 1.3 -- s HIGH period of the SCL clock tHIGH 4 -- 0.6 -- s Set-up time for a repeated START condition tSU; STA 4.7 -- 0.6 -- s Data hold time for I2C bus devices tHD; DAT 02 3.453 04 0.92 s tSU; DAT 2505 -- 1003, 6 Data set-up time -- ns 7 Rise time of SDA and SCL signals tr -- 1000 20 +0.1Cb 300 ns Fall time of SDA and SCL signals tf -- 300 20 +0.1Cb6 300 ns Set-up time for STOP condition tSU; STO 4 -- 0.6 -- s Bus free time between STOP and START condition tBUF 4.7 -- 1.3 -- s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD 2.7 V 38 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors 2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 7. Cb = total capacitance of the one bus line in pF. SDA tf tSU; DAT tr tLOW tf tHD; STA tSP tr tBUF SCL S tHD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 16. Timing definition for fast and standard mode devices on the I2C bus 3.8.3 UART See General switching specifications. 3.9 Human-machine interfaces (HMI) 3.9.1 TSI electrical specifications Table 34. TSI electrical specifications Symbol Description Min. Typ. Max. Unit TSI_RUNF Fixed power consumption in run mode -- 100 -- A TSI_RUNV Variable power consumption in run mode (depends on oscillator's current selection) 1.0 -- 128 A TSI_EN Power consumption in enable mode -- 100 -- A TSI_DIS Power consumption in disable mode -- 1.2 -- A TSI_TEN TSI analog enable time -- 66 -- s TSI_CREF TSI reference capacitor -- 1.0 -- pF TSI_DVOLT Voltage variation of VP & VM around nominal values 0.19 -- 1.03 V Kinetis KL05 32 KB Flash, Rev4 03/2014. 39 Freescale Semiconductor, Inc. Dimensions 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing's document number: If you want the drawing for this package Then use this document number 24-pin QFN 98ASA00474D 32-pin QFN 98ASA00473D 32-pin LQFP 98ASH70029A 48-pin LQFP 98ASH00962A 5 Pinout 5.1 KL05 signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 48 LQFP 32 QFN 32 LQFP 24 QFN Pin Name 1 1 1 1 PTB6/ IRQ_2/ LPTMR0_ALT3 DISABLED DISABLED PTB6/ IRQ_2/ LPTMR0_ALT3 TPM0_CH3 2 2 2 2 PTB7/ IRQ_3 DISABLED DISABLED PTB7/ IRQ_3 TPM0_CH2 3 -- -- -- PTA14 DISABLED DISABLED PTA14 TPM_CLKIN0 4 -- -- -- PTA15 DISABLED DISABLED PTA15 CLKOUT 5 3 3 3 VDD VDD VDD 6 4 4 3 VREFH VREFH VREFH 7 5 5 4 VREFL VREFL VREFL 8 6 6 4 VSS VSS VSS 40 Freescale Semiconductor, Inc. Default ALT0 ALT1 ALT2 ALT3 TPM_CLKIN1 Kinetis KL05 32 KB Flash, Rev4 03/2014. Pinout 48 LQFP 32 QFN 32 LQFP 24 QFN Pin Name Default 9 7 7 5 PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C0_SDA 10 8 8 6 PTA4/ LLWU_P0 XTAL0 XTAL0 PTA4/ LLWU_P0 I2C0_SDA I2C0_SCL 11 -- -- -- VSS VSS VSS 12 -- -- -- PTB18 DISABLED DISABLED PTB18 13 -- -- -- PTB19 DISABLED DISABLED PTB19 14 9 9 7 PTA5/ LLWU_P1/ RTC_CLK_IN DISABLED DISABLED PTA5/ LLWU_P1/ RTC_CLK_IN TPM0_CH5 SPI0_SS_b 15 10 10 8 PTA6/ LLWU_P2 DISABLED DISABLED PTA6/ LLWU_P2 TPM0_CH4 SPI0_MISO 16 11 11 -- PTB8 ADC0_SE11 ADC0_SE11 PTB8 TPM0_CH3 17 12 12 -- PTB9 ADC0_SE10 ADC0_SE10 PTB9 TPM0_CH2 18 -- -- -- PTA16/ IRQ_4 DISABLED DISABLED PTA16/ IRQ_4 19 -- -- -- PTA17/ IRQ_5 DISABLED DISABLED PTA17/ IRQ_5 20 -- -- -- PTA18/ IRQ_6 DISABLED DISABLED PTA18/ IRQ_6 21 13 13 9 PTB10 ADC0_SE9/ TSI0_IN7 ADC0_SE9/ TSI0_IN7 PTB10 TPM0_CH1 22 14 14 10 PTB11 ADC0_SE8/ TSI0_IN6 ADC0_SE8/ TSI0_IN6 PTB11 TPM0_CH0 23 15 15 11 PTA7/ IRQ_7/ LLWU_P3 ADC0_SE7/ TSI0_IN5 ADC0_SE7/ TSI0_IN5 PTA7/ IRQ_7/ LLWU_P3 SPI0_MISO SPI0_MOSI 24 16 16 12 PTB0/ IRQ_8/ LLWU_P4 ADC0_SE6/ TSI0_IN4 ADC0_SE6/ TSI0_IN4 PTB0/ IRQ_8/ LLWU_P4 EXTRG_IN SPI0_SCK 25 17 17 13 PTB1/ IRQ_9 ADC0_SE5/ TSI0_IN3/ DAC0_OUT/ CMP0_IN3 ADC0_SE5/ TSI0_IN3/ DAC0_OUT/ CMP0_IN3 PTB1/ IRQ_9 UART0_TX UART0_RX 26 18 18 14 PTB2/ IRQ_10/ LLWU_P5 ADC0_SE4/ TSI0_IN2 ADC0_SE4/ TSI0_IN2 PTB2/ IRQ_10/ LLWU_P5 UART0_RX UART0_TX 27 19 19 15 PTA8 ADC0_SE3/ TSI0_IN1 ADC0_SE3/ TSI0_IN1 PTA8 28 20 20 16 PTA9 ADC0_SE2/ TSI0_IN0 ADC0_SE2/ TSI0_IN0 PTA9 29 -- -- -- PTB20 DISABLED DISABLED PTB20 30 -- -- -- VSS VSS VSS 31 -- -- -- VDD VDD VDD 32 -- -- -- PTB14/ IRQ_11 DISABLED DISABLED Kinetis KL05 32 KB Flash, Rev4 03/2014. ALT0 ALT1 PTB14/ IRQ_11 ALT2 ALT3 EXTRG_IN 41 Freescale Semiconductor, Inc. Pinout 48 LQFP 32 QFN 32 LQFP 24 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 33 21 21 -- PTA10/ IRQ_12 DISABLED TSI0_IN11 PTA10/ IRQ_12 34 22 22 -- PTA11/ IRQ_13 DISABLED TSI0_IN10 PTA11/ IRQ_13 35 23 23 17 PTB3/ IRQ_14 DISABLED DISABLED PTB3/ IRQ_14 I2C0_SCL UART0_TX 36 24 24 18 PTB4/ IRQ_15/ LLWU_P6 DISABLED DISABLED PTB4/ IRQ_15/ LLWU_P6 I2C0_SDA UART0_RX 37 25 25 19 PTB5/ IRQ_16 NMI_b ADC0_SE1/ CMP0_IN1 PTB5/ IRQ_16 TPM1_CH1 NMI_b 38 26 26 20 PTA12/ IRQ_17/ LPTMR0_ALT2 ADC0_SE0/ CMP0_IN0 ADC0_SE0/ CMP0_IN0 PTA12/ IRQ_17/ LPTMR0_ALT2 TPM1_CH0 TPM_CLKIN0 39 27 27 -- PTA13 TSI0_IN9 TSI0_IN9 PTA13 40 28 28 -- PTB12 TSI0_IN8 TSI0_IN8 PTB12 41 -- -- -- PTA19 DISABLED DISABLED PTA19 42 -- -- -- PTB15 DISABLED DISABLED PTB15 SPI0_MOSI SPI0_MISO 43 -- -- -- PTB16 DISABLED DISABLED PTB16 SPI0_MISO SPI0_MOSI 44 -- -- -- PTB17 DISABLED DISABLED PTB17 TPM_CLKIN1 SPI0_SCK 45 29 29 21 PTB13 ADC0_SE13 ADC0_SE13 PTB13 TPM1_CH1 RTC_CLKOUT 46 30 30 22 PTA0/ IRQ_0/ LLWU_P7 SWD_CLK ADC0_SE12/ CMP0_IN2 PTA0/ IRQ_0/ LLWU_P7 TPM1_CH0 SWD_CLK 47 31 31 23 PTA1/ IRQ_1/ LPTMR0_ALT1 RESET_b DISABLED PTA1/ IRQ_1/ LPTMR0_ALT1 TPM_CLKIN0 RESET_b 48 32 32 24 PTA2 SWD_DIO DISABLED PTA2 CMP0_OUT SWD_DIO SPI0_SS_b 5.2 KL05 pinouts The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see KL05 signal multiplexing and pin assignments. 42 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTB17 PTB16 PTB15 PTA19 PTB12 PTA13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 48 47 46 45 44 43 42 41 40 39 38 37 Pinout VREFL 7 30 VSS VSS 8 29 PTB20 PTA3 9 28 PTA9 PTA4/LLWU_P0 10 27 PTA8 VSS 11 26 PTB2/IRQ_10/LLWU_P5 PTB18 12 25 PTB1/IRQ_9 24 VDD PTB0/IRQ_8/LLWU_P4 31 23 6 PTA7/IRQ_7/LLWU_P3 VREFH 22 PTB14/IRQ_11 PTB11 32 21 5 PTB10 VDD 20 PTA10/IRQ_12 PTA18/IRQ_6 33 19 4 PTA17/IRQ_5 PTA15 18 PTA11/IRQ_13 PTA16/IRQ_4 34 17 3 PTB9 PTA14 16 PTB3/IRQ_14 PTB8 35 15 2 PTA6/LLWU_P2 PTB7/IRQ_3 14 PTB4/IRQ_15/LLWU_P6 PTA5/LLWU_P1/RTC_CLK_IN 36 13 1 PTB19 PTB6/IRQ_2/LPTMR0_ALT3 Figure 17. KL05 48-pin LQFP pinout diagram Kinetis KL05 32 KB Flash, Rev4 03/2014. 43 Freescale Semiconductor, Inc. PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTB12 PTA13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 32 31 30 29 28 27 26 25 Pinout 21 PTA10/IRQ_12 VREFL 5 20 PTA9 VSS 6 19 PTA8 PTA3 7 18 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 8 17 PTB1/IRQ_9 PTA6/LLWU_P2 PTA5/LLWU_P1/RTC_CLK_IN 16 4 PTB0/IRQ_8/LLWU_P4 VREFH 15 PTA11/IRQ_13 PTA7/IRQ_7/LLWU_P3 22 14 3 PTB11 VDD 13 PTB3/IRQ_14 PTB10 23 12 2 PTB9 PTB7/IRQ_3 11 PTB4/IRQ_15/LLWU_P6 PTB8 24 10 1 9 PTB6/IRQ_2/LPTMR0_ALT3 Figure 18. KL05 32-pin LQFP pinout diagram 44 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTB12 PTA13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 32 31 30 29 28 27 26 25 Pinout 21 PTA10/IRQ_12 VREFL 5 20 PTA9 VSS 6 19 PTA8 PTA3 7 18 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 8 17 PTB1/IRQ_9 PTA6/LLWU_P2 PTA5/LLWU_P1/RTC_CLK_IN 16 4 PTB0/IRQ_8/LLWU_P4 VREFH 15 PTA11/IRQ_13 PTA7/IRQ_7/LLWU_P3 22 14 3 PTB11 VDD 13 PTB3/IRQ_14 PTB10 23 12 2 PTB9 PTB7/IRQ_3 11 PTB4/IRQ_15/LLWU_P6 PTB8 24 10 1 9 PTB6/IRQ_2/LPTMR0_ALT3 Figure 19. KL05 32-pin QFN pinout diagram Kinetis KL05 32 KB Flash, Rev4 03/2014. 45 Freescale Semiconductor, Inc. PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 24 23 22 21 20 19 Ordering parts 3 16 PTA9 VREFL VSS 4 15 PTA8 PTA3 5 14 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 6 13 PTB1/IRQ_9 PTB10 PTA6/LLWU_P2 PTA5/LLWU_P1/RTC_CLK_IN 12 VDD VREFH PTB0/IRQ_8/LLWU_P4 PTB3/IRQ_14 11 17 PTA7/IRQ_7/LLWU_P3 2 10 PTB7/IRQ_3 9 PTB4/IRQ_15/LLWU_P6 PTB11 18 8 1 7 PTB6/IRQ_2/LPTMR0_ALT3 Figure 20. KL05 24-pin QFN pinout diagram 6 Ordering parts 6.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PKL05 and MKL05 7 Part identification 46 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q KL## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Table 35. Part number fields descriptions Field Description Values Q Qualification status * M = Fully qualified, general market flow * P = Prequalification KL## Kinetis family * KL05 A Key attribute * Z = Cortex-M0+ FFF Program flash memory size * 8 = 8 KB * 16 = 16 KB * 32 = 32 KB R Silicon revision * (Blank) = Main * A = Revision after main T Temperature range (C) * V = -40 to 105 PP Package identifier * * * * CC Maximum CPU frequency (MHz) * 4 = 48 MHz N Packaging type * R = Tape and reel * (Blank) = Trays FK = 24 QFN (4 mm x 4 mm) LC = 32 LQFP (7 mm x 7 mm) FM = 32 QFN (5 mm x 5 mm) LF = 48 LQFP (7 mm x 7 mm) 7.4 Example This is an example part number: Kinetis KL05 32 KB Flash, Rev4 03/2014. 47 Freescale Semiconductor, Inc. Terminology and guidelines MKL05Z8VLC4 8 Terminology and guidelines 8.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 8.2 Definition: Operating behavior Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 8.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 Example This is an example of an attribute: 48 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Terminology and guidelines Symbol CIN_D Description Input capacitance: digital pins Min. -- Max. 7 Unit pF 8.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. 8.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. -0.3 Max. 1.2 Unit V 8.5 Result of exceeding a rating Failures in time (ppm) 40 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic Kinetis KL05 32 KB Flash, Rev4 03/2014. 49 Freescale Semiconductor, Inc. Terminology and guidelines 8.6 Relationship between ratings and operating requirements O ra pe g tin g tin ( nt me ire ) n. mi ra g tin era Op ) in. (m u req ax g tin era Op (m nt me ire u req .) x.) ma ing t era Op ( ing rat Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure - Operating (power on) nd Ha g lin ng i rat ) in. (m ng ati gr .) ax (m lin nd Ha Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure - Handling (power off) 8.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 50 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Terminology and guidelines 8.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. Max. 70 130 Unit A 8.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (A) 3500 150 C 3000 105 C 2500 25 C 2000 -40 C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 8.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Kinetis KL05 32 KB Flash, Rev4 03/2014. 51 Freescale Semiconductor, Inc. Revision history Table 36. Typical value conditions Symbol Description Value Unit TA Ambient temperature 25 C VDD 3.3 V supply voltage 3.3 V 9 Revision history The following table provides a revision history for this document. Table 37. Revision history Rev. No. Date 2 9/2012 Initial public release. 3 11/2012 Completed all the TBDs. 4 3/2014 52 Freescale Semiconductor, Inc. Substantial Changes * * * * * * * * * * * Updated the front page and restructured the chapters Added a note to the ILAT in the ESD handling ratings Updated Voltage and current operating ratings Added VODPU in the Voltage and current operating requirements Updated Voltage and current operating behaviors Updated Power mode transition operating behaviors Updated Power consumption operating behaviors Updated Capacitance attributes Updated footnote in the Device clock specifications Add thversall in the Flash timing specifications -- commands Updated Temp sensor slope and voltage and added a note to them in the 12-bit ADC electrical characteristics * Removed TA in the 12-bit DAC operating requirements * Added Inter-Integrated Circuit Interface (I2C) timing Kinetis KL05 32 KB Flash, Rev4 03/2014. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, the Freescale logo, Energy Efficient Solutions logo, and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex-M0+ are the registered trademarks of ARM Limited. (c) 2012-2014 Freescale Semiconductor, Inc. Document Number KL05P48M48SF1 Revision 4 03/2014