Kinetis KL05 32 KB Flash
48 MHz Cortex-M0+ Based Microcontroller
Designed with efficiency in mind. Features a size efficient, small
package, energy efficient ARM Cortex-M0+ 32-bit performance.
Shares the comprehensive enablement and scalability of the
Kinetis family.
This product offers:
• Run power consumption down to 45 μA/MHz in very low
power run mode
• Static power consumption down to 2 μA with full state
retention and 4 μs wakeup
• Ultra-efficient Cortex-M0+ processor running up to 48MHz
with industry leading throughput
• Memory option is up to 32 KB Flash and 4 KB RAM
• Energy-saving architecture is optimized for low power with
90 nm TFS technology, clock and power gating techniques,
and zero wait state flash memory controller
Performance
• 48 MHz ARM® Cortex®-M0+ core
Memories and memory interfaces
• Up to 32 KB program flash memory
• Up to 4 KB SRAM
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• COP Software watchdog
• 4-channel DMA controller, supporting up to 63 request
sources
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
Clocks
• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
• Multi-purpose clock source
• 1 kHz LPO clock
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• Up to 41 general-purpose input/output (GPIO)
Communication interfaces
• One 8-bit SPI module
• One low power UART module
• One I2C module
Analog Modules
• 12-bit SAR ADC
• 12-bit DAC
• Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
Timers
• Six channel Timer/PWM (TPM)
• One 2-channel Timer/PWM module
• Periodic interrupt timers
• 16-bit low-power timer (LPTMR)
• Real time clock
Security and integrity modules
• 80-bit unique identification number per chip
MKL05ZxxVFK4
MKL05ZxxVLC4
MKL05ZxxVFM4
MKL05ZxxVLF4
24-pin QFN (FK)
4 x 4 x 1 Pitch 0.5 mm
32-pin QFN (FM)
5 x 5 x 1 Pitch 0.5 mm
32-pin LQFP (LC)
7 x 7 x 1.4 Pitch 0.8
mm
48-pin LQFP (LF)
7 x 7 x 1.4 Pitch 0.5
mm
Freescale Semiconductor, Inc. KL05P48M48SF1
Data Sheet: Technical Data Rev 4 03/2014
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2012–2014 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information
Part Number Memory Maximum number of I\O's
Flash (KB) SRAM (KB)
MKL05Z8VFK4 8 1 22
MKL05Z16VFK4 16 2 22
MKL05Z32VFK4 32 4 22
MKL05Z8VLC4 8 1 28
MKL05Z16VLC4 16 2 28
MKL05Z32VLC4 32 4 28
MKL05Z8VFM4 8 1 28
MKL05Z16VFM4 16 2 28
MKL05Z32VFM4 32 4 28
MKL05Z16VLF4 16 2 41
MKL05Z32VLF4 32 4 41
Related Resources
Type Description
Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and
a dynamic product selector.
Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a
device for design suitability.
Reference Manual The Reference Manual contains a comprehensive description of the structure and function
(operation) of a device.
Data Sheet The Data Sheet includes electrical characteristics and signal connections.
Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask
set.
Package drawing Package dimensions are provided in package drawings.
2Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings..................................................................................4
1.1 Thermal handling ratings...............................................4
1.2 Moisture handling ratings...............................................4
1.3 ESD handling ratings.....................................................4
1.4 Voltage and current operating ratings............................4
2General.................................................................................5
2.1 AC electrical characteristics...........................................5
2.2 Nonswitching electrical specifications............................5
2.2.1 Voltage and current operating requirements......5
2.2.2 LVD and POR operating requirements..............6
2.2.3 Voltage and current operating behaviors...........7
2.2.4 Power mode transition operating behaviors.......8
2.2.5 Power consumption operating behaviors...........9
2.2.6 EMC performance..............................................15
2.2.7 Capacitance attributes.......................................16
2.3 Switching specifications.................................................16
2.3.1 Device clock specifications................................16
2.3.2 General switching specifications........................17
2.4 Thermal specifications...................................................17
2.4.1 Thermal operating requirements........................17
2.4.2 Thermal attributes..............................................17
3 Peripheral operating requirements and behaviors................18
3.1 Core modules................................................................18
3.1.1 SWD electricals .................................................18
3.2 System modules............................................................19
3.3 Clock modules...............................................................20
3.3.1 MCG specifications............................................20
3.3.2 Oscillator electrical specifications......................21
3.4 Memories and memory interfaces.................................23
3.4.1 Flash electrical specifications............................23
3.5 Security and integrity modules.......................................25
3.6 Analog............................................................................25
3.6.1 ADC electrical specifications..............................25
3.6.2 CMP and 6-bit DAC electrical specifications......28
3.6.3 12-bit DAC electrical characteristics..................30
3.7 Timers............................................................................33
3.8 Communication interfaces.............................................33
3.8.1 SPI switching specifications...............................33
3.8.2 Inter-Integrated Circuit Interface (I2C) timing.....38
3.8.3 UART.................................................................39
3.9 Human-machine interfaces (HMI)..................................39
3.9.1 TSI electrical specifications................................39
4 Dimensions...........................................................................40
4.1 Obtaining package dimensions......................................40
5 Pinout....................................................................................40
5.1 KL05 signal multiplexing and pin assignments..............40
5.2 KL05 pinouts..................................................................42
6 Ordering parts.......................................................................46
6.1 Determining valid orderable parts..................................46
7 Part identification...................................................................46
7.1 Description.....................................................................46
7.2 Format...........................................................................47
7.3 Fields.............................................................................47
7.4 Example.........................................................................47
8 Terminology and guidelines..................................................48
8.1 Definition: Operating requirement..................................48
8.2 Definition: Operating behavior.......................................48
8.3 Definition: Attribute........................................................48
8.4 Definition: Rating...........................................................49
8.5 Result of exceeding a rating..........................................49
8.6 Relationship between ratings and operating
requirements..................................................................49
8.7 Guidelines for ratings and operating requirements........50
8.8 Definition: Typical value.................................................50
8.9 Typical value conditions.................................................51
9 Revision history.....................................................................52
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Freescale Semiconductor, Inc.
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
–500 +500 V 2
ILAT Latch-up current at ambient temperature of 105 °C –100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Ratings
4Kinetis KL05 32 KB Flash, Rev4 03/2014.
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1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 120 mA
VIO IO pin input voltage –0.3 VDD + 0.3 V
IDInstantaneous maximum current single pin limit (applies to
all port pins)
–25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
General
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2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V —
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V —
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V —
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
—
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
—
VHYS Input hysteresis 0.06 × VDD — V —
IICIO IO pin negative DC injection current—single pin
• VIN < VSS–0.3V (negative current injection)
• VIN < VSS–0.3V (positive current injection)
–3
—
—
+3
mA
1
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
–25
—
—
+25
mA
—
VODPU Open drain pullup voltage level VDD VDD V2
VRAM VDD voltage required to retain RAM 1.2 — V —
1. All IO pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VIO_MIN
(=VSS-0.3V) and VIN is less than VIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VIO_MIN-VIN)/|IICIO|. The positive injection current limiting resistor is
calculated as R=(VIN-VIO_MAX)/|IICIO|. Select the larger of these two calculated resistances.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V —
VLVDH Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48 2.56 2.64 V —
Low-voltage warning thresholds — high range 1
Table continues on the next page...
General
6Kinetis KL05 32 KB Flash, Rev4 03/2014.
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Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVW1H
VLVW2H
VLVW3H
VLVW4H
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±60 — mV —
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V —
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±40 — mV —
VBG Bandgap voltage reference 0.97 1.00 1.03 V —
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs —
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — Normal drive pad (except
RESET)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
1, 2
VOH Output high voltage — High drive pad (except
RESET_b)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
1, 2
IOHT Output high current total for all ports — 100 mA
VOL Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
—
0.5
0.5
V
V
1
Table continues on the next page...
General
Kinetis KL05 32 KB Flash, Rev4 03/2014. 7
Freescale Semiconductor, Inc.
Table 7. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
VOL Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
—
—
0.5
0.5
V
V
1
IOLT Output low current total for all ports — 100 mA
IIN Input leakage current (per pin) for full temperature
range
— 1 μA3
IIN Input leakage current (per pin) at 25 °C — 0.025 μA3
IIN Input leakage current (total all pins) for full
temperature range
— 41 μA3
IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA
RPU Internal pullup resistors 20 50 kΩ4
1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit
tPOR After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
— — 300 μs1
• VLLS0 → RUN
—
95
115
μs
• VLLS1 → RUN
Table continues on the next page...
General
8Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table 8. Power mode transition operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit
— 93 115 μs
• VLLS3 → RUN
—
42
53
μs
• LLS → RUN
—
4
4.6
μs
• VLPS → RUN
—
4
4.4
μs
• STOP → RUN
—
4
4.4
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 9. Power consumption operating behaviors
Symbol Description Min. Typ. Max.1Unit Notes
IDDA Analog supply current — — See note mA 2
IDD_RUNCO Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus clock disabled,
code of while(1) loop executing from flash
• at 3.0 V
— 4.0 4.3 mA
3
IDD_RUN Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks disabled, code
executing from flash
• at 3.0 V
— 4.9 5.3 mA
3
IDD_RUN Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks enabled, code
executing from flash
• at 3.0 V
• at 25 °C
• at 125 °C
—
—
5.7
6.0
5.8
6.2
mA
3, 4
IDD_WAIT Wait mode current - core disabled / 48 MHz
system / 24 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled
• at 3.0 V
— 2.7 2.9 mA
3
Table continues on the next page...
General
Kinetis KL05 32 KB Flash, Rev4 03/2014. 9
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Table 9. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
IDD_WAIT Wait mode current - core disabled / 24 MHz
system / 24 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled
• at 3.0 V
— 2.2 2.3 mA
3
IDD_PSTOP2 Stop mode current with partial stop 2 clocking
option - core and system disabled / 10.5 MHz
bus / flash disabled (flash doze enabled)
• at 3.0 V
— 1.5 1.7 mA
3
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus
clock disabled, code executing from flash
• at 3.0 V
— 182 253 μA
5
IDD_VLPR Very low power run mode current - 4 MHz
core / 0.8 MHz bus and flash, all peripheral
clocks disabled, code executing from flash
• at 3.0 V
— 213 284 μA
5
IDD_VLPR Very low power run mode current - 4 MHz
core / 0.8 MHz bus and flash, all peripheral
clocks enabled, code executing from flash
• at 3.0 V
— 243 313 μA
4, 5
IDD_VLPW Very low power wait mode current - core
disabled / 4 MHz system / 0.8 MHz bus / flash
disabled (flash doze enabled), all peripheral
clocks disabled
• at 3.0 V
— 111 170 μA
5
IDD_STOP Stop mode current
• at 3.0 V
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
257
265
278
295
353
277
285
303
326
412
μA
IDD_VLPS Very-low-power stop mode current
• at 3.0 V
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
2.25
4.08
8.10
14.18
37.07
5.76
8.27
14.52
23.78
58.58
μA
IDD_LLS Low-leakage stop mode current
• at 3.0 V
Table continues on the next page...
General
10 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table 9. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
1.72
2.52
4.32
7.18
18.67
2.01
3.18
5.94
10.00
25.65
μA
IDD_VLLS3 Very-low-leakage stop mode 3 current
• at 3.0 V
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
1.16
1.78
3.23
5.57
14.80
1.36
2.27
4.38
7.53
19.74
μA
IDD_VLLS1 Very-low-leakage stop mode 1 current
• at 3.0 V
• at 25°C
• at 50°C
• at 70°C
• at 85°C
• at 105°C
—
—
—
—
—
0.64
1.14
2.35
4.37
12.40
0.81
1.50
3.20
5.80
16.13
μA
IDD_VLLS0 Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0)
• at 3.0 V
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
0.38
0.88
2.10
4.14
12.00
0.54
1.23
2.95
5.59
15.73
μA
IDD_VLLS0 Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1)
• at 3.0 V
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
0.30
0.79
2.01
4.05
11.96
0.45
1.12
2.82
5.45
15.63
μA
6
1. Data based on characterization results.
General
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2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode.
6. No brownout
Table 10. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206 228 237 245 251 258 uA
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
• VLLS1
• VLLS3
• LLS
• VLPS
• STOP
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
nA
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
22 22 22 22 22 22 µA
IRTC RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432 357 388 475 532 810 nA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
• MCGIRCLK (4 MHz internal
reference clock)
• OSCERCLK (4 MHz external
crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
Table continues on the next page...
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Table 10. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
ITPM TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No load
is placed on the I/O generating the
clock signal. Includes selected clock
source and I/O switching currents.
• MCGIRCLK (4 MHz internal
reference clock)
• OSCERCLK (4 MHz external
crystal)
86
235
86
256
86
265
86
274
86
280
86
287
µA
IBG Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
366 366 366 366 366 366 µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode, and BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
General
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Freescale Semiconductor, Inc.
4.00E-03
5.00E-03
6.00E-03
7.00E-03
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
All Peripheral CLK Gates
000.00E+00
1.00E-03
2.00E-03
3.00E-03
'1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2
1 2 3 4 6 12 24 48
Run Mode Current VS Core Frequency
CLK Ratio
Flash-Core
Core Freq (MHz)
All Off
All On
Current Consumption on VDD (A)
Figure 2. Run mode supply current vs. core frequency
General
14 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
200.00E-06
250.00E-06
300.00E-06
350.00E-06
000.00E+00
50.00E-06
100.00E-06
150.00E-06
'1-1 '1-2 '1-2 '1-4
1 2 4
VLPR Mode Current VS Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE
All Peripheral CLK Gates
CLK Ratio
Flash-Core
Core Freq (MHz)
Current Consumption on VDD (A)
All Off
All On
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation play a significant role in EMC performance. The system designer must
consult the following Freescale applications notes, available on freescale.com for
advice and guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
General
Kinetis KL05 32 KB Flash, Rev4 03/2014. 15
Freescale Semiconductor, Inc.
• AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
2.2.7 Capacitance attributes
Table 11. Capacitance attributes
Symbol Description Min. Max. Unit
CIN Input capacitance — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 12. Device clock specifications
Symbol Description Min. Max. Unit
Normal run mode
fSYS System and core clock — 48 MHz
fBUS Bus clock — 24 MHz
fFLASH Flash clock — 24 MHz
fLPTMR LPTMR clock — 24 MHz
VLPR and VLPS modes1
fSYS System and core clock — 4 MHz
fBUS Bus clock — 1 MHz
fFLASH Flash clock — 1 MHz
fLPTMR LPTMR clock2— 24 MHz
fERCLK External reference clock — 16 MHz
fLPTMR_ERCLK LPTMR external reference clock — 16 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
— 16 MHz
fTPM TPM asynchronous clock — 8 MHz
fUART0 UART0 asynchronous clock — 8 MHz
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
General
16 Kinetis KL05 32 KB Flash, Rev4 03/2014.
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2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 13. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled)
— Synchronous path
1.5 — Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 — ns 2
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2
Port rise and fall time — 36 ns 3
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 14. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C
2.4.2 Thermal attributes
Table 15. Thermal attributes
Board type Symbol Description 48
LQFP
32
LQFP
32 QFN 24 QFN Unit Notes
Single-layer (1S) RθJA Thermal resistance, junction
to ambient (natural
convection)
82 88 97 110 °C/W 1
Four-layer (2s2p) RθJA Thermal resistance, junction
to ambient (natural
convection)
58 59 34 42 °C/W
Table continues on the next page...
General
Kinetis KL05 32 KB Flash, Rev4 03/2014. 17
Freescale Semiconductor, Inc.
Table 15. Thermal attributes (continued)
Board type Symbol Description 48
LQFP
32
LQFP
32 QFN 24 QFN Unit Notes
Single-layer (1S) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
70 74 81 92 °C/W
Four-layer (2s2p) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
52 52 28 36 °C/W
— RθJB Thermal resistance, junction
to board
36 35 13 18 °C/W 2
— RθJC Thermal resistance, junction
to case
27 26 2.3 3.7 °C/W 3
—ΨJT Thermal characterization
parameter, junction to
package top outside center
(natural convection)
8 8 8 10 °C/W 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 16. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 SWD_CLK frequency of operation
• Serial wire debug
0
25
MHz
J2 SWD_CLK cycle period 1/J1 — ns
J3 SWD_CLK clock pulse width
Table continues on the next page...
Peripheral operating requirements and behaviors
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Freescale Semiconductor, Inc.
Table 16. SWD full voltage range electricals (continued)
Symbol Description Min. Max. Unit
• Serial wire debug 20 — ns
J4 SWD_CLK rise and fall times — 3 ns
J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns
J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns
J11 SWD_CLK high to SWD_DIO data valid — 32 ns
J12 SWD_CLK high to SWD_DIO high-Z 5 — ns
J2
J3 J3
J4 J4
SWD_CLK (input)
Figure 4. Serial wire clock input timing
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
Figure 5. Serial wire data timing
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 19
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3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 17. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
fints_t Internal reference frequency (slow clock) —
user trimmed
31.25 — 39.0625 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
— ± 0.3 ± 0.6 %fdco 1
Δfdco_t Total deviation of trimmed average DCO output
frequency over voltage and temperature
— +0.5/-0.7 ± 3 %fdco 1, 2
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
— ± 0.4 ± 1.5 %fdco 1, 2
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
— 4 — MHz
Δfintf_ft Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
— +1/-2 ± 3 %fintf_ft 2
fintf_t Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 — 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
— — kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
— — kHz
FLL
ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS = 00)
640 × ffll_ref
20 20.97 25 MHz 3, 4
Mid range (DRS = 01)
1280 × ffll_ref
40 41.94 48 MHz
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS = 00)
732 × ffll_ref
— 23.99 — MHz 5, 6
Mid range (DRS = 01) — 47.97 — MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
20 Kinetis KL05 32 KB Flash, Rev4 03/2014.
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Table 17. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
1464 × ffll_ref
Jcyc_fll FLL period jitter
• fVCO = 48 MHz
— 180 — ps 7
tfll_acquire FLL target frequency acquisition time — — 1 ms 8
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
950
1.2
1.5
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1
IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
—
—
—
—
—
—
25
400
500
2.5
3
4
—
—
—
—
—
—
μA
μA
μA
mA
mA
mA
1
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 21
Freescale Semiconductor, Inc.
Table 18. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
• 24 MHz
• 32 MHz
CxEXTAL load capacitance — — — 2, 3
CyXTAL load capacitance — — — 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — MΩ2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 — MΩ
Feedback resistor — high-frequency, low-
power mode (HGO=0)
— — — MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 — MΩ
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
— 200 — kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
0
—
kΩ
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
Peripheral operating requirements and behaviors
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3.3.2.2 Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 — 32 MHz
fec_extal Input clock frequency (external clock mode) — — 48 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— — ms 3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Peripheral operating requirements and behaviors
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Table 20. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time — 7.5 18 μs
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversall Erase All high-voltage time — 52 452 ms 1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs1
tpgmchk Program Check execution time — — 45 μs1
trdrsrc Read Resource execution time — — 30 μs1
tpgm4 Program Longword execution time — 65 145 μs
tersscr Erase Flash Sector execution time — 14 114 ms 2
trd1all Read 1s All Blocks execution time — — 0.5 ms
trdonce Read Once execution time — — 25 μs1
tpgmonce Program Once execution time — 65 — μs
tersall Erase All Blocks execution time — 61 500 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage
flash programming operation
— 2.5 6.0 mA
IDD_ERS Average current adder during high voltage
flash erase operation
— 1.5 4.0 mA
3.4.1.4 Reliability specifications
Table 23. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
Table continues on the next page...
Peripheral operating requirements and behaviors
24 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table 23. NVM reliability specifications (continued)
Symbol Description Min. Typ.1Max. Unit Notes
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
3.6.1.1 12-bit ADC operating conditions
Table 24. 12-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V3
VREFL ADC reference
voltage low
VSSA VSSA VSSA V3
VADIN Input voltage VREFL — VREFH V
CADIN Input
capacitance
• 8-bit / 10-bit / 12-bit
modes
— 4 5 pF
RADIN Input series
resistance
— 2 5 kΩ
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 24. 12-bit ADC operating conditions (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
RAS Analog source
resistance
(external)
12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
4
fADCK ADC conversion
clock frequency
≤ 12-bit mode 1.0 — 18.0 MHz 5
Crate ADC conversion
rate
≤ 12-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000
—
818.330
Ksps
6
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/
CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
RAS
VAS CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 6. ADC input impedance equivalency diagram
Peripheral operating requirements and behaviors
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3.6.1.2 12-bit ADC electrical characteristics
Table 25. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
fADACK
ADC
asynchronous
clock source
• ADLPC = 1, ADHSC =
0
• ADLPC = 1, ADHSC =
1
• ADLPC = 0, ADHSC =
0
• ADLPC = 0, ADHSC =
1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.7
±0.2
–1.1 to
+1.9
–0.3 to 0.5
LSB45
INL Integral non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±1.0
±0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB45
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
–4
–1.4
–5.4
–1.8
LSB4VADIN =
VDDA5
EQQuantization
error
• 12-bit modes — — ±0.5 LSB4
EIL Input leakage
error
IIn × RAS mV IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C 6
VTEMP25 Temp sensor
voltage
25 °C 706 716 726 mV 6
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
Peripheral operating requirements and behaviors
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3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. ADC conversion clock < 3 MHz
Figure 7. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 26. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
IDDHS Supply current, high-speed mode (EN = 1, PMODE =
1)
— — 200 μA
IDDLS Supply current, low-speed mode (EN = 1, PMODE =
0)
— — 20 μA
VAIN Analog input voltage VSS — VDD V
VAIO Analog input offset voltage — — 20 mV
VHAnalog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
—
—
5
10
—
—
mV
mV
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 26. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
20
30
—
—
mV
mV
VCMPOh Output high VDD – 0.5 — — V
VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN = 1,
PMODE = 1)
20 50 200 ns
tDLS Propagation delay, low-speed mode (EN = 1, PMODE
= 0)
80 250 600 ns
Analog comparator initialization delay2— — 40 μs
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to
DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
40.00E-03
50.00E-03
60.00E-03
70.00E-03
80.00E-03
90.00E-03
CMP Hysteresis (V)
CMP Hysteresis vs Vinn
0
1
2
HYSTCTR
Setting
000.00E+00
10.00E-03
20.00E-03
30.00E-03
1
CMP Hysteresis (V)
Vinn (V)
3
Figure 8. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 29
Freescale Semiconductor, Inc.
80.00E-03
100.00E-03
120.00E-03
140.00E-03
160.00E-03
180.00E-03
CMP Hysteresis (V)
CMP Hysteresis vs Vinn
0
1
2
HYSTCTR
Setting
-20.00E-03
000.00E+00
20.00E-03
40.00E-03
60.00E-03
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
CMP Hysteresis (V)
Vinn (V)
3
Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 27. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
CLOutput load capacitance — 100 pF 2
ILOutput load current — 1 mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
3.6.3.2 12-bit DAC operating behaviors
Table 28. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode — — 250 μA
IDDA_DACH
P
Supply current — high-speed mode — — 900 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs1
Table continues on the next page...
Peripheral operating requirements and behaviors
30 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table 28. 12-bit DAC operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
— 0.7 1 μs1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
— — 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— — ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— — ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— — ±1 LSB 4
VOFFSET Offset error — ±0.4 ±0.8 %FSR 5
EGGain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB
TCO Temperature coefficient offset voltage — 3.7 — μV/C 6
TGE Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance (load = 3 kΩ)— — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h
• High power (SPHP)
• Low power (SPLP)
1.2
0.05
1.7
0.12
—
—
V/μs
BW 3dB bandwidth
• High power (SPHP)
• Low power (SPLP)
550
40
—
—
—
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 31
Freescale Semiconductor, Inc.
Digital Code
DAC12 INL (LSB)
0
500 1000 1500 2000 2500 3000 3500 4000
2
4
6
8
-2
-4
-6
-8
0
Figure 10. Typical INL error vs. digital code
Peripheral operating requirements and behaviors
32 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Temperature °C
DAC12 Mid Level Code Voltage
25 55 85 105 125
1.499
-40
1.4985
1.498
1.4975
1.497
1.4965
1.496
Figure 11. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 33
Freescale Semiconductor, Inc.
3.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats used
for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 29. SPI master mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x
tperiph
ns 2
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph – 30 1024 x
tperiph
ns —
6 tSU Data setup time (inputs) 16 — ns —
7 tHI Data hold time (inputs) 0 — ns —
8 tvData valid (after SPSCK edge) — 10 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph – 25 ns —
tFI Fall time input
11 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
Table 30. SPI master mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x
tperiph
ns 2
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph – 30 1024 x
tperiph
ns —
6 tSU Data setup time (inputs) 96 — ns —
7 tHI Data hold time (inputs) 0 — ns —
Table continues on the next page...
Peripheral operating requirements and behaviors
34 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table 30. SPI master mode timing on slew rate enabled pads (continued)
Num. Symbol Description Min. Max. Unit Note
8 tvData valid (after SPSCK edge) — 52 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph – 25 ns —
tFI Fall time input
11 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
(OUTPUT)
2
8
6 7
MSB IN 2
LSB IN
MSB OUT 2 LSB OUT
9
5
5
3
(CPOL=0)
4
11
11
10
10
SPSCK
SPSCK
(CPOL=1)
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. If configured as an output.
SS 1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT) BIT 6 . . . 1
BIT 6 . . . 1
Figure 12. SPI master mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 35
Freescale Semiconductor, Inc.
<<CLASSIFICATION>>
<<NDA MESSAGE>>
38
2
6 7
MSB IN 2
BIT 6 . . . 1
MASTER MSB OUT 2 MASTER LSB OUT
5
5
8
10 11
PORT DATA PORT DATA
310 11 4
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
9
(OUTPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS 1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT) LSB IN
BIT 6 . . . 1
Figure 13. SPI master mode timing (CPHA = 1)
Table 31. SPI slave mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph – 30 — ns —
6 tSU Data setup time (inputs) 2 — ns —
7 tHI Data hold time (inputs) 7 — ns —
8 taSlave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
10 tvData valid (after SPSCK edge) — 22 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph – 25 ns —
tFI Fall time input
13 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Peripheral operating requirements and behaviors
36 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table 32. SPI slave mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph – 30 — ns —
6 tSU Data setup time (inputs) 2 — ns —
7 tHI Data hold time (inputs) 7 — ns —
8 taSlave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
10 tvData valid (after SPSCK edge) — 122 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph – 25 ns —
tFI Fall time input
13 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
2
10
6 7
MSB IN
BIT 6 . . . 1
SLAVE MSB SLAVE LSB OUT
11
5
5
3
8
4
13
NOTE: Not defined
12
12
11
SEE
NOTE
13
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
LSB IN
BIT 6 . . . 1
Figure 14. SPI slave mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 37
Freescale Semiconductor, Inc.
2
6 7
MSB IN
BIT 6 . . . 1
MSB OUT SLAVE LSB OUT
5
5
10
12 13
312 13
4
SLAVE
8
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
NOTE: Not defined
11
LSB IN
BIT 6 . . . 1
Figure 15. SPI slave mode timing (CPHA = 1)
3.8.2 Inter-Integrated Circuit Interface (I2C) timing
Table 33. I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 4001kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 — 0.6 — µs
LOW period of the SCL clock tLOW 4.7 — 1.3 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 — 0.6 — µs
Data hold time for I2C bus devices tHD; DAT 023.453040.92µs
Data set-up time tSU; DAT 2505— 1003, 6— ns
Rise time of SDA and SCL signals tr— 1000 20 +0.1Cb7300 ns
Fall time of SDA and SCL signals tf— 300 20 +0.1Cb6300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High
drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD ≥ 2.7 V
Peripheral operating requirements and behaviors
38 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
7. Cb = total capacitance of the one bus line in pF.
SDA
SCL
tHD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
Figure 16. Timing definition for fast and standard mode devices on the I2C bus
3.8.3 UART
See General switching specifications.
3.9 Human-machine interfaces (HMI)
3.9.1 TSI electrical specifications
Table 34. TSI electrical specifications
Symbol Description Min. Typ. Max. Unit
TSI_RUNF Fixed power consumption in run mode — 100 — µA
TSI_RUNV Variable power consumption in run mode
(depends on oscillator's current selection)
1.0 — 128 µA
TSI_EN Power consumption in enable mode — 100 — µA
TSI_DIS Power consumption in disable mode — 1.2 — µA
TSI_TEN TSI analog enable time — 66 — µs
TSI_CREF TSI reference capacitor — 1.0 — pF
TSI_DVOLT Voltage variation of VP & VM around nominal
values
0.19 — 1.03 V
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 39
Freescale Semiconductor, Inc.
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
24-pin QFN 98ASA00474D
32-pin QFN 98ASA00473D
32-pin LQFP 98ASH70029A
48-pin LQFP 98ASH00962A
5 Pinout
5.1 KL05 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
48
LQFP
32
QFN
32
LQFP
24
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3
1 1 1 1 PTB6/
IRQ_2/
LPTMR0_ALT3
DISABLED DISABLED PTB6/
IRQ_2/
LPTMR0_ALT3
TPM0_CH3 TPM_CLKIN1
2 2 2 2 PTB7/
IRQ_3
DISABLED DISABLED PTB7/
IRQ_3
TPM0_CH2
3 — — — PTA14 DISABLED DISABLED PTA14 TPM_CLKIN0
4 — — — PTA15 DISABLED DISABLED PTA15 CLKOUT
5 3 3 3 VDD VDD VDD
6 4 4 3 VREFH VREFH VREFH
7 5 5 4 VREFL VREFL VREFL
8 6 6 4 VSS VSS VSS
Dimensions
40 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
48
LQFP
32
QFN
32
LQFP
24
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3
9 7 7 5 PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C0_SDA
10 8 8 6 PTA4/
LLWU_P0
XTAL0 XTAL0 PTA4/
LLWU_P0
I2C0_SDA I2C0_SCL
11 — — — VSS VSS VSS
12 — — — PTB18 DISABLED DISABLED PTB18
13 — — — PTB19 DISABLED DISABLED PTB19
14 9 9 7 PTA5/
LLWU_P1/
RTC_CLK_IN
DISABLED DISABLED PTA5/
LLWU_P1/
RTC_CLK_IN
TPM0_CH5 SPI0_SS_b
15 10 10 8 PTA6/
LLWU_P2
DISABLED DISABLED PTA6/
LLWU_P2
TPM0_CH4 SPI0_MISO
16 11 11 — PTB8 ADC0_SE11 ADC0_SE11 PTB8 TPM0_CH3
17 12 12 — PTB9 ADC0_SE10 ADC0_SE10 PTB9 TPM0_CH2
18 — — — PTA16/
IRQ_4
DISABLED DISABLED PTA16/
IRQ_4
19 — — — PTA17/
IRQ_5
DISABLED DISABLED PTA17/
IRQ_5
20 — — — PTA18/
IRQ_6
DISABLED DISABLED PTA18/
IRQ_6
21 13 13 9 PTB10 ADC0_SE9/
TSI0_IN7
ADC0_SE9/
TSI0_IN7
PTB10 TPM0_CH1
22 14 14 10 PTB11 ADC0_SE8/
TSI0_IN6
ADC0_SE8/
TSI0_IN6
PTB11 TPM0_CH0
23 15 15 11 PTA7/
IRQ_7/
LLWU_P3
ADC0_SE7/
TSI0_IN5
ADC0_SE7/
TSI0_IN5
PTA7/
IRQ_7/
LLWU_P3
SPI0_MISO SPI0_MOSI
24 16 16 12 PTB0/
IRQ_8/
LLWU_P4
ADC0_SE6/
TSI0_IN4
ADC0_SE6/
TSI0_IN4
PTB0/
IRQ_8/
LLWU_P4
EXTRG_IN SPI0_SCK
25 17 17 13 PTB1/
IRQ_9
ADC0_SE5/
TSI0_IN3/
DAC0_OUT/
CMP0_IN3
ADC0_SE5/
TSI0_IN3/
DAC0_OUT/
CMP0_IN3
PTB1/
IRQ_9
UART0_TX UART0_RX
26 18 18 14 PTB2/
IRQ_10/
LLWU_P5
ADC0_SE4/
TSI0_IN2
ADC0_SE4/
TSI0_IN2
PTB2/
IRQ_10/
LLWU_P5
UART0_RX UART0_TX
27 19 19 15 PTA8 ADC0_SE3/
TSI0_IN1
ADC0_SE3/
TSI0_IN1
PTA8
28 20 20 16 PTA9 ADC0_SE2/
TSI0_IN0
ADC0_SE2/
TSI0_IN0
PTA9
29 — — — PTB20 DISABLED DISABLED PTB20
30 — — — VSS VSS VSS
31 — — — VDD VDD VDD
32 — — — PTB14/
IRQ_11
DISABLED DISABLED PTB14/
IRQ_11
EXTRG_IN
Pinout
Kinetis KL05 32 KB Flash, Rev4 03/2014. 41
Freescale Semiconductor, Inc.
48
LQFP
32
QFN
32
LQFP
24
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3
33 21 21 — PTA10/
IRQ_12
DISABLED TSI0_IN11 PTA10/
IRQ_12
34 22 22 — PTA11/
IRQ_13
DISABLED TSI0_IN10 PTA11/
IRQ_13
35 23 23 17 PTB3/
IRQ_14
DISABLED DISABLED PTB3/
IRQ_14
I2C0_SCL UART0_TX
36 24 24 18 PTB4/
IRQ_15/
LLWU_P6
DISABLED DISABLED PTB4/
IRQ_15/
LLWU_P6
I2C0_SDA UART0_RX
37 25 25 19 PTB5/
IRQ_16
NMI_b ADC0_SE1/
CMP0_IN1
PTB5/
IRQ_16
TPM1_CH1 NMI_b
38 26 26 20 PTA12/
IRQ_17/
LPTMR0_ALT2
ADC0_SE0/
CMP0_IN0
ADC0_SE0/
CMP0_IN0
PTA12/
IRQ_17/
LPTMR0_ALT2
TPM1_CH0 TPM_CLKIN0
39 27 27 — PTA13 TSI0_IN9 TSI0_IN9 PTA13
40 28 28 — PTB12 TSI0_IN8 TSI0_IN8 PTB12
41 — — — PTA19 DISABLED DISABLED PTA19 SPI0_SS_b
42 — — — PTB15 DISABLED DISABLED PTB15 SPI0_MOSI SPI0_MISO
43 — — — PTB16 DISABLED DISABLED PTB16 SPI0_MISO SPI0_MOSI
44 — — — PTB17 DISABLED DISABLED PTB17 TPM_CLKIN1 SPI0_SCK
45 29 29 21 PTB13 ADC0_SE13 ADC0_SE13 PTB13 TPM1_CH1 RTC_CLKOUT
46 30 30 22 PTA0/
IRQ_0/
LLWU_P7
SWD_CLK ADC0_SE12/
CMP0_IN2
PTA0/
IRQ_0/
LLWU_P7
TPM1_CH0 SWD_CLK
47 31 31 23 PTA1/
IRQ_1/
LPTMR0_ALT1
RESET_b DISABLED PTA1/
IRQ_1/
LPTMR0_ALT1
TPM_CLKIN0 RESET_b
48 32 32 24 PTA2 SWD_DIO DISABLED PTA2 CMP0_OUT SWD_DIO
5.2 KL05 pinouts
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see KL05 signal multiplexing and pin assignments.
Pinout
42 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
PTB18
VSS
PTA4/LLWU_P0
PTA3
VSS
VREFL
VREFH
VDD
PTA15
PTA14
PTB7/IRQ_3
PTB6/IRQ_2/LPTMR0_ALT3
12
11
10
9
8
7
6
5
4
3
2
1
48
47
46
45
44
43
42
41
40
39
38
37
PTA2
PTA1/IRQ_1/LPTMR0_ALT1
PTA0/IRQ_0/LLWU_P7
PTB13
PTB17
PTB16
PTB15
PTA19
PTB12
PTA13
PTA12/IRQ_17/LPTMR0_ALT2
PTB5/IRQ_16
36
35
34
33
PTB4/IRQ_15/LLWU_P6
PTB3/IRQ_14
PTA11/IRQ_13
PTA10/IRQ_12
32
31
30
29
28
27
26
25
PTB14/IRQ_11
VDD
VSS
PTB20
PTA9
PTA8
PTB2/IRQ_10/LLWU_P5
PTB1/IRQ_9
PTA18/IRQ_6
PTA17/IRQ_5
PTA16/IRQ_4
PTB9
24
23
22
21
20
19
18
17
PTB8
PTA6/LLWU_P2
PTA5/LLWU_P1/RTC_CLK_IN
PTB19
16
15
14
13
PTB0/IRQ_8/LLWU_P4
PTA7/IRQ_7/LLWU_P3
PTB11
PTB10
Figure 17. KL05 48-pin LQFP pinout diagram
Pinout
Kinetis KL05 32 KB Flash, Rev4 03/2014. 43
Freescale Semiconductor, Inc.
32
31
30
29
28
27
26
25
PTA2
PTA1/IRQ_1/LPTMR0_ALT1
PTA0/IRQ_0/LLWU_P7
PTB13
PTB12
PTA13
PTA12/IRQ_17/LPTMR0_ALT2
PTB5/IRQ_16
PTB9
PTB8
PTA6/LLWU_P2
PTA5/LLWU_P1/RTC_CLK_IN
12
11
10
9
PTB0/IRQ_8/LLWU_P4
PTA7/IRQ_7/LLWU_P3
PTB11
PTB10
16
15
14
13
PTA9
PTA8
PTB2/IRQ_10/LLWU_P5
PTB1/IRQ_9
24
23
22
21
20
19
18
17
PTB4/IRQ_15/LLWU_P6
PTB3/IRQ_14
PTA11/IRQ_13
PTA10/IRQ_12
PTA4/LLWU_P0
PTA3
VSS
VREFL
VREFH
VDD
PTB7/IRQ_3
PTB6/IRQ_2/LPTMR0_ALT3
8
7
6
5
4
3
2
1
Figure 18. KL05 32-pin LQFP pinout diagram
Pinout
44 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
32
31
30
29
28
27
26
25
PTA2
PTA1/IRQ_1/LPTMR0_ALT1
PTA0/IRQ_0/LLWU_P7
PTB13
PTB12
PTA13
PTA12/IRQ_17/LPTMR0_ALT2
PTB5/IRQ_16
PTB9
PTB8
PTA6/LLWU_P2
PTA5/LLWU_P1/RTC_CLK_IN
12
11
10
9
PTB0/IRQ_8/LLWU_P4
PTA7/IRQ_7/LLWU_P3
PTB11
PTB10
16
15
14
13
PTA9
PTA8
PTB2/IRQ_10/LLWU_P5
PTB1/IRQ_9
24
23
22
21
20
19
18
17
PTB4/IRQ_15/LLWU_P6
PTB3/IRQ_14
PTA11/IRQ_13
PTA10/IRQ_12
PTA4/LLWU_P0
PTA3
VSS
VREFL
VREFH
VDD
PTB7/IRQ_3
PTB6/IRQ_2/LPTMR0_ALT3
8
7
6
5
4
3
2
1
Figure 19. KL05 32-pin QFN pinout diagram
Pinout
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Freescale Semiconductor, Inc.
24
23
22
PTA2
PTA1/IRQ_1/LPTMR0_ALT1
PTA0/IRQ_0/LLWU_P7
PTA12/IRQ_17/LPTMR0_ALT2
PTB5/IRQ_16
21
20
19
PTB13
PTA9
PTA8
16
15
PTB4/IRQ_15/LLWU_P6
PTB3/IRQ_14
18
17
PTB2/IRQ_10/LLWU_P5
PTB1/IRQ_9
14
13
PTB0/IRQ_8/LLWU_P4
PTA7/IRQ_7/LLWU_P3
PTB11
PTB10
12
11
10
9
PTA6/LLWU_P2 8
PTA5/LLWU_P1/RTC_CLK_IN 7
PTA4/LLWU_P0
PTA3
VREFL VSS
VDD VREFH
PTB7/IRQ_3
PTB6/IRQ_2/LPTMR0_ALT3
6
5
4
3
2
1
Figure 20. KL05 24-pin QFN pinout diagram
6 Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PKL05 and MKL05
7 Part identification
Ordering parts
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7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 35. Part number fields descriptions
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
KL## Kinetis family • KL05
A Key attribute • Z = Cortex-M0+
FFF Program flash memory size • 8 = 8 KB
• 16 = 16 KB
• 32 = 32 KB
R Silicon revision • (Blank) = Main
• A = Revision after main
T Temperature range (°C) • V = –40 to 105
PP Package identifier • FK = 24 QFN (4 mm x 4 mm)
• LC = 32 LQFP (7 mm x 7 mm)
• FM = 32 QFN (5 mm x 5 mm)
• LF = 48 LQFP (7 mm x 7 mm)
CC Maximum CPU frequency (MHz) • 4 = 48 MHz
N Packaging type • R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
Part identification
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MKL05Z8VLC4
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
0.9 1.1 V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Terminology and guidelines
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Symbol Description Min. Max. Unit
CIN_D Input capacitance:
digital pins
— 7 pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if
exceeded, may cause permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
–0.3 1.2 V
8.5 Result of exceeding a rating
40
30
20
10
0
Measured characteristic
Operating rating
Failures in time (ppm)
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
Terminology and guidelines
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8.6 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
Terminology and guidelines
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8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak
pullup/pulldown
current
10 70 130 µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
0.90 0.95 1.00 1.05 1.10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
150 °C
105 °C
25 °C
–40 °C
VDD (V)
I(μA)
DD_STOP
TJ
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Terminology and guidelines
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Table 36. Typical value conditions
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
9 Revision history
The following table provides a revision history for this document.
Table 37. Revision history
Rev. No. Date Substantial Changes
2 9/2012 Initial public release.
3 11/2012 Completed all the TBDs.
4 3/2014 • Updated the front page and restructured the chapters
• Added a note to the ILAT in the ESD handling ratings
• Updated Voltage and current operating ratings
• Added VODPU in the Voltage and current operating requirements
• Updated Voltage and current operating behaviors
• Updated Power mode transition operating behaviors
• Updated Power consumption operating behaviors
• Updated Capacitance attributes
• Updated footnote in the Device clock specifications
• Add thversall in the Flash timing specifications — commands
• Updated Temp sensor slope and voltage and added a note to them
in the 12-bit ADC electrical characteristics
• Removed TA in the 12-bit DAC operating requirements
• Added Inter-Integrated Circuit Interface (I2C) timing
Revision history
52 Kinetis KL05 32 KB Flash, Rev4 03/2014.
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Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
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at the following address: freescale.com/SalesTermsandConditions.
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© 2012-2014 Freescale Semiconductor, Inc.
Document Number KL05P48M48SF1
Revision 4 03/2014