Kinetis KL05 32 KB Flash
48 MHz Cortex-M0+ Based Microcontroller
Designed with efficiency in mind. Features a size efficient, small
package, energy efficient ARM Cortex-M0+ 32-bit performance.
Shares the comprehensive enablement and scalability of the
Kinetis family.
This product offers:
Run power consumption down to 45 μA/MHz in very low
power run mode
Static power consumption down to 2 μA with full state
retention and 4 μs wakeup
Ultra-efficient Cortex-M0+ processor running up to 48MHz
with industry leading throughput
Memory option is up to 32 KB Flash and 4 KB RAM
Energy-saving architecture is optimized for low power with
90 nm TFS technology, clock and power gating techniques,
and zero wait state flash memory controller
Performance
48 MHz ARM® Cortex®-M0+ core
Memories and memory interfaces
Up to 32 KB program flash memory
Up to 4 KB SRAM
System peripherals
Nine low-power modes to provide power optimization
based on application requirements
COP Software watchdog
4-channel DMA controller, supporting up to 63 request
sources
Low-leakage wakeup unit
SWD debug interface and Micro Trace Buffer
Bit Manipulation Engine
Clocks
32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
Multi-purpose clock source
1 kHz LPO clock
Operating Characteristics
Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range (ambient): -40 to 105°C
Human-machine interface
Low-power hardware touch sensor interface (TSI)
Up to 41 general-purpose input/output (GPIO)
Communication interfaces
One 8-bit SPI module
One low power UART module
One I2C module
Analog Modules
12-bit SAR ADC
12-bit DAC
Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
Timers
Six channel Timer/PWM (TPM)
One 2-channel Timer/PWM module
Periodic interrupt timers
16-bit low-power timer (LPTMR)
Real time clock
Security and integrity modules
80-bit unique identification number per chip
MKL05ZxxVFK4
MKL05ZxxVLC4
MKL05ZxxVFM4
MKL05ZxxVLF4
24-pin QFN (FK)
4 x 4 x 1 Pitch 0.5 mm
32-pin QFN (FM)
5 x 5 x 1 Pitch 0.5 mm
32-pin LQFP (LC)
7 x 7 x 1.4 Pitch 0.8
mm
48-pin LQFP (LF)
7 x 7 x 1.4 Pitch 0.5
mm
Freescale Semiconductor, Inc. KL05P48M48SF1
Data Sheet: Technical Data Rev 4 03/2014
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2012–2014 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information
Part Number Memory Maximum number of I\O's
Flash (KB) SRAM (KB)
MKL05Z8VFK4 8 1 22
MKL05Z16VFK4 16 2 22
MKL05Z32VFK4 32 4 22
MKL05Z8VLC4 8 1 28
MKL05Z16VLC4 16 2 28
MKL05Z32VLC4 32 4 28
MKL05Z8VFM4 8 1 28
MKL05Z16VFM4 16 2 28
MKL05Z32VFM4 32 4 28
MKL05Z16VLF4 16 2 41
MKL05Z32VLF4 32 4 41
Related Resources
Type Description
Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and
a dynamic product selector.
Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a
device for design suitability.
Reference Manual The Reference Manual contains a comprehensive description of the structure and function
(operation) of a device.
Data Sheet The Data Sheet includes electrical characteristics and signal connections.
Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask
set.
Package drawing Package dimensions are provided in package drawings.
2Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings..................................................................................4
1.1 Thermal handling ratings...............................................4
1.2 Moisture handling ratings...............................................4
1.3 ESD handling ratings.....................................................4
1.4 Voltage and current operating ratings............................4
2General.................................................................................5
2.1 AC electrical characteristics...........................................5
2.2 Nonswitching electrical specifications............................5
2.2.1 Voltage and current operating requirements......5
2.2.2 LVD and POR operating requirements..............6
2.2.3 Voltage and current operating behaviors...........7
2.2.4 Power mode transition operating behaviors.......8
2.2.5 Power consumption operating behaviors...........9
2.2.6 EMC performance..............................................15
2.2.7 Capacitance attributes.......................................16
2.3 Switching specifications.................................................16
2.3.1 Device clock specifications................................16
2.3.2 General switching specifications........................17
2.4 Thermal specifications...................................................17
2.4.1 Thermal operating requirements........................17
2.4.2 Thermal attributes..............................................17
3 Peripheral operating requirements and behaviors................18
3.1 Core modules................................................................18
3.1.1 SWD electricals .................................................18
3.2 System modules............................................................19
3.3 Clock modules...............................................................20
3.3.1 MCG specifications............................................20
3.3.2 Oscillator electrical specifications......................21
3.4 Memories and memory interfaces.................................23
3.4.1 Flash electrical specifications............................23
3.5 Security and integrity modules.......................................25
3.6 Analog............................................................................25
3.6.1 ADC electrical specifications..............................25
3.6.2 CMP and 6-bit DAC electrical specifications......28
3.6.3 12-bit DAC electrical characteristics..................30
3.7 Timers............................................................................33
3.8 Communication interfaces.............................................33
3.8.1 SPI switching specifications...............................33
3.8.2 Inter-Integrated Circuit Interface (I2C) timing.....38
3.8.3 UART.................................................................39
3.9 Human-machine interfaces (HMI)..................................39
3.9.1 TSI electrical specifications................................39
4 Dimensions...........................................................................40
4.1 Obtaining package dimensions......................................40
5 Pinout....................................................................................40
5.1 KL05 signal multiplexing and pin assignments..............40
5.2 KL05 pinouts..................................................................42
6 Ordering parts.......................................................................46
6.1 Determining valid orderable parts..................................46
7 Part identification...................................................................46
7.1 Description.....................................................................46
7.2 Format...........................................................................47
7.3 Fields.............................................................................47
7.4 Example.........................................................................47
8 Terminology and guidelines..................................................48
8.1 Definition: Operating requirement..................................48
8.2 Definition: Operating behavior.......................................48
8.3 Definition: Attribute........................................................48
8.4 Definition: Rating...........................................................49
8.5 Result of exceeding a rating..........................................49
8.6 Relationship between ratings and operating
requirements..................................................................49
8.7 Guidelines for ratings and operating requirements........50
8.8 Definition: Typical value.................................................50
8.9 Typical value conditions.................................................51
9 Revision history.....................................................................52
Kinetis KL05 32 KB Flash, Rev4 03/2014. 3
Freescale Semiconductor, Inc.
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level 3 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
–500 +500 V 2
ILAT Latch-up current at ambient temperature of 105 °C –100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Ratings
4Kinetis KL05 32 KB Flash, Rev4 03/2014.
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1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current 120 mA
VIO IO pin input voltage –0.3 VDD + 0.3 V
IDInstantaneous maximum current single pin limit (applies to
all port pins)
–25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
CL=30 pF loads
Slew rate disabled
Normal drive strength
2.2 Nonswitching electrical specifications
General
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2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VIH Input high voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
V
V
VIL Input low voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD V
IICIO IO pin negative DC injection current—single pin
VIN < VSS–0.3V (negative current injection)
VIN < VSS–0.3V (positive current injection)
–3
+3
mA
1
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
Negative current injection
Positive current injection
–25
+25
mA
VODPU Open drain pullup voltage level VDD VDD V2
VRAM VDD voltage required to retain RAM 1.2 V
1. All IO pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VIO_MIN
(=VSS-0.3V) and VIN is less than VIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VIO_MIN-VIN)/|IICIO|. The positive injection current limiting resistor is
calculated as R=(VIN-VIO_MAX)/|IICIO|. Select the larger of these two calculated resistances.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48 2.56 2.64 V
Low-voltage warning thresholds — high range 1
Table continues on the next page...
General
6Kinetis KL05 32 KB Flash, Rev4 03/2014.
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Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
±60 mV
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
±40 mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — Normal drive pad (except
RESET)
2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VDD – 0.5
VDD – 0.5
V
V
1, 2
VOH Output high voltage — High drive pad (except
RESET_b)
2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
VDD – 0.5
VDD – 0.5
V
V
1, 2
IOHT Output high current total for all ports 100 mA
VOL Output low voltage — Normal drive pad
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
0.5
0.5
V
V
1
Table continues on the next page...
General
Kinetis KL05 32 KB Flash, Rev4 03/2014. 7
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Table 7. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
VOL Output low voltage — High drive pad
2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
0.5
0.5
V
V
1
IOLT Output low current total for all ports 100 mA
IIN Input leakage current (per pin) for full temperature
range
1 μA3
IIN Input leakage current (per pin) at 25 °C 0.025 μA3
IIN Input leakage current (total all pins) for full
temperature range
41 μA3
IOZ Hi-Z (off-state) leakage current (per pin) 1 μA
RPU Internal pullup resistors 20 50 kΩ4
1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSxRUN recovery times in the following table
assume this clock configuration:
CPU and system clocks = 48 MHz
Bus and flash clock = 24 MHz
FEI clock mode
POR and VLLSxRUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit
tPOR After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
300 μs1
VLLS0 RUN
95
115
μs
VLLS1 RUN
Table continues on the next page...
General
8Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table 8. Power mode transition operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit
93 115 μs
VLLS3 RUN
42
53
μs
LLS RUN
4
4.6
μs
VLPS RUN
4
4.4
μs
STOP RUN
4
4.4
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 9. Power consumption operating behaviors
Symbol Description Min. Typ. Max.1Unit Notes
IDDA Analog supply current See note mA 2
IDD_RUNCO Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus clock disabled,
code of while(1) loop executing from flash
at 3.0 V
4.0 4.3 mA
3
IDD_RUN Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks disabled, code
executing from flash
at 3.0 V
4.9 5.3 mA
3
IDD_RUN Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks enabled, code
executing from flash
at 3.0 V
at 25 °C
at 125 °C
5.7
6.0
5.8
6.2
mA
3, 4
IDD_WAIT Wait mode current - core disabled / 48 MHz
system / 24 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled
at 3.0 V
2.7 2.9 mA
3
Table continues on the next page...
General
Kinetis KL05 32 KB Flash, Rev4 03/2014. 9
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Table 9. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
IDD_WAIT Wait mode current - core disabled / 24 MHz
system / 24 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled
at 3.0 V
2.2 2.3 mA
3
IDD_PSTOP2 Stop mode current with partial stop 2 clocking
option - core and system disabled / 10.5 MHz
bus / flash disabled (flash doze enabled)
at 3.0 V
1.5 1.7 mA
3
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus
clock disabled, code executing from flash
at 3.0 V
182 253 μA
5
IDD_VLPR Very low power run mode current - 4 MHz
core / 0.8 MHz bus and flash, all peripheral
clocks disabled, code executing from flash
at 3.0 V
213 284 μA
5
IDD_VLPR Very low power run mode current - 4 MHz
core / 0.8 MHz bus and flash, all peripheral
clocks enabled, code executing from flash
at 3.0 V
243 313 μA
4, 5
IDD_VLPW Very low power wait mode current - core
disabled / 4 MHz system / 0.8 MHz bus / flash
disabled (flash doze enabled), all peripheral
clocks disabled
at 3.0 V
111 170 μA
5
IDD_STOP Stop mode current
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
257
265
278
295
353
277
285
303
326
412
μA
IDD_VLPS Very-low-power stop mode current
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
2.25
4.08
8.10
14.18
37.07
5.76
8.27
14.52
23.78
58.58
μA
IDD_LLS Low-leakage stop mode current
at 3.0 V
Table continues on the next page...
General
10 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
Table 9. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max.1Unit Notes
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
1.72
2.52
4.32
7.18
18.67
2.01
3.18
5.94
10.00
25.65
μA
IDD_VLLS3 Very-low-leakage stop mode 3 current
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
1.16
1.78
3.23
5.57
14.80
1.36
2.27
4.38
7.53
19.74
μA
IDD_VLLS1 Very-low-leakage stop mode 1 current
at 3.0 V
at 25°C
at 50°C
at 70°C
at 85°C
at 105°C
0.64
1.14
2.35
4.37
12.40
0.81
1.50
3.20
5.80
16.13
μA
IDD_VLLS0 Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0)
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
0.38
0.88
2.10
4.14
12.00
0.54
1.23
2.95
5.59
15.73
μA
IDD_VLLS0 Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1)
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
0.30
0.79
2.01
4.05
11.96
0.45
1.12
2.82
5.45
15.63
μA
6
1. Data based on characterization results.
General
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2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode.
6. No brownout
Table 10. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206 228 237 245 251 258 uA
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
VLLS3
LLS
VLPS
STOP
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
nA
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
22 22 22 22 22 22 µA
IRTC RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432 357 388 475 532 810 nA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
MCGIRCLK (4 MHz internal
reference clock)
OSCERCLK (4 MHz external
crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
Table continues on the next page...
General
12 Kinetis KL05 32 KB Flash, Rev4 03/2014.
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Table 10. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
ITPM TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No load
is placed on the I/O generating the
clock signal. Includes selected clock
source and I/O switching currents.
MCGIRCLK (4 MHz internal
reference clock)
OSCERCLK (4 MHz external
crystal)
86
235
86
256
86
265
86
274
86
280
86
287
µA
IBG Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
366 366 366 366 366 366 µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
MCG in FBE for run mode, and BLPE for VLPR mode
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
General
Kinetis KL05 32 KB Flash, Rev4 03/2014. 13
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4.00E-03
5.00E-03
6.00E-03
7.00E-03
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
All Peripheral CLK Gates
000.00E+00
1.00E-03
2.00E-03
3.00E-03
'1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2
1 2 3 4 6 12 24 48
Run Mode Current VS Core Frequency
CLK Ratio
Flash-Core
Core Freq (MHz)
All Off
All On
Current Consumption on VDD (A)
Figure 2. Run mode supply current vs. core frequency
General
14 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.
200.00E-06
250.00E-06
300.00E-06
350.00E-06
000.00E+00
50.00E-06
100.00E-06
150.00E-06
'1-1 '1-2 '1-2 '1-4
1 2 4
VLPR Mode Current VS Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE
All Peripheral CLK Gates
CLK Ratio
Flash-Core
Core Freq (MHz)
Current Consumption on VDD (A)
All Off
All On
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation play a significant role in EMC performance. The system designer must
consult the following Freescale applications notes, available on freescale.com for
advice and guidance specifically targeted at optimizing EMC performance.
AN2321: Designing for Board Level Electromagnetic Compatibility
AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
General
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AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
2.2.7 Capacitance attributes
Table 11. Capacitance attributes
Symbol Description Min. Max. Unit
CIN Input capacitance 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 12. Device clock specifications
Symbol Description Min. Max. Unit
Normal run mode
fSYS System and core clock 48 MHz
fBUS Bus clock 24 MHz
fFLASH Flash clock 24 MHz
fLPTMR LPTMR clock 24 MHz
VLPR and VLPS modes1
fSYS System and core clock 4 MHz
fBUS Bus clock 1 MHz
fFLASH Flash clock 1 MHz
fLPTMR LPTMR clock2 24 MHz
fERCLK External reference clock 16 MHz
fLPTMR_ERCLK LPTMR external reference clock 16 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
16 MHz
fTPM TPM asynchronous clock 8 MHz
fUART0 UART0 asynchronous clock 8 MHz
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
General
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2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 13. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled)
— Synchronous path
1.5 Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 ns 2
GPIO pin interrupt pulse width — Asynchronous path 16 ns 2
Port rise and fall time 36 ns 3
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 14. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C
2.4.2 Thermal attributes
Table 15. Thermal attributes
Board type Symbol Description 48
LQFP
32
LQFP
32 QFN 24 QFN Unit Notes
Single-layer (1S) RθJA Thermal resistance, junction
to ambient (natural
convection)
82 88 97 110 °C/W 1
Four-layer (2s2p) RθJA Thermal resistance, junction
to ambient (natural
convection)
58 59 34 42 °C/W
Table continues on the next page...
General
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Table 15. Thermal attributes (continued)
Board type Symbol Description 48
LQFP
32
LQFP
32 QFN 24 QFN Unit Notes
Single-layer (1S) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
70 74 81 92 °C/W
Four-layer (2s2p) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
52 52 28 36 °C/W
RθJB Thermal resistance, junction
to board
36 35 13 18 °C/W 2
RθJC Thermal resistance, junction
to case
27 26 2.3 3.7 °C/W 3
ΨJT Thermal characterization
parameter, junction to
package top outside center
(natural convection)
8 8 8 10 °C/W 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 16. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 SWD_CLK frequency of operation
Serial wire debug
0
25
MHz
J2 SWD_CLK cycle period 1/J1 ns
J3 SWD_CLK clock pulse width
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 16. SWD full voltage range electricals (continued)
Symbol Description Min. Max. Unit
Serial wire debug 20 ns
J4 SWD_CLK rise and fall times 3 ns
J9 SWD_DIO input data setup time to SWD_CLK rise 10 ns
J10 SWD_DIO input data hold time after SWD_CLK rise 0 ns
J11 SWD_CLK high to SWD_DIO data valid 32 ns
J12 SWD_CLK high to SWD_DIO high-Z 5 ns
J2
J3 J3
J4 J4
SWD_CLK (input)
Figure 4. Serial wire clock input timing
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
Figure 5. Serial wire data timing
Peripheral operating requirements and behaviors
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3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 17. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
32.768 kHz
fints_t Internal reference frequency (slow clock) —
user trimmed
31.25 39.0625 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
± 0.3 ± 0.6 %fdco 1
Δfdco_t Total deviation of trimmed average DCO output
frequency over voltage and temperature
+0.5/-0.7 ± 3 %fdco 1, 2
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
± 0.4 ± 1.5 %fdco 1, 2
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
4 MHz
Δfintf_ft Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/-2 ± 3 %fintf_ft 2
fintf_t Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
kHz
FLL
ffll_ref FLL reference frequency range 31.25 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS = 00)
640 × ffll_ref
20 20.97 25 MHz 3, 4
Mid range (DRS = 01)
1280 × ffll_ref
40 41.94 48 MHz
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS = 00)
732 × ffll_ref
23.99 MHz 5, 6
Mid range (DRS = 01) 47.97 MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 17. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
1464 × ffll_ref
Jcyc_fll FLL period jitter
fVCO = 48 MHz
180 ps 7
tfll_acquire FLL target frequency acquisition time 1 ms 8
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz
500
200
300
950
1.2
1.5
nA
μA
μA
μA
mA
mA
1
IDDOSC Supply current — high gain mode (HGO=1)
32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
25
400
500
2.5
3
4
μA
μA
μA
mA
mA
mA
1
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 18. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
24 MHz
32 MHz
CxEXTAL load capacitance 2, 3
CyXTAL load capacitance 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
10 MΩ
Feedback resistor — high-frequency, low-
power mode (HGO=0)
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1 MΩ
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
200 kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
0
kΩ
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6 V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
VDD V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
0.6 V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
Peripheral operating requirements and behaviors
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