MC14558BD - ON Semiconductor - Datasheet.Directory

MOTOROLA CMOS LOGIC DATA 1

MC14558B

 



The MC14558B decodes 4–bit binary coded decimal data dependent on

the state of auxiliary inputs, Enable and RBI, and provides an active–high

seven–segment output for a display driver.

An auxiliary input truth table is shown, in addition to the BCD to

seven–segment truth table, to indicate the functions available with the two

auxiliary inputs.

Leading Zero blanking is easily obtained with an external flip–flop in time

division multiplexed systems displaying most significant decade first.

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Segment Blanking for All Illegal Input Combinations

•Lamp Test Function

•Capability for Suppression of Non–Significant Zeros

•Lamp Intensity Function

•Capable of Driving Two Low–power TTL Loads. One Low–power

Schottky TTL Load or Two HTL Loads Over the Rated Temperature

Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS* (Voltages referenced to VSS)

Rating Symbol Value Unit

DC Supply Voltage VDD – 0.5 to + 18 V

Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 V

DC Input Voltage, per Pin Iin ± 10 mAdc

Operating Temperature Range TA– 55 to + 125

Power Dissipation, per Package† PD500 mW

Storage Temperature Range Tstg – 65 to + 150

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

Ceramic “L” Packages: – 12 mW/

C From 100

C To 125

AUXILIARY INPUT TRUTH TABLE

Enable

Pin 3 RBI

Pin 5

BCD

Input

Code RBO

Pin 4 Function Performed

0 0 X 0 Lamp Test

0 1 X 1 Blank Segments

1 1 0 1 Display Zero

1 0 0 0 Blank Segments

1 X 1 – 9 1 1–9 Displayed

X = Don’t Care

RBI = Ripple Blanking Input

RBO = Ripple Blanking Output



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

PIN ASSIGNMENT

125

VDD

RBO

ENABLE

VSS

RBI

0 1 2 3 4 5 6 7 8 9

DISPLAY

MOTOROLA CMOS LOGIC DATAMC14558B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Symbol

VDD

Vdc

– 55

C 25

C 125

Unit

Characteristic

Symbol

VDD

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage “0” Level

Vin = VDD or 0 VOL 5.0

—

0.05

—

0.05

—

0.05

Vdc

“1” Level

Vin = 0 or VDD VOH 5.0

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

—

4.95

9.95

14.95

—

Vdc

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL 5.0

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

Vdc

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH 5.0

3.5

7.0

—

3.5

7.0

2.75

5.50

8.25

—

3.5

7.0

—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH 5.0

5.0

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

mAdc

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

Input Current Iin 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc

Input Capacitance Cin — — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package) Vin = 0 or VDD

Iout = 0 µA

IDD 5.0

—

5.0

—

0.005

0.010

0.015

5.0

—

150

300

600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

IT5.0

IT = (1.2 µA/kHz) f + IDD

IT = (2.4 µA/kHz) f + IDD

IT = (3.6 µA/kHz) f + IDD

µAdc

#Noise immunity specified for worst–case input combination.

Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V

=2.0 V min @ VDD = 10 V

=2.5 V min @ VDD = 15 V

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf

where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.

**The formulas given are for the typical characteristics only at 25

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however ,

it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this

high-impedance circuit. For proper operation it is recommended that V in and Vout be constrained to the range VSS ≤ (Vin or

Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

MOTOROLA CMOS LOGIC DATA 3

MC14558B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25

C; see Figure 1)

Characteristic Symbol VDD Min Typ Max Unit

Output Rise Time

tTLH = (3.0 ns/pF) CL + 30 ns

tTLH = (1.5 ns/pF) CL + 15 ns

tTLH = (1.1 ns/pF) CL + 10 ns

tTLH 5.0

—

100

200

100

Output Fall Time

tTHL = (1.5 ns/pF) CL + 25 ns

tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 9.5 ns

tTHL 5.0

—

100

200

100

Propagation Delay Time

tPLH = (1.7 ns/pF) CL + 495 ns

tPLH = (0.66 ns/pF) CL + 187 ns

tPLH = (0.5 ns/pF) CL + 120 ns

tPLH 5.0

—

580

220

145

1160

440

230

Propagation Delay Time

tPHL = (1.7 ns/pF) CL + 695 ns

tPHL = (0.66 ns/pF) CL + 242 ns

tPHL = (0.5 ns/pF) CL + 160 ns

tPHL 5.0

—

—780

275

185

1560

550

370

*The formulae given are for the typical characteristics only.

TRUTH TABLE

Inputs Outputs*

Enable

Pin 3 RBI

Pin 5 D

Pin 6 C

Pin 2 B

Pin 1 A

Pin 7 a

Pin 13 b

Pin 12 c

Pin 11 d

Pin 10 e

Pin 9 f

Pin 15 g

Pin 14 RBO

Pin 4 Display

1 1 0 0 0 0 1 1 1 1 1 1 0 1

1 X 0 0 0 1 0 0 0 0 1 1 0 1

1 X 0 0 1 0 1 1 0 1 1 0 1 1

1 X 0 0 1 1 1 1 1 1 0 0 1 1

1 X 0 1 0 0 0 1 1 0 0 1 1 1

1 X 0 1 0 1 1 0 1 1 0 1 1 1

1 X 0 1 1 0 0 0 1 1 1 1 1 1

1 X 0 1 1 1 1 1 1 0 0 0 0 1

1 X 1 0 0 0 1 1 1 1 1 1 1 1

1 X 1 0 0 1 1 1 1 0 0 1 1 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 Blank

0 0 X X X X 1 1 1 1 1 1 1 0

0 1 X X X X 0 0 0 0 0 0 0 1 Blank

*All non–valid BCD input codes produce a blank display.

X = Don’t Care

Figure 1. Signal Waveforms

20 ns 20 ns

10% 90% 50%

tPLH tPHL

50% 10%

90%

tTLH tTHL

ANY OUTPUT

ANY INPUT

MOTOROLA CMOS LOGIC DATAMC14558B

LOGIC DIAGRAM

RBO

ENABLE

RBI

MOTOROLA CMOS LOGIC DATA 5

MC14558B

TYPICAL APPLICATIONS

Figure 2. Leading and Trailing Zero

Suppression with Lamp Test

VSS

LAMP TEST

N4 N3 N2 N1 N–1 N–2 N–3

En En En En En En En

VSS

RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO

N4 N3 N2 N1 N–1 N–2 N–3

En En En En En En En

RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO

Figure 3. Leading and Trailing Zero Suppression

with PWM Intensity Blanking and No Lamp Test

BLANKING

VDD

N4 N3 N2 N1 N–1 N–2 N–3

En En En En En En En

RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO

Figure 4. Zero Suppression with Lamp Test

and Intensity Blanking

LAMP TEST

BLANKING

MOTOROLA CMOS LOGIC DATAMC14558B

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

HGD

16 PL

SEATING

1 8

916

PLANE

–T–

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

–A–

–B–

–T–

SEATING

PLANE

16 PLD

0.25 (0.010) T

16 PLJ

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.750 0.785 19.05 19.93

B0.240 0.295 6.10 7.49

C––– 0.200 ––– 5.08

D0.015 0.020 0.39 0.50

E0.050 BSC 1.27 BSC

F0.055 0.065 1.40 1.65

G0.100 BSC 2.54 BSC

H0.008 0.015 0.21 0.38

K0.125 0.170 3.18 4.31

L0.300 BSC 7.62 BSC

M0 15 0 15

N0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA 7

MC14558B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

RX 45

8 PLP

–B–

–A–

0.25 (0.010) B S

–T–

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

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MC14558B/D

*MC14558B/D*

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