EDE5104ABSE-5A-E - Elpida Memory, Inc.

Document No. E0323E20 (Ver. 2.0)

Date Published December 2002 (K) Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2002

PRELIMINARY DATA SHEET

512M bits DDR-II SDRAM

EDE5104A BSE (128M words ×

××

× 4 bits)

EDE5108A BSE (64M words ×

××

× 8 bits)

EDE5116A BSE (32M words ×

××

× 16 bits)

Description

The EDE5104AB is a 512M bits DDR-II SDRAM

organized as 33,554,432 words × 4 bits × 4 banks.

The EDE5108AB is a 512M bits DDR-II SDRAM

organized as 16,777,216 words × 8 bits × 4 banks.

It packaged in 64-ball FBGA (µBGA) package.

The EDE5116AB is a 512M bits DDR-II SDRAM

organized as 8,388,608 words × 16 bits × 4 banks.

It is packaged in 84-ball FBGA (µBGA) package.

Features

• 1.8V power supply

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• Burst lengths: 4, 8

• /CAS Latency (CL): 3, 4, 5

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• 7.8µs average periodic refresh interval

• 1.8V (SSTL_18 compatible) I/O

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• Programmable RDQS, /RDQS output for making × 8

organization compatible to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation.

• FBGA(µBGA) package is lead free solder (Sn-Ag-Cu)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Ordering Information

Part number Mask

version Organization

(words × bits) Internal

Banks Data rate

(Mbps)

/CAS latency

Package

EDE5104ABSE-5A-E

EDE5104ABSE-4A-E B 128M × 4 4 533

400 4, 5

3, 4, 5 64-ball FBGA (µBGA)

EDE5108ABSE-5A-E

EDE5108ABSE-4A-E 64M × 8 533

400 4, 5

3, 4, 5

EDE5116ABSE-5A-E

EDE5116ABSE-4A-E 32M × 16 533

400 4, 5

3, 4, 5 84-ball FBGA (µBGA)

Part Number

Elpida Memory

Density / Bank

51: 512M /4 banks

Bit Organization

04: x4

08: x8

16: x16

Voltage, Interface

A: 1.8V, SSTL_18

Die Rev.

Package

SE: FBGA (µBGA with back cover)

Speed

5A: 533Mbps

4A: 400Mbps

Product Code

E: DDR-II

Type

D: Monolithic Device

E D E 51 04 A B SE - 4A - E

Lead Free

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Pin Configurations

/xxx indicates active low signal.

VDD

DQ6

(NC)*

VDDQ

DQ4

(NC)*

VDDL

VSS

VDD

NU/ /RDQS

(NC)*

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A12

VSS

DM/RDQS

(DM)*

VDDQ

DQ3

VSS

/WE

BA1

VSSQ

DQS

VDDQ

DQ2

VSSDL

/RAS

/CAS

A11

/DQS

VSSQ

DQ0

VSSQ

/CK

/CS

A13

VDDQ

DQ7

(NC)*

VDDQ

DQ5

(NC)*

VDD

VSS

(Top view)

64-ball FBGA (µBGA)

Note: ( )* marked pins are for ×4 organization.

ODT

(×8, ×4 organization)

VDD

VDDQ

VDD

VDDL

VSSQ UDMDQ14

DQ9

VSSQDQ12

VREF

VSSNC

VDDQ

DQ11

VSS

CKE /WE

VSS

VSSQ

UDQS

VDDQ

DQ10

VSSQ

/RAS

/UDQS

VSSQ DQ15

DQ8

VSSQ DQ13

/LDQS

/CK

RVDD A12 NC NC NC

VDDQ

DQ6

DQ4

VSSQ

DQ1VDDQ

VSSQ

LDM

VDDQ

DQ3

LDQS

VDDQ

VSSQ

DQ0 VDDQ

DQ2 VSSQ DQ5

DQ7

VDDQ

VSSDL CK VDD

VSS

A10

A11

VDD

VSS

(Top view)

84-ball FBGA (µBGA)

BA0 BA1 /CAS /CSNC

ODT

(×16 organization)

NC NC

NCNC

Pin nam e Function Pin nam e Function

A0 to A13 Address i nputs ODT ODT control

BA0, BA1 Bank s el ect VDD Supply vol t age for internal circuit

DQ0 to DQ15 Data input/output VSS Ground for internal circuit

DQS, /DQS

UDQS, /UDQS

LDQS, /LDQS Different ial data strobe VDDQ Supply volt age f or DQ circuit

RDQS, /RDQS Differential data strobe for read VSSQ Ground for DQ circuit

/CS Chip select VREF Input reference voltage

/RAS, /CAS, /WE Command input VDDL Supply voltage for DLL circui t

CKE Clock enable VSSDL Ground for DLL circuit

CK, /CK Differential Cloc k input NC*1 No connection

DM, UDM, LDM Write Data mask NU*2 Not usable

Notes: 1. Not internally connected with die.

2. Don’t use other than reserved functions.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

CONTENTS

Description.....................................................................................................................................................1

Features.........................................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Pin Configurations .........................................................................................................................................3

Electric al Specific atio ns.................................................................................................................................5

Block Diagram .............................................................................................................................................10

Pin Function................................................................................................................... ..............................11

Command Operation ...................................................................................................................................13

Simplif ied Sta te D iagr am.............................................................................................................................20

Operation of DDR-II SDRAM.......................................................................................................................21

Package Drawing ........................................................................................................................................54

Recommended Soldering Conditions..........................................................................................................54

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Electrical Specifications

• All voltages are referenced to VSS (GND)

• Execute power-up and Initialization sequence before proper device operation is achieved.

Absolute Maximum Ratings

Parameter Symbol Rating Unit Note

Power supply voltage VDD –0.5 to +2. 3 V 1

Power supply voltage for output VDDQ –0.5 to +2.3 V 1

Input volt age VIN –0.5 to +2.3 V 1

Output volt age VOUT –0.5 to +2.3 V 1

Operating temperature (ambient) TA 0 to +70 °C 1

Storage temperature TSTG –55 to +150 °C 1

Power dissipat i on PD 1.0 W 1

Short ci rcuit output current IOUT 50 mA 1

Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (SSTL_18)

• There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all

conditions VDDQ must be less than or equal to VDD.

Parameter Symbol min. Typ. max. Unit Notes

Supply volt age VDD 1.7 1.8 1.9 V 4

Supply voltage for output VDDQ 1.7 1.8 1.9 V 4

Input reference voltage VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 1, 2

Terminat i on vol tage VTT VREF – 0.04 VREF VREF + 0.04 V 3

DC input logic high VIH (dc) VREF + 0.125  VDDQ + 0.3V V

DC input low VIL (dc) –0.3  VREF – 0.125 V

AC input logi c high VIH (ac) VREF + 0.250   V

AC input low VIL (ac)   VREF – 0.250 V

Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically

the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected

to track variations in VDDQ.

2. Peak to peak AC noise on VREF may not exceed ±2% VREF (dc).

3. VTT of transmitting device must track VREF of receiving device.

4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and

VDDL tied together.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

DC Characteristics 1 (TA = 0 to +70°

°°

°C, VDD, VDDQ = 1.8V ± 0.1V)

max.

Parameter Symbol Grade × 4, × 8 × 16 Unit Test condition

Operating current

(ACT-PRE) IDD0 TBD TBD mA

one bank; tRC = tRC (min. ) ; tCK = tCK (min.) ; DQ,

DM, and DQS inputs changing twice per clock cycle;

address and c ontrol inputs changing once per cl ock

cycle

Operating current

(ACT-READ-PRE) IDD1 TBD TBD mA

one bank; Burst = 4; t RC = t RC (min.) ;

CL = 4; tCK = tCK (min.) ; IOUT = 0mA;

address and c ontrol inputs changing once per cl ock

cycle

Precharge power-down

standby c urrent IDD2P TBD TBD mA all banks idle; power-down mode; CK E = VIL (max.);

tCK = tCK (min.)

Idle st andby current IDD2N TBD TBD mA /CS = VIH (min.); all banks idle; CKE = VIH (min.);

tCK = tCK (min.) ; address and cont rol i nputs

changing once per clock cycle

Active power-down

standby c urrent IDD3P TBD TBD mA one bank active; power-down mode; CK E = VIL

(max.);

tCK = tCK (min.)

Acti ve standby current IDD3N TBD TBD mA

one bank; ac tive;/CS = V IH (min.);

CKE = VIH (min.); tRC = tRAS max; tCK = tCK

(min.); DQ, DM, and DQS i nputs changing twice per

clock cycle; address and c ontrol inputs changing

once per clock cyc l e

Operating current

(Burst read operating) IDD4R TBD TBD mA

one bank; Burst = 4; burs t; address and control

inputs changing once per cl ock cyc l e; DQ and DQS

outputs changing twice per cl ock cyc l e; CL = 4; tCK

= tCK (min.) ; IOUT = 0mA

Operating current

(Burst write operating) IDD4W TBD TBD mA

one bank; Burst = 4; writes; continuous burst;

address and c ontrol inputs changing once per cl ock

cycle; DQ and DQS inputs changing twice per cl ock

cycle; CL = 4;

tCK = tCK (min.)

Auto-refresh current IDD5 TB D TBD mA tRC = tRFC (min.)

Self-ref resh current IDD6 TBD TBD mA S el f Refresh Mode; CKE = 0.2V

Operating current

(Bank interleaving) IDD7 TBD TBD mA

Four bank interl eavi ng RE ADs (BL4) with auto

precharge, t RC = t RC (min.); Address and control

inputs change during Active, REA D, or WRITE

commands.

DC Characteristics 2 (TA = 0 to +70°

°°

°C, VDD, VDDQ = 1.8V ± 0.1V)

Parameter Symbol Unit Notes

Minimum required output pul l -up under A C

test l oad VOH VTT + 0.603 V 5

Maximum required output pull-down under

AC test load VOL VTT – 0. 603 V 5

Output ti ming measurem ent reference level VOTR 0.5 × VDDQ V 1

Output minim um si nk DC current IOL +13.4 mA 3, 4, 5

Output minimum s ource DC current IOH –13.4 mA 2, 4, 5

Note: 1. The VDDQ of the device under test is referenced.

2. VDDQ = 1.7V; VOUT = 1.42V.

3. VDDQ = 1.7V; VOUT = 0.28V.

4. The DC value of VREF applied to the receiving device is expected to be set to VTT.

5. After OCD calibration to 18Ω at TA = 25°C, VDD = VDDQ = 1.8V.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Pin Capacitance (TA = 25°C, VDD, VDDQ = 1.8V ± 0.1V)

Parameter Symbol Pins min. Typ max. Unit

Notes

CLK input pin capacit ance CCK CK 1.5 2.0 2.5 pF 1

Input pin capacitance CIN

/RAS, /CAS,

/W E, /CS,

CKE. ODT ,

Address

1.5 2.0 2.5 pF 1

Input/output pin capacitance CI/O

DQ, DQS, /DQS,

UDQS, /UDQS ,

LDQS, /LDQS ,

/RDQS, /RDQS,

DM, UDM, LDM

3.0 3.5 4.0 pF 2

Notes: 1. Matching within 0.25pF.

2. Matching within 0.50pF.

AC Characteristics (TA = 0 to +70°

°°

°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)

-5A -4A

Frequency (Mbps) 533 400

Parameter Symbol min. max. min. max. Unit Notes

DQ output access time from CK, /CK tAC –500 +500 –600 +600 ps

DQS output access time from CK, /CK tDQSCK –450 +450 –500 +500 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP min.

(tCL, t CH)  min.

(tCL, t CH)  ps

Clock cycle time tCK 3750 8000 5000 8000 ps

DQ and DM input hold time tDH 350  400  ps

DQ and DM input setup time tDS 350  400  ps

Control and Addres s input puls e width

for each input tIPW 0.6  0.6  tCK

DQ and DM input pulse width f or each

input tDIPW 0.35  0.35  tCK

Data-out high-i mpedance t i me from

CK,/CK tHZ  tAC max.  tAC max. ps

Data-out low-im pedance time from

CK,/CK tLZ tAC min. tAC max. tAC min. tAC max. ps

DQS-DQ skew for DQS and associated

DQ signals tDQSQ  300  350 ps

DQ hold skew fac tor tQHS  400  450 ps

DQ/DQS output hol d time from DQS tQH tHP – tQHS  tHP – tQHS  ps

Write c omm and to first DQS latc hi ng

transition tDQSS WL – 0.25 WL + 0.25 WL – 0.25 WL + 0.25 tCK

DQS input high pul se width tDQSH 0.35  0.35  tCK

DQS input low pulse width tDQSL 0.35  0.35  tCK

DQS falli ng edge to CK set up time tDSS 0.2  0.2  tCK

DQS falli ng edge hol d time from CK tDSH 0.2  0.2  tCK

Mode register s et command cycl e time tMRD 2  2  tCK

Write preamble set up time tWPRE S 0  0  tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.25  0.25  tCK

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

-5A -4A

Frequency (Mbps) 533 400

Parameter Symbol min. max. min. max. Unit Notes

Address and control input hol d time tIH 500  600  ps

ddress and A control input setup time tIS 500  600  ps

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Acti ve to precharge comm and tRAS 45  45  ns

Active to act i ve/ auto refresh c omm and

time tRC 60  65  ns

Act i ve t o read or write command delay tRCD 15  20  ns

Precharge co mmand peri od tRP 15  20  ns

Act i ve t o aut o-precharge delay tRA P tRCD mi n.  tRCD min.  ns

Act i ve bank A to ac t i ve bank B

com mand period

(EDE5104AB , EDE5108AB ) tRRD 7.5  10  ns

(EDE5116AB) tRRD 10  10  ns

Write recovery time t WR 15  15  ns

Auto precharge write recovery +

precharge time tDAL (tWR/tCK)+

(tRP/tCK)  (tWR/tCK)+

(tRP/tCK)  tCK 1

Internal write t o read command delay tWTR 7.5  10  ns

Exit self refresh to any c omm and tXSC 200  200  tCK

Exit power down to any non-read

command tXPNR 2  2  tCK

Exit precharge power down to read

command tXPRD 6 – AL  6 – AL  tCK 2

Exit acti ve power down to read

command tXARD 2  2  tCK 3

Exit acti ve power down to read

command

(slow exit/low power mode) tXARDS 6 – AL  6 – AL  tCK 3

Output impedance test driver delay tOIT 0 12 0 12 ns

Auto refresh to act i ve/auto refresh

com mand time tRFC 105  105  ns

Average periodic refresh interval tREFI  7.8  7.8 µs

Notes: 1. For each of the terms above, if not already an integer, round to the next highest integer.

2. AL: Additive Latency.

3. MRS A12 bit define which active power down exit timing to be applied.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

AC Electrical Characteristics and Operating Conditions

Parameter Symbol min max Unit Notes

ODT turn-on delay tAOND 2 2 tCK

ODT turn-on tAON tAC(min) tAC(max) + 1000 ps 1

ODT turn-on (power - down mode) tAONPD tAC(min) + 2000 2tCK + tAC(max) + 1000 ps

ODT turn-off del ay tAOFD 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max) + 600 ps 2

ODT turn-off (power - down mode) tAOFPD t AC(min) + 2000 2.5tCK + tAC(max) + 1000 ns

Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

2. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

Test Conditions

VTT

VREF

/CLK

CLK

VREF

VSS

SLEW = (VIH (ac) – VIL (ac))/∆t

Measurement point

VIH

VIL

VDD

VSS

DQ RT =25 Ω

∆t

tCL

tCK

tCH

VSWING

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Block Diagram

A0 to A13, BA0, BA1

/CS

/RAS

/CAS

/WE

Command decoder

Input & Output buffer

Latch circuit

Data control circuit

Column decoder

Row decoder

Memory cell array

Bank 0

Sense amp.

Bank 1

Bank 2

Bank 3

Control logic

Column

address

buffer

and

burst

counter

Row

address

buffer

and

refresh

counter

Mode

Clock

generator

/CK

CKE

DQS, /DQS

DLLCK, /CK RDQS, /RDQS

ODT

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Pin Function

CK, /CK (input pins)

CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the

positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK

(both directions of crossing).

/CS (input pin)

All commands are masked when /CS is registered High. /CS provides for external bank selection on systems with

multiple banks. /CS is considered part of the command code.

/RAS, /CAS, /WE (input pins)

/RAS, /CAS and /WE (along with /CS) define the command being entered.

A0 to A13 (input pins)

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write

commands to select one location out of the memory array in the respective bank.

[Address Pins Table]

Address (A 0 to A13)

Part number Row address Column address Notes

EDE5104AB AX0 to AX13 AY0 to A Y9, AY11

EDE5108AB AX0 to AX13 AY0 to A Y9

EDE5116AB AX0 to AX12 AY0 to A Y9 1

Notes: 1. A13 pin is NC for ×16 organization.

A10 (AP) (input pin)

A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = Low)

or all banks (A10 = High). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address

inputs also provide the op-code during mode register set commands.

BA0, BA1 (input pins)

BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also

determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.

[Bank Select Signal Table]

BA0 BA1

Bank 0 L L

Bank 1 H L

Bank 2 L H

Bank 3 H H

Remark: H: VIH. L: VIL.

CKE (input pin)

CKE High activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers.

Taking CKE Low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down

(row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is

asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self

refresh.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

DM, UDM and LDM (input pins)

DM is an input mask signal for write data. In 32M × 16 products, UDM and LDM control upper byte (DQ8 to DQ15)

and lower byte (DQ0 to DQ7). Input data is masked when DM is sampled High coincident with that input data during

a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches

the DQ and DQS loading. For ×8 configuration, DM function will be disabled when RDQS function is enabled by

EMRS.

DQ (input/output pins)

Bi-directional data bus.

DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS (input/output pins)

Output with read data, input with write data for source synchronous operation. In 32M × 16 products, UDQS, /UDQS

and LDQS, /LDQS control upper byte (DQ8 to DQ15) and lower byte (DQ0 to DQ7). Edge-aligned with read data,

centered in write data. Used to capture write data. /DQS can be disabled by EMRS.

RDQS, /RDQS (output pins)

Differential Data Strobe for READ operation only. DM and RDQS functions are switch able by EMRS. These pins

exist only in ×8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS.

ODT (input pins)

ODT (On Die Termina tion control) is a registered High signal that enables termination re sistanc e internal to the DDR

II SDRAM. W hen enabled, ODT is only applied to each DQ, DQS, /DQS, RDQS, /RDQS, and DM signal for × 4, × 8

configurations. For × 16 configuration, ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM

signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT.

VDD, VSS, VDDQ, VSSQ (power supply)

VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output

buffers.

VDDL and VSSDL (power supply)

VDDL and VSSDL are power supply pins for DLL circuits.

VREF (Power supply)

SSTL_18 reference voltage: (0.50 ± 0.01) × VDDQ

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Command Operation

Command Truth Table

The DDR-II SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.

CKE

Function

Symbol Previous

cycle Current

cycle

/CS

/RAS

/CAS

/W E BA1,

BA0 A13 to

A11

A10 A0 to

Notes

Mode register set MRS H H L L L L BA0 = 0 and MRS OP Code 1

Extended mode register set EMRS H H L L L L BA0 = 1 and EMRS OP Code 1

Auto (CBR) refresh REF H H L L L H × × × × 1

Self refresh entry SELF H L L L L H × × × × 1

Self ref resh exit SELFX L H H × × × × × × × 1

Single bank precharge PRE H H L L H L BA × L × 1, 2

Precharge all banks PALL H H L L H L × × H × 1

Bank ac tivate ACT H H L L H H BA Row Address 1, 2

Write WRIT H H L H L L BA Column L Column 1, 2, 3

Write with auto precharge WRITA H H L H L L BA Column H Column 1, 2, 3

Read READ H H L H L H BA Column L Column 1, 2, 3

Read with auto precharge READA H H L H L H BA Column H Column 1, 2, 3

No operation NOP H × L H H H × × × × 1

Device des el ect DES L H × H × × × × × × × 1

Power down mode entry PDEN H L × × × × × × × × 1, 4, 5

Power down mode exit PDEX L H × × × × × × × × 1, 4, 5

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. All DDR-II commands are defined by states of /CS, /RAS, /CAS, /W E, and CKE at the rising edge of the

clock.

2. Bank Select (BA0, BA1), determine which bank is to be operated upon.

3. Burst reads or writes should not be terminated other than specified as ″Reads interrupted by a Read″ in

Burst Read command [READ] or ″Writes interrupted by a Write″ in Burst Write command [WRIT].

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is

therefore limited by the refresh requirements of the device. One clock delay is required for mode entry and

exit.

5. The state of ODT does not affect the states described in this table. The ODT function is not available

during Self Refresh.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

CKE Truth Table

CKE Command

Current state Function Previous

Cycle Current

Cycle

/CS

/RAS

/CAS

/W E BA1,BA0,

A13 to A0

Notes

Self refresh INVALID H × × × × × × 1

Exit self refresh with device

deselect L H H × × × × 2

Exit self refresh with no

operation L H L H H H × 2

Illegal L H L Command Address 2

Maintain self refresh L L × × × × ×

Power down INVA LID H × × × × × × 1

Power down mode exit L H H × × × × 2

ILLEGAL L H L

Command

except NOP Address 2

Maintain power down mode L L × × × × ×

All bank s idle Device deselect H H H × × × 3

Refer to the current st ate truth

table H H L Command Address 3

Power down H L H × × ×

down next cycl e H L L Command Address 3

Entry self refresh H L L L L H × 4

Refer to operati ons in the

current s tate truth table H H × × × × ×

Any st ate other

than lis t ed

above Power down entry H L × × × × × 5

ILLEGAL L × × × × × ×

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. For the given Current State CKE must be low in the previous cycle.

2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The

minimum setup time for CKE (tCES) must be satisfied before any command other than self refresh exit.

3. The inputs (BA1, BA0, A13 to A0) depend on the command that is issued. See the Command Truth Table

for more information.

4. The Auto Refresh, Self Refresh mode, and the Mode Register Set modes can only be entered from the all

banks idle state.

5. Must be a legal command as defined in the Command Truth Table.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Function Truth Table

The following tables show the operations that are performed when each command is issued in each state of the

DDR SDRAM.

Current state /CS /RAS /CAS /WE Address Command Operation Notes

Idle H × × × × DE SL Nop or Power down

L H H H × NOP Nop or Power down

L H L H

BA, CA, A10 (AP) READ ILLEGAL 1

L H L H

BA, CA, A10 (AP) READA ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H

BA, RA ACT Row activating

L L H L

BA, A10 (AP) PRE Precharge

L L H L

A10 (AP) PALL Precharge all banks

L L L H × REF Auto refresh 2

L L L H × SELF Self refresh 2

L L L L BA, MRS-OPCODE MRS Mode register acc essing 2

L L L L BA, EMRS-OPCODE EMRS Extended mode regi ster accessing 2

Bank(s ) active H × × × × DESL Nop

L H H H × NOP Nop

L H L H

BA, CA, A10 (AP) READ Begin Read

L H L H

BA, CA, A10 (AP) READA Begin Read

L H L L

BA, CA, A10 (AP) WRIT Begin Write

L H L L

BA, CA, A10 (AP) WRITA Begin Write

L L H H

BA, RA ACT ILLEGAL 1

L L H L

BA, A10 (AP) PRE Precharge

L L H L

A10 (AP) PALL Precharge all banks

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Read H × × × × DESL Continue burst to end -> Row active

L H H H × NOP Continue burst to end -> Row active

L H L H

BA, CA, A10 (AP) READ Burst interrupt 1, 4

L H L H

BA, CA, A10 (AP) READA Burst interrupt 1, 4

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H

BA, RA ACT ILLEGAL 1

L L H L

BA, A10 (AP) PRE ILLEGAL 1

L L H L

A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Current state /CS /RAS /CAS /WE Address Command Operation Note

Write H × × × × DESL

Continue burst to end

-> Write rec overi ng

L H H H × NOP

Continue burst to end

-> Write rec overi ng

L H L H

BA, CA, A10 (AP) READ ILLEGAL 1

L H L H

BA, CA, A10 (AP) READA ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRIT Burst interrupt 1, 4

L H L L

BA, CA, A10 (AP) WRITA Burst interrupt 1, 4

L L H H

BA, RA ACT ILLEGAL 1

L L H L

BA, A10 (AP) PRE ILLEGAL 1

L L H L

A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Read with H × × × × DESL Continue burs t to end -> Precharging

auto precharge L H H H × NOP Continue burst to end -> Precharging

L H L H

BA, CA, A10 (AP) READ ILLEGAL 1

L H L H

BA, CA, A10 (AP) READA ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H

BA, RA ACT ILLEGAL 1

L L H L

BA, A10 (AP) PRE ILLEGAL 1

L L H L

A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Write with auto

Precharge H × × × × DESL

Continue burst to end

->Write rec overi ng with auto precharge

L H H H × NOP

Continue burst to end

->Write rec overi ng with auto precharge

L H L H

BA, CA, A10 (AP) READ ILLEGAL 1

L H L H

BA, CA, A10 (AP) READA ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H

BA, RA ACT ILLEGAL 1

L L H L

BA, A10 (AP) PRE ILLEGAL 1

L L H L

A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Current state /CS /RAS /CAS /WE Address Command Operation Note

Precharging H × × × × DESL Nop -> Enter idle after tRP

L H H H × NOP Nop -> Enter idle after tRP

L H L H

BA, CA, A10 (AP) READ ILLEGAL 1

L H L H

BA, CA, A10 (AP) READA ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H

BA, RA ACT ILLEGAL 1

L L H L

BA, A10 (AP) PRE Nop -> Enter idle after tRP

L L H L

A10 (AP) PALL Nop -> Enter idle aft er t RP

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Row activating H × × × × DESL Nop -> Ent er bank active after tRCD

L H H H × NOP Nop -> Enter bank ac tive after tRCD

L H L H

BA, CA, A10 (AP) READ ILLEGAL 1

L H L H

BA, CA, A10 (AP) READA ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H

BA, RA ACT ILLEGAL 1

L L H L

BA, A10 (AP) PRE ILLEGAL

L L H L

A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Write rec o veri ng H × × × × DESL Nop -> Ent er bank active after tWR

L H H H × NOP Nop -> E n t er bank acti ve after tWR

L H L H

BA, CA, A10 (AP) READ ILLEGAL 1

L H L H

BA, CA, A10 (AP) READA ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRIT New write

L H L L

BA, CA, A10 (AP) WRITA New write

L L H H

BA, RA ACT ILLEGAL 1

L L H L

BA, A10 (AP) PRE ILLEGAL 1

L L H L

A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Current state /CS /RAS /CAS /WE Address Command Operation Note

Write rec overi ng

with H × × × × DESL Nop -> Enter bank active af t er tWR

auto precharge L H H H × NOP Nop -> Enter bank active after tWR

L H L H

BA, CA, A10 (AP) READ ILLEGAL 1

L H L H

BA, CA, A10 (AP) READA ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H

BA, RA ACT ILLEGAL 1

L L H L

BA, A10 (AP) PRE ILLEGAL 1

L L H L

A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Refresh H × × × × DESL Nop -> Enter idle after tRFC

L H H H × NOP Nop -> Enter idle after tRFC

L H L H

BA, CA, A10 (AP) READ ILLEGAL

L H L H

BA, CA, A10 (AP) READA ILLEGAL

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL

L L H H

BA, RA ACT ILLEGAL

L L H L

BA, A10 (AP) PRE ILLEGAL

L L H L

A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Mode register

accessing H × × × × DESL Nop -> Enter idle after tMRD

L H H H × NOP Nop -> Enter idle after tMRD

L H L H

BA, CA, A10 (AP) READ ILLEGAL

L H L H

BA, CA, A10 (AP) READA ILLEGAL

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL

L L H H

BA, RA ACT ILLEGAL

L L H L

BA, A10 (AP) PRE ILLEGAL

L L H L

A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Current st at e /CS / RA S /CAS /WE Address Command Operation Note

Extended Mode H × × × × DESL Nop -> Enter idle after tMRD

L H L H

BA, CA, A10 (AP) READ ILLEGAL

L H L H

BA, CA, A10 (AP) READA ILLEGAL

L H L L

BA, CA, A10 (AP) WRIT ILLEGAL

L H L L

BA, CA, A10 (AP) WRITA ILLEGAL

L L H H BA, RA ACT ILLEGAL

L L H L BA, A10 (AP) PRE ILLEGAL

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCODE MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. This command may be issued for other banks, depending on the state of the banks.

2. All banks must be in "IDLE".

3. All AC timing specs must be met.

4. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings are illegal.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Simplified State Diagram

INITALIZATION AUTO REFRESH SELF REFRESH

MRS

EMRS

tRFC

tRCD

tMRD

tRP

MRS

PRE

REF

ACT

IDLE

ACTIVATING

PRECHARGE

BANK ACTIVE

WL + BL/2 + tWR

WRITA

RL + BL/2 + tRTP

READA

WRITE

WRITA

READA

WRIT

READ

CKEH

CKEL

CKEH

PDEN

CKEL

PDEN

PRECHARGE

POWER

DOWN

CKEL

SELFX

SELF

PRE

READA

ACTIVE

POWER

DOWN

Automatic sequence

Command sequence

READ

Simplified State Diagram

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Operation of DDR-II SDRAM

Read and write accesses to the DDR-II SDRAM are burst oriented; accesses start at a selected location and

continue for the fixed burst length of four or eight in a programmed sequence. Accesses begin with the registration of

an Active command, which is then followed by a Read or Write command. The address bits registered coincident

with the active command is used to select the bank and row to be accessed (BA0, BA1 select the bank; A0 to A13

select the row). The address bits registered coincident with the Read or Write command are used to select the

starting column location for the burst ac cess and to determine if the auto precharge command is to be issued. Prior

to normal operation, the DDR-II SDRAM must be initialized. The following sections provide detailed information

covering device initialization; register definition, command descriptions and device operation.

Power On and Initialization

DDR-II SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to

VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause

permanent damage to the device. VREF can be applied any time after VDDQ, but is expected to be nominally

coincident with VTT. By attempting to maintain CKE Low, the DQ and DQS outputs are in the High-Z state during

power-up. After all power supply, reference voltages, and the clocks are stable, the DDR-II SDRAM requires a 200µs

delay prior to applying an executable command.

Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be

brought high. Issuing the NOP command during tRFC period, a Precharge ALL command must be applied. Next a

mode register set command must be issued for the extended mode register, to enable the DLL. Then a mode

parameters. 200 clock cycles are required between the DLL reset and any read command. Precharge ALL command

should be applied, placing the device in the “all banks idle” state.

Once in the idle state, two Auto Refresh cycles must be performed. Additionally, a mode register set command for

the mode register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL)

must be performed. Finally, OCD impedance adjustment should be performed. At least, ERMS OCD Default

command must be issued. Following these cycles, the DDR-II SDRAM is ready for normal operation. Failure to

follow these steps may lead to unpredictable start-up modes.

Power-Up and Initialization Sequence

The following sequence is required for Power-up and Initialization.

1. Apply power and attempt to maintain CKE and ODT at a low state (all other inputs may be undefined.)

 Apply VDD before or at the same time as VDDQ.

 Apply VDDQ before or at the same time as VTT and VREF.

2. Start clock and maintain stable condition for a minimum of 200µs.

3. The minimum of 200µs after stable power and clock(CK, /CK), apply NOP and take CKE High.

4. Wait tRFC then issue precharge commands for all banks of the device.

5. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide Low to A0, High to BA0 and

Low to all of the rest address pins, A1 to A11 and BA1)

6. Issue a mode register set command for DLL reset. The additional 200 cycles of clock input is required to

lock the DLL. (To issue DLL reset command, provide High to A8 and Low to BA0)

7. Issue precharge commands for all banks of the device.

8. Issue 2 or more auto-refresh commands.

9. Issue a mode register set command with low to A8 to initialize device operation.

10. Carry out OCD impedance adjustment (Follow “OCD Flow Chart” in the chapter of Off-Chip Driver (OCD)

Impedance Adjustment). At least, EMRS OCD Default Command (A9=A8=A7=1) must be issued. Whenever

issue extended mode register set command for OCD, keep previous setting of A0 to A6, A0 to A13 and BA1

Command EMRS

PALL MRS

tRPtRFC tMRD

200 cycles (min)

tMRD

tMRD tRP tRFC tRFC

PALL MRS

REF REF EMRS

DLL enable DLL reset

Follow OCD

Flowchart

Any

command

/CK

CKE

EMRS

OCD calibration mode

exit

tOIT

OCD drive(1)

NOP

Power up and Initialization Sequence

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Programming the Mode Register

For application flexibility, burst type, /CAS latency, DLL reset function are user defined variables and must be

programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive /CAS latency,

and variable data-output impedance adjustment are also user defined variables and must be programmed with an

Extended Mode Register Set (EMRS) command. Re-executing the MRS and EMRS Commands can alter contents

of the MRS and EMRS. Even though the user chooses to modify only a subset of the MRS or EMRS variables, all

variables must be redefined when the MRS or EMRS commands are issued.

After initial power up, the both MRS and EMRS Commands must be issued before read or write cycles may begin.

All four banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set

Command can be issued. Either MRS or EMRS Commands are activated by the low signals of /CS, /RAS, /CAS and

/WE at the positive edge of the clock. W hen the bank address 0 (BA0) is low, the DDR-II SDRAM enables the MRS

command. W hen the bank address 0 (BA0) is high, the DDR-II SDRAM enables the EMRS command. The address

input data during this cycle defines the parameters to be set as shown in the MRS and EMRS table. A new

command may be issued after the mode register set command cycle time (tMRD). MRS, EMRS and Reset DLL do

not affect array contents, which means reinitialization including those can be executed any time after power-up

without affecting array contents.

DDR-II SDRAM Mode Register Set [MRS]

The mode register stores the data for controlling the various operating modes of DDR-II SDRAM. It controls /CAS

latency, burst sequence, test mode, DLL reset and various vendor specific options to make DDR-II SDRAM useful

for various applications. The default value of the mode register is not defined, therefore the mode register must be

written after power-up for proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /W E

and BA0, while controlling the state of address pins A0 to A13. The DDR-II SDRAM should be in all bank precharge

with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is

required to complete the write operation to the mode register. The mode register contents can be changed using the

same command and clock cycle requirements during normal operation as long as all banks are in the precharge

state. The mode register is divided into various fields depending on functionality. Burst address sequence type is

defined by A3, and, /CAS latency is defined by A4 to A6. The DDR-II doesn’t support half clock latency mode. A7 is

used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. A9 to A11 are used

for define W rite Recovery time in clocks using for Auto Prec harge. Users are required to set the appropriate values

according to tWR spec and operating frequency of the systems.

A12 is used for Active Power Down exit timing selection. If Slow exit is set, DLL is turned off during Active Power

Down, then Asynchronous ODT timings and tXARDS timing for exit should be used. Refer to the table for specific

codes.

*BA1, A12 and A13 are reserved for future use and must be programmed to 0 when setting the mode register.

00*

BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address field

0*0*

BA1

DLL reset

Yes

DLL TM /CAS latency BT Burst length Mode register

Mode

Normal

Test

/CAS latency

Latency

Reserved

Burst type

Sequential

Interleave

A12

Active power down exit timing

Fast exit (use tXARD timing)

Slow exit (use tXARDS timing)

Burst length

A11

WR for Auto Precharge

A10

Reserved

BA1

MRS mode

MRS

EMRS(1)

EMRS(2): Reserved

EMRS(3): Reserved

BA0

Mode Register Set (MRS)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

DDR-II SDRAM Extended Mode Register Set [EMRS]

The extended mode register stores the data for enabling or disabling the DLL, output driver strength and additive

latency. The default value of the extended mode register is not defined, therefore the extended mode register must

be written after power-up for proper operation. The extended mode register is written by asserting low on /CS, /RAS,

/CAS, /WE and High on BA0, wh ile controlling the states of address pins A0 to A13. The DDR-II SDRAM should be

in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set

command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode

as long as all banks are in the prec harge state. A0 is used for DLL enable or disable. A1 is used for enabling a half

strength data-output driver. A3 to A5 determines the additive latency, A7 to A9 are used for OCD control, A10 is

used for /DQS enable and A11 is used for RDQS enable. A12 is used for Qoff (output buffers disable).

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon

returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self

refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled

(and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the

internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a

violation of the tAC or tDQSCK parameters.

*1: BA1 and A13 are reserved for future use, and must be programmed to 0 when setting the extended mode register.

*2: Refer to the chapter "Off-chip Driver (OCD) impedance Adjustment" for detailed information

A13BA0BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address field

A11

RDQS enable

Disable

Enable

10*0*

/DQS

OCD program ODT Additive latency ODT D.I.C DLL Extended mode register

A10

/DQS enable

Enable

Disable

Additive latency

Latency

Reserved

DLL enable

Enable

Disable

BA1

MRS mode

MRS

EMRS(1)

EMRS(2): Reserved

EMRS(3): Reserved

ODT

(nominal Rtt)

ODT Disabled

150

Reserved

Driver impedance adjustment*

OCD calibration mode exit

Drive(1)

Drive(0)

Adjust mode

OCD calibration Default

Driver strength control

Output Driver

Impedance Control

Normal

Weak

Driver

Size

100%

60%

Operation

RDQS

Qoff

BA0

A12

Qoff

Output buffers enabled

Output buffers disabled

Extended Mode Register Set (EMRS)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

[Pin Function Matrix for RDQS, /RDQS, /DQS]

RDQS enable

(A11) /DQS enable

(A10) DM/ RDQS /RDQS /DQS

0(disable) 0(enable) DM High - Z /DQS

0(disable) 1(disable) DM High - Z High - Z

1(enable) 0(enable) RDQS /RDQS /DQS

1(enable) 1(disable) RDQS High - Z High - Z

Off-Chip Driver (OCD) Impedance Adjustment

DDR-II SDRAM supports driver calibration feature and the “OCD Flow Chart ” is an example of sequence. Every

calibration mode command should be followed by “OCD calibration mode exit” before any other command being

issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be

carefully controlled depending on system environment.

Test Test

ALL OK ALL OK

Need calibration Need calibration

EMRS: OCD calibration mode exit

MRS should be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

EMRS: Drive(0)

DQ & DQS Low ; /DQS High

EMRS: Drive(1)

DQ & DQS High ; /DQS Low

EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit

EMRS :

Enter Adjust Mode

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

Start

End

OCD Flow Chart

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Extended Mode Register Set for OCD Impedance Adjustment

OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out

by DDR-II SDRAM and drive of RDQS is dependent on EMRS bit enabling RDQS operation. In Drive(1) mode, all

DQ, DQS (and RDQS) signals are driven high and all /DQS signals are driven low. In drive(0) mode, all DQ, DQS

(and RDQS) signals are driven low and all /DQS signals are driven high.

In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver

characteristics follow approximate nominal V/I curve for 18Ω output drivers, but are not guaranteed. If tighter control

is required, which is controlled within 18Ω ± 3Ω driver impedance range, OCD must be used.

[OCD Mode Set Program]

A9 A8 A7 Operation

0 0 0 OCD calibration mode exit

0 0 1 Drive (1) DQ, DQS, (RDQS) High and /DQS Low

0 1 0 Drive (0) DQ, DQS, (RDQS) Low and /DQS High

1 0 0 Adjust mode

1 1 1 OCD calibration default

OCD Impedance Adjustment

To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst

code to DDR-II SDRAM as in table X. For this operation, burst length has to be set to BL = 4 via MRS command

before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in table X means

all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR-II

SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR-II SDRAM will be adjusted to the

same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further

increment or decrement code has no effect. The default setting may be any step within the 16 step range.

[OCD Adjustment Program]

4bits burst data input s to all DQs Operation

DT0 DT1 DT2 DT3 Pull-up dri ver s trength P ul l -down driver strength

0 0 0 0 NOP NOP

0 0 0 1 Increase by 1 step NOP

0 0 1 0 Dec rease by 1 step NOP

0 1 0 0 NOP Increase by 1 step

1 0 0 0 NOP Decrease by 1 step

0 1 0 1 I ncrease by 1 st ep Increase by 1 step

0 1 1 0 Dec rease by 1 step Increase by 1 step

1 0 0 1 I ncrease by 1 st ep Decrease by 1 step

1 0 1 0 Decrease by 1 step Decrease by 1 st ep

Other combinations Reserved

For proper operation of adjust mode, WL = RL − 1 = AL + CL − 1 clocks and tDS/tDH should be met as the following

timing diagram. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not affected by MRS

addressing mode (ie.sequentialorinterleave).

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

For proper operation of adjust mode , W L = RL − 1 = AL + CL − 1 clock s and t DS/t DH shou ld be me t as t he “Ou tput

Impedance Control Register Set Cycle”. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not

affected by MRS addressing mode (i.e. sequential or interleave).

Command EMRS

OCD adjust mode OCD calibration mode exit

NOP

DT0

tDS tDH

DT1 DT2 DT3

NOPEMRS

/CK

WL tWR

DQS, /DQS

DQ_in

Output Impedance Control Register Set Cycle

Drive Mode

Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR-II SDRAM Driver impedance before

OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “Enter drive mode” command and all

output drivers are turned-off tOIT after “OCD calibration mode exit” command as the ”Output Impedance

Measurement/Verify Cycle”.

Command

Enter drivemode OCD Calibration mode exit

NOP

/CK

DQS, /DQS High-Z High-Z

DQs High for drive (1)

DQs Low for drive (0)

tOIT

EMRS EMRS

tOIT

Output Impedance Measurement/Verify Cycle

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

ODT(On Die Termination)

On Die Termination (ODT), is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS,

/DQS, RDQS, /RDQS, and DM signal for × 4 × 8 configurations via the ODT control pin. For × 16 configuration ODT

is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM signal via the ODT control pin. The ODT

feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to

independently turn on/off termination resistance for any or all DRAM devices.

The ODT function is turned off and not supported in self refresh mode.

Switch sw1 or sw2 is enabled by ODT pin.

Selection between sw1 or sw2 is determined by Rtt (nomial) in EMRS

Termination included on all DQs, DM, DQS, /DQS, RDQS and /RDQS pins.

Target Rtt ( ) = (Rval1) / 2 or (Rval2) / 2

DRAM

input

buffer

VDDQ

VSSQ

sw1

sw1 sw2

Rval1

Input

VDDQ

VSSQ

sw2

Rval2

Functional Representation of ODT

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

DC Electrical Characteristics and Operating Conditions

Parameter Symbol min Typ max Unit Notes

Rtt effecti ve impedance val ue f o r E MRS (A6, A2) = 0, 1 ; 75 Ω Rtt1(eff) 60 75 90 Ω 1

Rtt effecti ve impedance val ue f o r E MRS (A6, A2) = 1, 0 ; 150 Ω Rtt2(eff) 120 150 180 Ω 1

Rtt mismatch tolerance between any pull-up and pull -down pair Rtt(mi s) −3.75  +3.75 % 1

Test Condition For Rtt Measurements *1

Measurement Definition for Rtt(eff)

Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC))

respectively.

VIH(AC) − VIL(A C)

I(VIH(AC)) − I(VIL(AC))

Rtt(eff) =

Measurement Definition for Rtt(mis)

Measure voltage (Vm) at test pin (midpoint) with no load.

2 × Vm

VDDQ

Rtt(mis) = × 100%

− 1

Notes: 1. VIH(AC), and VDDQ values defined in SSTL_18.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

/CK T0 T1 T2 T3 T4 T5 T6

ODT

CKE

Internal

Term Res. Rtt

tIS tIS

tAOND tAOFD

tAON max.

tAON min. tAOF min. tAOF max.

ODT Timing for Active and Standby Mode

/CK T0 T1 T2 T3 T4 T5 T6

ODT

CKE

Internal

Term Res.

Rtt

tIS tIS

tAONPD min.

tAONPD max.

tAOFPD min.

tAOFPD max.

ODT Timing for Power down Mode

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

ODT Control of Reads

At a minimum, ODT must be latched High by CK at (Read Latency – 3tCK) after the READ command and remain

High until (Read Latency + BL/2 – 2tCK) after the READ command (where Read Latency = AL + CL). The controller

is also required to activate it´s own termination with a turn on time the same as the DRAM and keeping it on until

valid data is no longer on the system bus.

/CK T0 T1 T2 T3 T4 T5 T6

ODT

at DRAM in slot2

at DRAM in slot1

Controller

Term Res.

DRAM

Term Res. Rtt (DRAM)

Rtt (Controller)

Command

(to slot1)

ODT

(to slot2)

NOPREAD

Command

DQS

READ

out0 out1 out2 out3

tAOND tAOFD

NOP

Read Example for a 2 Slot Registered System with 2nd Slot in Active Mode

(Read Latency =

= 3tCK ;

;;

; tAOND =

= 2tCK ;

;;

; tAOFD =

= 2.5tCK)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

/CK T0 T1 T2 T3 T4 T5 T6 T7

ODT

at DRAM in slot2

at DRAM in slot1

Controller

Term Res.

DRAM

Term Res.

Rtt (DRAM)

Rtt (Controller)

Command

(to slot1)

ODT

(to slot2)

NOPREAD

Command

DQS

READ

out0 out1 out2 out3

tAOND tAOFD

NOP

Read Example for a 2 Slot Registered System with 2nd Slot in Active Mode

(Read Latency =

= 4tCK ;

;;

; tAOND =

= 2tCK ;

;;

; tAOFD =

= 2.5tCK)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

At a minimum, ODT must be latched High by CK at (W rite Latency – 3 tCK) after the WRIT command and remain

high until (Write Latency + BL/2 – 2tCK) after the WRIT command(Where W rite Latency = Read Latency – 1tCK).

During writes, no ODT is required at the controller.

/CK T0 T1 T2 T3 T4 T5 T6

ODT

at DRAM in slot2

at DRAM in slot1

Controller

Term Res.

DRAM

Term Res.

Rtt (DRAM)

ODT

(to slot2)

Command

DQS

WRIT

in0 in1 in2 in3

tAOND tAOFD

NOP

Command

(to slot1)

WRIT NOP

Write Example for a 2 Slot Registered System with 2nd Slot in Active Mode

(Read Latency =

= 3tCK ;

;;

; tAOND =

= 2tCK ;

;;

; tAOFD =

= 2.5tCK)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

/CK T0 T1 T2 T3 T4 T5 T6

ODT

at DRAM in slot2

at DRAM in slot1

Controller

Term Res.

DRAM

Term Res.

Rtt (DRAM)

ODT

(to slot2)

Command

DQS

WRIT

in0 in1 in2 in3

tAOND tAOFD

NOP

Command

(to slot1)

NOPWRIT

Write Example for a 2 Slot Registered System with 2nd Slot in Active Mode

(Read Latency =

= 4tCK ;

;;

; tAOND =

= 2tCK ;

;;

; tAOFD =

= 2.5tCK)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Bank Activate Command [ACT]

The bank activate command is issued by holding /CAS and /WE High with /CS and /RAS Low at the rising edge of

the clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through

A13 is used to determine which row to activate in the selected bank. The Bank activate command must be applied

before any read or write operation can be executed. Immediately after the bank active command, the DDR-II

SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank

that has not satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to

delay when the R/W command is internally issued to the device. The additive latency value must be chosen to

assure tRCD (min.) is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been

activated it must be precharged before another bank activate command can be applied to the same bank. The bank

active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between

successive bank activate commands to the same bank is determined by the /RAS cycle time of the device (tRC),

which is equal to tRAS + tRP. The minimum time interval between successive bank activate commands to the

different bank is determined by (tRRD).

/CK

Address

Command

T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3

tRCD(min.)

tRAS tRP

tRC

ROW: 0

ACT

Bank0

Active Bank1

Active Bank0

Active

Bank0

Precharge Bank1

Precharge

Posted

READ Posted

READ

ACT PRE PRE ACT

COL: 0 ROW: 0ROW: 1 COL: 1

tRCD =1

tCCD

Additive latency (AL)

tRRD

Bank0 Read begins

Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS High,

/CS and /CAS Low at the clock’s rising edge. /WE must also be defined at this time to determine whether the access

cycle is a read operation (/WE high) or a write operation (/WE low).

The DDR-II SDRAM provides a fast column access operation. A single read or write Command will initiate a serial

read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific

segments of the page length. For example, the 32M bits × 4 I/O × 4 Banks chip has a page length of 2048 bits

(defined by CA0 to CA9, CA11). The page length of 2048 is divided into 512 uniquely addressable boundary

segments (4 bits each). A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the

column address supplied to the device during the read or write Command (CA0 to CA9, CA11). The second, third

and fourth access will also occur within this group segment, however, the burst order is a function of the starting

address, and the burst sequence.

A new burst access must not interrupt the previous 4-bit burst operation. The minimum /CAS to /CAS delay is

defined by tCCD, and is a minimum of 2 clocks for read or write cycles.

Posted /CAS

Posted /CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR-II

SDRAM. In this operation, the DDR-II SDRAM allows a /CAS read or write command to be issued immediately after

the /RAS bank activate command (or any time during the /RAS-/CAS-delay time, tRCD, period). The command is

held for the time of the additive latency (AL) before it is issued inside the device. The Read Latency (RL) is

controlled by the sum of AL and the /CAS latency (CL). Therefore if a user chooses to issue a R/W command before

the tRCD (min), then AL (greater than 0) must be written into the EMRS. The W rite Latency (W L) is always defined

as RL − 1 (read latency −1) where read latency is defined as the sum of additive latency plus /CAS latency

(RL=AL+CL).

-1

/CK

DQS, /DQS AL = 2

> tRCD

> tRAC

CL = 3

Command

0123456789101112

ACT READ NOP NOP

WRIT

out0 out1 out2 out3 in0 in1 in2 in3

WL = RL n–1 = 4

RL = AL + CL = 5

Read foll owed by a write to t he sam e bank

[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]

-10123456789101112

/CK

DQS, /DQS

AL = 0

> tRCD

> tRAC

CL = 3

Command

ACT READ WRIT

out0 out1 out2 out3 in0 in1 in2 in3

RL = AL + CL = 3

WL = RL n–1 = 2

NOP NOP NOP

Read foll owed by a write to t he sam e bank

[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory

locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst

length. DDR-II SDRAM supports 4 bits burst and 8bits burst modes only. For 8 bits burst mode, full interleave

address ordering is supported, however, sequential address ordering is nibble based for ease of implementation.

The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS,

which is similar to the DDR-I SDRAM operation. Seamless burst read or write operations are supported.

Unlike DDR-I devices, interruption of a burst read or writes operation is limited to ready by Read or W rite by W rite at

the boundary of Burst 4. Therefore the burst stop command is not supported on DDR-II SDRAM devices.

[Burst Length and Sequence]

Burst l ength Start i ng address (A2, A 1, A0) Sequential addres sing (decimal) Interleave addressi ng (decim al )

000 0, 1, 2, 3 0, 1, 2, 3

001 1, 2, 3, 0 1, 0, 3, 2

010 2, 3, 0, 1 2, 3, 0, 1

011 3, 0, 1, 2 3, 2, 1, 0

000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6

010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4

100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2

110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1

111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

Note: Page length is a function of I/O organization and column addressing

32M bits × 4 organization (CA0 to CA9, CA11); Page Length = 2048 bits

16M bits × 8 organization (CA0 to CA9); Page Length = 1024 bits

8M bits × 16 organization (CA0 to CA9); Page Length = 1024 bits

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Burst Read Command [READ]

The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising

edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start

of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency

(RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus.

The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out

appears on the DQ pin in phase with the DQS signal in a source synchronous manner.

The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register set

(MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the extended mode register set

(EMRS).

READ NOP

/CK

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

out0 out1 out2 out3

<tDQSCK

CL = 3

RL = 3

Burst Read Operation (RL = 3, BL = 4 (AL = 0 and CL = 3))

READ NOP

/CK

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

out0 out1 out2 out3 out4 out5 out6 out7

<tDQSCK

CL = 3

RL = 3

Burst Read Operation (RL = 3, BL = 8 (AL = 0 and CL = 3))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Posted

READ NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

AL = 2 CL = 3

RL = 5

out0 out1 out2 out3

<tDQSCK

Burst Read Operation (RL = 5, BL = 4 (AL = 2, CL = 3))

Posted

READ NOP

/CK T0 T1 T3 T4 T5 T6 T7 T8 T9

Command

DQS, /DQS

NOP Posted

WRIT

RL = 5

out0 out1 out2 out3 in0 in2

NOP

in3in1

tRTW (Read to Write = 4 clocks)

WL = RL - 1 = 4

Burst Read followed by Burst Write (RL = 5, WL = RL-1 = 4, BL = 4)

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-

around-time, which is 4 clocks.

Posted

READ NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

Posted

READ NOP

out0 out1 out2 out3 out5 out6out4

AL = 2 CL = 3

RL = 5

Seamless Burst Read Operation (RL = 5, AL = 2, and CL = 3) )

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Enabling a read command at every other clock supports the seamless burst read operation. This operation is

allowed regardless of same or different banks as long as the banks are activated.

READ NOP READ

/CK T0 T2 T4 T6 T8 T10T1 T3 T5 T7 T9 T11

Command

DQS, /DQS

NOP

RL = 4

Burst interrupt is only

allowed at this timing.

out0 out1 out2 out3 out0 out1 out2out3out4 out5 out6 out7

A B

Burst Read Interrupt by Read

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Burst Write Command [WRIT]

The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of

the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read

latency (RL) minus one and is equal to (AL + CL −1). A data strobe signal (DQS) should be driven low (preamble)

one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge

of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent

burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. W hen the burst

has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst

write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery

time (tWR).

WRIT NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T9

Command

DQS, /DQS

>tRP

>tWR

in2

PRE NOP ACT

in1 in3in0

=Completion of

the Burst Write

<tDQSS

WL = RL –1 = 2

Burst Write Operation (RL = 3, WL = 2, BL = 4 tWR = 2 (AL=0, CL=3))

WRIT NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

>tRP

>tWR

in2in1 in3in0 in6in5 in7in4

=Completion of

the Burst Write

<tDQSS

WL = RL –1 = 2

T9 T11

NOP ACT

PRE

Burst Write Operation (RL = 3, WL = 2, BL = 8 (AL=0, CL=3))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Posted

WRIT NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T9

Command

DQS, /DQS

WL = RL −1 = 4 >tWR

in0 in1 in2 in3

PRE

<tDQSS Completion of

the Burst Write

Burst Write Operation (RL = 5, WL = 4, BL = 4 tWR = 3 (AL=2, CL=3))

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

Command

DQS, /DQS

CL = 3

RL = 5

AL = 2

>tWTR

in0 in2

NOP

in1 in3

Posted

READ

WL = RL –1 = 4

Write to Read = CL + 1 + tWTR (2) = 6

out0 out1

Burst Write followed by Burst Read (RL = 5, BL = 4, WL = 4, tWTR = 2 (AL=2, CL=3))

The minimum number of clock from the burst write command to the burst read command is CL + 1 + a write to-read-

turn-around-time (tWTR). This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit

write data from the input buffer into sense amplifiers in the array.

NOP

/CK

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

in 0 in 2

NOP

in 1 in 3 in 4 in 6in 5 in 7

Posted

WRIT Posted

WRIT

WL = RL − 1 = 4

Seamless Burst Write Operation (RL = 5, WL = 4, BL = 4)

Enabling a write command every other cloc k supports the seamless burst write operation. This operation is allowed

regardless of same or different banks as long as the banks are activated.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

WRIT NOP WRIT

/CK T0 T2 T4 T6 T8 T10T1 T3 T5 T7 T9 T11

Command

DQS, /DQS

NOP

WL = 3

Burst interrupt is only

allowed at this timing.

in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 in6 in7

Write interrupt by Write (WL = 3, BL = 8)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Write data mask

One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR-II SDRAMs, Consistent with the

implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in

a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used

during read cycles.

DQS

/DQS

T1 T2 T3 T4 T5 T6

Write mask latency = 0

in in in in in in in in

Data Mask Timing

/CK

DQS, /DQS

Command

[tDQSS(min.)]

tWR

tDQSS

[tDQSS(max.)]

WRIT NOP

in0 in2 in3

Data Mask Function, WL = 3, AL = 0 shown

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Precharge Command [PRE]

The precharge command is used to prec harge or close a bank that has been activated. The precharge command is

triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge

command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10,

BA0 and BA1 are used to define which bank to precharge when the command is issued.

[Bank Selection for Precharge by Address Bits]

A10 BA0 BA1 Precharged Bank(s)

L L L Bank 0 only

L H L Bank 1 only

L L H Bank 2 only

L H H Bank 3 only

H × × All banks 0 to 3

Remark: H: VIH, L: VIL, ×: VIH or VIL

Burst Read Operation Followed by Precharge

Minimum read to precharge command spacing to the same bank = AL + BL/2 clocks

For the earliest possible precharge, the precharge command may be issued on the rising edge that is

“Additive latency (AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to the

same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

AL + 2 clocks

RL = 4

AL = 1

CL = 3

out0 out2

PRE NOP

out1 out3

Posted

READ ACT NOP

> tRP

> tRAS

Burst Read Operation Followed by Precharge (RL = 4, BL = 4 (AL=1, CL=3))

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

RL = 5

AL = 2

> tRAS CL = 3

CL = 3

out0 out2

NOPPRE

out1 out3

Posted

READ ACT NOP

> tRP

AL + 2 clocks

Burst Read Operation Followed by Precharge (RL = 5, BL = 4 (AL=2, CL=3))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

Command

DQS, /DQS

AL = 2 CL = 4

out0 out2

NOPPRE

out1 out3 out4 out6out5 out7

Posted

READ ACT NOP

> tRP

RL = 6

AL + BL/2 Clocks

> tRAS(min.)

Burst Read Operation Followed by Precharge (RL = 6 (AL=2, CL=4, BL=8))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Burst Write followed by Precharge

Minimum W rite to Precharge Command spacing to the same bank = WL + BL/2 clocks + tWR

For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge

command can be issued. This delay is known as a write recovery time (tW R) referenced from the completion of the

burst write to the precharge command. No precharge command should be issued prior to the tWR delay, as DDR-II

SDRAM allows the burst interrupt operation only Read by Read or Write by Write at the boundary of burst 4.

in3in1

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

> tWR

Completion of

the Burst Write

WL = 3

in0 in2

Posted

WRIT PRE

Burst Write followed by Precharge (WL = (RL-1) =3)

Posted

WRIT

/CK T0 T1 T2 T3 T4 T5 T6 T7 T9

Command

DQS, /DQS

WL = 4

in0 in1 in2 in3

PRE

> tWR

Completion of

the Burst Write

NOP

Burst Write followed by Precharge (WL = (RL-1) = 4)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

WRIT NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

>tRP

>tWR

in2in1 in3in0 in6in5 in7in4

=Completion of

the Burst Write

<tDQSS

WL = RL –1 = 2

T9 T11

NOP ACT

PRE

Burst Write followed by Precharge (WL = (RL-1) = 4,BL= 8)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge

command or the auto-precharge function. When a read or a write command is given to the DDR-II SDRAM, the

/CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin

precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write

Command is issued, then normal read or write burst operation is executed and the bank remains active at the

completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-

precharge function is engaged. During auto-precharge, a read Command will execute as normal with the exception

that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end

of the read burst.

Auto-precharge can also be implemented during Write commands. The precharge operation engaged by the Auto

precharge command will not begin until the last data of the burst write sequence is properly stored in the memory

array.

This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent

upon /CAS latency) thus improving system performance for random data ac cess. The /RAS lockout circuit internally

delays the Precharge operation until the array restore operation has been completed so that the auto precharge

command may be issued with any read or write command.

Burst Read with Auto Precharge [READA]

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR-II

SDRAM starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later from the read with

AP command when the condition that. W hen tRAS (min) is satisfied. If tRAS (min.) is not satisfied at the edge, the

start point so auto-precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command)

may be issued to the same bank if the following two conditions are satisfied simultaneously.

(1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

(2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

RL = 5

AL = 2

> tRC CL = 3

Auto precharge begins

CL = 3

out0 out2out1 out3

Posted

READ ACT

> tRP

> tRAS(min.)

A10 = 1

Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRC limit)

(RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

RL = 5

AL = 2

A10 = 1

> tRC CL = 3

CL = 3

Auto precharge begins

out0 out2out1 out3

Posted

READ ACT NOP

> tRP

> tRAS(min.)

Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRP limit)

(RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3)

READ ACT

/CK T0 T2 T4 T6 T8 T10T1 T3 T5 T7 T9 T11

Command

DQS, /DQS

NOP

RL = 5

AL = 2

A10 = 1

CL = 3

tRP

Auto Precharge begins.

out0 out1 out2 out3 out4 out5 out6 out7

tRC

tRAS (min.)

Burst Read with Auto Precharge Followed by an Activation to the Same Bank

(RL = 5, BL = 8 (AL = 2, CL = 3)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Burst Write with Auto-Precharge [WRITA]

If A10 is high when a write command is issued, the Write with auto-precharge function is engaged. The DDR-II

SDRAM automatically begins precharge operation after the completion of the burst writes plus write recovery time

(tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the

following two conditions are satisfied.

(1) The data-in to bank activate delay time (tWR + tRP) has been satisfied.

(2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.

in1 in3

/CK

T0 T1 T2 T3 T4 T5 T6 T7 T12

Command

DQS, /DQS

> tWR

> tRC

Auto Precharge Begins

Completion of the Burst Write

in0 in2

Posted

WRIT ACT

NOP

> tRP

WL = RL –1 = 2

A10 = 1

Burst Write with Auto-Precharge (tRC Limit) (WL = 2, tWR =2, tRP=3)

NOP

/CK T0 T3 T4 T5 T6 T7 T8 T9 T10

Command

DQS, /DQS

> tWR

> tRC

Auto Precharge Begins

Completion of the Burst Write

in0 in2

NOP

in1 in3

Posted

WRIT ACT

> tRP

WL = RL –1 = 4

A10 = 1

Burst Write with Auto-Precharge (tWR + tRP) (WL = 4, tWR =2, tRP=3)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

WRIT ACT

/CK T0 T2 T4 T6 T8 T10T3 T5 T7 T9 T11 T12 T13

Command

DQS, /DQS

NOP

WL = RL - 1 = 4

A10 = 1

tWR

tRP

Auto Precharge begins.

in0 in1 in2 in3 in4 in5 in6 in7

tRC

Burst Write with Auto Precharge Followed by an Activation to the Same Bank

(WL = 4, BL = 8, tWR = 2, tRP = 3)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Refresh Requirements

DDR-II SDRAM requires a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two

ways: by an explicit Automatic Refresh command, or by an internally timed event in Self Refresh mode. Dividing the

number of device rows into the rolling 64 ms interval defines the average refresh interval, tREFI, which is a guideline

to controllers for distributed refresh timing.

Automatic Refresh Command (/CAS Before /RAS Refresh) [REF]

When /CS, /RAS and /CAS are held low and /W E high at the rising edge of the clock, the chip enters the Automatic

Refresh mode (CBR). All banks of the DDR-II SDRAM must be precharged and idle for a minimum of the Precharge

time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device,

supplies the bank address during the refresh cycle. No control of the external address bus is required once this

cycle has started.

When the refresh cycle has completed, all banks of the DDR-II SDRAM will be in the precharged (idle) state. A

delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh

Command must be greater than or equal to the Auto Refresh cycle time (tRFC).

The DDR-II SDRAM requires Automatic Refresh cycles at an average periodic interval of tREFI (maximum). A

maximum of eight Automatic Refresh commands can be posted to any given DDR-II SDRAM, and the maximum

absolute interval between any Auto Refresh command and the next Auto Refresh command is 8 × tREFI.

NOPPRE

/CK T0 T1 T2 T3 T15 T7 T8

CKE

Command

> tRP

High

> tRFC > tRFC

CBRCBR NOP Any

Command

Automatic Refresh Command

Self Refresh Command [SELF]

The DDR-II SDRAM devic e has a built-in timer to accommodate Self Refresh o peration. The self refresh comm and

is defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock. Once the

Command is registered, CKE must be held low to keep the device in self refresh mode. When the SDRAM has

entered self refresh mode all of the external control signals, except CKE, are disabled. The clock is internally

disabled during self refresh operation to save power. The user may halt the external clock while the device is in Self

Refresh mode, however, the clock must be restarted before the device can exit self refresh operation. Once the

clock is cycling, the exit command will be registered asynchronously by bringing CKE high. After CKE is brought

high, an internal timer is started to insure CKE is held high for approximately 10ns before registering the self refresh

exit command. The p urpose of this circuit is to filter out noise glitches on the CKE input that m ay cause the DDR-II

SDRAM to erroneously exit self refresh operation. Once the self refresh command is registered, a delay equal or

longer than the tXSC must be satisfied before any command can be issued to the device. CKE must remain high

for the entire Self Refresh exit period (tXSC) and commands must be gated off with /CS held High. Alternatively,

NOP commands may be registered on each positive clock edge during the self refresh exit interval. (Self Refresh

Command)

SELF

/CK T0 T1 T2 T3 Tm Tn Tn+1

CKE

Command NOP

Any

Command

> tXSC

: VIH or VIL

Self Refresh Command

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Power-Down [PDEN]

Power-down is entered when CKE is registered (no accesses can be in progress). If power-down occurs when all

banks are id le, this mode is referred to as precharge power-down; if power-down occurs when there is a row active

in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output

buffers, excluding CK, /CK and CKE. In power down mode, CKE Low and a stable clock signal must be maintained

at the inputs of the DDR-II SDRAM, and all other input signals are “VIH or VIL”. Power-down duration is limited by

the refresh requirements of the device.

The power-down state is synchronously exited when CKE is registered High (along with a NOP or DESL). A valid,

executable command may be applied after satisfied tXPRD or tXARD for read command exiting form precharge

power-down or active power-down respectively ,and after satisfied tXPNR for non-read command.

/CK

CKE

Command

tIS

tXPRD, tXPNR

tXARD

tIS

VALID NOP

Enter power down mode

(Burst read or write operation

must not be in progress)

No column

access in progress Exit

power down

mode

NOP VALID

: VIH or VIL

Power Down

Burst Interruption

Interruption of a burst read or write cycle is prohibited.

No Operation Command [NOP]

The no operation command should be used in cases when the DDR-II SDRAM is in an idle or a wait state. The

purpose of the no operation command is to prevent the DDR-II SDRAM from registering any unwanted commands

between operations. A no operation command is registered when /CS is low with /RAS, /CAS, and /W E held high at

the rising edge of the clock. A no operation command will not terminate a previous operation that is still executing,

such as a burst read or write cycle.

Deselect Command [DESL]

The deselect command performs the same function as a no operation command. Deselect Command occurs when

/CS is brought high at the rising edge of the clock, the /RAS, /CAS, and /WE signals become don’t cares.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

Package Drawing

64-ball FBGA (µ

µµ

µBGA) (TBD)

Solder ball: Lead free (Sn-Ag-Cu)

80-ball FBGA (µ

µµ

µBGA) (TBD)

Solder ball: Lead free (Sn-Ag-Cu)

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the EDE51XXABSE.

Type of Surface Mount Device

EDE51XXABSE: 64-ball FBGA (µBGA) , 80-ball FBGA (µBGA) < Lead free (Sn-Ag-Cu) >

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate

oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop

generation of static electricity as much as possible, and quickly dissipate it, when once

it has occurred. Environmental control must be adequate. When it is dry, humidifier

should be used. It is recommended to avoid using insulators that easily build static

electricity. MOS devices must be stored and transported in an anti-static container,

static shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded using

wrist strap. MOS devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be

generated due to noise, etc., hence causing malfunction. CMOS devices behave

differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected

to V

or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process

of MOS does not define the initial operation status of the device. Immediately after the

power source is turned ON, the MOS devices with reset function have not yet been

initialized. Hence, power-on does not guarantee output pin levels, I/O settings or

contents of registers. MOS devices are not initialized until the reset signal is received.

Reset operation must be executed immediately after power-on for MOS devices having

reset function.

CME0107

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Preliminary Data Sheet E0323E20 ( Ver. 2.0)

µBGA is a registered trademark of Tessera, Inc.

M01E0107

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights

(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or

third parties by or arising from the use of the products or information listed in this document. No license,

express, implied or otherwise, is granted under any patents, copyrights or other intellectual property

rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for

illustrative purposes in semiconductor product operation and application examples. The incorporation of

these circuits, software and information in the design of the customer's equipment shall be done under

the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses

incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, users are instructed to contact Elpida Memory's sales office before using the product in

aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,

medical equipment for life support, or other such application in which especially high quality and

reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by

Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation

characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no

responsibility for failure or damage when the product is used beyond the guaranteed ranges and

conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so

that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other

consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be

used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign

Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance

with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by

U.S. export control regulations, or another country's export control laws or regulations, you must follow

the necessary procedures in accordance with such laws or regulations.

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The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.