ae CIRRUS LOGIC ME 2136639 0006154 928 MBCIR CL-CD2400/CD2401 Data Book FEATURES General @ Four full-duplex channels @ All channels support async, blsync, HDLC/ SDLC, and X.21 programmabie sync protocols M@ Bit rates to 64 kbit transmit and recelve, NRZ, NR2I, and Manchester data encoding supported @ Digital phase locked foop on each receiver @ independent bit rate generators for transmit and receive @ Clock sources can be Internal or external @ Transmit clock source can be recelve DPLL output @ Full on-chip DMA controller @ Data transfer by DMA or Interrupt mechanism selectable per channel per direction M@ Vectored interrupts with Fair Share mechanism for cascading (cont. next page) Four-Channel, Multi-Protocol! Communications Controller OVERVIEW The CL-CD2400 is a synchronous/asynchronous communications controller featuring full on-chip DMA for each channel in each direction. Combining the DMA and protocol controllers enables a more efficient host interface to be provided for both synchronous and asynchronous modes. An efficient vectored interrupt scheme is also provided to minimize host processing overhead and share service fairly among channels and cascaded devices. By providing the ability to simultaneously use more than one buffer area and to add data to existing buffers, efficient DMA control of data transfer can be achieved. 4SERIAL Functional Block Diagram INTERFACE CHANNELS MODEM RECEIVE/CRC im TRANSMIT/CRC _| TIMER/BRG/DPLL HOST RAM MODEM TERFACE IN HOST INTERFACE Loaic RECEIVECRC | TRANSMIT/CRC TIMER/BRG/DPLL ON-CHIP DMA CONTROLLER AND MODEM RECEIVE/CRC INTERFACE Lo FIRMWARE GIC ROM Risc PROCESSOR TRANSMIT/CRC TIMER/BRG/DPLL MODEM 7] RECEIVE/CRC *TTRANSMIT/CRC TIMER/BRG/DPLE rudy NOTE: The CL-CD2400 and CL-CD2401 are functional- and register-compatible. The CL-CD2400 comes in an 84-pin PLCC package and the CL-CD2401, a 100-pin QFP package. Because of the additional pins available to the CL-CD2401, the modam signals are de-multiplexed, making the controller compatible with more applications (i.e., X.21 bis). Uniess otherwise stated, all subsequent descriptions for the CL-CD2400 apply to the CL-CD2401. | August 1993 OS09577eo istin a> == CIRRUS LOGIC ene FE MB 2136639 OOOb1SS By MECIR CL-CD2400/2401 Multi-Protocol Controller phone numbers. This data book applies Es bate pees FEATURES General (cont.) a CRC generation and validation a 32 bytes of data FIFO per channel (16-byte transmit FIFO, plus 16-byte receive FIFQ) Async a DMA managed intelligently to minimize host Interaction transmit block mode buffer transmit append buffer receive buffer adjustments for exceptions receive timeout interrupts a Receive good data separated from exceptions a in-band flow control via programmable charac- ters = Out-of-band flow control a Line break detection and generation a Special character recognition and transmission w Receive and transmit timer supported = UNIX character processing Bisyne a Programmable for ASCII or EBCDIC encoding Supports transparent bisync a Recognition of all special characters enabling block separation CRC generation/validation without user intervention a Chaining of long receive blocks into multiple buffers Before beginning any new design with this device, please contact Clrrus Loglec, Inc., for the latest errata Information. See the back cover of this document for sales office locations and to CL-CD2400/CD240 ae 1 Revision t or later devices. ae ans Gan ee ee a Unchaining of multiple buffers Into long transmit blocks a Two general timers per channet HDLc/spLct s Address matching of either 2 x 16-bit addresses or 4 x &-bit addresses Idle-In flag or mark a CRC generation and validation Chaining of along receive frame Into multiple buffers a Unchaining of multiple buffers into a long transmit frame Option to send PAD characters before starting flags a Two general timers per channel X.21/Programmable SYNC a Full support of X.21 protocol = Detection of steady state conditions Transmission of steady state conditions synchronized to modem lead = Programmable SYN character a 1/2 SYN detect option a Idle In any line conditon a Optional SYN strip on receive t References to the HDLC protocol throughout this document aiso refer to the SDLC Protocol. . 2 Features S| August 1993MB 2136639 QOOOb15&6 7TO0 mBCIR CL-CD2400/2401 * re Multi-Protocol Controller CIRRUS LOGIC CONTENTS 1. PIN INFORMATION .............cccceecseseeens 8. SAMPLE PACKAGE ............cccccceecece 133 1.1 CL+CO2400 Pin Diagram..........cccccceeeseee 1.2 CL-CD2400 Pin Functions .......0.000.cceeeeee 9. ORDERING INFORMATION ....... oreee 135 1.3 CL-COD2401 Pin Diagram... ccc 1.4 CL-CO2401 Pin Functions .. . . . 1.5 Pin Descriptions ...........cccccsceeccesseeeee . List of Figures 2. REGISTER TABLE...............cccsseeeee 12) Figure 1-0. Functional Block Diagrattiecsc-csssssssssssssssees 1 2.1 CL-CD2400 Memory Map... 13 Figure 1~1. CL-CD2400 Pin Diagram.....cccsccecescecess 4 2.2 Register Definitions ...0.... ee eeeeseneee 18 Figure 1-2. CL-CD2400 Pin Functions... 5 ; Figure 1-3, CL-CO2401 Pin Diagram... 6 3. FUNCTIONAL DESCRIPTION.......... +29 Figure i~4. CL-CD2401 Pin Functions 7 3.1 Host Interface... cee Figure 3-0. Host Read Cycle oo... ce ecceecesscssesessens 29 3.2 Interrupts rirrrrerenasesensereeeecaenns Figure 3-1. Host Write Cycle .........ccccesesssscescccesees 30 3.3. FIFO and Timer Operations... 34 Figure 3-2. Interrupt Acknowledge Cycle 3h 3.40 DMA Operation 00... cee cccecccssessssccscecceens 35 Figure 3-3. Bus Acquisition Cycle .........cccccecsseceeses 36 3.5 Bit Rate Generation and Data Encoding...... 47 Figure 3-4. Data Transfer TIMiINg.......eecceeseseeneeeeeee 37 3.6 Hardware Configurations.......0.0cccccceeeee 52 Figure 3-5. Transmitter A/B Buffers... 39 Figure 3-6. Receiver A/B Buffers..,.......... 42 - P PROCESSING ............. . 4 4 Rorecot ROCESSING 55 Figure 3-7. OMA Transmit Buffer Selection.. 45 42 Bi hroneue Powe Wenner nes Figure 3-8. Bit Rate Generator/DPLL ........ ccc eee 48 : SYNENFONOUS TTOCESSING voces eeseeescsseeess Figure 3-9. Data Encoding. ...........ccccceeceecesseeees 51 4.3 Asynchronous Processing... . 4.4 UNIX Support Features... cece 4.5 X.21 Call Set-Up Mode... cece 4.6 Programmable Sync Mode... Figure 3-10. Transmit Data With External Clock In....... 51 Figure 3-11. Transmit Data With External Clock Out.... 52 Figure 3-12. DMA Connections for the CL-CD2400...... 53 . Figure 4-0, Receive Character Processing............... 62 4.7 Non-8-Bit Data Transfers... seeseeseee Figure 5-0. Init. Sequence for the CL-CD2400........... 67 5. PROGRAMMING EXAMPLES ............ 67 Figure7~0. Slave Read Cycle Timing.......... 5.1 Global initialization... csceecesecseeeseesee 68 Figure 7-1. Slave Write Cycle Timing..........-ss 5.2 Async Interrupt Setup Example................. 69 Figure7-2. _ Interrupt Acknowledge Cycle Timing.......128 5.3 HDLC DMA Channel Setup Example ........... 69 Figure 7-3. Bus Arbitration Cycle Timing.............0... 129 5.4 Bisyne Setup Example ......ccccccccceeceseeseees 70 Figure 74, Bus Release THING woe e eee eeeeeeeeeeeeeees 130 5.5 Receive DMA Interrupt Service Routine......71 Figure 7-5. DMA Read Cycle Timing.. 131 5.6 Transmit Interrupt Service Routine..........0.. 72 Figure 7-6. DMA Write Cycle Timing.............44. 132 Figure 8-0. CL-CD2400 Sample Package......... -++.133 6. DETAILED REGISTER DESCRIPTIONS 73 Figure 8-1. CL-CD2401 Sample Package................ 134 6.1 Global Registers 0.0.00... ccecccccccscceceeeeeees 6.2 Options Registers 6.3 Bit Rate and Clock Options Registers......... 92 List of Tables 6.4 Channel Command and Status Registers..... 94 6.5 Interrupt Registers .............cccccseeeeeeseeees 101 Table 1-0. CL-CD2400 and CL-CD2401 6.6 DMA Registers..... Pinout Differences... ccc cecseeeeeeneees 7 6.7 Timer Registers Table 3-0. Transmit and Interrupt Service Requests .... 32 Table 3-1. Data Clock Selection 7. ELECTRICAL SPECIFICATIONS....... 124 Using the Bit Rate Generators 50 7.1 Absolute Maximum Ratings ..........eees00 124 Table 3-2. Data Clock Selection Using External Clock, . 52 7.2 DC Electrical Characteristics .......0000........ 124 7.3 AC Electrical Characteristics.........0......... 125 * A page number cross-reference has been provided throughout this section for the location of each register. August 1993 NT Contents 3M@ 2236639 0006157 37 MICIR CL-CD2400/2401 Multi-Protocol Controller 1. PIN INFORMATION 1.1. Pin Diagram CL-CD2400 ~f%= f 2 ae 2. RERbOS DB x SSssgs gs ESESESES. & a OVoe0soeggcvonnnaaeaaneEzZa REREKSSRBRRRRSESS LESS 3 e CTS? [o} DATEN* TACOUT/DTR? [0] DATDIR RTS* [0] AESET* CTs* [1] IREQ? [3] TXCOUT/DTR [1} IREQ [2} RATS* {1} 69 IREO* (1) GNO 68 GND CTS* [2} 67 MM 1ACKouT* TXCOUT/DTR* [2] = 66 IACKIN* re CL-CD2400 ee BE ACKIN: CTS* [3] 84-Pin PLCC 64M ps: TXCOUT/DTR* {3} 33 AS RTS? [3] 62 RW Al?) 81 BGACK* Ale] 50 BGOUT* AB] 59 BGIN A[4) 58 BR 4(3} 57 BUSCLK A [2] 56 CLK Alt) 55 SiZ [1] A(o} 54 SIZ (0} Figure 1-1. CL-CD2400 Pin Diagram 4 Pin Information cmamamaans August 1993CL-CD2400/2401 Multi-Protaocol Contreller 1. PIN INFORMATION (cont.) 1.2 Pin Functions August 1993 Me 2136639 9006158 573 MECIR ec Ee, | === CIRRUS LOGIC A [0-7] A/D [0-15] CLK cs As ps RW DTACK* SIZ (0-1) BUSCLK BERR RESET TEST ADLD* AEN* DATDIR DATEN BYTESWAP HERES EET EL VE IACKIN IACKOUT* IREQ"[1-3) thy BR" BGIN* BGOUT BGACK Hit Host & DMA Signals Interrupt Signals Signals x RO TXCINICD RXCIN/DSR* ATS* crs" TXCOUT/DTR* viyft CL-CD2400 Serial Ch. 1 Serial Ch. 2 $ Serial Ch. 3 s Figure 1-2. Ln CL-CD2400 Pin Functions Pin Information 5MB 2136639 0006159 4OT MECIR = CL-CD2400/2401 ===CIRRUS LOGIC Multi-Pratocol Controller 1. PIN INFORMATION (cont) 1.3 Pin Diagram CL-CD2401 = at =% aSeSs ss 5 ES Z2Z02% 22502598 NES, 33 oOoo0 gegegeocoogoooouce x xxo - xx KEK XW RoR SSSREARKKESEEEU RS RXCIN(S bees AEN" TXCINIS Om ADLD DSR"{0 Se DATEN* CTSil0 exe DATDIA TXCOUT/OTR*[0 Te RESET RTS*(0! bes AXCOUT(O} DSR! es IREQ"(3) crs! emt IREQ"(2} TXCOUT/DTR'(1 See CD'3] ATS*(1 60 Se REG") DSA 2, 20 P= GND GND 62 - 19 fmm IACKOUT* ae 2 CL-CD2401 iE ec TXCOUT/OTR'[2 64 Pi 17 bee LACKING ore 2) = 8 100-Pin QFP 17 foes ACKIN: DSR"(3 66 15 fm DS a 87 14 fm AS TXCOUT/DTR'/3 68 13 Rw RTS(3 69 12 F BGACK' GND mad 70 11 bm COT] Al? nm 10 = BGOUT" Ale 7 9 p= BGIN' Als a 8 p= VOD Ala 1 7 fem BR Als 75 6 P= BUSCLK Al2 76 5 hm ck Als 7 4 siqi} Alo 78 3 siz VOD emg 79 2 [ GND AOS] 0 ZABSSSSSSRSARSLSSSSS 1 Pm cs Figure 1-3. CL-CD2401 Pin Diagram 6 Pin Information August 1993CL-CD2400/2401 Multi-Protocol Controller ( 1. PIN INFORMATION (cont) 1.4 Pin Functions A [0-7] AD [0-15] CLK cs* ASs* DS" Rw OTACK* SIZ [0-1] BUSCLK BEAR RESET* TEST ADLD* AEN DATDIA* DATEN* BYTESWAP IACKIN* lACKOUT iREQ"[1-3] BR BGIN* BGOouT* BGACK* M8 2136639 ooob1bO 12) MCIR ee FRR a ===" CIRRUS LOGIC Petty OUEEMAEAAL L Bus Arbitration Signals if Hast & DMA Signals interrupt Signais CL-CD2401 TXD < TXCIN RXCIN > = TxcouT [> AXCOUT [~ ATS < cts m< psa cp Serlal Ch. 0 Serial Ch. 1 % Ly Serlal Ch. 2 LB af VDD & GND Serial Ch. 3 Figure 1-4, CL-CD2401 Pin Functions Table 1-0, CL-CD2400 and CL-cD2401 Pinout Differences CL-CD2400 Per Serial Channel RxD TxD RTS* CTs" RXCIN/DSR* TXCOUT/DTR TXCIN/CD* August 1993 CL-CD2401 Per Serial Channel RxD TxD RTS* cTSs* DSR TXCOUT/DTR* RXCIN TXCIN RXCOUT cD* REResnn Pin Information 7MB 2136639 0006161 Ob8 MECIR SESS CL-CD2400/2401 ===" CIRRUS LOGIC Multi-Protocol Controller 1.5 Pin Descriptions Symbol Type Description CS" Input CHIP SELECT* - When low, the CL-CD2400 registers may be read or written by the host processor. AS* V/O (tristate) ADDRESS STROBE When the CL-CD2400 is a bus master, this pin is an output which indicates that RAW", A[0-7], and the externally latched A[8-31] are valid. DS* V/O (tristate) DATA STROBE* When the CL-CD2400 is not a bus master, this is an input used to strobe data into registers during write cycles and enable data onto the bus during read cycles. When the CL-CD2400 is a bus master, DS* is an output used to control data transfer to and from system memory. R/W* I/O (tristate) READ/WRITE* When the CL-CD2400 is not a bus master, this pin is an input which determines if a read or write operation is required when the CS* and DS signals are active. When the CL-CD2400 is a bus master, RAV" is an output and indicates whether a read from or a write to system memory is being performed. DTACK* /O (open drain) DATA TRANSFER ACKNOWLEOGE* When the CL-CD2400 is not a bus master, this is an output and indicates to the host when a read or write to the CL-CD2400 is complete. When BR is driven low by the CL-CD2400, DTACK* is an input which indicates that the system bus is no longer in use. When the CL-CD2400 is a bus master, DTACK* is an input which indicates when system memory read and write cycles are complete. SIZ[0-1] VO (tristate) SIZE [0-1] When not the active bus master, these are inputs which determine the size of the operand being read or written by the host. SIZ(1] S1IZ[0} 0 1 - Byte 1 QO -16Bit 0 0 -32 Bit ** 1 1 - 3 Bytes** When the CL-CD2400 is a bus master, this is an output determining the size of the operand being transferred to or from system memory. SIZ[1] SIZ[O] 0 1 - Byte * 1 0 - 16 Bit * See BYTESWAP description ** The CL-CD2400 will drive DTACK* even though the device will not respond to such byte alignment. IACKIN* Input INTERRUPT ACKNOWLEDGE IN* This input qualified with DS", and A[0-6] acknowledges CL-CD2400 interrupts. IACKOUT* Output INTERRUPT ACKNOWLEDGE OUT" This output is driven low during interrupt acknowledge cycles for which no internal interrupt is valid. 8 Pin Information August 1993MB 2136639 OOOblbe TTY MCIR CL-CD2400/2401 et Multi-Protocol Controller ===> CIRRUS LOGIC 1.5 Pin Descriptions (cont) Symbol Type Description IREQ*[1-3] VO (open drain) INTERRUPT REQUEST [1-3] These outputs signal that the CL- CD2400 has a valid interrupt for modem-lead activity (IREQ*[1]), transmit activity (IREQ"[2]), or receive activity (IREQ*[3}). BR* Output BUS REQUEST" This output is used to signal to the (open drain) host processor or bus arbiter that bus mastership is required by the CL-CD2400. BGIN* Input BUS GRANT IN* This input indicates that the bus is available after the current bus master relinquishes the bus. BGOUT* Output BUS GRANT OUT* This output is asserted when BGIN is low and no internal Bus Request has been made. A daisy-chain scheme of bus arbitration can be formed by connecting BGOUT* to BGIN* of the next device in the chain. If a priority scheme is preferred, Bus Requests must be prioritized externally and Bus Grant routed to the BGIN* of the appropriate device. BGACK* VO (open drain) BUS GRANT ACKNOWLEDGE As an input, this signal is used to determine if another alternate bus master is in control of the bus. As an output, it signals to other bus masters that this device is in control of the bus. BERR* Input BUS ERROR* - If this input becomes active while the CL-CD2400 is a bus master, the current bus cycle will be terminated, the bus relinquished, and an interrupt generated to indicate the error to the host processor. A[0-7] V/O (tristate) ADDRESS [0-7] When the CL-CD2400 is not a bus master, these pins are inputs used to determine which registers are being accessed, or which interrupt is being acknowledged. When ADLD* is low, A[0-7] output address bits 8 through 15 for external latching. When the CL-CD2400 is a bus master, A[0-7] output the least significant byte of the transfer address. A/D[0-15] V/O (tristate) ADDRESS/DATA [0-15] - When the CL-CD2400 is not a bus mas- ter, these pins provide the 16-bit data bus for reading and writing to the CL-CD2400 registers. When ADLD* is low, A/D[0-15] provide the upper address bits for external latching. When the CL-CD2400 is a bus master, A/D[0-15] provide a multiplexed address/data bus for reading and writing to system memory. ADLD* Output (tristate) ADDRESS LOAD* - This is a strobe used to externally latch the upper portion of the system address bus A[8-31]. While ADLD is low, address bits 16 through 31 are available on A/D[0:15], and address bits 8 through 15 on A[0-7]. ; AEN* Output (tristate) ADDRESS ENABLE* This output is used to output enable the external address bus drivers during CL-CD2400 DMA cycles. August 1993 a EEE eRe NaeRrenEeeRS Pin Information 9MH 2156639 OOOb163 93D MCIR en SSS CL-CD2400/2401 === == CIRRUS LOGIC Multi-Protocol Controller 1.5 Pin Descriptions Symbol Type Description DATDIR* Output (tristate) DATA DIRECTION* This output is active when either the CL- CD2400 is a bus master, or the CS" Pin is tow. It is used to control the external data buffers; when low, the buffers should be enabled in the CL-CD2400 to system bus direction. DATEN* Output (tristate) DATA ENABLE* This output is active when either the CL-CD2400 is a bus master, or the CS* and DS* Pirs are low. It is used to enable the external data bus buffers during host register read/write operations or during DMA operations. For operations on 32-bit buses, this signal needs to be gated with A[1] to select the correct half of the data bus. CLK Input CLOCK - system clock. BUSCLK Output BUS CLOCK - This is the system clock divided by 2 which is used internally to control certain bus operations. This pin is driven low during hardware reset. RESET* Input RESET - This signal should stay valid for a minimum of 20 ns. The reset state of the CL-CD2400 will be guaranteed at the rising edge of this signal. When RESET" is removed, the CL-CD2400 also performs a software initialization of its registers. TEST Input TEST In normal operation, this pin should be kept low. For board- level testing purposes, it provides a mechanism for forcing normal output pins to High Impedance Mode. When the TEST Pin is high, the following pins will be in High Impedance Mode: BUSCLK, BGOUT*, IACKOUT*, RXCout[0:3}], RTS*[0:3], DTR*[0:3] and TXD{(0:3}. To ensure all CL-CD2400 outputs are high impedance, either of the following two conditions must be met: the RESET* Pin can be driven iow, and the TEST Pin driven high; or, the CL-CD2400 is kept in the bus idle state (not accessed for read/write operations nor DMA active), and the TEST Pin is driven high. RTS*(0-3] Output REQUEST TO SEND [0-3] - This output can be controlled au- tomatically by the CL-CD2400 to indicate that data is being sent on the TXD Pin. TXCoutv/DTR* Output TRANSMIT CLOCK OUT/DATA TERMINAL READY* [0-3] - This [0-3] output can be controlled automatically by the CL-CD2400 to indicate a programmable threshold has been reached in the receive FIFO. It can also be programmed to output the transmit data clock. Following reset, this pin will be high and will stay high in Clock Mode until the transmit channel is enabled for the first time; after which, it remains active independent of the state of the transmit enable. In all modes, the clock transitions every bit time, even during idle fillin Asynchronous Mode. Data transitions are made on the negative going edge of TXCout. 10 Pin Information _ August 1993MB 2136639 O00b1by 377 MECIR CL-CD2400/2401 SSS Multi-Protocol Controller =] CIRRUS LOGIC 1.5 Pin Descriptions (cont.) Symbol Type Description RxXCout[0-3] Output RECEIVE CLOCK OUT [0-3] - This output provides a one-time bit rate clock for the receive data in all modes, except when an input (RXCin) one-time receive clock is used. After reset, this pin will be low until the channel is receive enabled for the first time, after which it remains active, independent of the state of receive enable. When in Asynchronous Mode, the output only transitions while receiving data and not during inter-character fill. The receive data is sampled on the positive-going edge of this clock. CTS*[0-3] Input CLEAR TO SEND* [0-3] This input can be programmed to contro! the flow of transmit data, for out-of-band flow control applications. TXCIN/CD* Input TRANSMIT CLOCK/CARRIER DETECT* [0-3] This pin is always [0-3) visible in the MSVR Register. On the CL-CD2400, it also inputs the transmit clock to the bit rate generator. On the CL-CD2401, these functions are separated onto two pins. When used as CD, this input can be programmed to validate receive data. RXCIN/DSR* Input RECEIVE CLOCK/DATA SET READY [0-3] This pin is always (0-3] visible in the MSVR Register. On the CL-CD2400, it also inputs the receive clock to the bit rate generator. On the CL-CD2401, these functions are separated onto two pins. When used as DSR, this input can be programmed to validate receive data. TXD[0-3) Output TRANSMIT DATA [0-3] Serial data output for each channel. RXD(0-3] Input RECEIVE DATA [0-3] - Serial data input for each channel. BYTESWAP Input This pin alters the byte ordering of data during certain 16-bit transfers and changes the half of the data bus on which byte transfers are made to comply with Intel or Motorola processor systems. BYTESWAP does not alter the bus handshake signals. When the BYTESWAP Pin is high, the byte on A/D[0:7] precedes that on A/D[8:15] in a string of transmit or receive bytes; when BYTESWAP is low, A/D[8:15} precedes A/D[0:7].. When the BYTESWAP Pin is high, bytes are transferred on A/D[0:7] when A[O} is low, and on A/D[8:15] when A[0} is high. When BYTESWAP is low, bytes are transferred on A/D[8:15] when A[0] is low, and A/D[0:7] when A[Q] is high. A different register map is used, depending on the state of this pin. BYTESWAP BYTE ALIGNMENT 0 Motorola byte alignment 1 Intel byte alignment August 1993 eT Pin Information 11re rE TE, a OE TO, a ENE S22 CIRRUS LOGIC 2. REGISTER TABLE Registers in the CL-CD2400 are either global or per-channel. The column 'Address Mode' in the Register Map on the following pages defines this attribute for each register. Only one set of global registers exists. The global registers are accessible by the host at any time. Four sets of per-channel registers exist; the set accessible at any one time is determined by the currently active channel number. The channel number is selected by the host in normal (non-interrupt) processing by writing to the Channel Access 12 Register Table MH 2136659 0006165 703 MCIR CL-CD2400/2401 Multi-Protocol Controller Register. The channel number in the Channel Access Register remains in force until changed by the host. The channel number is provided automatically by the CL-CD2400 during interrupt service routines and DMA transfers. In the following list, some register locations appear twice. They have different names and functions for Asynchronous Operation and Synchronous Protocol Operation. See Section 6 of this document for detailed descriptions of all register functions. August 1993MB 2136639 OOObLbE bYT MMICIR CL-CD2400/2401 S33 Multi-Protocol Controller ===" CIRRUS LOGIC 2.1 CL-CD2400 Memory Map 2.1.1 Global Registers Addr. Page Mode! INT2 MOT? Size Access No. Global Firmware Revision Code {GFRCR} G 8281 B R 70 Register Channel Access Register {CAR} G EC EE B RW 70 2.1.2 Option Registers Channel Mode Register {CMR} P 18 1B B RAW 71 Channel Option Register 1 {COR1} P 13 10 B RW 72 Channel Option Register 2 {COR2} P 14 17 B RAW 74 Channel Option Register 3 {COR3} P 15 16 B RW 78 Channel Option Register 4 {COR4} P 16 15 B RW 82 Channel Option Register 5 {COR5} P 17. 14 B RAW 83 Channel Option Register 6 {COR6} P 1B. sO+AB B RW 84 Channel Option Register 7 {COR7} P 04 07 B RW 86 Special Character Registert {SCHR1} P 1G 1F B RW Async 87 Special Character Register? {SCHR2} P 1D 1E B RW Async 87 Special Character Register3 {SCHR3} P 1E 1D B R/W Async 87 Special Character Register4 {SCHR4} P 1F 61C B RW Async 87 Special Character Range low {SCRI} P 20 23 B RW Async 88 Special Character Range high {SCRh} P 21 22 B R/W Async 88 LNext Character {LNXT} P 2D 2E B RW Async 88 Receive Frame Address Register1 {RFAR1} P 1c 1F B RAW Sync 88 Receive Frame Address Register2 {RFAR2} P 1D 1E B RW Sync 88 Receive Frame Address Register3 {RFAR3} P 1E #10 B RW Sync 88 Receive Frame Address Register4 {RFAR4} P 1F 61 B RW Sync 88 CRC Polynomial Select Register {CPSR} P D4 D6 B RAW Sync 88 NOTES: The following are applicable for Sections 2.1.1 through 2.1.7: 1 Address Mode G: Global register one set is always accessible. Address Mode P: Per-channel register - four Sets, one per channel, accessible via CAR or interrupt context. INT = address for Intel-style processor. 3 MOT = address for Motorola-style processor. August 1993 Register Table 13MM 2136639 000616? 546 MCIR CL-CD2400/2401 ae co : = CIRRUS LOGIC Multi-Protocol Controller 2.1.3 Bit Rate and Clock Option Registers Addr. Page Mode INT2 MOT? Size Access No. Receive Baud Rate Period Register {RBPR} P cg9 cB 8B RW 89 Receive Clock Option Register {RCOR} P CA C8 B RW 89 Transmit Baud Rate Period Register {TBPR} P Ci C3 B RAW 90 Transmit Clock Option Register {TCOR} Pp c2 Co B RAW 90 2.1.4 Channel Command and Status Registers Channel Command Register {CCR} P 10 13 B RAW 91 Special Transmit Command Register {STCR} P 11.12 B Rw 93 Channel Status Register {CSR} P 19 #1A B R 94 Modem Signal Value Registers {MSVR-RTS} P DC DE B RW 97 {MSVR-DTR} P DD DF B RAV 97 14 Register Table wenn menmmmmnennees August 1993@@ 2136639 O00b1b8 44a MECIR CL-CD2400/2401 ESS Multi-Protocol Controller === CIRRUS LOGIC 2.1.5 Interrupt Registers Addr. Page Mode! INT2 MOT3 Size Access No. Local Interrupt Vector Register {LIVR} P OA ag B RAW 98 Interrupt Enable Register {IER} P 12 #11 B RAW 99 Local Interrupting Channel Register {LICR} P 25 26 B RAW 100 Stack Register {STK} G EQ E2 B R 101 2.1.5.1 Receive Interrupt Registers Receive Priority Interrupt Level {RPILR} G E3 1 B Rw 102 Register Receive Interrupt Register {RIR} G EF ED B R 102 Receive Interrupt Status Register {RISR} G 8A 88 Ww RW 103 Receive Interrupt Status Register low {RISRI} G 8A 89 B R 103 Receive Interrupt Status Register high {RISRh} G 8B 88 B R 106 Receive FIFO Output Count {RFOC} P 33 30 B R 106 Receive Data Register {RDR} G FS F8 B R 106 Receive End Of Interrupt Register {REOIR} G 87 84 B Ww 107 2.1.5.2 Transmit Interrupt Registers Transmit Priority Interrupt Level {TPILR} G E2 0 B RW 108 Register Transmit Interrupt Register {TIR} G EE EC B R 108 Transmit Interrupt Status Register {TISR} G 89 8A B R 109 Transmit FIFO Transfer Count {TFTC} G 83 80 B R 110 Transmit Data Register {TDR} G F8 F8 B Ww 110 Transmit End Of Interrupt Register {TEOIR} G 86 85 B Ww 1 2.1.5.3 Modem Interrupt Registers Modem Priority Interrupt Level {MPILR} G Et 3 B RW 112 Register Modem interrupt Register {MIR} G ED EF B R 112 Modem (/Timer) Interrupt Status {MISR} G 88 8B B R 113 Register Modem End Of Interrupt Register {MEOIR} G 85 86 B Ww 113 August 1993 wummmmn =6 Register Table 15Se -, CIRRUS LOGIC 2.1.6 DMA Registers DMA Mode Register (write only) Bus Error Retry Count DMA Buffer Status 2.1.6.1 DMA Receive Registers A Receive Buffer Address Lower A Receive Buffer Address Upper B Receive Buffer Address Lower B Receive Buffer Address Upper A Receive Buffer Byte Count B Receive Buffer Byte Count A Receive Buffer Status B Receive Buffer Status Receive Current Buffer Address Lower Receive Current Buffer Address Upper 2.1.6.2. DMA Transmit Registers A Transmit Buffer Address Lower A Transmit Buffer Address Upper B Transmit Buffer Address Lower B Transmit Buffer Address Upper A Transmit Buffer Byte Count B Transmit Buffer Byte Count A Transmit Buffer Status B Transmit Buffer Status Transmit Current Buffer Address Lower Transmit Current Buffer Address Upper 16 Register Table Addr. Mode! {DMR} G {BERCNT} G {DMABSTS} P {ARBADRL} P {ARBADRU} P {BRBADRL} P {BRBADRU} P {ARBCNT} P {BRBCNT} P {ARBSTS} P {BRBSTS} P {RCBADRL} P {RCBADRU} P {ATBADRL} {ATBADRU} {BTBADRL} {BTBADRU} {ATBCNT} {BTBCNT} {ATBSTS} {BTBSTS} {TCBADRL} {TCBADRU} vvuVvVVVTVITVUVV MBH 2136639 0006169 359 BECIR CL-CD2400/2401 INT2 F4 8D 1A 40 42 44 46 48 4a 4c 4D 3c 3E 50 $2 54 56 58 5A 5C 5D 38 3A Multi-Protocol Controller MoT3 F6 8E 19 42 40 46 44 4A 48 4F 4e 3E 3c 52 50 56 54 5A 58 5F 5E 3A 38 Size oan ZSSEPVDSES2222 SSEMWMSSEe2zz2 Page Access No. WwW 114 RAV 114 R 115 RW 116 RW 116 RW 116 RW 116 RAW 116 RAW 116 RAW 116 RAW 116 R 117 R 117 RAW 107 RAW 117 R/V 117 RW 117 RW 117 RW 117 RAW 118 RAV 118 R 119 R 119 August 1993MB 2136639 006170 o79 MECIR CL-CD2400/2401 EES Multi-Protocol Controller ===" CIRRUS LOGIC 2.1.7 Timer Registers Addr. Page Mode! INT2 MOTS Size Access No. Timer Period Register {TPR} G D8 DA 8B RAW 119 Receive Timeout Period Register {RTPR} P 26 24 Ww RAW Async 119 Receive Timeout Period Register low {RTPRI P 26 25 B RAW Async 119 Receive Timeout Period Register high {RTPRh} P 27 24 B RW Async 119 General Timer 1 {GT1} P 28 2A Ww R Syne 120 General Timer 1 low {GTi} P 28 2B B R Sync 120 General Timer 1 high {GT th} P 29 2A B R Sync 120 General Timer 2 {GT2} P 2A 29 B R Sync 120 Transmit Timer Register {TTR} P 2A 29 B R Async 120 August 1993 qeunesmmnemmnesnemn wean Register Table 17ae ee er A a === CIRRUS LOGIC 2.2 Register Definitions 2.2.1 General Global Registers MB 2136639 0006171 TO? MCIR CL-CD2400/2401 Multi-Protocol Controller Global Firmware Revision Code {GFRCR} 82 81 B Register i Firmware Revision code Channel Access Register {CAR} EC EE B I 0 | 0 | 0 | 0 | 0 {. 0 | Ct | co | 18 Register Table een nen August 1993MB 2136639 0006172 T43 MECIR CL-CD2400/2401 = eo Conroe ===> CIRRUS LOGIC 2.2.2 Option Registers Channel Mode Register {CMR} 18 1B B RW | RxMode | TxMode | 0 0 0 chmd2 | chmd1 | chmdo | Channel Option Register 1 {COR1} 13 10 B R/W HDLC | AFLO | CirDet | AdMdet AdMded | Flags3 | Flags2 | Flags! | Flagso Asyne/Bisync/X.21 | Parity | Pat | Parvo Ignore | Chi3 | Chi2 Chit | Chio Channel Option Register 2 {COR2} 14 17 B R/W HDLC I 0 | FCS | 0 | 0 RtsAQ | CtsAE | DsrAE Async | IXM | TxIBE | ETc } 0 | ALM [| Ftsao | CtsAE | Dsrac | Bisync | urc | Bcc | E8coIC | CRCNinv | 0 | 0 | 0 [ 0 | X.21 z= | 0 | 0 | ETC | 0 | 0 | 0 0 | Channe! Option Register 3 {COR3} 15 16 B R/W HDLC/Bisync [ sndsyne | Altt | res | CRC | Idle | pad2 | pad1 pado | Async | ESCOE | RNGoE [FCT | SCDE Spistp | Stop2 | Stop1 Stopo | X.21 | 0 | SSDE | stpsyn | ScbE | 0 | 0 0 | 0 | Channel Option Register 4 {COR4} 16 15 B R/W | DSRzd | CDzd | CTSzd | 0 | FIFO Threshold | Channel Option Register 5 {COR5} 17 14 B R/W | OSRod | CDod | CTSod | 0 Rx Flow Control Threshold | August 1993 ee umes Register Table 19MH 21356639 0006173 gar @ECIR SS CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocol Controller 2.2.2 Option Registers (cont.) Channel Option Register 6 {COR6} 1B 18 B RAV Async | Igncr | ICRNL | INLCR | IgnBrk | NBrkint Park | INPCK | Parint | Channel Option Register 7 {COR7} 04 07 B RAW Async | stip | ue | Fcer [0 | 9 [| 0 | once | ocean | Special Character Register1 {SCHR1} 1G 1F B R/W Async Special Character Register2 {SCHR2} 1D 1E B R/W Async Special Character Register3 {SCHR3} 1E 1D B R/W Async Special Character Register4 {SCHR4} 1F 1c B R/W Async Special Character Range low {SCR} 20 23 B R/W Async Special Character Range high {SCRh} 21 22 B R/W Async LNext Character {LNXT} 2D 2E B RW Async Receive Frame Address Registert {RFAR1} 1C 1F B R/W Sync Receive Frame Address Register2 {RFAR2} 1D 1E B RW Sync Receive Frame Address Register3 {RFAR3} 1E 1D B RW Sync Receive Frame Address Register4 {RFAR4} 1F 1C B R/W Sync CRC Polynomial Select Register {CPSR} D4 D6 B RAW | res | res | res | res | res | res | res i poly | 20 Register Table mmnsmsmmsssmsmmsecaremmsmnsnsunsmsemmmnsnnmmnemsseneremmnnmnsneemne August 1993MH 2136639 OOOb1L74 71b MICIR CL-CD2400/2401 Sq Multi-Protocol Controller ===" CIRRUS LOGIC 2.2.3 Bit Rate and Clock Options Registers Receive Baud Rate Period Register {RBPR} cg cB B RAW | Receive Baud Rate Period (Divisor) | Receive Clock Option Register {RCOR} CA C8 B RAW TLVal | res | dpllEn | Optima } Dpiimda | CkSel2 | CikSelt | cikseto | Transmit Baud Rate Period Register {TBPR} Ci C3 B RAW | Transmit Baud Rate Period (Divisor) | Transmit Clock Option Register {TCOR} C2 co B RAW | CkSel2 | ClkSelt | ckseto | res | Ext-1X | res |] uM | tes | August 1993 TT ees Register Table 21MH 2156639 0006175 b52 MECIR CL-CD2400/2401 Multi-Protocol Controller 2.2.4 Channel Command and Status Registers Channel Command Register {CCR} 10 13 B RW | 0 | ClrCh | InitCh | RstAll | EnTx | DisTx | Enix | Disx {| 1 [om [om ] o [ o [ o [oo [ o | Special Transmit Command Register {STCR} 11 12 B RAW | 0 | AbortTx JAppdGmp | 0 | SndSpe | ssPc2 | SsPct | SSPCO Channel Status Register {CSR} 19 1A B R HDLC | RxEn | RxFlag | RxFrame | RxMark | TxEn | TxFlag | TxFrame TxMark | Async | Rxn | FxFloff | RxFlon | 0 | TxEn | TxFiott | TxFion | 0 | Bisyne | xen | RxiTB | RxFrme | 0 | TxEn | TeTe | TxFrme | 0 | X.21 | RxEn | 0 | FxSpe | 0 | ten | 0 | TxSpe | 0 | Modem Signal Value Registers {MSVR} RAW Modem Signal Value Register {MSVR-RTS} DC DE B RAW {MSVR-DTR} DD DF B R/AV [DSR/RxCk | CD/TxCk | cTs | DTRopt | res | Porto | oT | RTs | 22 Register Table = August 1993MH 2136639 0006176 599 MECIR CL-CD2400/2401 EEE Multi-Protocol Controller === CIRRUS LOGIC 2.2.5 Interrupt Registers Local Interrupt Vector Register {LIVR} 0A 09 B RAW | x [ x | x J x J x [ x Jom [mo ] Interrupt Enable Register {IER} 12 14 B RAW | Mdm | 0 | RET | 0 | RxD | Timer | TxMpty | TxD | ~ Local Interrupting Channel Register {LICR} 25 26 B RW Lx fx |x | x Po To px Tx] interrupt Stack Register {STK} EO E2 B R | civ 1] | MLvI [1] | tev [4] | 0 0 | TLvi [0] | MLvI {0] | Clu {0} August 1993 wa Register Table 23MB 2156639 0006127 425 MMCIR ee CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocol Controller 2.2.5.1 Receive Interrupt Registers Receive Priority Interrupt Level Register {RPILR} ES Ef B RAW Receive Interrupt Register {RIR} EF ED B R | Ren | Ract | Revi { 0 } vet [1] | Rvct (0) | Ren [1) | Ren (0) | Receive Interrupt Status Register {RISR} 8A 88 Ww R Receive Interrupt Status Register low {RISR} 8A 8g B R HDLC } 0 | EOF | rxabt | CRC | oF | Resin | o | Cirdet | Async | Timeout | SCdet2 | SCdeti | SCdeto | OE | PE | Fe | Break | Bisyne Lo | cor | mat [oo To To fo | 0 ' X.21 [ tva | sCdet2 | SCdet1 | scaet | OE | PE | 0 | Lchg | Receive Interrupt Status Register high {RISRh} 8B 88 B R | Ber | EOF [| con | o | saBe | o {| o | o | Receive FIFO Output Count {RFOC} 33 30 B R | 0 | 0 x | Axcta | Axcts | Axct2 [| Rxctt [ Axcto | Receive Data Register {RDR} FB F8 B R [Lo [= pe Tete pe to [Te] Receive End Of Interrupt Register {REOIR} 87 84 B WwW [TermButt | DiscExc | SetTm2 | SetTmt [ Notranst | Gap2 | Gap1 | Gapo | 24 Register Table _ enn August 1993ME 2136639 0006178 34, MECIR CL-CD2400/2401 Multi-Protocol Controller =m 2.2.5.2 Transmit Interrupt Registers Transmit Priority Interrupt Level Register {TPILR} E2 0 Transmit Interrupt Register {TIR} FE EC | Ten | Tact | Tei [0 [| twee in} | Tvet (0) | Ton it] | Ton (0) | Transmit Interrupt Status Register {TiISR} 89 8A | Ber | EOF | EOB | UE | BABB | 0 | TxEmpty | TxDat | Transmit FIFO Transfer Count {TFTC} 83 80 | 0 | 0 | 0 | Txct4 | Txct3 | Txct2 | Txctt | Txcto | Transmit Data Register {TDR} F8 F8 Lv [oe [To [ou [To [oe [ole] Transmit End Of Interrupt Register {TEOIR} 86 85 [Termeut | EOF | Settme | settmt | Notranst] 0 [oo { o | Modem Priority Interrupt Level Register {MPILR} E1 3 Modem Interrupt Register {MIR} ED EF | Men | Mact | Meoi [ 0 | Mvct [1] | Mvet [0] | Men [1] | Mcn (01 | Modem (/Timer) Interrupt Status {MISR} 88 8B Register | DSRChg | CDChg | oTschg | res I res res | Timer 2 | Timer | Modem End Of Interrupt Register {MEOIR} 85 86 {| 0 z= [ Settma [ settmt | o {| o | o | o | August 1993 === CIRRUS LOGIC B RAW B R B R B R B Ww B Ww B RAW B R B R B Ww was Register Table 25MH 2136639 0006179 eT& MECIR == CL-CD2400/2401 S20 IRRUS LOGIC Multi-Protocol Controller 2.2.6 DMA Registers DMA Mode Register {DMR} F4 F6 F8 W [ 0 | 0 | 0 | 0 | Bytepma | 0 | 0 | 0 | Bus Error Retry Count {BERCNT} 8D 8E B RW DMA Buffer Status {DMABSTS} 1A 19 B R | TDAIgn | RstApd | CrtBut | Append | Ntbuf | Tbusy I Nrbuf | Rbusy 2.2.6.1. DMA Receive Registers A Receive Buffer Address Lower {ARBADRL} 40 42 Ww RAW A Receive Buffer Address Upper {ARBADRU} 42 40 WwW R/AW B Receive Buffer Address Lower {BRBADRL} 44 46 W RW B Receive Buffer Address Upper {BRBADRU} 46 44 WwW RW A Buffer Receive Byte Count {ARBCNT} 48 4A WwW R B Buffer Receive Byte Count {BRBCNT} 4A 48 Ww R A Receive Buffer Status {ARBSTS} 4c 4F B RAW B Receive Buffer Status {BRBSTS} 4D 4E B Rw | Ber | coF | coB | o | o | o | 0 [24000wn | Receive Current Buffer Address Lower {RCBADRL} 3C 3E W R Receive Current Buffer Address Upper {RCBADRU} 3E 3G )CtCW R 26 Register Table we August 1993MB 2436639 0006180 TIT MECIR CL-CD2400/2401 SS Multi-Protocol Controller ==CIRRUS LOGIC 2.2.6.2 DMA Transmit Registers A Transmit Buffer Address Lower {ATBADRL} 50 52 WwW RAW A Transmit Buffer Address Upper {ATBADRU} = 552 50 WwW RAV B Transmit Buffer Address Lower {BTBADRL} 54 56 W RW B Transmit Buffer Address Upper {BTBADRU} 56 54 Ww RW A Buffer Transmit Byte Count {ATBCNT} 58 SA W RAW B Buffer Transmit Byte Count {BTBCNT} 5A 58 Ww RAW A Transmit Buffer Status {ATBSTS} 5C 5F B RAW B Transmit Buffer Status {BTBSTS} 5D 5E B RAW | Berr Eor | 0B } 0 | Append 0 { INTR |24000wn | Transmit Current Buffer Address Lower {TCBADRL} 38 3A Ww R Transmit Current Buffer Address Upper {TCBADRU} 3A 38 WwW R August 1993 an a Register Table 27Oe CE ce === CIRRUS LOGIC Mi 2136639 0006141 156 BACIR CL-CD2400/2401 Multi-Protocol Controller 2.2.7 Timer Registers Timer Period Register {TPR} D8 DA B | Binary Value Receive Timeout Period Register {RTPR} 26 24 WwW Receive Timeout Period Register low {RTPRE 26 25 B Receive Timeout Period Register high {RTPRh} 27 24 B General Timer 1 {GT1} 28 2A W General Timer 1 low {GTi} 28 2B B General Timer 1 high {GTin} 29 2A B Generat Timer 2 {GT2} 2A 29 B Transmit Timer Register {TTR} 2A 29 B 28 Register Table NE R/W Async R/W Async R/W Async R Sync R Sync R Sync R Sync R Async August 1993CL-CD2400/2401 Multi-Protocol Controller 3. FUNCTIONAL DESCRIPTION 3.1 Host Interface The Ct-CD2400 is a synchronous device with an asynchronous bus interface. A stable input clock is required on the CLK Pin nominally 20 MHz. CLK is divided by two internally, and the resulting signal is output on the BUSCLK Pin. The baud-rate generators and timers are also related to CLK. The AC timing characteristics in Section 7 show that many input signal set-up and output signal transitions are related to the edges of the CLK and BUSCLK Signals. It is possible, however, to use the CL-CD2400 in a purely asynchronous bus environment. The CL-CD2400 can act as either bus master during DMA transfers, or as a bus slave device during normal host read and write transfers. Both byte and word transfers are supported in each of the Bus Slave and DMA Bus Master cs 1 DS* RW ME 2156639 O0Ob182 84a M@ECIR i ee ET, ===" CIRRUS LOGIC Modes. Figures 3-0 and 3-1 show the signals involved in these transfers. 3.1.1 Host Read and Write Cycles The host read and write cycles begin with the activation of the Chip Select (CS*) and Data Strobe (DS*) Signals. The Data Direction (DATADIR*) and Data Enable (DATEN*) Signals are used fo control external data buffers. The falling edge of the Data Transfer Acknowledge (DTACK*) Signal indicates that the transfer is complete. DTACK* will be released when DS is deasserted. CS* should also be deasserted at that time. The Address Strobe (AS") is not used during slave cycles; it is an output during DMA transfers. Note that the following open-drain/tri-state outputs should have pull-up resistors attached: AEN", AS*, DATADIR*, DATEN* and DTACK. - - A/D [0:15] A (0:7), SIZ [0:1] > DTACK Figure 3-0. Host Read Cycle August 1993 Func. Desc. 29_ er ae EO, eee ane wcainibelececca_% SS" CIRRUS LOGIC MM 2136639 0006143 729 mmcIR CL-CD2400/2401 Multi-Protocel Controller A (0:18 Aten, safes) <__ > OTACK* Ld DATEN* ___ dC SN DATDIRS, Figure 3-1. 3.1.2 Byte, Word Transfers Data may be moved to and from the CL-CD2400 in either byte or word transfers. To accommodate various families of host processors, the BYTESWAP Input Pin is set to indicate the system byte-ordering scheme. The SIZE Pins (SIZ[1,0]) are used to indicate whether the transfer is one or two bytes wide. In systems where the even addresses represent the high-order byte, the BYTESWAP Input should be tied low, and byte transfers will take place on the A/D[15:8] Pins for even addresses and on the A/D[7:0] Pins for odd addresses. In systems where the high-order byte is on the odd address, the situation is reversed, and BYTESWAP should be tied high. Byte transfers to even addresses will take place on the A/D[7:0] Pins, and to odd addresses on the A/D[15:8] Pins. 3.2 Interrupts The CL-CD2400 uses Interrupt Requests to alert the host that certain events have taken place. Interrupt operations on the CL-CD2400 are 30 Func. Desc. ee Host Write Cycle tightly coupled with several registers described below. The concept of context affects the accessibility of these and other registers. 3.2.1 Contexts and Channels The registers in the CL-CD2400 are grouped into global, virtual, and four sets of per-channel registers. The CL-CD2400 is normally in the Background Context, where the Channel Access Register (CAR) selects the channel number for per-channel registers. The Interrupt Context begins with the interrupt acknowledge bus cycle, and ends with a write access to the appropriate End Of Interrupt Register. In the Interrupt Context, only the per-channel registers for the channel number being serviced are available; the CAR has no effect. Most Global Registers are available at all times, but some are shared by the four channels, such as the FIFO Registers. These are called virtual registers, and must be accessed only during the Interrupt Context. Interrupt contexts can be nested so that a higher priority interrupt service can preempt a lower priority one already in progress. The CL- August 1993CL-CD2400/2401 Multi-Protocol Controller CD2400 pushes the current Interrupt Context onto the stack, visible in the Stack (STK) Register, and enters the context for the newly acknowledged interrupt. Any register accesses will be in the new Interrupt Context until the host does a write to the appropriate EOIR for the top- level context. The CL-CD2400 will then pop the top level context off the stack and return to the previous Interrupt Context. 3.2.2 Interrupt Registers The Interrupt Enable Register (IER) and the Local Interrupt Vector Register (LIVR) are per- channel registers. 1ER contains bits used to enable or disable the various interrupt sources within the CL-CD2400. The LIVR value is output on the data bus during the interrupt acknowledge cycle. There are sets of three global registers that correspond to the three IREQn* | ff 7 IACKIN* ma wewed nee MH 2136635 cooky bbS MMICIR ee se SE SS="CIRRUS LOGIC types of interrupts: Receive, Transmit and Modem. The Priority Interrupt Level Registers, RPILR, TPILR and MPILR are programmed to contain the value that will be present on the address bus during the interrupt acknowledge bus cycle for each type of interrupt. The interrupt Status Registers, RISR, TISR or MISR, are examined during the interrupt service routine to determine the cause of each type of interrupt. The Transmit (TDR) and Receive (RDR) Data Registers provide access to the FIFO buffers for each channel. They must not be accessed outside of the proper interrupt context. A write operation to the End Of Interrupt Registers, REOIR, TEOIR or MEOIR, must be the last access to the CL-CD2400 at the end of this handler routine to return it to its Background Context. = 1 Clock Delay CL-CD2400 DS Samples Ad Bus [LlT_L. RW*, CS* A/D [0:15] A(0:7] DTACK* DEN* DATDIA* * Interrupt Vector is always driven on A/D[0:7] Figure 3-2. August 1993 Interrupt Acknowledge Cycle sean TE Func. Desc. 31Ln TE, SO, nee ===>" CIRRUS LOGIC 3.2.3 Groups and Types There are two general reasons for the CL- CD2400 to request service from the host Processor, data transfer and exceptional conditions. Furthermore, interrupts are grouped into three categories, each with an associated interrupt Request Signal: IREQ1*, IREQ2*, IREQ3*. Group 1 Modem Signal Change/Timer Events Group 2 Transmit interrupts Group 3 Receive Interrupts Group 1 is only used for exceptions. Groups 2 and 3 include both data transfer and exceptions. M@ 2136639 0006185 STL MMCIR CL-CD2400/2401 Multi-Protocol Controller Table 3-0 shows the possible causes of transmit and receive interrupt service requests. The cause of an interrupt request is encoded into the two least-significant bits of the vector presented on the data bus during the interrupt acknowledge cycle. The upper six bits of the vector come from the LIVR: Interrupt Vector LSBs 00 Receive Exception 01 Modem signal Change or Timer Event 10 Transmit Data or Exception 11 Receive Good Data Table 3-0. Transmit and Interrupt Service Requests Interrupt Cause Async Bisyne HDLC X.21/Prog Receive Good Data X Xx x x Not in DMA _ Mode Break Detect x Framing Error x Parity Error x X X Receive Timeout, no data xX Special Character Match X xX Transmitter Empty Xx X xX xX Tx FIFO Threshold x X X Not in DMA Mode Receive Overrun X X xX x Clear Detect x CRC Error X x Residual Bit Count X Receive Abort x End of Frame x x Xx Transmit Underrun X Bus Error X Xx X xK DMA Mode only End of Buffer X x x X DMA Mode only 32 Func. Desc. August 1993, CL-CD2400/2401 Multi-Protocol Controller 3.2.4 Hardware Signals and 1ACK Cycles The Interrupt Acknowledge (IACK) bus cycle begins with the Interrupt Acknowledge In (IACKIN*) and DS* asserted, and a value matching the appropriate PILR contents on the lower seven address bus bits, A[6:0]. If the IACK cycle is valid, that is, the PILR values match, the corresponding vector from the interrupting channel LIVR will be driven onto the data bus and DTACK asserted. DTACK" is released after DS* is removed. Figure 3-2 shows the interrupt acknowledge cycle timing. It is similar to the basic host read cycle except that IACKIN* is active, and CS* is inactive. The three IREQn* Pins are open-drain outputs requiring external pull-up resistors, nominally 4.7K ohm. The Interrupt Acknowledge Out (IACKOUT") is used to form a daisy chain in systems with more than one CL-CD2400 (see Section 3.2.5). 3.2.4.1. Programming the PILR Registers The three Priority Interrupt Level Registers must be programmed with values that correspond to the lower seven address bits that will be present on A[6:0] during the interrupt acknowledge bus cycle. Some CPUs output the priority level of the interrupt that they are acknowledging on the bus during the IACK cycle. In these systems the three PILR values will be unique. In other systems that do not use this scheme, the PILR values may be the same or different depending on the specific design. When all of the PILR registers contain the same value and multiple IREQn* lines are asserted, the CL-CD2400 imposes the following priority scheme to determine which interrupt request will be acknowledged: Highest Priority: Receive Interrupt Transmit Interrupt Lowest Priority: Modem Interrupt 3.2.4.2 Systems with Interrupt Controllers Some systems use an interrupt controller that Supplies its own vector during the interrupt acknowledge cycle. The CL-CD2400 needs an IACK cycle in response to its interrupt request in order to function properly. These systems can August 1993 7 ME 2136639 0006186 438 MECIR | | ===" CIRRUS LOGIC decode three distinct locations from the CL- CD2400 to produce an IACKIN* instead of CS*. The PILR registers should be programmed with the addresses of these three locations. Alternatively, a single location may be decoded and the three PILRs given identical values as described above. In either case, the host should read one of these locations before the first access to the device in an interrupt service routine. The CL-CD2400 will enter its interrupt acknowledge context for the proper type and channel, and the data returned will be the chip interrupt vector from the LIVR. 3.2.5 Multi-CL-CD2400 Systems Multiple CL-CD2400s can be chained together for systems requiring more than four channels. Each group of interrupt request lines IREQn* may be connected in a parallel wired-OR fashion. The system Interrupt Acknowledge Signal is connected to the Interrupt Acknowledge In (IACKIN*) Pin of the first device, and its Interrupt Acknowledge Out (IACKOUT*) is then connected to the IACKIN* of the next device, and so on, forming a chain of CL-CD2400s. 3.2.5.1 Keep/Pass Logic The acceptance of an interrupt acknowledge cycle by the CL-CD2400 depends on whether the part is requesting service and whether the lower seven address bits match the contents of the appropriate PILR Register. The following rules apply to the keep/pass logic: 1. If the CL-CD2400 does not have an interrupt asserted, the interrupt acknowledge is passed out on IACKOUT*. 2. If the CL-CD2400 is asserting one or more of its interrupts, but the interrupt priority levels driven on the address bus by the host does not match the contents of the appropriate PILR Register. This interrupt acknowledge is also passed out on the [ACKOUT". 3. If the CL-CD2400 is asserting an interrupt, and the interrupt priority level on the address bus matches the PILR Register for that interrupt type. The interrupt acknowledge will be accepted by the CL-CD2400, and the vector from the LIVR will be driven onto the data bus. ARRAS Func. Desc. 33 rT, a, me, ae PY ===> CIRRUS LOGIC 3.2.5.2 Falr Share Scheme When multiple CL-CD2400 are chained, the Fair Share logic in these devices guarantees that the interrupts from all CL-CD2400s in the system are presented to the host with equal urgency. There is no positional hierarchy in the interrupt scheme, i.e., the CL-CD2400 that is farthest from the host has an equal chance of getting its interrupts through as the CL-CD2400 that is nearest to the top of the interrupt chain. The fair share scheme is totally transparent to the user, and no enabling or disabling is required. When an interrupt request line is asserted, the fair bit for that type of interrupt on the asserting device is cleared. The fair bit will remain cleared until the interrupt line returns to a high state. The CL-CD2400 will not assert a new interrupt of that type while the corresponding fair bit is cleared. Therefore, when multiple CL-CD2400s assert interrupts together, each one will be serviced in turn, before they can reassert the same interrupt The IREQn* interrupt request lines are open- drain outputs that can be tied together in groups of the same type, creating a fair-share scheme for each group of interrupts. Alternatively, all three groups can be tied to a common request using the CL-CD2400 internal-priority scheme (see Section 3.2.4.1). 3.3. FIFO and Timer Operations Each channel in the CL-CD2400 has a 16-byte receive FIFO and a 16-byte transmit FIFO. The FIFOs are accessible through the Receive Data Register (RDR) and Transmit Data Register (TDR) registers. These virtual registers are shared among the four channels; therefore, they may not be accessed outside an interrupt context. Each channel's threshold level is common for both FIFOs. It is set via Channel Option Register 4 (COR4), with a maximum threshold value of 12. The FIFO threshold is meaningful in both DMA and non-DMA Modes. In DMA Mode, the FIFO threshoid determines when transfer bursts should occur. In non-DMA Mode, the threshold level determines when transfer-interrupts are asserted. 34 Func. Desc. MM 2136639 O00b187 374 MECIR CL-CD2400/2401 Multi-Protocol Control 3.3.1 Recelve FIFO Operation In the Asynchronous Mode, a good data interrupt is initiated when the number of characters in the FIFO is greater than the FIFO threshold. Note that receive timeout and receive data exception conditions also cause an interrupt to the host. In the Synchronous Mode, an interrupt request for data transfer is initiated when the number of characters is greater than the FIFO threshold, or an end of frame is reached. 3.3.2 Transmit FIFO Operation The TxDat and TxEmpty Bits in the IER control the generation of transmit FIFO interrupts. The CL-CD2400 will initiate an interrupt request for more data when the number of empty bytes in the FIFO is greater than the threshold set. During synchronous operation, when the last byte of the frame is transferred to the FIFO, the CL-CD2400 will stop asserting transmit interrupts until the frame is sent. 3.3.3 Timers The global Timer Period Register (TPR) provides a timer prescale tick as a clock source for the timers. The TPR counter is clocked by the system clock (CLK) divided by 2048. In order to maintain timer accuracy, the TPR Register should not be programmed with a value not less than 10 (OA hex) a tick of about 1 millisecond when CLK is 20 MHz. Each channel has two timers, one 16-bit general timer 1 (GT1) and one 8-bit general timer 2 (GT2). Their operation and programming are different in synchronous and asynchronous protocols. 3.3.4 Timers In Synchronous Protocols In synchronous protocols, the timers have no special significance for the CL-CD2400; they are available to support the protocols. They are started by host commands or by interrupts generated by the CL-CD2400. General timers 1 and 2 can be started in either of two ways: 1. By loading a new value to GT1 or GT2 when the timer is not running; August 1993CL-CD2400/2401 Multi-Protocol Controller 2. By setting the SetTm1 or SetTm2 Bits in the End of Interrupt Register when terminating an interrupt service routine. In this case, the value should be written to the appropriate interrupt Status Register (RISR, TISR, MISR). These timers can be disabled via a command through the Channel Command Register (CCR). - 3.3.5 Timers In Asynchronous Protocols The receive timer is restarted from the value programmed in RTPR every time a character is received and loaded into the FIFO, or data is read by the host. For example: receive FIFO threshold is set to 8, and six characters are stored in the receive FIFO. If no more characters are received and the receiver timer times-out, a receive interrupt will be asserted (in DMA mode, DMA transfer will occur). The host is expected to retrieve all six characters from the receive FIFO. Assuming the host is still enabling this feature (i.e., RET bit from the IER Register Bit 5 is still set), and if there is no character being received and receiver timer times-out, a Receive Exception Timeout Interrupt (a Group 3 Interrupt) will be asserted. The timer can be disabled if the value in RTPA is set to zero or the RET bit is cleared. 3.3.6 Transmit Timer The Transmit Timer Register (TTR) is used only if the embedded transmit command is enabled in the COR2 Register. The delay transmit command specifies the delay period loaded in the TTR; no further transmit operations are performed until this timer reaches zero. The current state of the line is held at either 0 for send break' or 1 for inter-character fill. 3.4 DMA Operation The CL-CD2400 uses a simple, but powerful, double-buffering method that is readily compatible with higher-level buffer control pro - cedures, such as circular queues, link lists, and buffer pools. Each transmitter and each receiver is assigned an 'A' buffer and a B buffer. When transmitting, the host processor will alternately fill the A and B buffers and command the CL- CD2400 to transmit the buffers one at a time. When receiving, the CL-CD2400 will fill the A and B buffers and inform the host processor when each is ready. August 1993 a ae ENRON MM 2136639 0006188 cOO MICIR ee a, ec? === CIRRUS LOGIC A simple ownership bit is used for each buffer; this ensures that there are no deadlocks between the host and the CL-CD2400 regarding the use of a particular buffer. By using the simple and flexible DMA management of the CL-CD2400, the user host processor is concerned with transmit/receive data on a block-by-block basis. The user does not need to be concerned with character-by- character transfers, or even filling/emptying the FIFOs. The DMA control is user-selectable per channe! and operates independently of one another. The CL-CD2400 can perform DMA operations in any of the supported line protocols. A special Append Mode feature can reduce host CPU overhead for asynchronous data streams. DMA operations are channel- and direction-specific. In each channel, either the transmitter and the receiver, or both, can be independently programmed for OMA Mode via the Channel Mode Register (CMA), When the CL-CD2400 acquires the bus for a DMA transfer, only data for one channel and in one direction will be transferred; then, bus ownership is relinquished. A maximum of 16 bytes the depth of the transmit and receive FIFOs are transferred during any ownership cycle. Whenever possible, DMA cycles are 16 bits wide, and buffers have the proper byte alignment. Unaligned buffers will be sent using only 8-bit-wide transfers. If the buffer begins on an even address and contains an odd number of bytes, the CL-CD2400 will use 16-bit transfers for all the words in the buffer except the last transfer, which will be eight bits. If one buffer in a chain ends on an odd address, the next buffer in the chain should also start on an odd address to keep the proper alignment and the most efficient bus usage. In this case, only the last transfer of the first buffer and the first transter of the next buffer will be eight bits wide; all others will be 16 bits. The CL-CD2400 can be forced to perform only byte-wide DMA operations by setting the Byte DMA Bit in the DMA Mode Register (DMR). Func. Desc. 35===> CIRRUS LOGIC 3.4.1 Bus Acquisition Cycle 1. CL-CD2400 asserts BR* and waits for BGIN. When BGIN* is detected, the CL-CD2400 can access the bus after the current bus owner relinquishes control of the bus. If BGACK is high when BGIN* goes low, then the bus is free to access. In this case, go to Step 5. MB 2136639 0006189 147 MMCIR CL-CD2400/2401 Multi-Protocol Controller 4. If BGACK* is low when BGIN* goes low, then the bus is in use. The CL-CD2400 will wait for BGACK* to go high. -. Once the CL-CD2400 senses that BGACK* is high, the CL-CD2400 will wait for the current bus cycle to terminate (DS* and DTACK* high) and then assert BGACK" by driving it low. At that time, the CL-CD2400 owns the bus. After driving BGACK* low, the CL-CD2400 will drive BR* high. Example in which the CL-CD2400 was required to wait to access the bus: BR" BGIN* ~ lf r Someone else owns the bus and gives itup here >! The CL-CD2400 owns the bus at this point >! Figure 3-3. Bus Acquisition Cycle 3.4.2 DMA Data Transfer After the CL-CD2400 acquires the bus, it will pulse ADLD* once. This will load the upper 24 address bits to the external 24-bit latch. This will happen only once per DMA grant cycle. The AD[0:15] Bits are remapped to memory address (MA) Bits MA[16:31], and A[0:7] are mapped to 36 Func. Desc. ES MAj8:15]. If during DMA, the upper 24 bits need to change, the CL-CD2400 will relinquish the bus and then re-acquire the bus. During each DMA read/write cycle, the lower eight memory address bits, MA(0:7] come from A[0:7]. August 1993CL-CD2400/2401 Multi-Protocol Controller Example of one DMA access after bus is acquired: ME 2136639 00061590 965 MCIR aa a ee S=="CIRRUS LOGIC ADLD* \V/ AEN* Ff AS ee Cy ae DTACK* Sf LS Figure 3-4. Data Transfer Timing 3.4.3 Bus Error Handling When a bus error is detected during a DMA sequence, the CL-CD2400 witl terminate the current bus cycle and relinquish the bus. Any data transfer in the bus ownership cycle is ignored, and the original conditions are restored. A subsequent retry attempt would start again from these original conditions. If there is a non-zero value in the Bus Error Retry Count Register (BERCNT), the register is decremented, and the failed transfer will be retried automatically. If the BERCNT is zero, a bus error interrupt is generated, and DMA transfers are suspended on the failing buffer until the interrupt is serviced. 3.4.4 A/B Buffers and Chaining The buffer management of the CL-CD2400 uses a dual-buffer scheme. There is an A/B buffer pair for each transmitter and each receiver. Each buffer is controlted by an ownership status bit, called 24000WN. When 24000WN = 1, the CL-CD2400 'owns' the buffer. When 24000WN = 0, the host 'owns' the buffer. A simple rule pre- August 1993 EERE vents confusion in the buffer management: Neither the CL-CD2400 nor the host will seize buffer ownership. Each will always relinquish ownership to the other. The host gives ownership of a receive buffer to the CL-CD2400 when the receive buffer is ready. The CL-CD2400 is then free to write received data into the buffer. The CL-CD2400 gives ownership of the receive buffer back after the receive data is in the buffer. The host gives ownership of a transmit buffer to the CL-CD2400 when the transmit buffer is ready to transmit. The CL-CD2400 will then transmit the contents of the buffer. When this is complete, the CL-CD2400 will give ownership back to the host. The CL-CD2400 keeps track of which buffer (A or B) is to be used next in the status bits: Ntbuf for transmit and Nrbuf for receive. The relationship between the 2400OWN Bit and the next bits is shown on the following page. The receive buffers are handled in the same way using the Nrbuf (next receive buffer). Func. Desc. 37NNT [S=="CIRRUS LOGIC 2400 2400 = Transmit Ntbuf OWN-A OWN-B Action 0 0 0 Send nothing 0 1 0 Host sets up Buffer A 1 1 0 CL-CD2400 accepts buffer A and marks B as next 1 0 0 CL-CD2400 com- pletes A tx, and passes it to host 1 0 1 Host sets up Buffer 8 0 0 1 CL-CD2400 accepts B and marks A as next 0 1 1 Host sets up Buffer A 1 1 0 CL-C02400 completes B tx, passes to host, accepts A and marks B as next 1 0 0 CL-CD2400 com- pletes A tx and passes it to host Chaining is used to break up relatively long frames into shorter blocks in memory, and is useful where there are frequent smaller frames and occasional long frames. Chaining allows more efficient use of the user RAM. The EOF Status Bit is used to control chaining in Synchronous Mades. Chaining applies to both transmit and receive. For transmit, the host de- termines EOF Bit; for receive, the CL-CD2400 determines the EOF Bit. In Transmit DMA, when the first buffer is supplied to the CL-CD2400, it is treated as the start of frame the CRC is reset and leading pad/flag/syn characters are transmitted, followed by the data. If the EOF Bit is set, the CRC and closing flag/syn will be appended, and the next buffer will again be treated as the start of frame. If the EOF Bit is not set, the CL-CD2400 treats the buffer as the first part of a larger frame and chains into the next buffer (does not reset CRC); this process then continues until a buffer is supplied with the EOF Bit set. 3.4.5 Transmit DMA Transfer As in receive data transfers, two buffers are available for DMA transmit transfers. The Trans- 38 Func. Desc. Le a M@@ 2136639 0006191 &T5 MBCIR CL-CD2400/2401 Multi-Protocol Controller mit Buffer Address and Transmit Buffer Count Registers (ATBADR/BTBADR and ATBCNT/ BTBCNT) contain the start address of and the byte count in the buffers. These registers are set by the host when initiating a transfer. The CL- CD2400 makes a copy of the registers to perform the transfer, leaving the originals unchanged. Transfer of buffers between the host and the CL- CD2400 is controlled by the Transmit Buffer Status (ATBSTS/BTBSTS) Registers. Buffers can contain either complete frames/ blocks of data, linked together to form a complete frame/block, or used in an Append Mode to transmit data as it arrives from another process. The first two transfer types are Block Mode transfers, the last is the Append Mode, and both are described below. The management of the buffers reduces the processor overhead as- sociated with short data transfers and increases the minimum response time requirements for frame-based transmissions. Chain Mode Transfer In this mode, the frame should be complete in buffers in memory before transmission is started. The Append Status Bit should not be set; the Start of Frame Bit must be set to begin transmission, and the last buffer bit must be set if this buffer is the last in a chained block or is a complete frame/block. When the CRC Bit is set, the CL-CD2400 will generate and transmit a Cyclic Redundancy Check Word for the frame using the polynomial selected by the CRC Polynomial Select Register {(CPSR). A host interrupt will be generated after the buffer is transmitted, if the interrupt required bit is set. Transmit buffers can be chained to support large frames. To minimize bus usage, the first buffer of the chain should begin on an even address in host memory. The CL-CD2400 will begin fetching a frame from a buffer performing DMA transfer, reading two bytes at a time. The CL-CD2400 cannot realign data between external memory and the FIFO. If one buffer of the chain ends on an odd address, the next buffer in the chain should begin on an odd address. Otherwise, only single-byte transfers will be made for the rest of the buffer. AR August 1993CL-CD2400/2401 Multi-Protocol Controller Append Mode Transfer This is available for Buffer A in Asynchronous Mode only. If Buffer A is set to Append Node, the host can enable the CL-CD2400 to transmit data in the buffer before it is completely filled. The CL-CD2400 will start transmitting new data when it is appended to the buffer. This mode is useful for terminal echo routines that do not wait for a complete block to be formed before starting transmission. In this mode, transmission is started when the buffer is made available to the CL-CD2400 by the host; the ATBADR[0-3] and the ATBCNT[L,H] are @@ 2136639 0006192 731 MICIR CIRRUS LOGIC transfer takes place by programming the ATBCNT[L,H] with the accumulated byte count. The ATBCNT should be written as a 16-bit word in this case, to avoid confusion between two byte operations. The ATBADR(0-3] should not be reprogrammed during the Append Mode. If the memory space has to be moved, the Append Mode has to be disabled first. When the final data is added to the append buffer and ATBCNT has been updated, the host should set the AppdCmp Bit in STCR. When the CL-CD2400 has completed the final transmission, it will clear the 24000WN Bit in the ATBSTS Register, and generate an end of buffer interrupt. Only the 'A' buffer can be used in the Append Mode. initialized. Subsequent triggering of DMA CL-CD2400 Transmit Physical DMA Registers Memory ATBADA (32) Starting Address 4 , ATBCNT (16) Buffer Byta Count _ Buter ATBSTS (8) y rate Fi TCBADRA (32) Current Address a (Cumrernty using Buti A) "Tt BTBADR (22) Starting Address A vianams BTBCNT (16) Buffer Byte Court > Her BTBSTS (8) } | {Starus Rey rer} Figure 3-5. Transmitter A/B Buffers NOTE: Number of bits in each register is shown in parentheses (). Buffer A and Buffer B do not need to be the same length. 3.4.6 Synchronous Transmitter Examples In Figure 3-5, Buffers A and B are contained in RAM external to the CL-CD2400._ All else (DMABSTS, ATBADR, TCBADR, ATBCNT, ATBSTS, BTBADR, BTBCNT and BTBSTS) are inside the CL-CD2400. Example #1: Transmit a frame out of Channel 1, with no chaining. 1. The host checks the Ntbuf Bit in the DMABSTS Register for Channel 1 to deter- mine which buffer is next. In this example, August 1993 ne Ntbuf = 0 indicating that Buffer A will be used next. 2. The host sets up the buffer data, the starting address, ATBADR, and the buffer byte count, ATBCNT. 3. The host then sets up the ATBSTS (A buffer Status) Register. The EOF Bit is set to indi- cate that there is no chaining. The 24000WN Bit is set to give ownership to the CL-CD2400. By setting 24000WN, the host commands the CL-CD2400 to start transmis- sion. Thus, everything must be ready (starting address, buffer data, byte count) prior to setting 24000WN. ee Func. Desc. 39 eee ee POS nr eee TE Leino of ===>" CIRRUS LOGIC The CL-CD2400 will start frame transmission out of Channel 1. When transmission is started, the CL-CD2400 will set bit Tobusy in DMABSTS. As transmission progresses, the current buffer pointer, TCBADR, is updated by the CL-CD2400. Also, at the start of transmission, the Next Buffer Bit, Ntbuf, is set to 1 to tell the host that Buffer B will be next. The CL-CD2400 will complete frame transmission by adding any necessary CRCs and trailing frame delimiters. When the CL-CD2400 completes the transmission, the CL-CD2400 will clear the Tbusy Bit. Then, the CL-CD2400 will set the EOB Bit and clear the 2400OWN Bit in the ATBSTS. This will tell the host that the transmission is complete, and give ownership of the buffer back to the host. The CL-CD2400 will then optionally interrupt the host, with EOF and EOB in the TISR both set to indicate that the transmission is complete, and there was no chaining. Example #2: Transmit out of Channel 0, and chain three buffers into one frame. The frame is 240 bytes long, and the maximum buffer size is 100. 1. 40 Func. Desc. The host checks the Ntbuf Bit in the DMABSTS Register for Channel 0 to deter- mine which buffer is next. In this example, Nibuf = 1 indicates Buffer B will be used next. The host sets up the buffer data, the starting address, BTBADR, and the buffer byte count, BTBCNT, for the first 'link' of the chain to be transmitted. For this example, BTBCNT = 100. The host then sets-up the BTBSTS (B buffer status) Register. The EOF Bit is clear to indicate that this buffer is the first link in a chain. The 2400OWN Bit is set to give own- ership to the CL-CD2400. By setting 24000WN, the host commands the CL- CD2400 to start transmission. Thus, everything must be ready (starting address, MB 2136639 0006193 678 MECIR CL-CD2400/2401 Multi-Protocol Controller buffer, data count) prior to setting 24000WN. At this point, the host knows that it has the time it takes to transmit 100 bytes to set up the next buffer link. If the host fails to do this in time, there will be a transmitter underrun, and the frame is aborted in HDLC or bisynchronous. The CL-CD2400 starts transmitting Buffer B from Channel 0. When this is started, the Nitbuf Bit is cleared to 0 to show that Buffer A will be next. This helps the host keep track of which buffer is next. As transmission pro- gresses, the current buffer pointer, TCBADR is updated by the CL-CD2400. During this, or prior, the host will have made Buffer A ready. For Buffer A, the EOF Bit in the ATBSTS Register is cleared by the host, indicating that the buffer is not the end of the chain. At the end of transmission of this buffer, the CL-CD2400 does not add any CRCs nor end of frame delimiters because there is more data for the current frame. After the CL-CD2400 has completed transmission of the first link out of Buffer B, the CL-CD2400 will set the EOB Bit and clear the 24000WN Bit in the BTBSTS. This will tell the host that the transmission is complete, and give ownership of the buffer back to the host. The CL-CD2400 will then optionally interrupt the host with EOF clear and EOB set in the TISR to indicate that the transmission is completed, and that there was chaining. . The CL-CD2400 now sees from the ATBSTS Register that it has ownership of Buffer A for transmission of the next link. It also sees that the EOF is clear so that this link is not the last fink in the transmitted chain. 10. The CL-CD2400 will continue transmission of the current frame, but now transmission is from Buffer A. This will be the second link which will be 100 bytes long. During this time, the host must set up a new Buffer B for August 1993rns, CL-CD2400/2401 Multi-Protocol Controller the third, and final, link. The BTBCNT for the last link will be set to 40 bytes. 11. After the CL-CD2400 has completed transmission of the second link out of Buffer A, the CL-CD2400 will set the EOB Bit and clear the 2400OWN Bit in the ATBSTS. This will tell the host that the transmission is completed, and give ownership of the buffer back to the host. As with the first link, the CL-CD2400 will not add CRCs nor ending frame delimiters to this link. 12. The CL-CD2400 will then optionally interrupt the host with EOF clear and EOB set in the TISR to indicate that the transmission is completed, and there was chaining. 13. By this time, the host has set up a new buffer for Buffer B. The EOF Bit in the BTBSTS is set to indicate that this is the last link in the chain. 14. The CL-CD2400 then transmits Buffer B in the same manner shown above. As before, the CL-CD2400 transmits the number of bytes indicated in the BTBCNT, which is 40 for the third segment. 15. When the CL-CD2400 completes transmission, any necessary CRCs and ending frame delimiters are transmitted. 16. The CL-CD2400 will then optionally interrupt the host with EOF and EOB set in the TISR to indicate that the transmission is complete, and this was the last link in the chain. 3.4.7 Receive DMA Transfer In all protocol modes, two host memory buffers can be made available to each receive channel, via the Receive Buffer Address and Receive Buffer Count Registers (ARBADR/BRBADR and ARBCNT/BRBCNT). To make a buffer available, the user must supply the buffer address in the Receive Buffer Address Registers; the number of free bytes in the buffer must be written in the Receive Buffer Count Registers, and the buffer August 1993 nee MH 2136639 OOOb194 Soy MECIR aeee i CIRRUS LOGIC Status must be updated in Receive Buffer Status Register (ARBSTS/BRBSTS). The CL-CD2400 is then free to use the buffer for receive data, and will update the Buffer Status Register as appropriate. When the buffer is no longer in use, the CL-CD2400 will write the number of bytes stored in the buffer in RBCNT and update Status in RBSTS. This frees the host to take control of this buffer and supply a new buffer in its place. The CL-CD2400 automatically switches to the other buffer whenever one buffer becomes full, or the end of a frame has been reached. lf the other buffer has not been allocated, the host still has the time required to fill the CL-CD2400 16-byte FIFO in which to respond and avoid loss of data. Special actions are taken depending on the channel protocol. in HDLC and bisyne, the end-of-frame/data block boundaries are recognized by the CL-CD2400. When a data- block boundary is detected, the current buffer is automatically terminated. If the other buffer is allocated and owned by the CL-CD2400, it will become the current buffer. End-of-frame/block interrupts will also be generated to the host. In Asynchronous Mode, a host interrupt is generated when there are receive exceptions (framing error, special character, etc.), but the buffer is not terminated. The data and exception Status are made available to the host, just as when the Asynchronous Mode is purely interrupt-driven. New data will be buffered internally in the FIFO until the host services the exception interrupt. The host has three options when terminating an exception interrupt: 1. 2, 3. The exception character can be discarded. The buffer can be terminated; if it is, no additional interrupt would be generated. The transfer count is not provided in A/BRBCNT, but can be calculated via Receive Current Buffer Address (RCBADR). A user-defined gap can be left in the buffer. These selections are communicated to the CL- CD2400 by the value written by the host to the Receive End Of Interrupt Register, when the Receive Interrupt service is completed. a A eT eETEENEEETEeS Func. Desc. 41ee ET IT, Cina a ===" CIRRUS LOGIC Leaving an 'n' byte gap enables the host to insert status of its own in the current buffer, while continuing to receive data in the same buffer. This eliminates the overhead of allocating a new buffer. The host must have noted the starting lo- cation of the gap while in the exception interrupt. This is done by reading the Receive Current Buffer Address Register. The address in this register is guaranteed to be stable during the Receive Interrupt, and to point to the next free character location in the current OMA buffer. If the size of the gap supplied by the host is suf- ficient to fill or complete the current buffer, the CL-CD2400 will automatically switch to the CL-CD2400 Receiver DMA Registers ARBCNT (16) ARBADR (32) Starting Address " A Buffer Byte Count M 2136635 CL-CD2400/2401 Multi-Protocol Controller other buffer and advance the Receive Current Buffer Address enough to complete the desired gap. The CL-CD2400 will readjust data alignment in its internal FIFO as needed to maintain alignment with the external buffer. Receiver A/B Buffers in the following drawing, Buffers A and B are contained in RAM external to the CL-CD2400. All others (DMABSTS, ARBADR, ARBCNT, ARBSTS, RCBADR, BRBADR, BRBCNT and BRBSTS) are inside the CL-CD2400. Physical Memory Receiver (Currentty using Buffer A) BRBCNT (16) ARBSTS (8) y (Status Register) RCBADR (32) jesse / Lo BRIBADR (32) Starting Address A Butfer Byte Count p| Buffer A iW a Receiver BRBSTS (8) {Status Register) | Buffer B Figure 3-6. Receiver A/B Buffers NOTE: need to be the same length. Example #1: Receive a frame from Channel 1; no chaining. 1. The host must first make a receive buffer available before a frame can be received. Thus, the host checks the Nrbuf Bit in the DMABSTS Register for channel 1 to deter- mine which buffer is next. In this example, Nrbuf = 0 indicates Buffer A will be used next. 42 Func. Desc. Number of bits in each register is shown in parentheses (). Buffer A and Buffer B do not 2. The host sets up the starting address, ARBADR, and the buffer byte count, ARBCNT. When the host writes the count, ARBCNT, the host has defined the size limit for the buffer. 3. The host then gives the buffer to the CL- CD2400 by setting the 2400OWN Bit in the status register, ARBSTS. This tells the CL- CD2400 that it is now OK to write received August 1993 0006195 440 MMICIRwaa CL-CD2400/2401 Multi-Protocal Controller 4. The Rbusy Bit in the DMABSTS Register for channel 1 is 0 until a frame starts to be re- ceived. When frame data starts coming in, the CL-CD2400 will set Rbusy to tell the host that Buffer B is next. As data bytes are written into the buffer, the current buffer pointer, RCBADR, is updated by the CL- CD2400. At the end of the received frame, the CL- CD2400 tests for correct end of frame delim- iter and CRC. When the received frame is complete, the CL-CD2400 clears the Rbusy Bit. In this example, there is no receive chaining, so the received frame byte count is less than or equal to the buffer size count, ARBCNT. The CL-CD2400 will write the value of the actual received byte count into the same register, ARBCNT. [Recognize the host has written the maximum buffer size in ARBCNT when the buffer is given to the CL- CD2400. But when the buffer is given back to the host, the CL-CD2400 has written the actual byte count of the received buffer into ARBCNT,] Then, the CL-CD2400 will set the EOB and EOF bits. This tells the host that the end of the buffer and frame have been reached. The CL-CD2400 will also clear the 24000WN Bit to give the buffer back to the host. Example #2: Receive a frame on channel 0, which consists of three buffers chained together. The frame is 240 bytes long, and the maximum buffer size is 100. 1. August 1993 The host checks the Nrbuf Bit in the DMABSTS Register for channel 0 to deter- mine which buffer is next. In this example, Nrbuf = 1 indicates Buffer B will be used next. The host sets up the starting address, BRBADR. Buffer size is set to 100 in this ex- ample. Thus, the host sets BRBCNT = 100. The host then sets the 2400OWN Bit to give ownership to the CL-CD2400. The host should know the amount of time it takes to receive 100 bytes, because this is the minimum time the host has to set up the Le 10. 11. ME 2136639 OOOb19b 387 MECIR er LIN TED ===" CIRRUS LOGIC next buffer link. If the host fails to do this in time, there will be a receiver overrun, and the received frame will be lost. Suppose that the CL-CD2400 starts receiving data into Buffer B of channel 0. When this is started, the Nrbuf Bit is cleared to 0 by the CL-CD2400 to help the host keep track of which buffer is next. (During this time, or prior, the host will have made Buffer A ready.) After the CL-CD2400 has received the first link of the frame into Buffer B, the CL- CD2400 will set the EOB and SOB bits and clear the EOF Bit. This will indicate that the first link in a chain has been received. Also, the CL-CD2400 will clear the 24000WN Bit, and give ownership of the buffer back to the host. For the first received link, the received byte count, BRBCNT, remains unchanged at 100, since the received data filled the buffer. The CL-CD2400 will then optionally interrupt the host with EOF clear and EOB set in the RISR to indicate that the received buffer is complete, and that there was chaining. The CL-CD2400 now sees from the ARBSTS Register that it has ownership of Buffer A for transmission of the next link.' As the frame continues to be received, the data will go into Buffer A. This will be the second link, which will be 100 bytes long. During this time, the host must set up a new Buffer B for the third, and final, link. After the CL-CD2400 has received the second link into Buffer A, the CL-CD2400 will set EOB Bit and clear the 2400OWN Bit in the ARBSTS. This will give ownership of the buffer back to the host. As with the first link, the received byte count, ARBCNT, remains unchanged at 100 since the received data filled the buffer. The CL-CD2400 will then optionally interrupt the host with EOF clear and EOB Func. Desc. 43 a,eR, ee, ae === CIRRUS LOGIC set in the RISR to indicate that the received buffer is complete, and there was chaining. 12. By this time, the host has set up a new buffer for Buffer B. 13. The CL-CD2400 will then receive data into Buffer B in the same manner shown above. 14. In this example, the third link does not fill the buffer. Thus, when the end of frame delim- iter is detected by the CL-CD2400, the value of 40 (for 40 received bytes) will be written into the received byte count, BRBCNT. 15. Next, the CL-CD2400 will set the EOB and EOF bits to show that the buffer is complete, and that this is the last link in the chain. 16. The CL-CD2400 will then optionally interrupt the host with EOF and EOB set in the RISR to indicate that the received frame is complete, and this was the last link in the chain. 3.4.7.1. Buffer Allocation The CL-CD2400 contains two DMA descriptors that can be loaded by the CPU to specify transmit buffers. These descriptors are designated A/B, and each consists of a 32-bit address (A/BTBADR), a 16-bit count (A/BTBCNT), and an 8-bit status (A/BTBSTS). The status register contains an ownership bit, 24000WN. When this bit is set, the CL-CD2400 owns the descriptor, and it should not be written to by the CPU. When the bit is clear, the descriptor is owned by the CPU. When DMA is selected and the channel is enabled, the CL-CD2400 waits for ownership of Buffer A. When ownership of A is given by setting the 2400OWN Bit, the buffer will be transmitted, and then the ownership bit will be cleared. The CL-CD2400 will then wait for ownership of Buffer B; this process continues, toggling between the two buffer descriptors. The DMABSTS Register contains a status bit (NtBuf) that informs the CPU of the next buffer to transmit to ensure that the CPU and CL-CD2400 44 Func. Desc. _ MB 2136639 0006197 213 MCIR CL-CD2400/2401 Multi-Protocol Controller 3.4.7.3 Chained Buffers In synchronous modes, when the frame size exceeds the maximum buffer size, a frame may be transmitted from a number of separate buffers. This is achieved simply by not setting the EOF Bit in the Transmit Buffer Status Register (A/BTBSTS) until the last buffer of the frame. The CL-CD2400 will transmit the buffers as one frame; it will append the CRC only when all the data is transmitted from the buffer with the EOF stay in synchronization. This procedure ensures that a pipeline of data is available for the CL- CD2400 to send, maximizing the bandwidth utilization and minimizing the possibility of underruns. Figure 3-7 on the following page illustrates this procedure. Interrupts for Transmit DMA Two types of transmit interrupts are available in DMA Mode; they are enabled via the Interrupt Enable Register (IER) and controlled by the TxD and TxMpty bits. When the TxMpty interrupt is enabled, interrupts will be generated when there is no transmit data available to send. For example, the TxMpty interrupt can be used by the CPU to determine when line turn-around can occur on half-duplex Normaily, the TxDat interrupt is used to indicate the end of each transmit buffer. The interrupt is scheduled internally when the last data is read from the transmit buffer into the FIFO. Because only one interrupt is generated for each buffer, the TxD Bit in the IER Register can be left permanently enabled. required selectively for individual buffers, the INTR Bit in the A/BTBSTS registers can be used to selectively enable interrupts. If interrupts are If the above procedure for allocating buffers is used, the CPU has the transmission time of the last buffer to allocate the next to avoid possible underruns. The EOF Bit in the Transmit Interrupt Status Register will be set for the interrupt associated with the last buffer. August 1993M@@ 2136639 0006198 15T MICIR CL-CD2400/2401 = Multi-Protocol Controller >, CIRRUS LOGIC Read DMABSTS to Determine Next Transmit Butfer (NtBuf) Update Descriptor and Set 24000WN More Data to Send ? Other Buffer 24000WN Bit ? Update Descriptor and Set 24000WN mee Figure 3~7. DMA Transmit Buffer Selection 3.4.7.4 Append Mode The Append Mode reduces the CPU overhead required to provide asynchronous terminal echoing functionality; this is also necessary for any similar application that involves an unpredictable data stream. The A buffer can be set into Append Mode via the ATBSTS Register. This buffer can then be used for the echoed data, while the B Buffer will be used for all other output data. The append buffer allows data transraission to start from a buffer before all the data is available for transmission. For example, terminal echoing requires that each character is echoed (or translated and echoed) before the complete line is typed. August 1993 To operate in Append Mode, the ATBADR and ATBCNT would be set as normal (the ATBCNT can be zero), and the 2400OWN and the Append Bit set in the ATBSTS. When any data is available for transmission, it is placed in the RAM buffer by the CPU, and the total buffer byte count is updated in the ATBCNT. The CL- CD2400 will now scan the ATBCNT Register for any changes; if new data is found, it will be read from the buffer and transmitted. When no more data is found in the append buffer, the CL-CD2400 will scan the B Buffer for ownership. If the B Buffer is owned by the CL- CD2400, then the data in that buffer will be transmitted uninterrupted; at the end of the el Func. Desc. 45transmission, the A Buffer count will continue to be scanned for new data. For correct operation of this feature, the ATBCNT Register should be updated with a Word Write Operation. If only byte access is possible, the value should not exceed 256 bytes. This mode allows multiple transfers to be performed through a single buffer; it saves CPU overhead by either processing multiple buffers or in handling interrupts with every character. Line retransmission becomes as simple as stepping back in the buffer and resending. To terminate the Append Mode, a command can be given via the STCR Register that will cause the A Buffer to be terminated when alt current data has been sent. 3.4.7.5 Transmit Bus Errors When a transmit bus error interrupt is generated, the TISR and A/BTBSTS Registers both indicate a bus error status. The current transfer address is available in the TCBADR[(0-3] Registers, and the bus error occurred on the last transfer that started at this address. This means the actual error address may be up to 16 bytes further in the buffer. Following a bus error condition, the CPU has the choice of either discontinuing the current buffer or retrying from the start of the last transfer. To discontinue, the current buffer and the TermBuff Bit should be set when TEOIR is written to at the end of the interrupt. In Synchronous Mode, the frame will still be in progress and needs to be aborted via the Special Transmit Command Register (STCR). To retry the frame, the CPU should set the 24000WN Bit in the A/BTBSTS Register, and not set the TermBuff Bit when writing to TEOIR at the end of the interrupt. This will cause the last transfer to be retried; should a bus error occur again, the above procedure will repeat. The CPU should check to ensure that a bad location is not continually retried. 3.4.7.6 Recelve Buffer Interrupts When a receive buffer is complete, the CL- CD2400 will generate an End-of-Frame Receive Exception Interrupt. It will provide the CPU with RISR status and information on which buffer is complete. 46 Func. Desc. ME 2136639 0006199 O56 MMICIR CL-CD2400/2401 Multi-Protocol Contro When a receive error occurs, the chip stops DMA at the point of error and generates a Bus Error Receive Exception Interrupt. RISR will indicate the cause of the exception, and RCBADR provides the next location in the receive buffer. The CPU has five options: 1. Terminate the buffer; 2. Discard the exception; 3. Terminate the buffer and discard the exception; 4. Continue from the current position in the buffer; 5. Leave 'n' byte gap in the buffer and then continue. The required option is written to the Receive End-of-Interrupt Register (REOIR) by the CPU to terminate the interrupt. If the Terminate Buffer option is chosen, the 24000WN Bit in the A/BRBSTS Register should first be cleared by the CPU; or, anew buffer can be supplied by the CPU. 3.4.7.7 Receive Time Out In Asynchronous DMA Mode In asynchronous DMA mode, the only way that the CD2400 will release the ownership is reaching the end-of-buffer. Receive timeout or any exceptions will not release the ownership if end-of-buffer condition is not met. The following illustrates recommended procedures to handle receive timeout in asynchronous DMA mode. Scenario 1: Buffer A is currently selected, receive timeout occurs, host wants to continue on: Recommendation: Do nothing in the receive timeout interrupt service routine. Scenario 2: Buffer A is currently selected, receive timeout occurs, host doesnt require DMA anymore: Recommendation: Reset ownership bits in A(B) RBSTS, and set TermBuff in REOIR in the receive timeout interrupt service routine. Scenario 3: Buffer A is currently used, receive timeout occurs, host wants to start DMA in buffer B: August 1993ane CL-CD2400/2401 Recommendation: Set TermBuff in REOIR in the receive timeout interrupt service routine. The D2400 will then switch to buffer B. Note that when a receive timeout occurs in buffer B, the CD2400 will pop back to buffer A, unless the host clears both ownership bits. The above scenarios will apply if buffer B is selected first. 3.4.7.8 Recelve Bus Errors When a receive bus error interrupt is generated, the RISR and A/BRBSTS Registers both indicate a bus error status. The current transfer address is available in the RCBADR(0-3] Registers, the bus error occurred on the last transfer that started at this address. This means that the actual error address may be up to 16 bytes further on in the buffer. Following a bus error condition, the CPU has the choice of either discontinuing the current buffer, or retrying from the start of the last transfer. if the buffer is to be discontinued, the number of valid receive bytes can be calculated by subtracting the starting address A/BRBADR(0-3] from the current address RCBADRI[0-3]. The CPU should set the TermBuff Bit in REOIR in order to terminate this buffer and move to the next. The transfer that failed to the first buffer due to the bus error is still in the Receive FIFO and will be transferred to the next buffer following the end of interrupt. To retry the buffer from the failure point, the CPU should set the 2400QOWN Bit in the A/BRBSTS Register; the CPU should not set the TermButf Bit when writing to REOIR at the end of the interrupt. This will cause the last transfer to be retried; should a bus error occur again, the above procedure will repeat. The CPU should check to ensure that a bad location is not continually retried. 3.5 Bit Rate Generation and Data Encoding 3.5.1 BRG and DPLL Operation Data clocks are generated in the CL-CD2400 by feeding one of a number of clock sources into a August 1993 ee MB 2436639 o00b200 438 MECIR ee, nr ==" CIRRUS LOGIC ) | programmable divider. The clock source and di- visor are programmable separately for each channel and direction by the user. Clock options are programmed in the Transmit Clock Option Register and the Receive Clock Option Register. The divisors are programmed in the Transmit Bit Rate Period Register and the Receive Bit Rate Period Register. The possible clock sources are: Transmit 1. Clk 0 CLK input/8 2. Clik 1 CLK input/32 3. Clk 2 CLK input/128 4. Clk 3 ~ CLK input/512 5. Clk 4 CLK input/2048 6. TXCLK Pin 7. Receive bit clock Recelve 1. Clk 0 CLK input/8 2. Clk 1 CLK input/32 3. Clk 2 CLK input/128 4. Cik 3 CLK input/512 5. Clk 4 CLK inpuv/2048 6. RXCLK Pin The CLK input is nominally 20 MHz. The divisor can be programmed for values from 1 to 255. To maximize the accuracy of edge de- tection in Asynchronous and DPLL Modes, the highest frequency clock and largest divisor combination should be selected. An external clock input may be used, and it may be at a multiple of the desired bit rate. If so, the appropriate divisor value must be loaded into the Bit Rate Period Register. If the external clock is at the desired bit rate, (1x clock) a value of Oth must be loaded into the associated Bit Rate Period Register. The receive bit rate generator can also be pro - grammed to act as a Digital Phase Locked Loop (DPLL). In that mode, the clock select and divisor are programmed to be as near as possible to the nominal receive bit rate. Clock Phase adjustments are made by the DPLL logic to lock to the incoming data stream. The receive bit clock is an optional input to the transmitter. This makes it possible to use the OPLL derived clock to synchronize the transmit data stream. Table 3-1 shows examples for programming Standard bit rates. The value to be loaded to set Func. Desc. 47i re OT OE, Se ee Gc! ===>" CIRRUS LOGIC a given bit rate is determined by the following equation: Frequency of ; chosen clock source Bit Rate divisor = ~__ | - 1 Desired Bit Rate The above equation will, in general, yield a non- integer result. The nearest integer value, along with the clock source, is the optimum choice for that bit rate. The value loaded in the period regis- ter must be that integer expressed as an 8-bit bi- nary value. The bit rate error is the difference between the integer value and the ideal value, expressed as a percentage. Example 1: Illustrates programming the bit rate generator at 19.2 kbps using internal clock, at a MH 2136639 0006201 574 MECIR CL-CD2400/2401 ulti-Protocol Controller system clock frequency of 20 MHz. Divisor loaded into R(T)BPR = 129 or 81H Value loaded into R(T)COR = 00H, to select clkO Example 2: Illustrates programming the bit rate generator at 56000 bps using external clock. Again, the system clock frequency is assumed to be at 20 MHz. The user provides a 1.25-MHz clock on the RxCin or TxCin Pin. Divisor loaded into R(T)BPR = 21 or 15H Value loaded into RCOR = 06H, to select External Clock Mode Value loaded into TCOR = COH, to select External Clock Mode Period Register | ' (RBPR or TBPR) Mux Adjustments applied here (for DPLL only) System Count Register Clock (RBCR or TBCR) clk 0>| 0 clk 1->} 1 clk 2>| 2 ' chk 3->] 3 dec/inc +N clk 4>} 4 Mux Zero Detect 5 RXCin or TXCia>| 6 Lo RX bit cle >| 7 (for TX BRG only) From RCOR/TCOR Figure 3-8. Bit Rate Generator/DPLL 48 Func. Desc. August 1993J MBH 2156639 O00be02 4O0 MBCIR CL-CD2400/2401 Multi-Protocol Controller | CIRRUS LOGIC Receive Clock Option Register {RCOR} 7 6 5 4 3 2 1 0 | TLVal | 0 | dpllEn | Oplimdt | Dplimdo CikSel2 | ClkSel1 | Cikseld | Transmit Clock Option Register {TCOR} 7 6 5 4 3 2 1 0 | cxser | cxsert | cKselo | 0 L eeix [| o {| um | o | ClkSel2 CikSel1 CikSel0 Select 0 0 0 Clk 0 0 0 1 Clk 1 0 1 0 Clk 2 0 1 1 Clk 3 1 0 0 Clk 4 1 0 1 Reserved 1 1 0 External clock 1 1 1 Reserved (RCOR) 1 1 1 Receive clock (TCOR) August 1993 RRR Func. Desc. 49ET, ee SETH S22 CIRRUS LOGIC Table 3-1. Clock freq. = 20 MHz MB 21356639 OOOb203 347 MICIR CL-CD2400/2401 Multi-Protocol Controller Data Clock Selection Using the Bit Rate Generators Clock freq. = 19.66 MHz Bit Rate Divisor Clock Error(%) Divisor Clock Error(%) 50 C2 clk4 -0.16 BF clk4 = +0.00 110 58 clk4 -0.25 56 clk4 = -0.31 150 40 clk4 +0.16 3F clk4 +0.00 300 81 clk3 +0.16 7F cik3 +0.00 600 40 clk3 +0.16 3F clk3 +0.00 1200 81 clk2 +0.16 7F clk2 +0.00 2400 40 clk2 +0.16 3F clk2 +0.00 3600 AD clk1 -0.22 AA clki -0.20 4800 81 clk +0.16 7F clk1 +0.00 7200 56 clk1 -0.23 54 clk1 = +0.39 9600 40 clk1 +0.16 3F clki +0.00 19200 81 clkO +0.16 1B clk0 = +0.00 38400 40 clkO +0.16 3F clkO =+0.00 ' 6000 2C clkO -0.79 2B clkO = -0.26 64000 26 clkO +0.16 25 clkO = +1.05 Clock freq. = 17.92 MHz Clock freq. = 18.432 MHz Bit Rate Divisor Clock Error(%) Divisor Clock Error(%) 19200 74 cikO -0.29 EF clkO 0.00 38400 39 clkO +0.57 77 clkO 0.00 56000 27 clkO 0.00 3B clk0 0.00 64000 22 clkO 0.00 28 clkO = +0.36 23 clkO 0.00 Glock freq. = 19.712 MHz Divisor Clock Error(%) TF cikO +0.26 3F clkO +0.26 2B clkO 0.00 26 cikO -1.30 NOTE: All divisors are in hexadecimal. Transmit and receive data can be encoded/ decoded in NRZ, NRZI or Manchester formats. For NRZI, at the start of transmission, a learning data stream of contiguous zeros achieves bit synchronization; for Manchester, an alternating pattern of ones and zeros is required. NRZ, NRZI, Manchester Data encoding schemes used in various synchronous protocols. In NRZ, the signal condition represents the data type, high for a logic 1 and 50 - Func. Desc. a low for a logic 0. In NRZ & NRZI type of encoding, the transitions of the data stream occur at the beginning of the bit cell. In NRZI, the signal condition switches to the opposite state to send a binary 0. In Manchester encod- ing, the transitions are always in the middle of the bit cell. A high-to-low transition is made to send a logic 1, and a low-to-high transition to send a logic 0. The timing diagrams below illus- trate the encoding method. The data bits are 0110010. August 1993CL-CD2400/2401 Multi-Protocol Controller Example 3: This example illustrates program- ming the Digital Phase locked loop at 64 kbps in NRZ! Mode using the internal clock, at a system clock frequency of 20 MHz. Divisor loaded into RCOR = 38 or 26h Value loaded into RCOR = 28h, to enable the DPLL, NRZI framing and select clk0. Example 4: This example illustrates program- ming the Digital Phase locked loop in the x1 External Clock Mode, with Manchester encoding. Divisor loaded into RBPR = Oth, to enable x1 external clock Value loaded into RCOR = 36h, to enable the DPLL, select Manchester framing, and external clock. MB 2136639 OO00b204 283 MMICIR ) === CIRRUS LOGIC When using an n-times external clock, the high- est possible clock frequency and largest divisor combination is recommended. The frequency of an external clock should be less than the system CLK input divided by 16, (i.e., for 20-MHz opera- tion, the data clock should be less than 1.25 MHz). Note that R(T)BPR is an 8-bit register; therefore the largest divisor value is 255. Typically, the external clock can vary with respect to data up to 64 kHz. The equation to compute the divisor value is Frequency of . | external clock source Bit Rate divisor Desired Bit Rate PLE LI LE LILI LSJ 920% TL fo [ NRZI TT] | | | | | Manchester Figure 3-9. Data Encoding i TxCin _xX NRZ TxData xX Figure 3-10. Transmit Data With External Clock In NOTE: When using external receive clock in the Receive Mode, data is sampled on the low-to-high going edge of RXCin. August 1993 Func. Desc. 51MB 2136639 OOObe05 11T M@CIR CL-CD2400/2401 Multi-Protocol Controller NRZ TxData together. These pins are tri-state not open collector, but an external pull-up resistor (2.2K- 5.0K) must be connected to each line to ensure a logic one when no CL-CD2400 is a bus When no higher-priority alternate bus masters are present, a daisy chain priority scheme can be implemented by wire ORing the BR* and BGACK* and connecting directly to the 680X0. The 680X0 BG* signal is then connected to the first device in the chain and daisy chained to the remaining devices. A lower priority bus master can then be connected at the end of the chain. If a higher priority bus master is present, the BG* signal must be qualified before being passed into the highest priority CL-CD2400. If a priority encoded scheme is required, the BR* signals must be prioritized externally and BG* signals ===" CIRRUS LOGIC ~L OU TxCout Figure 3-11. Transmit Data With External Clock Out Table 3-2. Data Clock Selection Using External Clock Clock = 20 MHz Bit Rate Ext. clk. freq. Divisor (hex) "Master. 50 9.765 kHz C2 110 9.765 kHz 57 150 9.765 kHz 40 300 39.062 kHz 81 600 39.062 kHz 40 1200 156.250 kHz 81 2400 156.250 kHz 40 3600 625.00 kHz EF 4800 625.00 kHz 81 7200 1.250 MHz AC 9600 1.250 MHz 81 19200 1.250 MHz 40 38400 1.250 MHz 1F 56000 1.250 MHz 15 SOT - 64000 1.250 MHz 12 routed to individual devices. 3.6 Hardware Configurations In order to demultiplex the A/D[0:15] bus into separate address and data buses, external buffers and latches are required. To reduce ex- ternal circuitry, these external devices can be shared in multi-CL-CD2400 applications. The common control lines (ADLD*, AEN*, DATDIR, DATEN*) to the external devices are wire-ORed 52 Func. Desc. a 3.6.2 Interface to a 32-Bit Data Bus To interface to a 32-bit data bus, two 16-bit data buffers must be used to isolate the CL-CD2400 A/D{0:15] pins from either half of the 32-bit bus. The A[1] address pin determines if the lower or upper half of the data bus is in use for a particu- lar bus cycle. The CL-CD2400 always drives all 16 data bits during a Register Read or a DMA Write Operation, regardless of the size of the actual transfer. August 1993MH 2456639 O00b20b OSE MECIR CL-CD2400/2401 EES Multi-Protocel Controller : CIRRUS LOGIC 3.6.3 DMA Connections for the CL-CD2400 DATEN* en 16-Bit I | DATOIR" _dir,| Data Xevr . | aw: DATA (0:15) o ps, o . = DTACK* ren . 8 A/D {0:15} tt i16:31) - Oo ADILD* STROBE" | 15.31) 30-Bit - Bt A [0:7] (8:15) Address Driver | Ma [0:31] {0:7} nd AEN* en AST, Figure 3-12. DMA Connections for the CL-CD2400 The 24-bit latch is REQUIRED. The 16-bit xcvr is OPTIONAL depending on application. 7 The 32-bit driver is OPTIONAL depending on drive needs. August 1993 = TER Func. Desc. 53MH 2136639 OO0b207 TI2 MMCIR _ ae, == CL-CD2400/2401 @ IRRUS LOGIC Multi-Protocol Controller 3.6.4 Recommended CL-CD2400 as a DTE and a DCE Interface The table below shows the recommended Data Terminal Equipment (DTE) connections between the CL-CD2400 and RS-232-C, X.21 and X.21 bis standard interfaces. CL-CD2400 CL-CD2401 RS-232-C X.21 X.21bis(V.24) RXD RXD BB R 104 TXD TXD BA T 103 RTS" RTS* CA Cc 105 CTS* CTS* CB ! 106 RXCIN/DSR* DSR* cc - 107 TXCOUT/DTR* TXCOUT/DTR* -/CD - 108.2 - RXCIN DD s 115 - TXCIN DB S 114 - RXCOUT DA - 113 TXCIN/CD* cD* -/CF - 109 The table below shows the recommended Data Communication Equipment (DCE) connections between the CL-CD2400 and RS-232-C, X.21 and X.21 bis standard interfaces. CL-CD2400 CL-CD2401 RS-232-C X.21 X.21bis(V.24) RXD RXD BA T 103 TXD TXD BB R 104 RTS* RTS* CB I 106 CTS CTS* CA Cc 105 RXCIN/DSR* DSR cD - 108.2 TXCOUT/DTR* TXCOUT/DTR* DB/CC Ss 114/107 - RXCIN ~- - - - TXCIN DA - 113 - RXCOUT DD - 115 TXCIN/CD* CcD* DA/- - - NOTE: X.21 is completely different from X.21 bis. Reference: CCITT 1988 Blue Book 54 Func. Desc. = amen 86 August 1993ees, CL-CD2400/2401 Multi-Protocol Controller 4. PROTOCOL PROCESSING 4.1 HDLC Processing 4.1.1. HDLC Transmit Mode The transmitter can be programmed to idle in either flag (01111110) or mark (continuous 1's) mode via Idle Bit in Channel Option Register 3 (COR3). When idle in mark is selected, frame transmission can be programmed to be prepended by a programmable number of pad characters and a programmable number of flags. The pad character can be selected as either 00 or AA; the pad characters allow the remote receivers Phase Locked Loop to synchronize quickly to the data. When NAZI encoding is used, the 00 character guarantees a transition every bit time; for Manchester encoding, AA guarantees exactly one transition per bit time. if the transmitter is idling in mark, frame transmission is started when data is made available to the transmitter, either via the Transmit Data Register (TDR) or a DMA buffer. First the programmable number of pad characters will be transmitted, and then the programmable number of flag characters. Data characters will then be transmitted and a CRC value accumulated using each data character. When end of frame status is passed to the CL- CD2400 via the TEOIR or the A/BTBSTS, and the remaining data is transmitted, the CRC anda closing flag will be appended to the frame. Ifa new frame is available immediately, the correct number of opening flags will be transmitted and data transmission started. If data is not available, the line will be returned to its idle condition. If data underrun occurs, the CL-CD2400 will not append a CRC, but will abort the transmission by sending eight continuous 1's, and then revert to the idle condition. An underrun interrupt will be generated, and if interrupt transfer is being used, the CPU should provide an EOF response in TEOIR. If DMA Transfer Mode is being used, the CL-CD2400 will discard DMA buffers until an EOF buffer is found; transmission will then resume from the next buffer. This ensures correct operation when a multiple buffer frame underruns. When programmed in NRZI Mode and idle in mark, after the closing flag and the first eight August 1993 = a MB 2156639 OO0b208 925 MCIR i ee a cmmphikitia sin re ETO ae == CIRRUS LOGIC ones are transmitted, the transmit data line is sampled to determine if it is a logic high or low. If it is low, an extra zero is transmitted to force the line to be a logic high. When idle in Flag Mode is selected, the send pad and opening number of flags have no significance; transmission will be started when data is first made available in the FIFO. If no data underrun occurs, the frame is terminated normally with a CRC, and then continuous flags are generated. If an underrun does occur, then no GRC is appended, eight ones are transmitted, and then continuous flags and an underrun interrupt will be generated. 4.1.2 HDLC Receive Mode When enabled, the receiver enters Flag Hunt Mode. When the first flag is detected, the next non-flag/abort character is treated as the start of frame. If no address recognition is enabled, frame reception then continues; if Address Recognition Mode is enabled, the incoming data is compared with the receive address registers. Two modes of address recognition are available: 1. First byte of address field only, (four possible matches available against RFAR[1:4]); 2. First and second byte address field, (two possible matches available against RFAR[1:2), RFAR[3:4)). For the purposes of address matching, the address extension bit is not interpreted by the chip. The address matching occurs on either the complete first byte, or complete first and second byte of the frame. If no address match is recognized, Flag Hunt Mode is once again entered, thereby discarding the current frame. If a match is found, normal frame reception continues. When the closing flag of the frame is detected, the data remaining in the FIFO is passed to the CPU, either through DMA transfers or good data interrupts, and then an End Of Frame (EOF) interrupt is generated. The CRC can be either validated or ignored. If the CL-CD2400 does not check the CRC, it will be passed onto the host. A validated CRC can be discarded or passed onto the host for diagnostic purposes. The next non-flag/abort character will restart the process; the current state of the receive process is visible to the CPU via the CSR Register, which indicates whether data, flag or Protocol Proc. 55ren ee TO men = === CIRRUS LOGIC mark are currently being received. To support the Data Phase of an X.21 connection, a Clear Detect feature can be enabled via COR1. When enabled, the receive data and CTS* Pin are monitored for the Clear Indication (0, off) from the remote. If detected, the remainder of the current frame will be discarded, and a clear detect indication will be passed to the CPU via the RISR. However, the channel remains in HDLC Mode until modified by the CPU. 4.2. Bisync Processing In both transmit and receive, the CL-CD2400 interprets the first characters of data to determine the type of frame, and to compile the corresponding BCC. The host uses the Channel Option Register 2 (COR2) to program the character set (ASCIi or EBCDIC) and determine whether to use CRC or LRC. 4.2.1 Bisync Transmit Processing The CL-CD2400 can be programmed to idle in either SYN or mark. When idling in mark, a programmable number of leading pad characters can be transmitted before each data frame. The leading pads ensure the Remote Phase locked loop has sufficient transitions to achieve bit synchronization before data starts. The leading pad character can be programmed as AA (suitable for NRZ and Manchester), or 00 (suitable for NRZI). When data is available in the FIFO, transmission will be started; any required leading pads will be sent, followed by a SYN pair and the CPU- supplied data. The CL-CD2400 monitors the transmit data to determine frame type and compute the correct BCC, eliminating unnecessary characters from the calculation. If SYN sequences are embedded in the data supplied by the CPU, they will be transmitted but excluded from the BCC calculation. If a frame transmission is aborted via the Special Transmit Command Register, an EOT and trailing pad will be transmitted and the line returned to its idle state. A frame is terminated normally when an End Of Frame (EOF) indication is passed to the CL-CD2400, either in Transmit End Of Interrupt Register (TEOIR), or in the A/B Transmit DMA Buffer Status Register (A/BTBSTS). If the frame ends with an EOT or ENQ condition, the trailing pad is appended and transmission is 56 Protocol! Proc. MB 2136639 0006209 465 MBCIR CL-CD2400/2401 Multi-Protocol Controller complete; otherwise, any accumulated BCC is appended, followed by the trailing pad, and the line returned to its idle state. 4.2.2 Bisync Receive Processing After initialization, the receiver starts in Synchronous Hunt Mode, and will discard data until a pair of SYN characters are detected. The next non-SYN data is assumed to be the start of frame. The receive data is continuously monitored to determine the type of frame (transparent/non-transparent, BCC/no BCC). The BCC, if required, is compiled, excluding any characters which should not be part of the calculation. When a frame terminating condition is detected, and if a BCC has been accumulated, it is checked and the end of frame information passed to the CPU via the Receive Interrupt Status Register. If the frame is terminated with an ENQ condition, the BCC is not checked, and an abort indication is passed to the CPU in RISR. An extra-frame-termination process is available by programming an extra-frame-termination character into COR6. When this character is detected, the receive frame is terminated immediately, and no BCC is computed. Following an initialize channel command, the COREG is set to the value of DLE (10hex) by the internal code; the user may alter this to any other value. To detect the condition where the frame termination character has been corrupted on a non-transparent line, COR6 can be programmed to the idle condition FF hex. To use this on a transparent line, the data should not equal FF; if the value in COR6 is preceded by the DLE character, it does not cause frame termination. NOTE: This feature is not available on revisions prior to Revision H. 4.3 Async Processing Data is transmitted according to the format op- tions defined in the Channel Option Registers. These options determine the character length, parity, and stop bit length. New data sent from the host will be transmitted in a continuous stream, unless one of the following happens: 1. Transmitter disabled - transmission termi- nated at the end of the current character un- til transmitter enabled. August 1993 aCL-CD2400/2401 Multi-Protocol Controller 2. XOFF received from line transmission terminated at end of the current character until XON received or transmitter enabled. 3. Out of band flow control ~ transmission terminated at the end of the current character until out of band flow control removed. 4. In-line command received in data stream from host in-line command is executed and transmission resumed. 5. Send special character command from host - the current character is completed and the special character is transmitted after which normal transmission is resumed. 4.3.1 For in-band flaw control modes to be active, the Special Character Detect Mode must be enabled. In-Band Flow Control Transmitter In-Band Flow Control Transmit in-band flow control is enabled when the Transmit In-Band Enable (TxIBE) Bit in COR2 is set to 1. When TxIBE = 0, in-band flow control is disabled, the Implied XON Mode (IXM) Bit, also in COR2, has no meaning. The XON and XOFF characters are defined in the Special Character Registers SCHR[1:2]. When in-band flow control is enabled (TxIBE = 1), upon receipt of an XOFF character, the channel will stop transmission after the current character in the Transmit Shift Register and the current character in the Transmit Holding Register are transmitted. When IXM = 0, transmission will restart after an XON character is received. When IXM = 1, transmission wilt restart after any character is received. The Flow Control Transparency (FCT) Mode Bit in CORG is used to determine if the received flow control characters are to be passed to the host. lf FCT = 1, the characters are not passed to the host. if FCT = 0, they are passed to the host as exception characters. This bit does not affect non-flow control special characters. Additional status information about transmitter in- band flow control is available in the Channel August 1993 MB 2136639 0006210 58? MICIR e ee === CIRRUS LOGIC Status Register (CSR). The Transmit Flow Off (TxFloff) Bit and the Transmit Flow On (TxFlon) Bit are used. TxFioff = 0 is normal. TxFloff = 1 means that the channel has been requested by the remote to stop transmission. This bit is reset to 0 when the channei receives restart, as described above. This bit is reset to 0 when the transmitter is enabled or disabled, or the channel is reset. TxFlon = 0 is normal. TxFlon = 1 means that the channe! has been requested by the remote to restart transmission. This bit is reset to 0 once the channel has restarted transmission. This bit is reset to 0 when the transmitter is enabled or disabled, or the channel is reset. Receiver In-Band Flow Control The channel can request the remote to stop transmission by sending an XOFF character. Likewise, the channel can request the remote to restart transmission by sending an XON characters. The XON/XOFF characters is transmitted by setting the SndSpc Bit in STCR to al. The CSR contains status bits Receive Flow Off (RxFloff} and Receive Flow On (RxFlon) that are used for receiver in-band flow control. RxFloff = 0 is normal. RxFloff = 1 means the channel has requested that the remote stop its transmission. This bit is reset to 0 when the channel requests the that the remote restart its transmission. This bit is reset to 0 when the re- ceiver is enabled or disabled, or the channel is reset. RxFlon = 0 is normal. RxFlon = 1 means that the channel has requested that the remote restart its transmission. This bit is reset to 0 when the next non-flow control character is received. This bit is reset to 0 when the receiver is enabled or disabled, or the channel is reset. Protocol Proc. 57. Ce ee F e === CIRRUS LOGIC 4.3.2 Out-of-Band Flow Control Receive out-of-band flow contro! is enabled when the CTS Automatic Enable (CtsAE) Bit is set to 1. In this mode, character transmission will begin only after the CTS* Pin is active (low). In asynchronous transmission, if CTS* goes inac- tive (high) after transmission has started, the channel will stop transmission after the current character in the Transmit Shift Register, and the current character in the Transmit Holding Register are transmitted. In synchronous modes, if CTS* goes inactive, the channel will stop transmission after the current frame. in either case, transmission will restart after CTS* goes active. The CL-CD2400 can automatically flow control the remote device via the DTR*Pin. This mode is selected by setting a non-zero DTR* threshold in CORS5; when both the threshold in COR4 and the threshold in CORS5 are exceeded, the CL- CD2400 will set the DTR* Pin high. When the data in the FIFO falls below the DTR* threshold, the DTR* Pin is automatically driven low. Each channel of the CL-CD2400 has four pins that can be used either as a modem control or general-purpose input/output pins. The modem signal names assigned to these four pins have been chosen to provide an easy reference for system designers. In fact, they are all simply general-pupose inputs and outputs (if automatic out-of-band flow-control is not used) that can be individually controlled via the modem signal value register(s). Since the pins are general- purpose, system designers may choose to connect the pins in any way that suits the application. However, when the system software design employs automatic out-of-band flow control with the pins, then the signal naming convention no longer holds true in some cases, depending on whether the device is used as DCE or OTE. In this case, itis best to think of the pins in terms of their actual uses within the CL-CD2400 and connect them accordingly, without regard to their names. The RTS* and CTS* pins are associated with transmitter and the DTR* and DSR* pins are associated with the receiver. The table below shows Cirrus Logics recommended signal hook- up if automatic, out-of-band flow control is desired. 58 Protocol Proc. M@! 2136639 0006211 413 MBCIR CL-CD2400/2401 Multi-Protocol Controller CbD2400 Out-of-Band DCE DTE PinName_ Flow Control CTs DTR Signal remote to transmit RTS Not implemented in this direction RTS RTS Request remote permission to transmit CTS CTS Enable transmitter For example, if the CL-CD2400 is designed to be DCE and automatic out-of-band flow control is desired, the pin DTR should be connected to remote CTS input. If the CD2400 is to be used as the DTE side, then the CD2400 CTS output would be connected to the remote CTS input. Note that if automatic out-of-band flow controt is implemented, the activity of DTR and DSR pins do not implement the function assigned to those . signal names by the signalling conventions of the CCITT and other standards organization. These names would only apply to these pins if they are under program control and not under automatic CL-CD2400 control. In fact, the DTR function enables the modem to go on- and off- line, depending on the state of the pin. If automatic control is used, then DTR would go inactive when the receive FIFO reached the programmed threshold thus causing the modem to drop the connection (carrier) to the remote, which would not be the correct function based on the state of the receive FIFO. 4.3.3 Line Break Detection and Generatlon A line break on the receiver occurs when the in- put at the receive data (RXD) Pin is all zeros (low) for at least one full character time. This is indicated when the Break Bit in RISRL is set to 1. Line break generation out of the transmitter is possible when the Embedded Transmit Command (ETC) Bit in COR2 is set to 1. A line break is generated when the output at the transmit data (TXD) Pin is all zeroes (low) for at least one full character time. Line breaks may be transmitted by embedding certain sequences in the data stream as defined August 1993MP 21366349 o00be12 J5T MCIR CL-CD2400/2401 SS Multi-Protocol Controller ==" CIRRUS LOGIC Line breaks may be transmitted by embedding _ ting breaks only of ETC = 1. The embedded certain sequences in the data stream as defined sequences to transmit a break are: below. These sequences are valid for transmit- 00h-81h Send BREAK ~ Send a line break for at least one character time. 00h-82h-xxh Insert Delay To increase the break generation beyond one character time, the Insert Delay sequence may be used. The inserted delay will be xx, where xx is a binary number. The delay will be xx times the tick set by the Timer Period Register (TPR). The minimum period of TPR should be 1 millisecond. If the Insert Delay sequence is not preceded by a Send BREAK sequence, then there will be an inserted delay of all 1's (high) on the output for duration xx. 00h-83h Stop BREAK - This must follow the Send BREAK sequence, or the Insert Delay sequence. 00h-00h Send NUL If the user needs to send a NUL character, and ETC = 1, the user may embed 00h-00h to send one NUL character. If there are less than 8-bits per character, the user may also send a NUL character by sending an 80h. NOTE: In addition to Insert Delay, a break may also be increased beyond one full character by transmitting more than one 'Send BREAK' sequence at a time. August 1993 wan = Protocol Proc, 59===] CIRRUS LOGIC 4.3.4 Special Characters Special Character Transmission Selected special characters may be sent pre- emptively by setting the Send Special Character Command (SndSpc) Bit in the STCR. The CL- CD2400 channel acknowledges the command by clearing the STCR. Along with the SndSpe Bit, the host needs to set-up the three Special Character Select (SSPCO, SSPC1, SSPC2) bits, also in the STCR, to select which character is to be sent. When the host commands a special character transmission, the channel will complete transmit- ting any characters in the Transmit Shift Register and Transmit Holding Register, and then transmit the special character sequence. Any other characters awaiting transmission in the FIFO or through DMA will be transmitted after the special character. If the transmitter is off due to in-band flow control, the special characters will override and be sent. Special characters will override out-of- band flow control. Also, if the transmitter is disabled, the special character send command will override, and the character will be sent. SSPC2 SSPC1 SSCPO 0 0 1 Send Special Character #1 0 1 0 Send Special Character #2 0 1 1 Send Special Character #3 1 0 0 Send Special Character #4 0 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved 60 Protocol Proc. M@ 2136639 0006213 2%b MBCIR CL-CD2400/2401 Multi-Protocol Controller Special Character Recognition and Special Character Range Special character recognition is enabled when the Special Character Detection (SCDE) Bit in COR3 is set to 1. The special characters are programmed in the SCHR Registers, and are the same characters used for the transmitter. If the Flow Control Transparency (FCT) Bit in COR3 is set to 1, the channel will process the flow control characters and discard them. Otherwise, if FCT = 0, the received flow control characters will be processed and passed onto the host via exception interrupt. In the event of an error (framing and/or parity) in a received character sequence, the channel will not interpret this character as a special character. But, if an overrun condition occurred after a special character is detected, the new character is lost and the overrun status is set. In this condition, the CL-CD2400 will give both an Overrun exception and a special character recognition status. Special Character Range The Special Character Ran (SCRI and SCRh) Registers d ge low and high lefine an inclusive range for special character recognition in the Asynchronous Mode. It may be useful for identifying that a received character is within a certain range, such as a control character. To disable this function, if special character detection is enabled, make both SCRI and SCRh equal! to Special Character #1 (SCHR1). Special characters and range detection is through the three special character detect (SCdet0, SCdet1, SCdet2) bits in the RISR1 Register. The meanings of these bits are listed on the following page. ae August 1993CL-CD2400/2401 Multi-Pr MB 2456639 CO0b214 122 MCIR _ee, a, TE, ETRE === CIRRUS LOGIC No special characters/range detected Special character 1 matched Special character 2 matched Special character 3 matched if character 1 and 3 sequence not enabled Special character 4 matched if character 2 and 4 sequence not enabied SCdet2 SCdet1 SCdetO 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1 The hex value of the receive character is within the range SCRI < receive character < SCRh. 4.4 UNIX Support Features Channel Option Register 6 (COR6) provides several functions required by UNIX TTY drivers, to further reduce the amount of character by character processing that the CPU is required to perform. Separate receive and transmit bits are provided to perform carriage return(CR)/new line(NL) translations. In transmit NL can be converted to CR NL, or CR converted to NL. In receive, CR can be discarded, NL converted to CR, or CR converted to NL. In receive processing separate modes are Provided to handle break conditions and character error conditions. Break conditions can be handied in the normal way (via a receive Status interrupt), or the condition can be discarded, or the break can be translated to a NULL (00) and passed as normal data to the August 1993 ES CPU. Parity and framing errors can either be handled as normal (via receive status interrupts), discarded, translated to a NULL (00) and passed to the CPU as normal data, or the character can be passed to the CPU as normal data, preceded by the sequence FF 00. The LNext option (COR7LNE) provides a mechanism to transfer flow control and other special characters without invoking flow control or special character interrupts at the receiver. ff the LNext option is enabled when the LNext character is received, the following character is just passed to the CPU as a normal character. The LNext character is programmed via the LNext Register. The |Strip feature (COR7) strips the eighth bit off each error-free received character. It has no effect on the transmitted data. Figure 4-0 shows the exact order of the CL-CD2400 character processing steps in flowchart form. Protocol Proc. 61ME 2136639 0006215 O69 MBCIR eS CL-CD2400/2401 SE IRRUS LOGIC Multi-Protocol Controller Character Received {STRIP COR7 SpISTRIP COR 7 Zaro Bit 7 For Special Char Match Only Flaw Contral Processing CHAR = SCHR3/4 Exception Interrupt Figure 4~0. CL-CD2400 Asynchronous Receive Character Processing 62 Protocol Proc. TT August 1993MB 2136639 O00belb TTS MMCIR CL-CD2400/2401 SSS 4 ETE Multi-Protocol Controller , ===> CIRRUS LOGIC CHAR = \.N BREAK > Y Process Break Options COR 6 IgnBrk NBrkint Action 0 0 Exception Interrupt 1 0 Discard Character 1 1 Replace with 0 V Done vy Process Parity Options COR 6 ParMod INPCK Parint Action 0 0 0 Exception interrupt 0 0 1 Replace with 0 7 Q 1 0 Ignore Error ~ 0 1 1 Discard Character 1 Q 1 Replace with FF+00+ Char , , Done Figure 4-0. CL-CD2400 Asynchronous Receive Character Processing (cont) August 1993 -_ A m= Protocol Proc. 63MH 2136639 0006217? 931 MCIR SSeS CL-CD2400/2401 ==" CIRRUS LOGIC Multi-Protocol Controller Excepti intoruor fm Bone ) Process Translation Options j CHAR FIFO Add Extra FF to FIFO Char to FIFO ( Done ) Figure 4-0. CL-CD2400 Asynchronous Recelve Character Processing (cont.) 64 Protocol Proc. August 1993on CL-CD2400/2401 Multi-Protocol Controller 4.5 X.21 Call Set-Up Mode The X.21 call setup protocol uses a combination of synchronous data and control leads to control call progress, between a DCE and a DTE. The data can be in the form of steady state conditions (all ones, all zeros, alternating ones and zeros), or character synchronous data. The control leads are used in conjunction with the Steady state data conditions to pass change of state information between the DCE and DTE. 4.5.1 X.21 Transmit In order to minimize the CPU intervention in the transmit direction, a modified version of the Embedded Transmit Command (ETC) is used. The ETC Mode is controlled via COR2, and when enabled, provides a means of transmitting steady state, or repetitive data patterns synchronized to the control lead. The ETC consists of a sequence of four bytes passed to the CL-CD2400 as normal transmit data; the format of the bytes is as follows: Byte 7- 80 this indicates the start of a command sequence Byte 2 this indicates the required state of the control lead 00 = set the control lead off 01 = set the control lead on 02-FF reserved Byte 3- data character to be transmitted, this is transmitted as is, with no parity added. If parity is required, it must be included in the byte, i.e., to transmit '+' with odd parity, the value AB would be loaded. Byte 4- is a count of the number of times to transmit the character. If the count is zero the character will be sent indefinitely until new data is made available (this would be the normal mode for the steady state conditions). When the count is zero the CL-CD2400 will always send the data a minimum of three times even if new data is made available sooner. 4.5.2 X.21 Receive In receive, the CL-CD2400 validates the steady State conditions passing just the change of state information to the CPU. Steady state conditions validated are the all ones, all zeros, alternating ones and zeros, SYN, and the characters MH 3439 OOOb218 878 MECIR ) === CIRRUS LOGIC programmed in SCHR1:3. To be validated a condition must be present for two character times with a stable value on the CTS* Pin (CTS* is used in X.21 as the | lead in a DTE or C lead in a DCE). To enable the detection of the steady state conditions, the SSDE Bit must be set in COR3, this enables the detection of the all ones, all zeros and the alternating ones and zeros conditions with a stable value on the CTS Pin. When the SSDE Bit is set the StrpSyn and SCDE may also be set if required, (if SSDE is not set then the StrpSyn and SCDE bits have no effect). The StrpSyn Bit, when set, treats SYN characters in the same way as the steady state conditions, that is when two valid SYN characters are detected a receive special character interrupt is generated and following SYN characters are stripped from the incoming data stream. If the StrpSyn Bit is not set, the SYN character is still used to achieve character synchronization, but all received SYN characters are passed to the CPU, as normal receive data. The SCDE Bit enables the detection of the special characters defined in SCHR1-3, in the same manner as the steady state conditions. When detected for two consecutive character times, a special character detect interrupt will be generated, and following repetitions of the same character will be stripped from the receive data. An example of the use of this bit would be to detect the 'BEL off condition for a DTE incoming call, and then strip its repetition until the next State change. Character synchronization must be achieved before SCHR1-3 can be detected. 4.6 Programmable Sync Mode By selecting options correctly, the X.21 Mode can be used for most general-purpose synchronous applications. 4.6.1 Programmable Sync Transmit Without the Embedded Transmit Command (ETC in COR2) enabled, the data supplied to the channel is transmitted unaltered. When no data is available in the transmit FIFO, the ASCI! SYN Character (16) will be sent to fill idle time. If some other character is required to idle the line, two methods are available. August 1993 Protocol Proc. 65eR ee EE, a TR, NRT) OE TT SS CIRRUS LOGIC The idle character can be supplied as normal data, this has the drawback that host intervention is required to either fill the FIFO or to supply a new buffer periodically while there is no real data to send. The other method is to use the Embedded Transmit Command to repeat the required data pattern until transmit data is available. The ETC command functions is follows: When an 80hex character is encountered in the transmit data, it and the following three characters are treated as a special command; the format of the bytes is as follows: Byte 1- must be equal to 80 to start a command sequence. Byte 2 indicates the required state of the RTS* Pin. 00 = The RTS Pin is set inactive (high) 01 = The RTS* Pin is set active (low) 02-FF reserved Byte 3~ the required character for transmission. It will be sent as an 8-bit character without parity (any required parity value should be included by the host). Byte 4 the number of times the above character should be sent; if set to zero, the character will be sent until new data is supplied but a minimum of three times. To idle-in mark with the RTS* line off, the following command could be written '80 00 FF 00'. In order to sent the character '80' while the ETC command is enabled and the RTS* Pin is asserted, the following sequence should be written '80 07 80 01. NOTE: This feature is not available in revisions prior to Revision H. 66 Protocol Proc. = M@ 2136639 0006219 704 MCIR CL-CD2400/2401 Multi-Protocol Controller 4.6.2 Programmable Sync Receive in Receive Mode, the SYN character can be programmed via COR6 to any required value, when the channel is initialized COR6 is set to the value16 by the internal code. If a parity mode is enabled, the parity bit should not be set in CORS. Synchronization can be achieved with either a single or double SYN pattern, this is controlled by the Single SYN (SglSyn) Bit in ORS. When an end of frame is detected, the Sync Hunt Mode may be reentered by issuing the Clear Receiver (CirRcv) command in the Channel Command Register (CCR). 4.7 Non-8-Bit Data Transfers In Asynchronous Mode and in Non-HDLC Synchronous Modes, it is possible to transmit and receive less than 8 bits per character. For asynchronous, there may be 5, 6, 7, or 8 bits per character. For some synchronous (non- HDLC) applications, there may be 7-bit ASCII with parity handled by the chip. In each case where there is less than 8 bits per character, the data transfer will always be from the low-order bit locations. For HDLC, there are always 8 bits per character transmitted. The CL-CD2400 will transmit only byte-aligned frames. The CL-CD2400 will receive HDLC frames using transfers of 8 bits per character, except for the last character received before the FCS. if this last character is not aligned to an 8-bit boundary, the Resind (Residual Indication) Bit will be set, along with the EOF Bit in RISR. August 1993ns MB 21436639 0006220 42b MCIR CL-CD2400/2401 = Multi-Protocol Controller S==CIRRUS LOGIC 5. PROGRAMMING EXAMPLES This section provides some examples of CL-CD2400 programming. Included are examples of global and per-channel initialization, and two interrupt service routines. The code was written in Borlande Turbo C++. Power Up RESET ALL Command (any CCR) A host command Wait for GFRCR to be non-zero Do not issue a RESET ALL command immediately after power up Set up global registers: TPR and PILR1:3, Disable RX, TX (CAR-CCR) Singie channe Set up CAR channel- reconfiguration specific register first Set up channel-specific registers in any order: CMR, COR1:5, TBPR, TCOR, RBPR, RCOR, CPSR, LIVR, GT1:2, RFAR1-4 (sync), SCHR1:4, SCR, ATPR (async) Last step in channel configuration: CCR, IER A channel is configured Figure 5-0. Initialization Sequence for the CL-CD2400 August 1993 SERA Programming... 67M@ 2136634 SS CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocol Controller 5.1. Global Initialization This section shows an example of global initialization. The host waits for a hardware reset, determined by a non-zero value in the Global Firmware Revision Code Register (GFRCR). A Reset All command is sent to the CL-CD2400 via the Channel Command Register (CCR). The host will put a non-zero value into GFRCR when initialization is complete. The Priority Interrupt Level Registers should be loaded with the value of the seven address lines A[6:0] during interrupt acknowledge cycles. The Timer Prescale Register (TPR) loads the dividing counter that inputs each of the other timers in the CL-CD2400. The DMA Mode Register and the Bus Error Count Register are used in DMA Modes only. After the global portion is done, the per-channel registers need to be initialized. Transfers and Interrupts should be enabled after all other initialization is complete. /f Global Initialization while( linportb( GFRCR ) ) // wait for hardware reset : Hf wait outportb( CCR, RESET_ALL ); // Reset command while( tinportb( GFRCR ) ) // wait for reset command ; /f wait outportb( PILR1, 0x02 ); Hf Priority Interrupt outportb( PILR2, 0x04 ); /! Level Registers outportb( PILR3, 0x06 ); outportb( TPR, 0x40); /! Set timer prescale outporib( BERCNT, 0); // Bus error count outportb( DMR, 0); // DMA mode 16-bit Hf per-channel initialization for( i=0; i<4; i++) { outportb( CAR, i); /f set channel number init_chan( cor, bpr ); /#/ initialize channel outportb( CCR, INIT_CH | EN_RX | EN_TX ); while( inportb(CCR) } ; 4 wait outportb( IER, TX_DATA|RX_DATA ); // enable interrupts 68 Programming... August 1993 OO0bee2)l 3be MBCIRME 2136639 O00be22 279 MHCIR TE, a ===" CIRRUS LOGIC CL-CD2400/2401 Multi-Protocol Controller 5.2 Async Interrupt Setup Example This section shows an example for an asynchronous channel running at 19,200 bits per second, with 8 bits/character, 1 stop bit, and no parity. The Sample program enables in-band flow control and implied XON Mode. This code assumes that the proper channel has been set via the Channel Access Register (CAR). August 1993 outportb( LIVR, 0x40); outportb( RCOR, 0); outportb( RBPR, 0x81 ); outportb( TCOR, 0); outportb( TBPR, 0x81 ); outportb( CMR, ASYNC ); outportb( COR1, PARIGN | CHARS ); outporth( COR2, IXM | TXIBE ); outportb( COR3, STOP1 | FCT); outportb( COR4, thresh ); outportb( CORS, 0); 5.3 HDLC DMA Channel Setup Example This per-channel initialization exam The setup specifies two extra ope transfers should be used. outportb( LIVR, 0x30 ); outportb( RCOR, DPLL_NRZ1); outportb( RBPR, 64); outportb( TCOR, 0 ); outportb( TBPR, 64 ); outportb( CMR, RX_DMA | TX_DMA | HDLC ): outportb( CPSR, CPSR_CRC_V41 ): outporto( COR1, NO_ADDR | FLAG_2); outportb( COR2, CRC_V41 ); outportb( COR3, 0); outportb( COR4, thresh ); outportb( CORS, 0); if Receive clock option /! Baud Rate divisor # Transmit clock option // Baud Rate divisor ft Async Mode, interrupt 4 8 bit chars, no parity Hf in-band flow,implied XON 11 stop, flow control // FIFO threshold # Set interrupt vector /f Receive clock option /! Baud rate divisor # Transmit clock option /! Baud rate divisor /t Mode register /f CRC polynomial select ff No address matching, /f 2 opening flags Hf FIFO threshold ns | Programming... ple is for the HDLC protocol at 38.4 Kbps with NRZI encoding. ning flags before frames, no address matching and that DMA 69MB 2136639 0006223 135 MICIR ae CL-CD2400/2401 s 27 CIRRUS LOGIC Multi-Protocol Controlle 5.4 Bisync Setup Examples Channel 0, BISYNC, EBCDIC, CRC16, DMA mode CAR 0 CMA C1 ; DMA TX and RX, Bisync mode CORi 07 ; 8 bit no parity COR2 20 ; CRC mode, EBCDIC, CRC transmitted non-inverted COR3 EA ; 55H pad, CRC preset to 0, idle mark, TX 2 pads COR4 09 ; FIFO threshold set to 9 CPSR 01 ; CRC16 TCOR 00 TBPR 26 ; 64 kbit RCOR 06 RBPR 01 ; 1x external clock, NRZ data MSVRD 10 ; use DTR as TxCLKout CCR 2A ; init channel, enable TX and RX DMA ; assign receive DMA buffers IER 0A ; enable RxD, TxD interrupts Channel 0, BISYNC, ASCII, LRC, Interrupt mode CAR 0 CMR 01 ; interrupt mode, bisyne COR C6 ;7 bit data, odd parity COR2 80 ; LRC mode COR3 CA ; pad = 55H, idle in mark, TX 2 pads COR4 07 ; FIFO threshold = 7 TCOR 00 TBPR 26 ; 64 Kbit RCOR- 06 RBPR- 01 ; external 1x receive clock, NRZ data MSVRD 10 ; DTR used as TxCLKout CCR 2A ; init channel, enable TX and RX IER 0A ; Enable TxD and RxD interrupts ZO Progra sri LG. . , mmmnmmmmnnnnsnnennseenssnsnasateeasanenesenea nena DS Sa August 1993MM 2156639 ooobez2y 0?) MECIR CL-CD2400/2401 Multi-Protocol Controller SEE IRRUS LOG IC 5.5 Receive DMA Interrupt Service Routine This example shows an interrupt service routine for the CL-CD2400 in DMA Mode. The buffer class array ib[ ] is used for notational convenience, and its exact implementation is user-defined. The upper() and lower() functions should return the upper and lower 16 bits of the DMA address for the current buffer segment. The nxt_buf() accesses the next segment. if the system uses separate interrupt handlers for receive, transmit, and modem interrupts, the channel number can be obtained from the lower two bits of the Interrupt Register RIR/TIR/MIR. Otherwise, use LIVR first to determine the type of interrupt. Receive 'good data interrupts should not occur during DMA transfers. The normal exception is when End Of Frame is received. DMABSTS shows which buffer the CL-CD2400 expects to use next. Fill the descriptor registers for that buffer, including the 2400OWN Bit, and return. The last access to the CL-CD2400 during the service routine is the REOIR Register. int risrl = inportb( RISAL ); // low status _intch = = inportb( RIR ) & 0x03; // channel number switch( inport(LIVR) & 0x03 ) { case LIVR_GOODDATA: break; /! shouldn't happen in DMA case LIVR_EXCEPTION: H EOF is 'normal' exception if( risrl & RISR_EOF ) { if( inportb(DMABSTS) & DMABS_NRBUF ) { / buffer B next outport( BRBADRU, ib{ch].upper() ); outport( BRBADRL, ib[ch].lower() ); outport( BRBCNT, BUF_MAX ); outport( BRBSTS, OWN_2400 ); ib{ch].nxt_buf(); // get next buffer }else { 4 buffer A next outport( ARBADRU, ib[ch].upper() ); outport( ARBADRL, ib[ch].lower() ); outport( ARBCNT, BUF_MAX ); outport( ARBSTS, OWN_2400 ); ib[ch].nxt_buf(); /f get next buffer } } outportb( REOIR, ZERO ); August 1993 neemanmeenmnnnanae Programming... 71MB 2136639 O00be25 CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocol Controller 5.6 Transmit interrupt Service Routine This example is a transmit interrupt service handler example. When using a synchronous protocol, transmitters must declare an End Of Frame if an underrun occurs. If the end of buffer is encountered before data is transferred by this interrupt service, then the NOTRANS Bit in TEOIR should be set along with EOF. TEOIR is always the last access of an interrupt service routine. int teoir = ZERO; Hi default int tisr = inportb( TISR ); /f status intch = inportb( TIR ) & 0x03; // channel number switch( tisr ) { case TISR_UE: teoir = TEOIR_EOF; Hf underflow break; case TISR_TXDATA: tite = inportb( TFTC ); // FIFO count for( i=O; ixtftc; i++) { if( ob[ch].is_eob() ) { #1 end of buffer ? ob[ch].nxt_buf(); /f get next buffer teoir = TEOIR_EOF; if(i==0 ) teoir |= NOTRANS; break; } else outportb( TDR, ob{ch].nxt_char() ); //send next character } } outportb( TEOIR, teoir ); 72 Programming... auaes August 1993 TOS MMCIRMB 21356639 OO0becb 944 MICIR CL-CD2400/2401 = Multi-Protocol Controller === CIRRUS LOGIC 6. DETAILED REGISTER DESCRIPTIONS 6.1 Global Registers INT MOT SIZ ACCESS Global Firmware Revision Code {GFRCR} 82 81 B R Register 7 6 5 4 3 2 1 ) t Firmware Revision code | This register serves two functions in providing the host with information about the CL-CD2400. When the CL-CD2400 is initialized by a hardware RESET signal, or by a software Reset All command issued through any channel Channel Command Register, the CL-CD2400 zeros his register at the Start of the initialization. At the conclusion of the initialization, the CL-CD2400 writes its firmware revision code to the GFRCR. All valid CL-CD2400 revision codes are non-zero, the revision code is incremented by one with each new release, e.g., GFRCR for Revision | = 09 hex. Host software must confirm that the GFRCR contents are non-zero before proceeding to configure the CL-CD2400 for normal operation. Channel Access Register {CAR} EC EE B RAW 6 5 4 3 2 1 0 Leo fete TeTs foyvaya | This register contains the channel number used for the channel-oriented host read or write opera- tions, when the host is not in an interrupt service routine. The CL-CD2400 supplies the interrupting channel number during all interrupt service operations. The Channel Access Register contents are not used during interrupt service. Note that this means that an interrupt service routine is restricted to accessing only the register set of the interrupting channel and global registers. Bits 7-2 Reserved must be zero. Bits 1-0 Channel Number ci Channel Number 0 O Channel 0 Oo 61 Channel 1 1 O Channel 2 1 4 Channel 3 August 1993 ee a Detailed Reg... 73ME 2156639 0006227 3an MECIR CL-CD2400/2401 SEC IRRUS LOGIC Multi-Protocol Controller 6.2 Option Registers INT MOT S!Z ACCESS Channel Mode Register {CMR} 18 1B B RW 7 6 5 4 3 2 1 0 | RxMode | TxMode | 0 | 0 | 0 | chmd2 | chmat | chmdo | Bit 7 Receive Transfer Mode 0 - Interrupt 1- DMA Bit 6 Transmit Transfer Mode 0 Interrupt 1-DMA Bits 5-3 Reserved must be zero. Bits 2-0 Protocol Mode select An initialize command must be given to the CL-CD2400 through the Channel Command Register, if these options are changed. chmd2 chmd1 chmdd 0 0 0 HDLC 0 0 1 bisync 0 1 0 async 0 1 1 X.21 1 0 0 reserved 1 0 1 reserved 1 1 Q reserved 1 1 1 reserved 74 Detailed Reg... - August 1993MB 2156639 O00b228 717 MECIR CL-CD2400/2401 } Multi-Protocol Controller ===" CIRRUS LOGIC Channel Option Register 1 {COR1} 13 10 B RAW HDLC Mode An Initialize command must be given to CL-CD2400 through the Channel Command Register if any options specified in this register are changed. 7 6 5 4 3 2 1 0 | AFLO | CirDet | AdMdet | AdMdeo | Flags3 | Flags2 | Flags1 Flags0_ | Bit 7 Address Field Length Option O = Address field is 1 octet in length 1 = Address fieid is 2 octets in length Bit 6 Clear Detect for X.21 Data Transfer Phase 0 = Clear detect disabled 1 = Clear detect enabled A clear is defined as two consecutive all zero receive characters with the CTS* Pin high. Bits 5-4 Addressing Modes 00 = no address recognition 01=4* 1 byte 10 =2"* 2 byte. If this bit is set, RFAR1, RFAR2, RFAR3, RFAR4 should contain the address to be matched. If AFLO is set to 1, an address match will be made against the RFAR1 and RFAR2 pair or the RFAR3 and RFAR4 pair. Bits 3-0 Inter-frame flag option Defines the minimum number of flags transmitted before a frame is started. Flags3. Flags2 Flags1 Flags0 0 0 0 0 - minimum of 1 opening flag, with shared closing/opening flags permitted 0 0 0 1 through minimum number of opening flags sent 1 1 1 1 The minimum number of opening flags will always precede a frame when idle in mark mode is set or will always separate two consecutively transmitted frames. No restriction is placed on the number of flags between received frames. August 1993 =n Detailed Reg... 75MB 2156639 000b229 653 MCIR Ss CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocal Controller Channel Option Register 1 (cont.) Asynchronous, Bisynchronous and X.21 Modes 7 6 5 4 3 2 1 0 | Parity | ParM1 | Paro | Ignore | Chi3 | Chi2 Chit | cio | Bit 7 Parity '1' = odd parity 0 = even parity Bits 6-5 Parity Mode 1 and 0 - Defines Parity Mode for both transmitter and receiver: ParM1 ParM0 Parity 0 0 no parity 0 1 force parity (odd parity = force 1, even = force 0) 1 0 normal parity 1 1 reserved Bit 4 Ignore Ignore Parity 0 = evaluate parity on received characters 1 = do not evaluate parity on received characters Bits 3-0 Character Length Chi3 Ch Chi1 Chid Character Length 0 1 0 0 5 bits 0 1 0 1 6 bits 0 1 1 0 7 bits 0 1 1 1 8 bits 76 Detailed Reg... a ae August 1993MB 2156639 0006230 375 MCIR CL-CD2400/2401 SSE Multi-Protecol Controller CIRRUS LOGIC Channel Option Register 2 {COR2} 14 17 B RAV HDLC Mode 7 6 5 4 3 2 1 0 | 0 | FCSApd | 0 | CRCNinv | 0 | RtsAo | CtsAE | Osrae | Bit 7 Reserved must be zero. Bit 6 FCS Append 0 = Receive CRC is not passed to the host at end of frame 1 = Receive CRC is passed to the host at end of frame Bit 5 Reserved - must be zero. Bit 4 CRCNinv 0 = CRC is transmitted inverted (i.e., CRC V.41) 1 = CRC is not transmitted inverted (i.e., CRC-16) Bit 3 Reserved must be zero. Bit 2 RTS Automatic Output Enable. When set, if the channel is enabled, the CL-CD2400 will automatically assert the RTS" output when it has characters to send. When Idle-in Mark Mode is selected, RTS will be asserted prior to opening flags and will remain asserted until after a closing flag has been transmitted. Bit 1 CTS Automatic Enable. Enables CTS input to be used as automatic transmitter enable/disable. If enabled, the CTS input is checked before frame transmission is started. Bit 0 DSR Automatic Enable. Enable the DSR* input as automatic receiver enable/disable. If enabled, the pin is checked at the beginning of each received frame. August 1993 m= - Detailed Reg... 77MB 21356639 0006231 201 MECIR CL-CD2400/2401 CIRRUS LOGIC Multi-Protocol Controller Channel Option Register 2 {COR?2} 14 17 B R/W Asynchronous Mode 7 6 5 4 3 2 1 0 | xm | TxiBe | Tc } oo | Ru | Risto. | CtsAE | DsrAE | Bit 7 Implied XON Mode (Async) This bit only has meaning when TXIBE is enabled. During Transmit In-Band Flow Control Mode, the CL-CD2400 stops transmission upon detection of an XOFF character. The IXM Bit determines whether the CL-CD2400 should restart transmission based on receipt of an XON character or any character. IXXM=0 Following receipt of an XOFF character, transmission will only be resumed by receipt of an XON character or a transmit enable command via CCR. XM=1 Following receipt of an XOFF character, transmission will be resumed by the receipt of any character or a transmit enable command via CCR. If the character that restarts transmission is not an XON character, itis not subjected to the Flow Control Transparency feature, i.e., it will be passed to the host CPU. The XOFF character will restart transmission if the channel is in a flow- off condition. Bit 6 Transmit in-Band (XON/XOFF) Flow Control Enable The CL-CD2400, upon receipt of the XOFF character, terminates transmission after the current character in the Transmit Shift Register, and the character in transmit holding register, are sent. The CL-CD2400 will resume transmission upon receipt of the XON character, any character (depending on the state of the IXM Bit) or a transmit enable command via CCR. The XON and XOFF character must be programmed in SCHR1 and SCHR2 respectively. When they are programmed to the same value, the flow control state is toggled on each reception. 78 Detailed Reg... __- ee] August 1993MB 2136639 0006232 148 MECIR CL-CD2400/2401 Multi-Protocol Controller SS" CIRRUS LOGIC Channel Option Register 2 Asynchronous Mode (cont) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Embedded Transmitter Command Enable (Async) : if set, the embedded special transmitter command functions are enabled. (See Section 4.3.3) The null (all zero) character is used as the ESCape character. The following functions are supported: 00H OOH Send one 00H character as normal data OOH 81H Send Break Enter line Break condition for at least 1 character time. (If the insert delay special character sequence immediately follows the Send Break sequence, the duration of the break transmission is extended by the amount of the programmed delay.) QOH 82H XXH Insert Delay - Insert a delay of 'XX' (interpreted as an unsigned binary number) times the programmed timer 'tick' set by the Prescaler Period Registers. (A zero delay count results in no delay.) OOH 83H - Stop Break - Exit line Break condition and resume normal character transmission. Reserved must be zero. Remote Loopback Mode 1 enables the Remote Loopback Mode 0' disables the Remote Loopback Mode RTS Automatic Output Enable. When set, if the channel is enabled, the CL-CD2400 will automatically assert the RTS* output when it has characters to send. RTS* will not be deasserted until after a stop bit has been transmitted. CTS Automatic Enable. Enables CTS* input to be used as automatic transmitter enable or disable. in Asynchronous Mode, the option is evaluated prior to each character transmission. In Sync modes, the option is checked prior to each frame transmission. DSR Automatic Enable. Enable the DSR* input as automatic receiver enable/disable. In Asynchronous Mode, the option is evaluated at the end of each character received. In Syne modes, the option is checked at the beginning of each received frame. August 1993 es Detailed Req... 79MM 2136639 0006233 084 MICIR ee SSS CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocol Controller Channel Option Register 2 (cont) Bisynchronous Mode 7 6 5 4 3 2 1 0 1 LRC BCC | EBCDIC | CACNinv | SYNs3 SYNs2 | SYNs1 | SYNsO Bit 7 Longitudinal Redundancy Check 0 = CRC16 used for BCC 1 = LRC used for BCC Bit 6 BCC Append 0 = Receive BCC is not passed to the host at end of frame 1 = Receive BCC is passed to the host at end of frame Bit 5 EBCDIC 0 = ASCI! used as character set 1 = EBCDIC used as character set Bit 4 CRCNinv 0 = CRC is transmitted inverted (i.e., CRC V.41) 1 = CRC is not transmitted inverted (i.e., CRC-16) Bits 3-0 Extra SYN Characters This field determines the number of extra Synchronize (SYN) characters that will be transmitted before a frame is started. The two required SYNs are not included in this count. SYNs3 SYNs2 SYNsi SYNsO 0 0 0 0 two SYN characters will be sent 0 0 0 1 through 1 1 1 1 - two + N SYNs will be sent NOTE: This feature is not available in revisions prior to Revision H. X.21 Mode 7 6 5 4 3 2 1 0 Leo | o> fecf{o fTofTo fo fo | In X.21 Mode, the CL-CD2400 uses the RTS* Pin as the C lead. C ON is defined as RTS* low andC OFF as RTS* high. Bits 7-6 Reserved must be zero. Bit 5 Embedded Transmitter Command Enable. If set, the embedded special transmitter command functions are enabled. In X.21 Mode, this feature is provided to simplify the transmission of both repetitive data, and data synchronized to the C lead. The command is a sequence of four consecutive bytes supplied as normal transmit data by the host processor. Bits 4-0 Reserved must be zero. 80 Detailed Reg... Oe = on ] August 1993MB 2436639 coob234 TiO MECIR CL-CD2400/2401 SS Multi-Protocol Controller ==" CIRRUS LOGIC Channel Option Register 2 (cont) X.21 Mode (cont) Byte 1 This must be equal to 80 to start a command sequence. Byte 2 This indicates the required state of the C lead to be synchronized with the transmit data. 00 = set the C lead to OFF 01 = set the C lead to ON 02-FF reserved Byte 3 This is the required data character for transmission. It will be sent as an 8-bit character without parity (any required parity should be included in the character by the host). Byte 4 This is a count of the number of times the character should be sent, if set to zero the character will be sent until more data is provided to the transmitter (but always a minimum of three times). Channel Option Register 3 {COR3} 15 16 B RAW In Synchronous Mode, COR3 is used to specify the learning pattern (pad character) sent by the CL- CD2400 to synchronize the DPLL at the remote end. The pad character sent depends on the kind of encoding used. HDLC Mode 7 6 5 4 3 2 1 0 | sndpad | Alt | FCsPre | FCS | idle | pad2 | padt | padO In Synchronous Mode, COR3 is used to specify the learning pattern(pad character) sent by the CL- CD2400 to synchronize the DPLL at the remote end. The pad character (00h or AAh) sent depends on the kind of encoding used. Bit 7 1 = CL-CD2400 will send pad character(s) before sending flag when coming out of the Mark tdiing Mode. 0 = CL-CD2400 will not send any pad character. Bit 6 altt send sync pattern. 1 = AAh (Manchester/NRZ Encoding) is sent as pad character. 0 = 00h (NRZI Encoding) is sent as pad character. Bit 5 FCS Preset 0 = FCS is preset to all ones (i.e., CRC V.41). 1 = FCS is preset to all zeros (i.e., CRC-16). Bit 4 FCS Mode. 1 = Disable FCS generation and checking, CL-CD2400 treats the entire frame as data. 0 = Normal FCS Mode. The CL-CD2400 generates and appends CRC on transmit and validates GRC on receive using CRC polynomial selected through CRC Polynomial Select Register. Bit 3 Idle Mode . 0 = idle in flag 1 =idle in mark August 1993 -~ ame Detailed Reg... 81MB 2136639 0006235 957 MMCIR CL-CD2400/2401 ee 0 ore CIRRUS LOGIC Multi-Protocol Controller Channel Option Register 3 (cont) HDLC Mode (cont) Bits 2-0 Character Count specifies the number of synchronous characters sent. pad2 pad1 pado 0 0 0 reserved 0 0 1 1 pad character sent 0 1 0 2 pad characters sent 0 1 1 3 pad characters sent 1 0 0 4 pad characters sent 101-111 are reserved Asynchronous Mode 7 6 5 4 3 2 1 0 | Esco | RngDE | FCT | SCDE | Splstp | Stop2 | Stopt | Stopo | Bit 7 ESCDE = Extended Special Character Detect Enable 0 = Special Character detect for SCHR 3 and 4 is disabled. 1 = Special Character detect for SCHR 3 and 4 is enabled; a special character interrupt will be generated following the receipt of a character matching SCHR3 or SCHR4. Bit 6 RngDE = Range Detect Enable 0 = Range Detect disabled. 1 = Characters between SCRI and SCRh (inclusive) generate special character interrupts. Bit 5 FCT Flow Control Transparency Mode 0 = Flow control characters received will be passed to the host via receive exception interrupts. 1 = Flow control characters received will not be passed to the host. This bit has no effect unless both TxIBE (COR2) and SCDE (COR3) are set. Bit 4 Special Character Detection 0 = Special character detect for SCHR1 and 2 is disabled, = Special character detect for SCHA1 and 2 is enabled. This bit must be set along with TxIBE (COR2) before FCT (COR3) becomes effective. Bit 3 Special Character | Strip - When Set, this bit causes the receive character to be |- Stripped [bit 7 set to zero] for the special character matching functions only. The character passed to the host is unaffected. This function allows special character processing of data without knowing if the data is 8 bit no parity or 7 bit with parity. B2 Detailed Reg... sm RE August 1993MH 2156639 oO0b23b 493 MICIR CL-CD2400/2401 Multi-Protocol Controller ===" CIRRUS LOGIC Channel Option Register 3 (cont) Bisynchronous Mode Bits 2-0 Stop Bit Length Specifies the length of the stop bit Stop2 Stop1 Stop0 Stop Bit Length 0 1 0 1 stop bit 0 1 1 1.5 stop bits 1 0 0 2 stop bits 000- 001 and 110 - 111 Reserved 7 6 5 4 3 2 1 0 | sndpad | $55 | FCSPre | FCS Idle | pad2 | pad1 | padO Bit 7 1 = CL-CD2400 will send pad character(s) before sending SYN when coming out of the Mark Idle Mode. 0 = CL-CD2400 will not send any pad character. Bit 6 S55 = Send pad pattern 1 = 55h is sent as pad character. 0 = AAh is sent as pad character. Bit 5 FCS Preset 0 = FCS is preset to all ones. 1 = FCS is preset to all zeros. Bit 4 FCS Mode 1 = Disable FCS generation and checking, CL-CD2400 treats the entire frame as data. 0 = Normal FCS Mode. The CL-CD2400 generates and appends CRC on transmit and validates CRC on receive using CRC polynomial selected through CRC Polynomial Select Register. Bit 3 Idle Mode 0 = idle in SYN 1 = idle in mark Bits 2-0 character count specifies the number of pad characters sent. pad2 padt pado reserved 1 pad character sent 2 pad characters sent 3 pad characters sent 4 pad characters sent =~OQooo o-+-00 o-Oo-0 101 - 111 are reserved August 1993 = ee wmmmens =Detailed Reg... 83MB 2136639 000623? ?2T MHCIR 7 CL-CD2400/2401 SSE IRRUS LOGIC Multi-Protocol Controller Channel Option Register 3 (cont) X.21 Mode 7 6 5 4 3 2 1 0 | SgiSyn | SSDE | Strpsyn | SCDE | 0 | 0 0 | 0 | Bit 7 Single SYN. This bit determines the number of SYN characters that need to be received before Character Synchronization Mode is considered received. 0 = Two SYN Characters are required 1 = One SYN Character is required. The SYN Character can be reprogrammed via COR6. NOTE: This feature is not available in revisions prior to Revision H. Bit 6 Steady State Detect Enable, when set to a 1, this bit enables the checking of special receive conditions relevant to X.21. The special conditions are: 1. All zeros 2. All ones 3. Alternating zeros and ones 4. Change in the condition of the CTS* Pin (CTS* is used as the | lead for a DTE, or C lead for a DCE). To be detected as a special condition, a change must be present for at least 16-bit times. When detected, a receive exception interrupt is generated with the relevant status set in RISR. After detection of the special condition, no further data is passed to the host until different data is received. In certain phases of the X.21 call setup, there is no character synchronization. When a data change takes place in a Non-Character Synchronous Phase, a partial character can be detected before the steady state is detected or character sync is achieved. In these conditions, the partial character is passed to the host as normal data. Bit 5 Strip SYN. When this bit is set, SYN characters are treated as special receive conditions; when two SYN characters are received, a special character interrupt is generated (see RISR), and following SYN characters are filtered out. If the bit is not set, SYN characters are treated as normal data and passed to the host in good data interrupts; they are still used to obtain character synchronization with the data. Bit 4 Special Character Detect Enable is only available when the SSDE Mode is enabled. If enabled, the characters programmed in SCHR1-3 are treated as the steady state conditions in the SSDE Mode; they are validated for two character times, a special character interrupt is generated, and then further repetitions of the same data pattern are filtered from the data stream. Bit 3-0 Reserved must be zero. 84 Detailed Reg... sassasssumen = A August 1993M@ 21356639 0006238 bbb MECIR CL-CD2400/2401 Sean Multi-Protocol Controller ===> CIRRUS LOGIC Channel Option Register 4 {COR4} 16 15 B RAW (Modem Change Options and FIFO Transfer Threshold) 7 6 5 4 3 2 1 ) | DSRzd | CDzd | CTSzd | 0 | FIFO Threshold | Bit 7 DSRzd = 1 Detect one to zero transition on the DSR* input (zero to one transition of DSR (MSVR) Bit) Bit 6 CDzd = 1 Detect one to zero transition on the CD* input (zero to one transition of CD (MSVR) Bit) Bit 5 CTSzd = 1 Detect one to zero transition on the CTS* input (zero to one transition of CTS (MSVR) Bit) Bit 4 Reserved must be zero. Bits 3-0 FIFO Threshold in characters ~ Note: the maximum value allowable for this field is 12 (OC hex). These 4 bits, binary encoded field, set the FIFO transfer threshold FOR BOTH TRANSMIT AND RECEIVE FIFOs, FOR BOTH INTERRUPT AND DMA TRANSFER MODES. In the Asynchronous Mode, a Good Data transfer will be initiated for the number of characters in the FIFO greater the specified threshold. Receive timeout and the occur- rence of a receive data exception are also cause to initiate a receive transfer. In Synchronous modes, data transfer will be initiated when the number of characters in the FIFO is greater than the specified threshold. An end of frame is also cause to initiate a receive transfer. For transmit operation, the CL-CD2400 will attempt to refill the transmit FIFO when the empty space in the FIFO is greater than the set threshold. In the case of synchronous frame transmissions, the CL-CD2400 will stop refilling the transmit FIFO once the last character in the frame has been transferred to the FIFO. August 1993 wma Detailed Reg... 85ME 2136639 0006239 ST2 mmcir SS CL-CD2400/2401 ==" CIRRUS LOGIC Multi-Protocol Controller Channel Option Register 5 {COR5} 17 14 B RAV 7 6 5 4 3 2 1 0 | DSRod | CDod | CTSod | 0 | Rx Flow Control Threshold This register is used to define the current state change options to be monitored. Bit 7 DSRod = 1 Detect zero to one transition on DSR input (one to zero transition of DSR (MSVR) Bit) Bit 6 CDod = 1 Detect zero to one transition on CD input (one to zero transition of CD (MSVR) Bit) Bit 5 CTSod = 1 Detect zero to one transition on CTS input (one to zero transition of CTS (MSVR) Bit) Bit 4 Reserved must be zero. Bits 3-0 Receive Flow Control! FIFO Threshold These 4 bits, binary encoded field, define the Receive FIFO hardware flow control threshold. It sets the threshold in the receive FIFO at which automatic hardware (DTR/DSR) flow control is activated. A threshold value of zero disables the hardware flow control mechanism. When the number of characters in the Receive FIFO exceeds this threshold, the DTR* Pin deasserts; when the number of characters is equal to or less than the threshold, DTR* is asserted. 86 Detailed Reg... neem August 1993MB 2136639 O00be40 214 BICIR CL-CD2400/2401 SSa5 Multi-Protocol Controller === CIRRUS LOGIC Channel Option Register 6 {COR6} 1B 18 B RAW Async Asynchronous Mode 7 6 5 4 3 2 1 0 [ onc | ICRNL | INLCR | IgnBrk | NBrkint | ParMrk | INPCK | Parint | CR is defined as 0D hex, NL as 0A hex and NULL as 00 hex. Bit 7-5 These three bits are used to enable translation of received CR/NL characters as follows: ignCr ICrRNL INLCR 0 0 Q -no special action on CR and NL 0 0 1 ~ NL translated to CR 0 1 0 -CR translated to NL 0 1 1 CR translated to NL and NL translated to CR 1 0 Q -CR discarded 1 0 1 CR discarded and NL translated to CR 1 1 0 --CR discarded 1 1 1 CR discarded and NL translated to CR Bit 4-3 Break Action These bits determine the action taken after a break condition is received. IgnBrk NBrkint 0 0 Generate an exception interrupt 0 1 Translate to a NULL character 1 0 Reserved 1 1 Discard character Bit 2-0 Parityframing error actions These bits determine the action taken when a parity or framing error is received. Following the generation of a break exception interrupt, a receive exception interrupt will be generated with RET Bit (RISRI) set when the end of break is detected. The RET interrupt must be enabled in IER to enable this feature. ParMrk = INPCK Parint 0 0 O - Generated an exception interrupt 0 0 1 Translated to a NULL character 0 1 0 Ignore error; character passed on as good data 0 1 1 Discard error character 1 0 0 -- Reserved 1 0 1 Translate to a sequence of FF NULL and the error character and pass on as good data 1 1 0 Reserved 1 1 1 Reserved When ParMrk = 1 and Parint = 1, each occurrence of FF hex in the data stream will be preceded by FF hex in order to distinguish it from a parity error sequence. August 1993 a = m= Detailed Reg... 87Me 2136639 0006241 150 MCIR _ CL-CD2400/2401 CIRRUS LOGIC Multi-Protocol Controller Channel Option Register 6 {COR6} 1B 18 B R/W Async Bisynchronous Mode 7 6 5 4 3 2 1 0 | Special Frame Termination Character | In Bisync Mode, this register provides a frame-termination method for a receive character other than one already defined in the Bisync specification. When the initialize channel command in Channel Command Register (CCR) is processed, this register is set to the value of DLE (10); this deactivates the function because DLE processing is always performed before a match with COR6 is performed. Following the completion of the initialization command, the user can program the register to any character value for which frame termination is required. One use of this could be to terminate non-transparent frames for which the termination character has been corrupted. If the idle line character (FF in 8-Bit Mode, 7F in 7-Bit Mode) is programmed in CORE when a normal termination character is corrupted [i.e., ETX 03 changed to (07)], the BCC will be received as data, and the idle line condition will cause the frame to terminate. The idle line character will be the last character in the frame. No attempt is made to perform a CRC check on the receive data under these conditions. NOTE: This feature is not available in revisions prior to Revision H. X.21 Mode 7 6 5 4 3 2 1 0 } SYN Character | In X.21 Mode, this register contains the character that is used to find character synchronization with the receive data. When the initialize channel command in CCR is processed, the register is set to the value of ASCII SYN (16). If the user requires a different synchronization character, the following sequence can be used: 1. Issue channel initialize command; 2. Wait for command to be performed (CCR returned to 0); 3. Reprogram COR6 to desired value and issue receive enable command. NOTE: This feature is not available in revisions prior to Revision H. 88 Detailed Reg... a August 1993MH 2136639 oo0b24e O59? MMCIR CL-CD2400/2401 Multi-Protocol Controller = CIRRUS LOGIC Channel Option Register 7 {COR7} 04 07 B R/W Async Asynchronous Mode 7 6 5 4 3 2 1 0 [| IStrip a: I Foer | o | 0 | 0 | oNtcR | ocRNL | CR is defined as 0D hex, NL as 0A hex and NULL as 00 hex. Bit 7 (Strip when this bit is set, the most significant bit of receive characters is stripped, leaving 7-bit characters. |Strip is applied before special character processing, but after all other character processing. Bit 6 LNext this bit enables the LNext option. 0 = All receive characters are processed for special character detection. 1 = The character following the LNext character is not processed for special character matching or flow control. This provides a mechanism to transfer flow control and special characters as normal data, without invoking flow control action in the CL-CD2400, and without generating special interrupts. The LNext character is defined in the LNXT Register, and, when processed, is always passed to the host CPU as normal data. Bit 5 Flow control on error characters 0 = Characters received with an error will not be processed for special character/flow control matching. 1 = All receive characters, even those with errors, will be processed for special character/flow control processing. Bit 4-2 Reserved must be zero. Bit 1-0 Transmit processing for CR and NL; these bits define Translation Mode when CR and/or NL are present in the transmit data. ONLCR OCRNL 0 0 No special action 0 1 CR translated to NL 1 0 NL translated to the sequence CR NL 1 1 - CR translated to NL, and NL translated to the sequence CR NL August 1993) ae wane mm Detailed Reg... 89MH 2136639 oo0b243 T23 MMCIR === CL-CD2400/2401 SS0 IRRUS LOGIC Multi-Protocol Controller Special Character Registers Asynchronous Mode Special character registers can be used for detecting specific receive characters in the incoming data stream, and can be used to transmit character (via STCR) preempting any data in the transmit FIFO. Special Character Register1 {SCHR1} 1c 1F B R/W Async Special Character Register2 {SCHR2} 1D 1E B R/W Async Special characters 1 and 2 are used in conjunction with the SCDE Bit of COR3 to detect incoming characters; when both SCDE and TxIBE (COR2) are set, they define the in-band flow control characters XON and XOFF. SCHR1 = XON SCHR2 = XOFF In addition to the SCDE and TxIBE bits, if the FCT Bit (COR3) is set when flow control characters are received, they will be stripped from the data stream. Special Character Register3 {SCHR3} 1E 1D B R/W Async Special Character Register4 {SCHR4} 1F 1c B R/W Async Special characters 3 and 4 are used in conjunction with the ESCDE Bit of COR3 to detect characters in the receive data stream and generate receive special character interrupts. NOTE: Special characters 3 and 4 are not stripped from the data stream if Flow Control Transparency (FCT) Mode is enabled. 90 Detailed Reg... am en] August 1993ms MM 2136639 ooobe4Y T&T MBCIR CL-CD2400/2401 Multi-Protocol Controller == CIRRUS LOGIC Special Character Range Special Character Range low {SCR}} 20 23 B RW Async Special Character Range high {SCRh} 21 22 B R/W Async These bytes define an inclusive range for special character recognition in the Asynchronous Mode. It may be useful for identifying that a received character is within a user defined range and is, for example, a control character. LNext Character {LNXT} 2D 2E B R/W Async (This register defines the LNext character. If the LNext function is enabled (Bit 6 of COR7), the CL- CD2400 will examine received characters and compare them against this value. If a match occurs, this character and the following will be placed in the FIFO without any special processing. In effect, the LNext function causes the CL-CD2400 to ignore characters with special meaning, such as flow control characters. There are two exceptions. If the character following the LNext character is either a 'break' or an 'errored' character, LNext will be placed in the FIFO, and the following character will be treated as it normally would be for these error conditions. Rx Frame Address Registers Receive Frame Address Register1 {RFAR1} 1C 1F B RAW Sync Receive Frame Address Register2 {RFAR2} 1D 1E B RW Sync Receive Frame Address Register3 {RFAR3} 1E 1D B RW Sync Receive Frame Address Register4 {RFAR4} 1F 1c B R/W Sync Reception of a frame can be qualified with a matched one or two byte address field either as 4 one- byte alternatives or 2 two-byte alternatives. Control of how the ADR Registers are used for address recognition is detailed in the description of the Channel Option Registers. CRC Polynomial Select Register {CPSR} D4 D6 B RAW Sync 7 6 5 4 3 2 1 0 Le fe Toe To To Te Te J wy | Bits 7-1 Reserved must be zero. Bit 0 Polynomial select 1 = CRC-16 polynomial (normally used for bisync protocol and preset to 0's) "16 + x15 + x72 + 1], 0 = CRC V.41 polynomial (normally used for HDLC protocol and preset to 1's) [x16 + x""12 + x5 + 1] August 1993 ween 8 Detailed Reg... 91MB 2436639 O00b245 &Tb MCIR a SS CL-CD2400/2401 == IRRUS LOGIC Multi-Protocol Controller 6.3 Bit Rate and Clock Options Registers Receive Baud Rate Generator Registers Receive Baud Rate Period Register {RBPR} cg CB B RAV 7 6 5 4 3 2 1 0 | Receive Baud Rate Period (Divisor) This register contains the preload value for the receive baud rate counter. When using an internal clock option or an n-times external clock, the preload value, in conjunction with the receiver clock source chosen, will determine the receive baud rate. If a 1x external clock is used, a value of O1h must be loaded in the RBPR. Receive Clock Option Register {RCOR} CA C8 B RAW 7 6 5 4 3 2 1 a | TLVal | 0 | dpliEn | Dplimds | Opiimdo | ClkSel2 | CkkSelt | ckseto This register is used to select the DPLL Mode, and the desired clock source for the receive baud rate generator. Bit 7 TLVal Transmit Line Value This reflects the logical value of the transmit data pin. Bit 6 Reserved must be zero. Bit 5 DPLL enable 1 = DPLL is enabled 0 = DPLL is disabled Bits 4-3 DPLL Mode select and used to select the type of data encoding used. Dpiimdt Dpilmd0d Encoding 0 0 NRZ 0 1 NRdzi 1 0 Manchester 1 1 Reserved Bits 2-0 These three bits are used to select the clock source for the receive baud rate generator or DPLL. clkSel2 clkSel1 clkSel0 clock source 0 0 0 Clk 0 0 0 1 Clik 1 0 1 0 Clk 2 0 1 1 Clk 3 1 0 0 Clk 4 1 0 1 Reserved 1 1 0 External clock 1 1 1 Reserved NOTE: See the detailed description of clock options in Section 3.5. 92 Detailed Reg... - August 1993M8 2136639 OOobey4 73a MPcIR CL-CD2400/2401 SSS Multi-Protocol Controller =="CIRRUS LOGIC 6.3 Bit Rate and Clock Options Registers (cont,) Transmit Baud Rate Generator Registers Transmit Baud Rate Period Register {TBPR} C1 C3 B RAV 7 6 5 4 3 2 1 0 | Transmit Baud Rate Period (Divisor} | This register contains the preload value for the transmit baud rate count. When using one of the internal clocks or an n-times external clock, the preload value, in conjunction with the transmitter clock source chosen, will determine the transmit baud rate. If a 1x external clock or the Receive Clock is used, a value of 01h must be loaded in the TBPR. Transmit Clock Option Register {TCOR} C2 co B R/AW 7 6 5 4 3 2 1 0 | Cikset2 | CikSelt | ckseio | 0 | Ext-1x | 0 | um | o | This register controls the transmit baud rate generator and Local Loopback Mode. Bits 7-5 Are used to select the clock source for the transmit baud rate generator. ClkSel2ClkSel1. ClkSel0_~ Select 0 0 0 Clk 0 0 0 1 Clk 1 0 1 0 Clk 2 0 1 1 Clk 3 1 0 0 Clk 4 1 0 1 Reserved 1 1 0 External clock 1 1 1 Receive clock NOTE: See the detailed description of clock options in Section 3.5. Bit 4 Reserved must be zero. Bit 3 Times 1 external clock. This bit is set to 1 when user supplies the data clock on TxCIN{i] Pin whose frequency is equal to the transmit data rate. When using the external 1x clock or the clock from the receiver's DPLL, the TBPR must be programmed to Oth. Bit 2 Reserved must be zero. Bit 1 Local Loopback Mode 1 enables the Local Loopback Mode 'O' disables the Local Loopback Mode Bit 0 Reserved must be zero. August 1993 rn ETERS Detailed Reg... 93M@ 2136639 0006247 479 MECIR a == CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocol Controller 6.4 Channel Command and Status Registers Channel Command Register {CCR} 10 13 B RAW 7 6 5 4 3 2 1 0 [ 9 | Groh | Initch | Rstan | eEntx | Distx | Enkx | Dishx | 7 6 5 4 3 2 1 0 | 4 j cwrr | crt2 | crrv | o | o | a } 9 | There are two CCR command sets. If Bit 7 is zero, the commands affect basic channel control. If Bit 7 is one, additional commands are available which control timer functions. The various command and control bits in this register perform largely independent functions. The host may assert multiple command bits to achieve the desired effect. The CL-CD2400 will clear the register to zero after it accepts and acts on a host command. The host must verify that the contents of this register are zero prior to issuing a new command. If the Reset All command is issued, all other commands are ignored. All other combinations are legal, and the order of processing will be as follows: Clear Channel Initialize Channel Enable Receive Disable Receive Enable Transmit Disable Transmit PAPwWn > NOTE: Processing CCR commands is a !ow-priority task for the internal firmware, since they seldom occur. The user must take care when waiting for command completions at critical times, i.e., during interrupt service routines. Channel Control Commands (Bit 7 = 0) Bit 7 Must be zero. Bit 6 Clear Channel Command When this command is issued, the CL-CD2400 clears the data FIFOs and current transmit and receive status of the channel in the CSR. If the channel is currently transmitting a frame in synchronous protocol, the host should issue the Transmit Abort, Special Transmit Command, prior to issuing a Clear Command Command. Channel parameters will not be affected by a Channel Clear command. The Clear Channel command causes both receive and transmit FIFOs to be cleared, the transmitter and receiver to be disabled and all DMA Status Registers (DMABSTS, A/BRBSTS and A/BTBSTS) to be cleared. Bit 5 Initialize Channel if any change is made to the Protocol Mode Select bits in the Channe] Mode Register (CMR) or to the Channel Option Register 1 (COR1), the channel must be reinitialized via this command. The command causes the internal protocol-specific registers to be initialized. 94 Detailed Reg... om See August 1993MM 2136639 0006248 5O5 MMCIR CL-CD2400/2401 SS ET Multi-Protocol Controller CIRRUS LOGIC Channel Command Register (cont.) Bit 4 Reset All An on-chip firmware initialization of alf channels is performed. All channel and global parameters are reset to their power on reset condition. This command is the strongest the host may issue. None of the other command bits is interpreted if the Reset All command is given. The host must re-initialize the CL-CD2400 following the execution of this command just as after a hardware Power-On Reset. When this command is completed, the GFRCR will be updated with the firmware revision code. Bit 3 Enable Transmitter Enables the transmitter by setting TxEn in the Channel Status Register (CSR). In Asynchronous Mode, this command also clears the transmit flow control options. Bit 2 Disable Transmitter Disables the transmitter by clearing TxEn in the Channel Status Register (CSR). In Asynchronous Mode, the transmit flow control bits will be cleared. Bit 1 Enable Receiver Enables the receiver by setting the RxEn Bit in the CSR. In Asynchronous Mode, the receive flow control bits will also be cleared, Bit 0 Disable Receiver Disables the receiver by clearing the RxEn Bit in the CSR. In Asynchronous Mode, the receive flow control bits will also be cleared. Miscellaneous Channel Commands (Bit 7 = 1) Either one or both of the timers may be cleared with a single command. Note that if the running timer value is 01h at the time this command is issued, there is a small chance that the timer will expire and cause a timer interrupt before the command is processed. Bit 7 Bit 6 Bit 5 Bit 4 Must be one. Clear Timer 1 General Timer 1 is cleared. Clear Timer 2 General Timer 2 is cleared. Clear Receiver Command This command only affects the receiver. It resets all receiver functions like a combination of Clear Channel, Initialize Channel and Enable Receiver commands. CirRev clears the receive FIFO and clears receive status in the CSR Register, except for the RevEn Bit. ClrRev clears receive DMA buffer status in ARBSTS, BRBSTS and receive status bits in DMABSTS. Clearing the 24000WN Bits in both Receive Buffer Status Registers means that DMA buffers will have to be given back to the CL-CD2400 before receive transfers will begin again. For Synchronous Modes, this command puts the receiver back into Syn/Flag Hunt Mode. The CirRcv command can be used in Programmable Sync Mode to reconfigure the receiver for the next frame, once the end of frame has been detected. NOTE: This command is not available in revisions prior to Revision H. August 1993 a aRAEIROTRTEEEENINANe Detailed Reg... 95MB 2136639 GO0b249 441 MCIR = CL-CD2400/2401 SSS CIRRUS LOGIC Multi-Protocol Controller Miscellaneous Channel Commands (cont.) Bits 3-0 Reserved must be zero. Special Transmit Command Register {STCR} 11 12 B RAW 7 6 5 4 3 2 1 0 | 0 | AbortTx JAppdcme | 0 | SndSpe | sspc2_| ssPct | ssPco_ | The CL-CD2400 will clear the register to zero when it accepts a host CPU command. Bit 7 Reserved must be zero. . Bit 6 Abort Transmission (HDLC) Terminate the frame currently in transmission with an abort sequence. In DMA Mode, all data up to the next EOF is discarded. Bit 5 Append Complete (Asynchronous DMA Mode) This bit should be set by the host when the last addition has been made to the append buffer. Bit 4 Reserved must be zero. Bit 3 Send Special Character(s) Command A command used in Asynchronous Mode to send a user-defined special character or special-character sequence. The special character will be transmitted ahead on any data remaining in the FIFO. Bits 2-0 Special Character Select SSPC2 SSCP1 SSPCO Function 0 0 0 Reserved 0 0 1 Send Special Character #1 0 1 0 Send Special Character #2 0 1 1 Send Special Character #3 1 0 0 Send Special Character #4 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 96 Detailed Reg... August 1993M@ 2136639 O00b250 163 MECIR CL-CD2400/2401 Multi-Protocol Controller === CIRRUS LOGIC Channel Status Register {CSR} 19 1A B R This status register stores the current state of the channel. It may be read by the host at any time. The states of the RxEn and the TxEn Bits are controlled by host CPU commands to the CCR Register. HDLC Mode 7 6 5 4 3 2 1 0 | RxEn | RxFlag | RxFrame | RxMark | TxEn | TxFlag | TxFrame | TxMark | Bit 7 Receiver Enable 0 = Receiver is disabled 1 = Receiver is enabled Bit 6 Rx Flag 0 = Currently not receiving flag/sync 1 = Currently receiving flag/sync Bit 5 _ Rx Frame 0 = Currently not receiving frame 1 = Currenily receiving frame Bit 4 Rx Mark 0 = Currently not receiving continuous mark 1 = Currently receiving continuous mark Bit 3 Transmitter Enable 0 = Transmitter is disabled 1 = Transmitter is enabled Bit 2 Tx Flag 0 = Currently not transmitting flag 1 = Currently transmitting flag Bit 1 Tx Frame 0 = Currently not transmitting frame 1 = Currently transmitting frame Bit 0 Tx Mark 0 = Currently not transmitting continuous ones 1 = Currently transmitting continuous ones August 1993 ers Detailed Reg... 97ME 2136639 O006251 OTT MECIR CL-CD2400/2401 CIRRUS LOGIC Multi-Protocol Controller Channel Status Register (cont) Asynchronous Mode If the host determines that a flow control state is inappropriate, it may be cleared by enabling or disabling the transmitter or receiver by CCR command. 7 6 5 4 3 2 1 0 [ RxEn | RxFioff RxFlon | 0 | TxEn | TxFloff | TxFion | 0 Bit 7 Receiver Enable 0 = Receiver is disabled 1 = Receiver is enabled Bit 6 Receive Flow Off 0 = Normal 1 = The CL-CD2400 has requested the remote to stop transmission (Send XOFF (command has been given to the channel). This bit will be reset when the CL-CD2400 has requested the remote to restart transmission, or when the receiver is enabled or disabled, or the channel is reset. Bit 5 Receive Flow On 0 = Normal 1 = The CL-CD2400 has requested the remote to restart character transmission (Send XON command has been given to the channel). This bit is reset when the next (non-flow control) character is received, or when the receiver is enabled, or disabled or the channel is reset. Bit 4 Unused. Bit 3 Transmitter Enable 0 = Transmitter is disabled 1 = Transmitter is enabled Bit 2 Transmit Flow Off 0 = Normal 1 = The CL-CD2400 has been requested by the remote to stop transmission. This bit is reset when the CL-CD2400 receives a request to resume transmission, or when the transmitter is enabled or disabled, or the channel is reset. Bit 1 Transmit Flow On 0 = Normal 1 = The CL-CD2400 has been requested by the remote to resume transmission. This bit is reset once character transmission is resumed, or when the transmitter is enabled or disabled, or the channel is reset. Bit 0 Unused. 98 Detailed Reg... ee ee] August 1993MB 2456639 gog0beSe T3b MCIR CL-CD2400/2401 ea . Multi-Protocol Controller SS CIRRUS LOGIC Channel Status Register (cont) Bisynchronous Mode 7 6 5 4 3 2 1 0 | RxEn | RxiTB | RxFrme | 0 { TxEn | TxITB | TxFrme | 0 Bit 7 Receiver Enable 0 = Receiver is disabled 1 = Receiver is enabled Bit 6 Receive ITB. This bit indicates that the last frame received was terminated with an ITB. This means that the leading character of the next receive frame will be included in the BCC calculation. Bit 5 Receive frame. This bit indicates that the CL-CD2400 is currently receiving a frame. Bit 4 Reserved must be zero. Bit 3 Transmitter Enable 0 = Transmitter is disabled 1 = Transmitter is enabled Bit 2 Transmit ITB. This bit is set if the last frame transmitted ended in an ITB character., i.e., the leading character of the next frame will be included in the BCC calculation. Bit 1 Transmit Frame. When set, this bit indicates a frame is currently being transmitted. Bit 0 Reserved must be zero. X.21 Mode 7 6 5 4 3 2 1 0 | RxEn | 0 | RxSpe | 0 | Txen | 0 | TxSpe_ | 0 | Bit 7 Receiver Enable 0 = Receiver is disabled 1 = Receiver is enabled Bit 6 Reserved must be zero. Bit 5 Receive Special. When set, this indicates that the channel is in a steady-state condition. Such conditions generate a receive Special character interrupt. Bit 4 Reserved must be zero. Bit 3 Transmitter Enable 0 = Transmitter is disabled 1 = Transmitter is enabled Bits 2, 0 Reserved must be zero. Bit 1 Transmit Special. When set, this indicates that the CL-CD2400 is currently transmitting an ETC command, as defined in COR2. August 1993 a Detailed Reg... 99MB 2136639 0006253 972 MCIR SSS CL-CD2400/2401 CIRRUS LOGIC Multi-Protocol Controller Modem Signal Value Registers {MSVR} RAV Modem Signal Value Register {MSVR-RTS} DC DE B RAW {MSVR-DTR} DD DF B RAW 7 6 5 4 3 2 1 0 [DSR/RxCK] CD/TxCk | CTs | oTRopt | 0 | Portid | OTR | RTS | Either of these registers is read to determine the current input levels on the input modem pins. Note that the pin definitions for these signals is negative true while the register values are positive true. Two registers are provided for control of the outputs DTR and RTS. Writing to the MSVR-DTR Register affects only the DTR Pin. Writing to the MSVR-RTS Register affects only the RTS Pin. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DSR Current state of Data Set Ready input. Note that this pin may optionally be used as Receive Clock input in synchronous modes. Reading the Receive Clock input gives an inverted sample of the state of the Receive Clock at the time the read occurs. CD Current state of Carrier Detect input. Note that this pin may optionally be used as Transmit Clock input in synchronous modes. Reading the Transmit Clock input gives an inverted sample of the state of the Transmit Clock at the time the read occurs. CTS Current state of Clear to Send input. DTR option written via MSVR-DTR Register. 0 = value of DTR Bit is output on TXCout/DTR? Pin 1 = Transmit clock is output on TXCout/DTR* Pin NOTE: if the Transmit clock source is a 1x clock on the TXCin/CD* Pin, this signal cannot be driven on TXCoutv/DTR*. Reserved must be zero. PortID This bit is read only. It can be used to determine which modem clock option pins are available. 0 = Device is the CL-CD2401 1 = Device is the CL-CD2400. DTR Current state of Data Terminal Ready output. RTS Current state of Request to Send output. 100 Detalied FRG... mnnnremsrrenereenneSSSESREIE August 1993MB 2136639 OOObeS4 805 MmCIR CL-CD2400/2401 Ee Multi-Protocol Controller ==> CIRRUS LOGIC 6.5 Interrupt Registers Local Interrupt Vector Register {LIVR} OA 09 B RAW The host effectively controls Bits 7 through 2; the chip provides Bits 1 and 0 within an Interrupt Acknowledge context. 7 6 5 4 3 2 1 0 Lx {| x [| x |] x | x [x [Tm ][m ] The CL-CD2400 has one Local Interrupt Vector Register per channel, each with six host-defined bits. The host may choose to embed the channel number and the protocol in use on the channel in the channel vector. The CL-CD2400 will supply two modified bits signifying the type of interrupt service required. Bits 7-2 User-defined. These six bits may be used as the CL-CD2400 chip 1D number. Bits 1-0 Interrupt type 1-0. These three bits indicate the group/type of interrupt occurring. IT[1:0] GROUP/TYPE 01 Group 1: Modem Signal Change Interrupt/ General Timer Interrupt 10 Group 2: Transmit Data Interrupt 11 Group 3: Receive Data Interrupt 00 Group 3: Receive Exception Interrupt Note that because the CL-CD2400 provides a unique Local Interrupt Vector Register for each channel, the host has the option to include the channel number within the interrupt vector. August 1993 ET ummm 86Detailed Reg... 101M@@ 2136639 O00b2S5 745 MHCIR ETT. SS CL-CD2400/2401 22" CIRRUS LOGIC Multi-Protocol Controller Interrupt Enable Register {IER} 12 11 B RAW 7 6 5 4 3 2 1 0 | Mdm | 0 | RET | 0 | RxD | TIMER | TxMply | TxD Bit 7 Modem Pin Change Detect Master interrupt enable for modem change detect functions. The host may select which modem pins are watched for input change and select either or both directions of change by programming the change detect option bits in COR4 and CORS. A group1 type interrupt (See LIVR description) is generated from this enable. Bit 6 Reserved ~ must be zero. Bit 5 RET (Async) In Asynchronous Mode, this bit enables a group 3 Receive Exception Timeout interrupt when a receive data timeout occurs with an empty receive FIFO. This provides a mechanism for the host to manage a partially full receive buffer when receive data stops. Bit 4 Reserved must be zero. Bit 3 Rx Data The receive FIFO threshold has been reached in Interrupt Transfer Mode, causing a group 3 Receive Data Interrupt. Any receive exception causes a group 3 Receive Exception Interrupt. Bit 2 Timer General Timer(s) Timeout In Synchronous Mode this bit enables a group 1 interrupt when either timer reaches zero. Bit 1 Tx Mpty Transmitter Empty. When enabled, a group 2 interrupt is generated when the channel is completely empty of transmit data. Bit 0 Tx Data Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer Mode. Group 2 interrupts will be generated at the end of transmit DMA buffers or when the FIFO threshold is reached in Interrupt Transfer Mode. 102 Detailed Reg... wa =s-s Aurgust 1993MH 21356639 ooobess 6&1 MECIR CL-CD2400/2401 SS Multi-Protocol Controller === CIRRUS LOGIC Local Interrupting Channel Register {LICR} 25 26 B RAW 7 6 5 4 3 2 1 0 Lx [x Tx Tx Te Te [xy] These per-channel registers are initialized with each channel number. The locations are RAM registers and may be used for any purpose. Bits 7-4 User-defined. Bits 3-2 Defines the interrupting channel number ci Channel Number 0 0 Channel 0 0 1 Channel! 1 1 0 Channel 2 1 1 Channel 3 Bits 1-0 User-defined. August 1993 ne _ananeo Detailed Reg... 103MB 2136639 OO0beS? sia MECIR Sa CL-CD2400/2401 SS====CIRRUS LOGIC Multi-Protocol Controller Stack Register {STK} EO E2 B R 7 6 5 4 3 2 1 0 | civ 1] | MLvi [1] | TL [1] | 0 | 0 | TL [0] } MLvI [0] | CLvI [0] This register is a four-deep-by-two-bit-wide stack that holds the internal interrupt nesting history. The stack is pushed from bits 7 and 0 towards the center during an interrupt acknowledge cycle and popped from the center during a write to an end of interrupt register. CLvt [0:1] These bits provide the currently active interrupt level. CLvI [1] CLvI [0] 0 0 No interrupt active; CAR provides the current channel number 0 1 Currently in a modem interrupt service, MIR provides the current channel number. 1 0 Currently in a transmit interrupt service, TIR provides the current channel number. 1 1 Currently in a receive interrupt service, RIR provides the current channel number. MLvi [0:1] These bits hold a previously active interrupt now nested. TLV [0:1] These bits hold the oldest interrupt now nested 2 deep. 104 Detailed Reg... | August 1993MB 2156639 0006258 454 MECIR CL-CD2400/2401 SSS Multi-Protocol Controller CIRRUS LOGIC 6.5.1 Receive Interrupt Registers Receive Priority Interrupt Level Register {RPILR} E3 E1 B RAW This register must be initialized by the host to contain the codes that will be presented on the address bus by the host system to indicate which of the three CL-CD2400 interrupt types (i.e., modem, transmit or receive) is being acknowledged when IACKIN* is asserted. The CL-CD2400 compares bits 0-6 in this register with A[0-6] to determine if the acknowledge l!evel is correct. The value programmed in the MSB of the register has no effect on the IACK cycle. RPILR must contain the code used to acknowledge receive interrupts. NOTE: Bit 7 of the register is always read back as '0'".. When each of the three Priority Interrupt Level Registers is programmed with the same value, they are internally prioritized, with receive as the highest priority, followed by transmit and modem. Receive Interrupt Register {RIR} EF ED B R 7 6 5 4 3 2 1 0 | Ren | Ract | Reoi | 0 | Rvot {1] | vet [0] | Ren [1] | Ren (01 | Bit 7 Ren Receive enable is set by the CL-CD2400 to initiate a receive interrupt request sequence. It is cleared during a valid receive interrupt acknowledge cycle. Bit 6 Ract Receive active is set automatically when Ren is set, and the Fair Share logic allows the assertion of a receive interrupt request. It is cleared when the host CPU writes to the Receive End of Interrupt Register. Bit 5 Reoi Receive end of interrupt is set automatically when the host CPU writes to the receive end of interrupt register while in a receive interrupt routine. Ren Ract Reoi Sequence of Events 0 0 0 Idle 1 0 0 Receive interrupt requested, but not asserted 1 1 0 Receive interrupt is asserted 0 1 0 Receive interrupt is acknowledged 0 0 1 Receive interrupt service routine is completed Bit 4 Unused Bits 3-2 Rvect [0:1] Receive vector bits are set by the CL-CD2400 to provide the lower two bits of the vector supplied to the host CPU during an interrupt acknowledge cycle. Receive good data vector is decoded as follows: Rvct [1] = 1, and Rvct [0] = 1. Receive exception vector is decoded as follows: Rvct [1] = 0, and Rvct [0] = 0. Bits 1-0 Ren [0:1] Receive channel number is set by the CL-CD2400 to indicate the channel requiring receive interrupt service. August 1993 ee Detailed Reg... 105M@@ 2136639 0006259 350 MCIR ee a CL-CD2400/2401 == CIRRUS LOGIC Multi-Protocol Controller Receive Interrupt Status Register {RISR} 8A 88 Ww RAW Receive Interrupt Status Register Low ({RISR} 8A 89 B RAV HDLC Mode 7 6 5 4 3 2 1 0 | o | EOF | rxabt {| oRc | O& | Resind | 0 | Girdet | Bit 6 Receiving of a data frame is essentially complete. Bit 5 Received Abort sequence terminating the frame. Bit 4 CRC Error on current frame. Bit 3 Overrun Error indicates that new data has arrived, but the CL-CD2400 FIFO or holding registers are full. The new data is lost, and the overrun indication is flagged on the last character received before the overrun occurred. In HDLC and Bisync Modes, the remainder of a frame, following an overrun, will be discarded. Bit 2 Residual Indication indicates that the last character of the frame was a partial character. Bit 0 Clear Detect indicates an X.21 Data Transfer Phase Clear Signal has been detected. This is defined as two consecutive all-zero receive characters with the CTS* Pin high. Clear Detect Mode is enabled via COR1. During an interrupt service routine, the host may use this register to provide a timer value as detailed in the Receive End of Interrupt Register. The host can only load one of the two timers in the interrupt service routine. 106 Detailed Reg... enna = August 1993M@@ 2136639 0006260 O02 MECIR CL-CD2400/2401 SS Multi-Protocol Controller ===CIRRUS LOGIC Receive Interrupt Status Register Low (cont) Asynchronous Mode 7 6 5 4 3 2 1 0 | Timeout | SCdet2 | SCdet | SCdetd | OE | PE | FE | Break | Bit 7 Timeout indicates that the Receive FIFO is empty, and no data has been received within the receive timeout period. There is no data character associated with this status, and no other status bits are valid if the Timeout Bit is set. Bits 6-4 Special Character Detect SCdet[2:0] Status 000 None detected 001 Special Character 1 matched 010 Special Character 2 matched 011 Special Character 3 matched (only if ESCDE is enabled in COR3) 100 Special Character 4 matched (only if ESCDE is enabled in COR3) 111 Character is within the inclusive range of the characters in the Special Character Range low and high registers (only if RngDE is enabled in COR3) Special character match can be enabled for error characters via COR7. Bit 3 Overrun Error indicates that new data has arrived, but the CL-CD2400 FIFO or holding registers are full. The new data is lost and the overrun indication is flagged on the last character received before the overrun occurred. Bit 2 Parity Error indicates that a parity error has occurred. Bit 1 Framing Error indicates that a bad stop bit has been detected. Bit 0 Break indicates that a Break has been detected. Bisynchronous Mode 7 6 5 4 3 2 1 0 {9 | cor | mat [or [To [ o [ o [ o | Bit 6 Receiving of a data frame is essentially complete. Bit 5 Received Abort sequence terminating the frame. Bit 4 CRC error on current frame. Bit 3 Overrun Error indicates that new data has arrived, but the CL-CD2400 FIFO or holding registers are full. The new data is lost, and the overrun indication is flagged on the last character received before the overrun occurred. During an interrupt service routine, the host may use this register to provide a timer value as detailed in the Receive End of Interrupt Register. August 1993 a ETE Detailed Reg... 107M8 2136639 OO0b2b1 TH4 MECIR SSS CL-CD2400/2401 = CIRRUS LOGIC Multi-Protocol Controller Receive interrupt Status Register Low (cont.) X.21 Mode 7 6 5 4 3 2 1 O | tval | scdet2 | scaett | scdeto | o& | PE | 0 | tchg For X.21 Operation, the CTS* Pin is used as the | lead for DTE or C lead for a DCE, a low level on CTS* is interpreted as an ON condition and a high level on CTS* as an OFF condition. Bit 7 Lead value 0 = OFF 1=ON Bit 6-4 Special Character Detect all the following conditions must be met two consecutive character times. SCdet[2:0] Status 000 None detected 001 Matched the value in SCHR1 010 Matched the value in SCHR2 011 Matched the value in SCHR3 100 Ail 0 condition 101 All 1 condition 110 Alternating 1 0 condition 111 SYN detect Bit 3 Overrun Error indicates that new data has arrived, but the CL-CD2400 FIFO or holding registers are full. The new data is lost and the overrun indication is flagged on the last character received before the overrun occurred. Bit 2 Parity Error ~ indicates that a parity error has occurred. Bit 0 Lead Change this indicates a change of state on the CTS* Pin from the previous character time. Because there is no character sync during some phases of the X.21 call setup, an LChg indication may precede a special character interrupt. During an interrupt service routine, the host may use this register to provide a timer value as detailed in the Receive End of Interrupt Register. 108 Detailed Reg... a SE REE REENETEOTEETNEEEROEEEEe August 1993MB 2156639 Oogb2be 445 MECIR CL-CD2400/2401 SES Multi-Protocol Controller CIRRUS LOGIC Receive Interrupt Status Register High {RISRh} 8B 88 B RAW 7 6 5 4 3 2 1 0 | Berr | EOF | EOB | 0 | BABB | 0 | 0 | 0 | This register is used in DMA Mode only. Bit 7 Bus error (written by CL-CD2400) 0 = No bus error. 1 = Bus error was detected on the last transfer. The actual address at which the error occurred is available in the Receive Current Buffer Address Register. In response to a_ bus error status, the host has two possible options. 1. Retry from the next position in the buffer. 2. Terminate this buffer through setting TermBuff Bit in REOIR, and move onto the next. Bit 6 Reception of a data frame is complete (Sync DMA Mode only). Bit 5 The End Of a receive Buffer has been reached. Used only for DMA supported transmission. The end of one of the host supplied receive buffers has been reached. Bit 4 Reserved must be zero. Bit 3 Status occurs during buffer A or buffer B data transfer 0 = Buffer A 1 = Buffer B Bits 2-0 Reserved must be zero. Receive FIFO Output Count {RFOC} 33 30 B R 7 6 5 4 3 2 1 0 0 | 0 | 0 RxCt4 | RxCB | RxCt2 | RxCtt Rxcto | Bits 7-5 Unused Bits 4-0 Receive data count. If the receive channel is interrupt driven, a non-zero value in this bit field is the number of data characters available for transfer within the current receive interrupt. Receive Data Register {RDR} F8 F8 B R (Read Only) 7 6 5 4 3 2 1 0 | o7 | 1 | o | o { 3 { o [| o | ow | This virtual register accesses the receive data FIFO of a channel interrupting for receive data transfer. This register address is used for all channels to transfer receive FIFO data to the host, if programmed in Interrupt Transfer Mode. Data must be read as bytes, and follows the rules of Section 6.3 for the positioning of valid data on the bus. If the BYTESWAP Pin is high, data is valid on A/D[0:7], if BYTESWAP is low, data is valid on A/D[8:15]. This is true because the RDR is on an even address. August 1993 a ___mememmeme Detailed Reg... 109MH 21566359 0006263 411 MECIR CL-CD2400/2401 Se CIRRUS LOGIC Multi-Protocol Controller Recelve End Of Interrupt Register {REOIR} 87 84 B Ww 7 6 5 4 3 2 1 0 | TermButt | DiscExc | SetTm2 | SetTm1 | Notranst | Gap2 | Gap1 Gapod | The CL-CD2400 interprets values written to this register at the completion of all Receive interrupts. Bit 7 Terminate Current DMA Buffer. If this bit is set, the current receive buffer is terminated and data transfer is switched to the other buffer. This bit should only be set in response to an async exception interrupt. If the buffer is terminated in response to an exception character (i.e., parity error) interrupt and the discard exception character bit is not set, the exception character is written at the start of the next buffer. Before writing the terminate buffer command to REOIR, a new buffer descriptor may be written to the current buffer. Bit 6 Discard Exception Character (DMA Mode only). When this bit is set in response to an async exception interrupt, the exception character is not transferred to memory. Bit 5 Set general timer 2 in Synchronous Modes. 0 = do not set general timer 1 = load the value, to general timer 2, provided in RISRI. Bit 4 Set general timer 1 in Synchronous Modes. 0 = do not set general timer 1 1 = load the value, to the high byte of general timer 1, provided in RISRI. At the end of an interrupt service routine, the user may set a timer by setting a timer value in the Receive Interrupt Status Register. When the timer reaches 0, CL-CD2400 will generate a modem/timer group interrupt to the host. Bit 3 No transfer of data. This bit must be set by the host, if no data is transferred from the receive FIFO during a receive interrupt. Bits 2-0 Size of the optional gaps to be left in DMA Buffer, starting at the current location, before resuming data transfer. The CL-CD2400 will move its buffer address pointer forward the selected number of bytes. It will not write to any location in the gap.' If the gap is large enough to complete or extend beyond the end of the current buffer, it will be completed, and the gap continued in the other receive buffer. If the discard exception character is not selected, the character on which the exception occurred is written to the buffer following the gap. 110 Detailed Reg... a wna August 1993MB 2136639 Ooobeby ?58 MECIR CL-CD2400/2401 SSS Multi-Protocol Controller = CIRRUS LOGIC Transmit Priority Interrupt Level Register {TPILR} 2 EO B R/w This register must be initialized by the host to contain the codes that will be presented on the address bus by the host system to indicate which of the three CL-CO2400 interrupt types (i.e., modem, transmit or receive) is being acknowledged when IACKIN* is asserted. The CL-CD2400 compares bits 0-6 in this register with A[0-6] to determine if the acknowledge level is correct. The value programmed in the . MSB of the register has no effect on the IACK cycle. TPILR must contain the code used to acknowledge transmit interrupts. NOTE: Bit 7 of this register is always read back as 0. When each of the three Priority Interrupt Level Registers are programmed with the same value, they are internally prioritized, with receive as the highest priority, followed by transmit and modem. Transmit Interrupt Register {TIR} EE EC B R 7 6 5 4 3 2 1 0 | Ten | Tact | Teoi | O | Tvet [1] | Tvct [0] } Ton [1] | Ton (0) Bit 7 Ten Transmit enable is set by the CL-CD2400 to initiate a transmit interrupt request sequence. It is cleared during a valid transmit interrupt acknowledge cycle. Bit 6 Tact Transmit active is set automatically when Ten is set, and the Fair Share logic allows the assertion of a transmit interrupt request. It is cleared when the host CPU writes to the Transmit End of Interrupt Register. Bit 5 Teoi Transmit end of interrupt is set automatically when the host CPU writes to the transmit end of interrupt register while in a transmit interrupt routine. Ten Tact Teol Sequence of Events 0 0 0 idle 1 0 0 Transmit interrupt requested, but not asserted 1 1 0 Transmit interrupt is asserted 0 1 0 Transmit interrupt is acknowledged 0 0 1 Transmit interrupt service routine is completed Bit 4 Unused Bits 3-2 Tvet [0:1] Transmit vector bits are set by the CL-CD2400 to provide the lower two bits of the vector supplied to the host CPU during an interrupt acknowledge cycle. Transmit vector is decoded as follows: Tvct [1] = 1, and Tvct [0] = 0. Bits 1-0 Ten [0:1] Transmit channel number is set by the CL-CD2400 to indicate the channel requiring transmit interrupt service. August 1993 =e Detalled Reg... 111M@@ 2136639 0006265 694 MECIR SS CL-CD2400/2401 = CIRRUS LOGIC Multi-Protocol Controller Transmit Interrupt Status Register {TISR} 89 8A B RW 7 6 5 4 3 2 1 o | Ber | EOF | EOB | UE | BABB | 0 | TxEmpty | TrDat | When the host receives a transmit interrupt, the following status is provided in this register: Bit 7 Bus error {written by CL-CD2400) 0 = no bus error 1 = bus error was detected on the last transfer. The actual address at which the error was detected is available in the Transmit Current Buffer Address Register. In response to a bus error status, the host must choose between these two options by the value of the TermBuff Bit in the TEOIR Register: 1. Setting TermBuff terminates this buffer and moves onto the next; 2. Clearing TermBuff continues with the next position in the current buffer. Bit 6 Transmit end of frame indication in DMA Mode. The interrupt for this condition is generated when the final data character of a transmit frame is transferred to the internal transmit FIFO. To maximize frame throughput, the host will wish to initiate the next frame transmission when EOFrame becomes true. If a half-duplex serial line must be turned around, the host must wait for TxEmpty to become true. The interrupt Enable Register contains bits that permit the host to choose which of these conditions will actually cause the interrupt. Bit 5 The end of a Transmit Buffer has been reached. Used only for DMA supported transmission. Bit 4 Transmit Underrun. Data was not available in time during synchronous frame transmission, and an underrun error has occurred. Following a transmit underrun, all data up to the next EOF is discarded. Bit 3 Buffer that has exception 0 = Buffer A 1 = Buffer B Bit 1 Transmitter Empty, the frame or character transmission is completed, and the transmit serial output is in its selected idle condition. Bit 0 Transmit Data is below the FIFO threshold. During an interrupt service routine, the host may use this register to provide a timer value as detailed in the Transmit End of Interrupt Register. The host can only load one of the two timers in each interrupt service routine. 112 Detailed Reg... ve August 1993MB 2136639 O00b2bb 520 MMCIR CL-CD2400/2401 Multi-Protocol Controller CIRRUS LOGIC Transmit FIFO Transfer Count {TFTC} 83 80 B R 6 5 4 3 2 1 7 0 | 0 | 0 | 0 | Txct4 | Txcta | Txc2 | Txct1 | Txco | Bits 7-5 Unused Bits 4-0 Transmit data count. If the Transmit channel is interrupt driven, a non-zero value is a request for data. These bits give the number of spaces available in the Transmit FIFO. Transmit Data Register {TDR} F8 F8 B WwW 7 6 5 4 3 2 1 0 { 07 | D | DS | D4 D3 | De { D1 DO | This register accesses the transmit data FIFO of a channel interrupting for transmit data transfer. This register address is used for all channels to transfer transmit FIFO data to the host, if programmed in Interrupt Transfer Mode. Data must be written as bytes, and follows the rules of Section 5.4 for positioning valid data on the bus. If the BYTESWAP Pin is high, data must be valid on A/D[0:7]; if BYTESWAP is low, data must be valid on A/D[8:15], because the TDR is on an even address. Transmit End Of Interrupt Register The Transmit End Of Interrupt Register must be written to by the corresponding host interrupt service routine to signal to the CL-CD2400 that the current interrupt service is concluded. This must be the last access to the CL-CD2400 during an interrupt service routine. Writing to this register will generate an internal End of Interrupt signal which pops the CL-CD2400 interrupt context stack. Depending on the circumstances of an individual interrupt service, the host may be required to pass a parameter to the CL-CD2400 through these registers. August 1993 _eseeeemnem a wan Detailed Reg... 113MB 2156639 OO0Ob2eb? 4b? MCIR CL-CD2400/2401 == = CIRRU. S LOGIC Multi-Protocol Controller Transmit End Of Interrupt Register {TEOIR} 86 85 B Ww 7 6 5 4 3 2 1 0 | TermButf] EOF SetTm2 | SetTm1 | Nontransf| 0 | 0 | 0 | Bit 7 1 = Terminate buffer in DMA Mode forces the current buffer to be discarded. Note: If current interrupt is a transmit end-of-buffer interrupt, setting this bit at the end of the service routine will cause the next buffer to be terminated also. Bit 6 End of Frame in synchronous modes using interrupt-driven data transfer. O = this data transfer does not complete the frame/block. 1 = this data transfer does complete the frame/biock. Bit 5 Set general timer 2 in synchronous modes. 0 = do not set general timer 2. 1 = load the value, provided in TISR, to general timer 2. Bit 4 Set general timer 1 in synchronous modes. 0 = do not set general timer 1. 1 = load the value, provided in TISR, to the high byte of general timer 1. At the end of an interrupt service routine, the user may set a timer by setting a timer value in the Transmit Interrupt Status Register. When the timer reaches 0, CL-CD2400 will generate a modem/timer group interrupt to the host. Bit 3 No transfer of data. This bit must be set by the host, if no data is transferred to the transmit FIFO during a data transfer interrupt. Bits 2-0 Reserved must be zero. 114 Detailed Reg... - August 1993Mf 2136639 OOObebs 373 MCIR CL-CD2400/2401 S Multi-Protocol Controller CIRRUS LOGIC 6.5.3 Modem/Timer Interrupt Registers Modem Priority Interrupt Level Register {MPILR} &1 E3 B R/wW This register must be initialized by the host to contain the codes that will be presented on the address bus by the host system to indicate which of the three CL-CD2400 interrupt types (i.e., modem, transmit. or receive) is being acknowledged when IACKIN* is asserted. The CL-CD2400 compares bits 0-6 in this register with A[0-6] to determine if the acknowledge tevel is correct. The value programmed in the MSB of the register has no effect on the IACK cycle. MPILR must contain the code used to acknowledge modem/timer interrupts. NOTE: Bit 7 of this register is always read back as '0'. When each of the three Priority Interrupt Level Registers is programmed with the same value, they are internally prioritized, with receive as the highest priority, followed by transmit and modem. Modem Interrupt Register {MIR} ED EF B R 7 6 5 4 3 2 1 0 | Men | Mact | Meci | 0 | Mvet [1] | Mvect [0} | Men [1} | Men {o] | Bit 7 Men Modem enable is set by the CL-CD2400 to initiate a modem interrupt request sequence. it is cleared during a valid modem interrupt acknowledge cycle. Bit 6 Mact Modem active is set automatically when Men is set, and the Fair Share logic allows the assertion of a modem interrupt request. It is cleared when the host CPU writes to the Modem End of Interrupt Register. Bit 5 Meoi Modem end of interrupt is set automatically when the host CPU writes to the Modem End of Interrupt Register while in a modem interrupt routine. Men Mact Meoij Sequence of Events 0 0 0 Idle J 0 0 Modem interrupt requested, but not asserted 1 1 0 Modem interrupt is asserted 0 1 0 Modem interrupt is acknowledged 0 0 1 Modem interrupt service routine is completed Bit 4 Unused Bits 3-2 Mvct [0:1] Modem vector bits are set by the CL-CD2400 to provide the lower two bits of the vector supplied to the host CPU during an interrupt acknowledge cycle. Modem vector is decoded as follows: Mvet [1] = 0,and Mvct [0] = 1. Bits 1-0 Mcn [0:1] Modem channel number is set by the CL-CD2400 to indicate the channel requiring modem interrupt service. August 1993 ees [2 ta || (i Reg... 115M 2136639 0006269 23T MCIR eS CL-CD2400/2401 = = CIRRUS LOGIC Multi-Protocoal Controller Modem (/Timer) Interrupt Status {MISR} 88 8B B RW Register 7 6 5 4 3 2 1 0 [ osrctg | cpchg | ctschgf 0 [ 0 | 0 | Timer2 } Timert | When the host receives a modem interrupt, the following status is provided in this register: Bit 7 DSR Changed. A logic '1' indicates that a change has been detected on the DSR* input. The change detect is programmed in COR4 and CORS. Bit 6 CD Changed. A logic '1' indicates that a change has been detected on the CD input. The change detect is programmed in COR4 and CORS. Bit 5 CTS Changed. A logic '1' indicates that a change has been detected on the CTS input. The change detect is programmed in COR4 and CORS. Bit 1 General Timer 2 timed out (count reaches zero before being reset or disabled). Bit 0 General Timer 1 timed out (count reaches zero before being reset or disabled). During an interrupt service routine, the host may use this register to provide a timer value as detailed in the Modem End of Interrupt Register. The host can only load one of the two timers in each interrupt service routine. Modem End Of interrupt Register {MEOIR} 85 86 B Ww 7 6 5 4 3 2 1 0 [| o | 0 [Ssettme [settm[ o [| 0 | o | o | Bits 7, 6 Reserved must be zero. Bit 5 Set general timer 2 in synchronous modes. 0 = do not set general timer 2. 1 = load the value, provided in MISR, to general timer 2. Bit 4 Set general timer 1 in synchronous modes. 0 = do not set general timer 1. 1 = load the value, provided in MISR, to the high byte of general timer 1. At the end of an interrupt service routine, the user may set the timer by setting a timer value in the Modem Interrupt Status Register. When the timer reaches 0, CL-CD2400 will generate a modem/timer group interrupt to the host. Bits 3-0 Reserved must be zero. 116 Detailed Reg... August 1993MW 2136639 0006270 TS] MECIR CL-CD2400/2401 SSS Multi-Protocol Controller === CIRRUS LOGIC 6.6 DMA Registers DMA Mode Register (Write Only) {DMR} F4 F6 B Ww 7 6 5 4 3 2 1 a This register is write only. No misoperation will occur if the register is read, but the read value will not be consistent. Bits 7-4 Reserved must be zero. Bit 3 Byte DMA 0 = The CL-CD2400 will attempt to perform 16-bit data transfers whenever possible, and 8-bit only when necessary (when only one byte is available or odd address boundaries). 1 = The CL-CD2400 will always perform 8-bit DMA transfers, the position of the data on the bus will still follow the normal rules relating to the BYTESWAP Pin. Bits 2-0 Reserved must be zero. Bus Error Retry Count {BERCNT} 8D 8E B RW 7 6 5 4 3 2 1 0 | Binary Value | When this register is programmed to zero, any bus error causes a receive/transmit interrupt to be generated and DMA Operations suspended to the buffer in error, until the interrupt is processed by the host CPU. When this register contains a non-zero value and when a bus error occurs, the CL-CD2400 will retry the same DMA Operation and decrement the register value by one. When the value reaches zero, the next bus error will cause an interrupt, at which time a new count may be loaded by the host CPU. August 1993 meee, 1tailed Reg... 117ME 2136639 0006271 994 MBCIR EEeESEes CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocol Controller DMA Buffer Status {DMABSTS} 1A 19 B R Z 6 5 4 3 2 1 0 | TDAtign | RstApd | crteut | Append | NtBuf | Tbusy | Nrbuf | Rousy When CL-CD2400 requires an external buffer for DMA transfer, it checks Ntbuf/Nrbuf Bits to decide which buffer to use. Once CL-C02400 starts using the buffer, it toggles Ntbuf/Nrbuf Bits, and sets Tbusy/Rbusy Bits. Ntbuf and Nrbuf are set to Buffer A at system initialization. Bit 7 This status bit is used internally to manage data alignment in the transmit FIFO. Bit 6 Reset Append Mode is set after the terminate append buffer command in STCR has been recognized, and is cleared after the remaining data has been flushed from the buffer. Bit 5 Current transmit buffer is used internally to mark the actual buffer in use. Bit 4 Append (Only Buffer A can be used as an append buffer) Transmit append buffer usage indicator 0 = Append buffer is not in use. 1 = Append buffer is in use. Bit 3 Ntbuf Next transmit buffer 0 = Buffer A is the next transmit buffer 1 = Buffer B is the next transmit buffer This bit is toggled when transmission is started from a buffer, i.e., when data is first read from Buffer A, the bit is set to indicate that Buffer B is next. Bit 2 Tbusy Current transmit buffer is in use? 0 = No buffer is in use. 1 = Current transmit buffer is in use. Bit 1 Nrbuf Next receive buffer O = Buffer A is the next receive buffer 1 = Buffer B is the next receive buffer This bit is toggled when receive data is first written to a buffer, i.e., when data is first written to Buffer A, the bit is set to indicate Buffer B is next. Bit 0 Rbusy Current receive buffer is in use? 0 = No buffer is in use. 1 = Current receive buffer is in use. 118 Detailed Reg... August 1993= ~ MM 2136639 0004272 824 MMCIR CL-CD2400/2401 Multi-Protocol Controller = ===" CIRRUS LOGIC 6.6.1 DMA Receive Registers A Receive Buffer Address Lower {ARBADRL} 40 42 Ww RW A Receive Buffer Address Upper {ARBADRU} 42 40 Ww RAW B Receive Buffer Address Lower {BRBADRL} 44 46 Ww RW B Receive Buffer Address Upper {BRBADRU} 46 44 Ww R/W Receive Buffer Address Registers A and B (32-Bit) These registers contain the start addresses of two external buffers which will be used by the CL-CD2400 to store the next two receive data blocks. They are written to by the host and copied internally to control the data transfer to the memory. A Receive Buffer Byte Count {ARBCNT} 48 4A WwW RAW B Receive Buffer Byte Count {BRBCNT} 4A 48 W RAW These registers contain the number of bytes stored in the external data buffers by the CL-CD2400. The count is updated after a block of data is moved to memory and the buffer is terminated. As initially written by the host, the register contains the number of bytes which the buffer can hold. A Receive Buffer Status {ARBSTS} 4C 4F B RAW B Receive Buffer Status {BRBSTS} 4D 4E B RAW 7 6 5 4 3 2 1 0 {| Ber | EOF { -oB [| o fo [| 0 } 0 [24000wn | These registers contain the current status of associated receive buffers and enable the buffers to be passed between the host and CL-CD2400. Status bits are defined as: Bit 7 Bus error (set by the CL-CD2400 and Cleared by the host CPU) 0 = no bus error 1 = bus error occurred on the last transfer; the suspect address is available in RCBADR Bit 6 End of frame (set by the CL-CD2400 and cleared by the host CPU) 0 = this buffer does not terminate a frame 1 = this buffer terminates a frame Bit 5 Buffer complete (set by the CL-CD2400 and cleared by the host CPU) O = buffer not complete 1 = buffer complete Bits 4-1 Reserved must be zero. Bit 0 Ownership of the transfer buffer (set by the host CPU and cleared by the CL-CD2400) 0 = buffer not free to be used by CL-CD2400 1 = buffer free to be used by CL-CD2400 When the buffer completed bit is set by the CL-CD2400, the buffer is free for the host to process (RBCNT information is updated to the number of bytes available in the buffer, and a new buffer can be allocated). August 1993 EE aeTEnSe Detailed Reg... 119MP 2136639 0006273 760 MCIR ein EE CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocol Controller Receive Current Buffer Address Lower {RCBADRL} 3C 3E W R Receive Current Buffer Address Upper {RCBADRU} 3E 3C WwW R Contains the address of the current DMA buffer being used for receive data. Updated at the end of receive data transfers. This register is for the private use of the CL-CD2400 in managing DMA transfers. In Asynchronous Mode, the host may read this register during a Receive Exception Interrupt to determine how much data is in the buffer. The address is the location of the next character to be transferred to the buffer. The host will need that information to process newly arrived data in the buffer if it is being used in the Append Mode, and the data timeout has occurred. It is also needed if an exception has occurred, and a gap is to be left in the FIFO for the insertion of status information by the host. In the case of a bus error during receive data transfer, this register provides the start address of the transfer causing the bus error. 6.6.2 DMA Transmit Registers A Transmit Buffer Address Lower {ATBADRL} 50 52 WwW RAW A Transmit Buffer Address Upper {ATBADRU} 52 50 WwW RAV B Transmit Buffer Address Lower {BTBADRL} 54 56 Ww R/AW B Transmit Buffer Address Upper {BTBADRU} 56 54 WwW RWW Transmit Buffer Address Registers A and B (32-Bit) These registers contain the start addresses of two external buffers which will be used by the CL- CD2400 to transmit the next data blocks. They are written to by the host and copied internally to control the data transfer from the memory to the CL-CD2400 FIFO. A Transmit Buffer Byte Count {ATBCNT} 58 5A WwW RW B Transmit Buffer Byte Count {BTBCNT} 5A 58 Ww RAW These registers contain the count of bytes in the buffers to be transmitted. 120 Detailed Reg... aneneusmmsssssssssnnsnnnnRn SSS August 1993ME 2136639 000b274 &T? MECIR CL-CD2400/2401 Multi-Protocol Controller ==="CIRRUS LOGIC A Transmit Buffer Status {ATBSTS} 5C 5F B RAW B Transmit Buffer Status {BTBSTS} 5D 5E B RW 7 6 5 4 3 2 1 0 | Berr | EOF | EOB 0 | Append | 0 | INTR [24000wn | This register contains the status of the associated transmit buffer, and enables successive buffers to be passed between the host and CL-CD2400. Status bits within the register are defined as: Bit 7 Bus error (set by the CL-C02400 and cleared by the host CPU) 0 = no bus error 1 = bus error occurred on the !ast transfer; the suspect address is available in TCBADR Bit 6 End of Frame (set and cleared by host CPU) O = this buffer is not the last in frame/block 1 = this buffer is the last in frame/block BitS The End Of a Transmit Buffer has been reached. Used only for DMA supported transfer. The end of one of the host supplied transmit buffers has been reached. This bit is set by the CL-CD2400 and cleared by the host CPU. Bit 4 Reserved must be zero. Bit 3 Append (Asynchronous Mode; set and cleared by the host CPU) 0 = no data will be appended to the buffer 1 = data may be appended to buffer after tx started Bit 2 Reserved must be zero. Bit 1 Interrupt 0 = no interrupt required after the buffer is sent 1 = interrupt required after the buffer is sent Bit 0 Ownership of the transfer buffer (set by the host CPU and cleared by the CL-CD2400) 0 = buffer not ready to be used by CL-CD2400 1 = buffer is ready for CL-CD2400 to transmit To start transmission of a buffer, the host must set the Transmit Buffer Address (ATBADR/BTBADR) and Transmit Buffer Count (ATBCNT/BTBCNT) Registers, and then set the 24000WN Bit. If the CL- CD2400 is to generate and send the CRC for the frame, the CRC Bit in COR1 must be set. If the buffer contains the end of a frame, the EOF Bit must also be set. When the buffer has been sent, the EOB Bit will be set by the CL-CD2400, and 24000WN will be reset, allowing a new buffer to be allocated. Setting the Append Bit allows data to be added to the buffer after transmission has begun. In this mode, the host sets ATADR and ATCNT as normal, but when new data is appended to the buffer, the Transmit Buffer Count (ATBCNT/BTBCNT) can be updated. When the A buffer is used in Append Mode, the CL-CD2400 will not set the EOB Bit. When the host has completed use of the buffer, it must issue the Append Complete command through STCR. The CL-CD2400, upon transmitting the last characters from the buffer, will set EOB, thus allowing the host to allocate a new transmit buffer. August 1993 a wmaman Detailed Reg... 121MB 2156639 0006275 533 MCIR rr ESS CL-CD2400/2401 _ = CIRRUS LOGIC Multi-Protocol Controller Transmit Current Buffer Address Lower {TCBADRL} 38 3A W R Transmit Current Buffer Address Upper {TCBADRU} 3A 38 Ww R Contains the address into the current DMA buffer being used for transmit data. Updated at the end of transmit data transfers. In the case of a bus error during transmit data transfer, this register contains the start address of the transfer causing the bus error. 6.7 Timer Registers Timer Period Register {TPR} D8 DA B RAW 7 6 5 4 3 2 1 0 | Binary Value | This register provides the initialization value for the timer prescaler which is itself clocked by a prescaled clock equal to system clock/2048. The timer prescaler establishes the clock for the various on-chip timers (including RTPR, TTR and the general timers available to the host in the synchronous modes). The minimum value loaded in this register to maintain accuracy in the timer is 0A hex. Receive Timeout Period Register {RTPR} 26 24 WwW R/W Async Receive Timeout Period Register Low {RTPR} 26 25 B R/W Async Receive Timeout Period Register High {RTPRh} 27 24 B R/W Asynec Receive Timeout Period Register (16-bits) This value sets the receive data timeout period. As each character is moved to the receive FIFO or the last data is transferred from the FIFO to the host, the Receive Timer (an internal timer) is reloaded with the Receive Timeout Period Register. The Receive Timer is decremented on each tick of the prescaler counter, whose period is controlled by TPR. If the Receive Timer reaches zero, it will cause a receive data interrupt. 122 Detailed Reg... m August 1993MH 2436639 OOOb27b 47T MMCIR CL-CD2400/2401 a Multi-Protocol Controller = CIRRUS LOGIC General Timer 1 {GT1} 28 2A W R Sync General Timer 1 Low {GTI} 28 2B B R Sync General Timer 1 High {GT1h} 29 2A B R Sync General Timer 14 This 16-bit timer may be started by the user whenever it is inactive by writing a 16-bit timeout value to the register. When non-zero, it is decremented on each prescaler clock 'tick.'. When it reaches zero, a Modem/Timer group interrupt is generated to the host. The timer may be disabled by Channel Command Register command. in addition, during a Receive or Transmit interrupt, the user may reload a running timer (high byte only) by providing a reload value in the Interrupt Status Register and a reload timer command in the End of Interrupt Register for the interrupt being serviced. Only one general timer may be restarted this way in a single-interrupt routine. General Timer 2 {GT2} 2A 29 B R Sync General Timer 2 This 8-bit timer may be started by the user whenever it is inactive by writing an 8-bit timeout value to the timer register. When non-zero, it is decremented on each prescaler clock tick... When it reaches zero, a Modem/Timer group interrupt is generated to the host. The timer may be disabled by Channel Command Register command if the timer's current value is greater than 1. In addition, during a Receive or Transmit interrupt, the user may reload a running timer by providing a reload value in the Interrupt Status Register and a reload timer command in the End of Interrupt Register for the interrupt being serviced. Only one general timer may be restarted this way in a single-interrupt routine. Transmit Timer Register {TTR} 2A 29 B R Async Transmit Timer Register This asynchronous mode timer is managed by the CL-CD2400 to implement embedded transmit delays when that option is used by the host (see description of Channel Option Register 2). August 1993 nN Detailed Reg... 123MB 2136639 OO0b277 306 @ECIR CL-CD2400/2401 enee ei: =" CIRRUS LOGIC 7. ELECTRICAL SPECIFICATIONS 7.1 Absolute Maximum Ratings Operating ambient temperature .........scsssccsssscccsssssssssecssseeeeccosssec. 0C to 70C Storage temperature sateen wn se 65C to 150C All voltages with respect to GroUNd.......cccssssessssssssececscssssessecsseccce -0.5 to Vee +0.5 Volts Supply voitage (Vcc) ... teeaaes we .... +7.0 Volts Power dissipation...... sess seseavevesaneaneecesneseavanssesesseeasane 0.25 Watt NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions above those indicated in the Operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Before beginning any new design with this device, please contact Cirrus Logie, inc., for the latest errata information. See the back cover of this document for sales office locations and phone numbers. This data book applies to CL-CD2400/CD2401 Revision | or later devices. 7.2 DC Electrical Characteristics (@ Vee = 5V 5%, TA = 0C to 70C) Symbol Parameter MIN MAX Units Test Conditions VIL input Low Voltage -0.5 0.8 V ViH Input High Voitage (ALL PINS*) 2.0 Vee Vv VOL Output Low Voltage 0.4 Vv lOL = 2.4mA VOH Output High Voltage 2.4 Vv IOH = -400 pA Nie Input Leakage Current -10 10 pA 0 < Vin < Voc ILL Data Bus 3-state Leakage Current -10 10 pA 0 < Vout < Voc loc Open-Drain Output Leakage -10 10 pA 0 < Vout <Voe Icc Power Supply Current 50 mA CLK = 20 MHz Cin Input Capacitance 10 pF Cout Output Capacitance 10 pF * Except: VIH Input High Voltage for 2.7 Vec Vv CLK, RESET* and BGIN* 124 Electrical Specs smusummesumue August 1993CL-CD2400/2401 ESS re OO . ie EE Multi Protocol Controter Ss" CIRRUS LOGIC 7.3 AC Electrical Characteristics CL-CD2400 Timing Parameters Parameter MIN MAX Parameter MIN MAX ty CLK high to BUSCLK high 35 tg CLK high to BUSCLK low 35 Host Read/Write t4; DS" and CS* iow setup to CLK high 7 tag Reserved Bus Arbitration t4g Reserved t11 CLK high to BGACK* tristate 30 t44 RM" setup to CLK high 0 tia BGIN* low to address valid 4 60 tas CLK high to data valid 70 tia Address hold after CLK high o t4g Data setup time to CLK high 5 t14 CLK high to address tristate 35 t47 Data hold time after CLK high 25 tis CLK high to ADLD* low 35 tag Address setup time to CLK high 5 tyg CLK high to ADLD* high 35 tag Address hold time after CLK high 30 {47 Address setup to ADLD* high 15 tsq CLK high to DTACK* low (read cycle) 35 tig CLK high to AEN*/DATEN*/ 40 ts, CLK high to DTACK low 35 DATDIR* high (write cycle) tig CLK high to AEN*/DATEN*/ 40 t52 (CS* and DS") low to 40 DATDIR* tristate DATEN*/DATDIR low t29 CLK high to AEN*/DATEN*/ 40 tsg3 DS* high ta DATEN*/DATDIR* tristata 35 DATDIR* low ts4 DS" high to data bus tristate 35 tss DS* high to DTACK* high impedance 35 DMA Read t21 Data setup to CLK high 20 Interrupt Acknowledge toa Data hold after CLK high 30 te1 CLK high to IACKIN*, DS* setup 50 tag CLK high to address valid 60 t63 CLK high to Data valid 70 ta4 CLK low to AS* low 35 te4 Address setup to IACKIN* low 10 te5 CLK high to AS" high 35 te5 Address hold after IACKIN high 0 tag CLK low to DS* low 35 tgg CLK high to DTACK* low 40 to7 CLK high to DS* high 35 tg7 (IACKIN and DS*) low and BUSCLK 70 tog DTACK* low setup to CLK high 10 high to DATEN and DATDIR* low tag DTACK" high setup to GLK high 50 (to avoid false termination) DMA Write tg, CLK high to data valid 70 tga Data hold after CLK high 5 t33 CLK low to DS* low 35 tg4 CLK high to DS* high 35 tg5 DTACK* low setup to CLK high 10 tgg DTACK* high setup to CLK high 50 (to avoid false termination) M@@ 2136639 O00b278 242 MECIR el (1) This timing assumes the following conditions BGACK* high, DTACK* high, DS* high, BUSCLK high. AUZUSt 1993 _t nes FIC CHC al Specs 125MH 2136639 0006279 1489 MECIR a CL-CD2400/2401 S22 CIRRUS LOGIC Multi-Protocol Controller BUSCLK os.cs : 3 2 { RW" / P! tug <t e! tug no C= A0[0:15] _ <P dE} DTACK* <7! _____ r! te ~ > tsg DATENS. a /DATDIR* Figure 7-0. Slave Read Cycle Timing 126 Electrical Specs ST August 1993MB 21356539 0006280 4To9 MECIR CL-CD2400/2401 Multi-Protocol Controller _ S= CIRRUS LOGIC i a tay <_< DS*, CS* \ | j wii | Pi tus 3 >} ta7 << wits ee | AID{O:15] f + ty Pri losin DTACK* a >: tse 't53 <a DATENS { Figure 7-1. Slave Write Cycle Timing August 1993 Electrical Specs 127Mi 2136639 0006281 437 MCIR ee CL-CD2400/2401 SS CIRRUS LOGIC Multi-Protocol Controller BUSCLK NL ff > ter <_ IACKIN RAW" ; f Serlot ie A/D [0:15] 7 a DTACK* ; i e! te =< e} t53 DATEN', __ a DATDIR* Figure 7-2. Interrupt Acknowledge Cycle Timing 128 Electrical Specs on August 1993CL-CD2400/2401 Multi-Protocol Controller CLK BUSCLK BR* BGIN* ADLD* A(0:7) A/D[0:15] AS AEN*/DATEN*/ DATDIR* BGACK* RW August 1993 MB 2136639 0006282 773 EECIR SS" CIRRUS LOGIC A8:15] i Xf A(0:7] A[16:31] Y NOTE e! 24 g o!t20 Qo $C NOTE: In DMA Read Cycle, three pins will be three-stated in DMA Write Cycle, three pins will be D[0:15] Bus Arbitration Cycle Timing Electrical Specs 129MB 2136635 0006243 LOT MICIR CL-CD2400/2401 Multi-Protocal Controller BUSCLK == CIRRUS LOGIC AS*, Ds* ; er! thy Nere A(0:7] A/D[0:15] i} BGACK* DATEN*, AEN*, DATDIR* Bus Release Timing Figure 7-4. a | August 1993 130 Electrical SpecsMB 21356639 0006244 Sub MCIR CL-CD2400/2401 Multi-Protocel Controller Ss" CIRRUS LOGIC ) a! toa + : e! tas << AS*, ON i of \ ; we! tog i e! be i bg ee SS} toy < : AD(0:15} <p }___ P tog i<| : Ph tg at DTACK* ye Figure 7-5. DMA Read Cycle Timing August 1993) _- mens 8 Electrical Specs 131MM 2136639 0006245 482 MECIR CL-CD2400/2401 === CIRRUS LOGIC Multi-Protocol Controller CLK BUSCLK AS", DS* >! tog << A0-7 : X : | Xx pe! tay i i i it AD0:15} 3 a ment ts6 ; : _-: tgs _-_ DTACK* ff Figure 7-6. DMA Write Cycle Timing 132 Electrical Specs ene August 1993MB 2136639 O00b28b 319 MCIR CL-CD2400/2401 SS ===> CIRRUS LOGIC | t See Detail 4 * 0.013 0.021 Cro OF Cy Ly Y YO TT CT ar 0.026 | r 0, ~<_- 0032 0.050 0.013 0.026 0.018 ~ 0.032 DIMENSION MIN MAX A 0.165 0.200 Al 0.090 0.130 Detail A A D 1.185 1.195 NS 0.025 Dt 1.150 1.188 0.045 D2 1.090 1.130 03 1.000 REF E 1.185 1.195 EI 4.150 1.158 E2 1.090 1.130 ES 1.000 REF >| I~ 0.020 MIN r 9.0077 _| 0.0103 Base Plane Seating Plane NOTES: 1) 2) 3} 4) 5) 8} 7% Refer to JEDEC Publication 95, 1993 for symbal descriptions. All dimensions are in inches, and controlling dimension is inch. D1 and Et do not include mold flash, which is 0.010 inch maximum. D2/E2 will be determined at the seating plane. Copper lead frame and lead finish will be solder plate or matte tin plate. Formed leads shall be planar within 0.004 inch with respect to one another. The top half of the package above the lead frame may be smaller than the bottom half of the package by a maximum of 0.010 inch. Figure 8-0. CL-CD2400 (84-Pin PLCC) Sample Package March 1992 ens SAmpie Pkos. 133MB 2136639 O00b287 255 MECIR SESS CL-CD2400/2401 2 CIRRUS LOGIC Multi-Protocol Controller 8. SAMPLE PACKAGES (cont) 23.20 (0.913) 13.90 (0.54 14/10 (0.555. CL-CD2401 100-Pin EIAJ PQFP po 17.40 (0.685) @ Pin 1 indicator = 48.20 (0.717) 4 Pin 100 cog = TOON UOT MINTHHOUCWPAOHGOHEeOeU dog bod oad NMOOOORDBEBGAODODORAODOGADTGTOWVGKBDUdGdRBGCAUHAAaO 0.10 {o00% t r f 0 MIN ms t t I 4 10 MAX 0.05 (0.002) 2.62 (0.103 337 (0-133 0.05 (0.020) NOTES: Dimensions are in millimeters and parenthetically in inches. Figure 8-1. CL-CD2401 (100-Pin ElIAJ QFP) Sample Package NOTE: Dimensions for the QFP package are in inches. 134 Sample Pkgs. sss " _ August 1993MH 2136639 0006288 191 mMCIR CL-CD2400/2401 ) Multi-Protocol Controller ===" CIRRUS LOGIC sg. ORDERING INFORMATION CL-CD2400-10PC | CL-CD2401 - 10QC - 1 Cirrus Lagic, Inc. | | L L Revision t Product Line: Temperature Range: 0- 70C (Communications, Data) C = Commercial Part Number Package Type: P = Plastic Leaded Chip Carrier (PLCC) Q = Plastic Quad Flat Package (EIAJ PQFP) Internal Reference Number Tt Contact Cirrus Logic, Inc., for up-to-date information on revisions. August 1993 ms | Order Info. 135