1
LT3027
3027fa
V
OUT
100µV/DIV 20µV
RMS
3027 TA01b
APPLICATIO S
U
DESCRIPTIO
U
FEATURES
TYPICAL APPLICATIO
U
Dual 100mA,
Low Dropout, Low Noise,
Micropower Regulator with
Independent Inputs
■
Low Noise: 20µV
RMS
(10Hz to 100kHz)
■
Low Quiescent Current: 25µA/Channel
■
Independent Inputs
■
Wide Input Voltage Range: 1.8V to 20V
■
Output Current: 100mA/Channel
■
Very Low Shutdown Current: <0.1
µ
A
■
Low Dropout Voltage: 300mV at 100mA
■
Adjustable Output from 1.22V to 20V
■
Stable with 1µF Output Capacitor
■
Stable with Aluminum, Tantalum or
Ceramic Capacitors
■
Reverse Battery Protected
■
No Protection Diodes Needed
■
Overcurrent and Overtemperature Protected
■
Tracking/Sequencing Capability
■
Thermally Enhanced 10-Lead MSOP and DFN
Packages
The LT
®
3027 is a dual, micropower, low noise, low drop-
out regulator with independent inputs. With an external
0.01µF bypass capacitor, output noise is a low 20µV
RMS
over a 10Hz to 100kHz bandwidth. Designed for use in
battery-powered systems, the low 25µA quiescent current
per channel makes it an ideal choice. In shutdown, quies-
cent current drops to less than 0.1µA. Shutdown control
is independent for each channel, allowing for flexibility in
power management. The device is capable of operating
over an input voltage from 1.8V to 20V, and can supply
100mA of output current from each channel with a drop-
out voltage of 300mV. Quiescent current is well controlled
in dropout.
The LT3027 regulator is stable with output capacitors as
low as 1µF. Small ceramic capacitors can be used without
the series resistance required by other regulators.
Internal protection circuitry includes reverse battery pro-
tection, current limiting and thermal limiting protection.
The device is available as an adjustable device with a
1.22V reference voltage. The LT3027 regulator is available
in the thermally enhanced 10-lead MSOP and low profile
(0.75mm) 3mm × 3mm DFN packages.
10Hz to 100kHz Output Noise
3.3V/2.5V Low Noise Regulators
■
Cellular Phones
■
Pagers
■
Battery-Powered Systems
■
Frequency Synthesizers
■
Wireless Modems
■
Tracking/Sequencing Power Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
IN1
0.01µF
0.01µF
10µF
3027 TA01
OUT1
V
IN1
3.7V TO
20V BYP1
ADJ1
OUT2
BYP2
ADJ2
GND
LT3027
3.3V AT 100mA
20µV
RMS
NOISE
2.5V AT 100mA
20µV
RMS
NOISE
1µFSHDN1
IN2
V
IN2
2.9V TO
20V
1µFSHDN2 10µF
422k
249k
261k
249k
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6118263, 6144250.
2
LT3027
3027fa
(Note 1)
IN1, IN2 Pin Voltage .............................................. ±20V
OUT1, OUT2 Pin Voltage ....................................... ±20V
Input to Output Differential Voltage ....................... ±20V
ADJ1, ADJ2 Pin Voltage ......................................... ±7V
BYP1, BYP2 Pin Voltage ....................................... ±0.6V
SHDN1, SHDN2 Pin Voltage ................................. ±20V
Output Short-Circut Duration.......................... Indefinite
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage I
LOAD
= 100mA ●1.8 2.3 V
(Notes 3, 10)
ADJ1, ADJ2 Pin Voltage V
IN
= 2V, I
LOAD
= 1mA 1.205 1.220 1.235 V
(Note 3, 4) 2.3V < V
IN
< 20V, 1mA < I
LOAD
< 100mA ●1.190 1.220 1.250 V
Line Regulation (Note 3) ∆V
IN
= 2V to 20V, I
LOAD
= 1mA ●110 mV
Load Regulation (Note 3) V
IN
= 2.3V, ∆I
LOAD
= 1mA to 100mA 1 12 mV
V
IN
= 2.3V, ∆I
LOAD
= 1mA to 100mA ●25 mV
Dropout Voltage I
LOAD
= 1mA 0.10 0.15 V
V
IN
= V
OUT(NOMINAL)
I
LOAD
= 1mA ●0.19 V
(Notes 5, 6, 10) I
LOAD
= 10mA 0.17 0.22 V
I
LOAD
= 10mA ●0.29 V
I
LOAD
= 50mA 0.24 0.28 V
I
LOAD
= 50mA ●0.38 V
I
LOAD
= 100mA 0.30 0.35 V
I
LOAD
= 100mA ●0.45 V
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 2)
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
ELECTRICAL CHARACTERISTICS
LT3027EDD
LT3027IDD
ORDER PART
NUMBER
DD PART
MARKING
Operating Junction Temperature Range
(Note 2) ............................................ – 40°C to 125°C
Storage Temperature Range
DD Package ...................................... – 65°C to 125°C
MSE Package ................................... – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
10
9
6
7
8
4
5
3
2
1OUT2
IN2
IN1
SHDN1
OUT1
BYP2
ADJ2
SHDN2
ADJ1
BYP1
11
1
2
3
4
5
BYP2
ADJ2
SHDN2
ADJ1
BYP1
10
9
8
7
6
OUT2
IN2
IN1
SHDN1
OUT1
TOP VIEW
MSE PACKAGE
10-LEAD PLASTIC MSOP
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
11
LT3027EMSE
LT3027IMSE
ORDER PART
NUMBER
MSE PART
MARKING
T
JMAX
= 125°C, θ
JA
= 43°C/ W, θ
JC
= 3°C/ W
T
JMAX
= 150°C, θ
JA
= 40°C/ W, θ
JC
= 10°C/ W
LBKM
LBMC
LTBKK
LTBMD
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3
LT3027
3027fa
PARAMETER CONDITIONS MIN TYP MAX UNITS
GND Pin Current (Per Channel) I
LOAD
= 0mA ●25 50 µA
V
IN
= V
OUT(NOMINAL)
I
LOAD
= 1mA ●60 120 µA
(Notes 5, 7) I
LOAD
= 10mA ●250 400 µA
I
LOAD
= 50mA ●12 mA
I
LOAD
= 100mA ●2.4 4 mA
Output Voltage Noise C
OUT
= 10µF, C
BYP
= 0.01µF, I
LOAD
= 100mA, BW = 10Hz to 100kHz 20 µV
RMS
ADJ1/ADJ2 Pin Bias Current (Notes 3, 8) 30 100 nA
Shutdown Threshold V
OUT
= Off to On ●0.8 1.4 V
V
OUT
= On to Off ●0.25 0.65 V
SHDN1/SHDN2 Pin Current V
SHDN
= 0V ●0 0.5 µA
(Note 9) V
SHDN
= 20V ●13 µA
Quiescent Current in Shutdown V
IN
= 6V, V
SHDN
= 0V (Both SHDN Pins) 0.01 0.1 µA
Ripple Rejection (Note 3) V
IN
= 2.72V (Avg), V
RIPPLE
= 0.5V
P-P
, f
RIPPLE
= 120Hz, 55 65 dB
I
LOAD
= 100mA
Current Limit V
IN
= 7V, V
OUT
= 0V 200 mA
V
IN
= 2.3V, ∆V
OUT
= – 5% ●110 mA
Input Reverse Leakage Current V
IN
= – 20V, V
OUT
= 0V ●1mA
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 2)
ELECTRICAL CHARACTERISTICS
Note 5: To satisfy requirements for minimum input voltage, the LT3027 is
tested and specified for these conditions with an external resistor divider
(two 250k resistors) for an output voltage of 2.44V. The external resistor
divider will add a 5µA DC load on the output.
Note 6: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
output voltage will be equal to: V
IN
– V
DROPOUT
.
Note 7: GND pin current is tested with V
IN
= 2.44V and a current source
load. This means the device is tested while operating in its dropout region
or at the minimum input voltage specification. This is the worst-case GND
pin current. The GND pin current will decrease slightly at higher input
voltages.
Note 8: ADJ1 and ADJ2 pin bias current flows into the pin.
Note 9: SHDN1 and SHDN2 pin current flows into the pin.
Note 10: For the LT3027 dropout voltage will be limited by the minimum
input voltage specification under some output voltage/load conditions. See
the curve of Minimum Input Voltage in the Typical Performance
Characteristics.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT3027 regulator is tested and specified under pulse load
conditions such that T
J
≈ T
A
. The LT3027E is guaranteed to meet
performance specifications from 0°C to 125°C junction temperature.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LT3027I is guaranteed and tested over the
full –40°C to 125°C operating junction temperature range.
Note 3: The LT3027 is tested and specified for these conditions with the
ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply for
all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
4
LT3027
3027fa
OUTPUT CURRENT (mA)
500
450
400
350
300
250
200
150
100
50
0
DROPOUT VOLTAGE (mV)
3027 G02
0 10203040 50 60 70 80 90 100
T
J
≤ 125°C
T
J
≤ 25°C
= TEST POINTS
TEMPERATURE (°C)
–50
QUIESCENT CURRENT (µA)
100
3027 G03
050
40
35
30
25
20
15
10
5
0
–25 25 75 125
V
IN
= 6V
R
L
= 250k
I
L
= 5µA
V
SHDN
= V
IN
V
SHDN
= 0V
Guaranteed Dropout Voltage
Quiescent Current
Dropout Voltage
TEMPERATURE (°C)
–50
DROPOUT VOLTAGE (mV)
050 75
3027 G03
–25 25 100 125
IL = 100mA
IL = 50mA
IL = 10mA
IL = 1mA
500
450
400
350
300
250
200
150
100
50
0
OUTPUT CURRENT (mA)
500
450
400
350
300
250
200
150
100
50
0
DROPOUT VOLTAGE (mV)
3027 G01
0 10203040 50 60 70 80 90 100
TJ = 125°C
TJ = 25°C
Typical Dropout Voltage
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INPUT VOLTAGE (V)
02 6 10 14 18
QUIESCENT CURRENT (µA)
30
25
20
15
10
5
04 8 12 16
3027 G06
20
TJ = 25°C
RL = 250k
IL = 5µA
VSHDN = VIN
VSHDN = 0V
Quiescent Current
ADJ1 or ADJ2 Pin Voltage
TEMPERATURE (°C)
–50
ADJ PIN VOLTAGE (V)
100
3027 G05
050
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
–25 25 75 125
I
L
= 1mA
INPUT VOLTAGE (V)
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
GND PIN CURRENT (mA)
3027 G07
012345678910
T
J = 25°C
*FOR VOUT = 1.22V
RL = 12.2Ω
IL = 100mA*
RL = 24.4Ω
IL = 50mA*
RL = 122Ω
IL = 10mA*
RL = 1.22k
IL = 1mA*
OUTPUT CURRENT (mA)
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
GND PIN CURRENT (mA)
3027 G08
0 10203040 50 60 70 80 90 100
V
IN
= V
OUT(NOMINAL)
+ 1V
GND Pin Current GND Pin Current vs ILOAD
TEMPERATURE (°C)
–50
SHDN PIN THRESHOLD (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0050 75
3027 G09
–25 25 100 125
I
L
= 1mA
SHDN1 or SHDN2 Pin Threshold
(On-to-Off)
5
LT3027
3027fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
SHDN1 or SHDN2 Pin Input
Current
ADJ1 or ADJ2 Pin Bias Current Current Limit
TEMPERATURE (°C)
–50
SHDN PIN INPUT CURRENT (µA)
050 75
3027 G12
–25 25 100 125
VSHDN = 20V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
TEMPERATURE (°C)
–50
ADJ PIN BIAS CURRENT (nA)
100
90
80
70
60
50
40
30
20
10
0050 75
3027 G13
–25 25 100 125
INPUT VOLTAGE (V)
0
SHORT-CIRCUIT CURRENT (mA)
245
3027 G14
1367
350
300
250
200
150
100
50
0
VOUT = 0V
TJ = 25°C
Current Limit
TEMPERATURE (°C)
–50
CURRENT LIMIT (mA)
050 75
3027 G15
–25 25 100 125
350
300
250
200
150
100
50
0
VIN = 7V
VOUT = 0V
SHDN PIN VOLTAGE (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
SHDN PIN INPUT CURRENT (µA)
3027 G11
012345678910
SHDN1 or SHDN2 Pin Input
Current
TEMPERATURE (°C)
–50
SHDN PIN THRESHOLD (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0050 75
3027 G10
–25 25 100 125
IL = 100mA
IL = 1mA
SHDN1 or SHDN2 Pin Threshold
(Off-to-On)
Input Ripple Rejection
FREQUENCY (kHz)
RIPPLE REJECTION (dB)
80
70
60
50
40
30
20
10
0
0.01 1 10 1000
3027 G18
0.1 100
I
L
= 100mA
V
IN
= 2.3V + 50mV
RMS
RIPPLE
C
BYP
= 0
C
OUT
= 10µF
C
OUT
= 1µF
Input Ripple Rejection
FREQUENCY (kHz)
RIPPLE REJECTION (dB)
80
70
60
50
40
30
20
10
0
0.01 1 10 1000
3027 G19
0.1 100
IL = 100mA
VIN = 2.3V + 50mVRMS RIPPLE
COUT = 10µF
CBYP = 0.01µF
CBYP = 1000pF
CBYP = 100pF
6
LT3027
3027fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50
RIPPLE REJECTION (dB)
100
3027 G20
050
80
70
60
50
40
30
20
10
0
–25 25 75 125
V
IN
= V
OUT (NOMINAL)
+
1V + 0.5V
P-P
RIPPLE
AT f = 120Hz
I
L
= 50mA
Input Ripple Rejection
Minimum Input Voltage
TEMPERATURE (°C)
–50
MINIMUM INPUT VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0050 75
3027 G22
–25 25 100 125
IL = 100mA
IL = 50mA
Load Regulation Output Noise Spectral Density
Output Noise Spectral Density
RMS Output Noise vs
Bypass Capacitor
50µs/DIV
C
OUT1
, C
OUT2
= 10µF
C
BYP1
, C
BYP2
= 0.01µF
∆I
L1
= 10mA to 100mA
∆I
L2
= 10mA to 100mA
V
IN
= 6V, V
OUT1
= V
OUT2
= 5V
V
OUT1
20mV/DIV
V
OUT2
20mV/DIV
3027 G21a
FREQUENCY (kHz)
CHANNEL-TO-CHANNEL ISOLATION (dB)
100
90
80
70
60
50
40
30
20
10
0
0.01 1 10 1000
3027 G21b
0.1 100
I
LOAD
= 100mA PER CHANNEL
TEMPERATURE (°C)
–50
LOAD REGULATION (mV)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
05075
3027 G23
–25 25 100 125
∆IL = 1mA TO 100mA
FREQUENCY (kHz)
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
0.01 1 10 100
3027 G24
0.1
10
1
0.1
0.01
V
OUT
SET FOR 5V
V
OUT
=V
ADJ
C
OUT
= 10µF
C
BYP
= 0
I
L
= 100mA
FREQUENCY (kHz)
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
0.01 1 10 100
3027 G25
0.1
10
1
0.1
0.01
V
OUT
SET FOR 5V
V
OUT
=V
ADJ
C
OUT
= 10µF
I
L
= 100mA
C
BYP
= 1000pF
C
BYP
= 100pF
C
BYP
= 0.01µF
C
BYP
(pF)
10
OUTPUT NOISE (µV
RMS
)
160
140
120
100
80
60
40
20
0
100 1k 10k
3027 G26
V
OUT
SET FOR 5V
V
OUT
=V
ADJ
C
OUT
= 10µF
I
L
= 100mA
f = 10Hz TO 100kHz
Channel-to-Channel Isolation
Channel-to-Channel Isolation
7
LT3027
3027fa
Transient Response
CBYP = 0
Transient Response
CBYP = 0.01µF
TYPICAL PERFOR A CE CHARACTERISTICS
UW
10Hz to 100kHz Output Noise
CBYP = 0
VOUT
100µV/DIV
10Hz to 100kHz Output Noise
CBYP = 100pF
1ms/DIV
COUT = 10µF
IL = 100mA
VOUT SET FOR 5V OUT
VOUT
100µV/DIV
1ms/DIV
COUT = 10µF
IL = 100mA
VOUT SET FOR 5V OUT
RMS Output Noise vs
Load Current (10Hz to 100kHz)
10Hz to 100kHz Output Noise
CBYP = 1000pF
VOUT
100µV/DIV
10Hz to 100kHz Output Noise
CBYP = 0.01µF
1ms/DIV
COUT = 10µF
IL = 100mA
VOUT SET FOR 5V OUT
VOUT
100µV/DIV
1ms/DIV
COUT = 10µF
IL = 100mA
VOUT SET FOR 5V OUT
TIME (µs)
0.2
0.1
0
–0.1
–0.2
OUTPUT VOLTAGE
DEVIATION (V)
100
50
0
LOAD CURRENT
(mA)
3027 G32
0 400 800 1200 1600 2000
V
IN
= 6V
C
IN
= 10µF
C
OUT
= 10µF
V
OUT
SET FOR 5V OUT
TIME (µs)
0.04
0.02
0
–0.02
–0.04
OUTPUT VOLTAGE
DEVIATION (V)
100
50
0
LOAD CURRENT
(mA)
3027 G33
0 40 60 10020 80 120 140 180160 200
VIN = 6V
CIN = 10µF
COUT = 10µF
VOUT SET FOR 5V OUT
LOAD CURRENT (mA)
0.01
OUTPUT NOISE (µV
RMS
)
160
140
120
100
80
60
40
20
0
0.1 1 10010
3027 G27
V
OUT
SET FOR 5V
V
OUT
SET FOR 5V
V
OUT
=V
ADJ
V
OUT
=V
ADJ
C
OUT
= 10µF
C
BYP
= 0µF
C
BYP
= 0.01µF
3027 G30 3027 G31
3027 G28 3027 G29
8
LT3027
3027fa
SHDN1/SHDN2 (Pins 7/3): Shutdown. The SHDN1/SHDN2
pins are used to put the corresponding channel of the
LT3027 regulator into a low power shutdown state. The
output will be off when the pin is pulled low. The
SHDN1/SHDN2 pins can be driven either by 5V logic or
open-collector logic with pull-up resistors. The pull-up
resistors are required to supply the pull-up current of the
open-collector gates, normally several microamperes,
and the SHDN1/SHDN2 pin current, typically 1µA. If
unused, the pin must be connected to V
IN
. The device will
not function if the SHDN1/SHDN2 pins are not connected.
IN1/IN2 (Pins 8/9): Inputs. Power is supplied to the device
through the IN pins. A bypass capacitor is required on this
pin if the device is more than six inches away from the main
input filter capacitor. In general, the output impedance of
a battery rises with frequency, so it is advisable to include
a bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1µF to 10µF is sufficient. The
LT3027 regulator is designed to withstand reverse volt-
ages on the IN pin with respect to ground and the OUT pin.
In the case of a reverse input, which can happen if a battery
is plugged in backwards, the device will act as if there is a
diode in series with its input. There will be no reverse
current flow into the regulator and no reverse voltage will
appear at the load. The device will protect both itself and
the load.
Exposed Pad (Pin 11): Ground. This pin must be soldered
to the PCB and electrically connected to ground.
ADJ1/ADJ2 (Pins 4/2): Adjust Pin. These are the inputs to
the error amplifiers. These pins are internally clamped to
±7V. They have a bias current of 30nA which flows into the
pin (see curve of ADJ1/ADJ2 Pin Bias Current vs Tempera-
ture in the Typical Performance Characteristics section).
The ADJ1 and ADJ2 pin voltage is 1.22V referenced to
ground and the output voltage range is 1.22V to 20V.
BYP1/BYP2 (Pins 5/1): Bypass. The BYP1/BYP2 pins are
used to bypass the reference of the LT3027 regulator to
achieve low noise performance from the regulator. The
BYP1/BYP2 pins are clamped internally to ±0.6V (one
V
BE
) from ground. A small capacitor from the correspond-
ing output to this pin will bypass the reference to lower the
output voltage noise. A maximum value of 0.01µF can be
used for reducing output voltage noise to a typical 20µV
RMS
over a 10Hz to 100kHz bandwidth. If not used, this pin
must be left unconnected.
OUT1/OUT2 (Pins 6/10): Output. The outputs supply
power to the loads. A minimum output capacitor of 1µF is
required to prevent oscillations. Larger output capacitors
will be required for applications with large transient loads
to limit peak voltage transients. See the Applications
Information section for more information on output ca-
pacitance and reverse output characteristics.
UU
U
PI FU CTIO S
9
LT3027
3027fa
APPLICATIO S I FOR ATIO
WUUU
The LT3027 is a dual 100mA low dropout regulator with
independent inputs, micropower quiescent current and
shutdown. The device is capable of supplying 100mA per
channel at a dropout voltage of 300mV. Output voltage
noise can be lowered to 20µV
RMS
over a 10Hz to 100kHz
bandwidth with the addition of a 0.01µF reference bypass
capacitor. Additionally, the reference bypass capacitor will
improve transient response of the regulator, lowering the
settling time for transient load conditions. The low oper-
ating quiescent current (25µA per channel) drops to less
than 1µA in shutdown. In addition to the low quiescent
current, the LT3027 regulator incorporates several pro-
tection features which make it ideal for use in battery-
powered systems. The device is protected against reverse
input voltages. Additionally, in dual supply applications
where the regulator load is returned to a negative supply,
the output can be pulled below ground by as much as 20V
and still allow the device to start and operate.
Adjustable Operation
The LT3027 has an output voltage range of 1.22V to 20V.
The output voltage is set by the ratio of two external resis-
tors as shown in Figure 1. The device servos the output to
maintain the corresponding ADJ pin voltage at 1.22V ref-
erenced to ground. The current in R1 is then equal to 1.22V/
R1 and the current in R2 is the current in R1 plus the ADJ
pin bias current. The ADJ pin bias current, 30nA at 25°C,
flows through R2 into the ADJ pin. The output voltage can
be calculated using the formula in Figure 1. The value of R1
should be no greater than 250k to minimize errors in the
output voltage caused by the ADJ pin bias current. Note that
in shutdown the output is turned off and the divider current
will be zero. Curves of ADJ Pin Voltage vs Temperature and
ADJ Pin Bias Current vs Temperature appear in the Typical
Performance Characteristics.
The device is tested and specified with the ADJ pin tied to
the corresponding OUT pin for an output voltage of 1.22V.
Specifications for output voltages greater than 1.22V will
be proportional to the ratio of the desired output voltage to
1.22V: V
OUT
/1.22V. For example, load regulation for an
output current change of 1mA to 100mA is –1mV typical
at V
OUT
= 1.22V. At V
OUT
= 12V, load regulation is:
(12V/1.22V)(–1mV) = –9.8mV
Bypass Capacitance and Low Noise Performance
The LT3027 regulator may be used with the addition of a
bypass capacitor from V
OUT
to the corresponding BYP pin
to lower output voltage noise. A good quality low leakage
capacitor is recommended. This capacitor will bypass the
reference of the regulator, providing a low frequency noise
pole. The noise pole provided by this bypass capacitor will
lower the output voltage noise to as low as 20µV
RMS
with
the addition of a 0.01µF bypass capacitor. Using a bypass
capacitor has the added benefit of improving transient
response. With no bypass capacitor and a 10µF output
capacitor, a 10mA to 100mA load step will settle to within
1% of its final value in less than 100µs. With the addition
of a 0.01µF bypass capacitor, the output will stay within
1% for a 10mA to 100mA load step (see Transient Reponse
in Typical Performance Characteristics section). However,
regulator start-up time is inversely proportional to the size
of the bypass capacitor, slowing to 15ms with a 0.01µF
bypass capacitor and 10µF output capacitor.
Figure 1. Adjustable Operation
IN
3027 F01
R2
LT3027
OUT
VIN
VOUT
ADJ
GND
R1
+
VV
R
RIR
VV
InAATC
OUTPUT RANGE V TO V
OUT ADJ
ADJ
ADJ
=+
⎛
⎝
⎜⎞
⎠
⎟+
()()
=
=°
122 1 2
12
122
30 25
122 20
.
.
= .
10
LT3027
3027fa
APPLICATIO S I FOR ATIO
WUUU
Output Capacitance and Transient Response
The LT3027 regulator is designed to be stable with a wide
range of output capacitors. The ESR of the output capaci-
tor affects stability, most notably with small
capacitors. A minimum output capacitor of 1µF with an
ESR of 3Ω or less is recommended to prevent oscilla-
tions. The LT3027 is a micropower device and output
transient response will be a function of output capaci-
tance. Larger values of output capacitance decrease the
peak deviations and provide improved transient response
for larger load current changes. Bypass capacitors, used
to decouple individual components powered by the
LT3027, will increase the effective output capacitor value.
With larger capacitors used to bypass the reference (for
low noise operation), larger values of output capacitors
are needed. For 100pF of bypass capacitance, 2.2µF of
output capacitor is recommended. With a 330pF bypass
capacitor or larger, a 3.3µF output capacitor is recom-
mended. The shaded region of Figure 2 defines the region
over which the LT3027 regulator is stable. The minimum
ESR needed is defined by the amount of bypass capaci-
tance used, while the maximum ESR is 3Ω.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common di-
electrics used are specified with EIA temperature charac-
teristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V
dielectrics are good for providing high capacitances in a
small package, but they tend to have strong voltage and
temperature coefficients as shown in Figures 3 and 4.
When used with a 5V regulator, a 16V 10µF Y5V capacitor
can exhibit an effective value as low as 1µF to 2µF for the
DC bias voltage applied and over the operating tempera-
ture range. The X5R and X7R dielectrics result in more
stable characteristics and are more suitable for use as the
output capacitor. The X7R type has better stability across
temperature, while the X5R is less expensive and is
available in higher values. Care still must be exercised
when using X5R and X7R capacitors; the X5R and X7R
codes only specify operating temperature range and maxi-
mum capacitance change over temperature. Capacitance
change due to DC bias with X5R and X7R capacitors is
better than Y5V and Z5U capacitors, but can still be
significant enough to drop capacitor values below appro-
priate levels. Capacitor DC bias characteristics tend to
improve as component case size increases, but expected
capacitance at operating voltage should be verified.
Figure 2. Stability
OUTPUT CAPACITANCE (µF)
1
ESR (Ω)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
310
3027 F02
245
678
9
STABLE REGION
C
BYP
= 330pF
C
BYP
= 100pF
C
BYP
= 0
C
BYP
> 3300pF
Figure 4. Ceramic Capacitor Temperature Characteristics
Figure 3. Ceramic Capacitor DC Bias Characteristics
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100
25 75
3027 F04
–25 0 50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3027 F03
20
0
–20
–40
–60
–80
–100 04810
26 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
11
LT3027
3027fa
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
Table 1. MSE Package, 10-Lead MSOP
COPPER AREA THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm
2
2500mm
2
2500mm
2
40°C/W
1000mm
2
2500mm
2
2500mm
2
45°C/W
225mm
2
2500mm
2
2500mm
2
50°C/W
100mm
2
2500mm
2
2500mm
2
62°C/W
*Device is mounted on topside.
Table 2. DD Package, 10-Lead DFN
COPPER AREA THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm
2
2500mm
2
2500mm
2
40°C/W
1000mm
2
2500mm
2
2500mm
2
45°C/W
225mm
2
2500mm
2
2500mm
2
50°C/W
100mm
2
2500mm
2
2500mm
2
62°C/W
*Device is mounted on topside.
The thermal resistance juncton-to-case (θ
JC
), measured
at the Exposed Pad on the back of the die is 10°C/W for the
10-lead MS package and 3°C for the 10-lead DFN package.
Calculating Junction Temperature
Example: Given an output voltage on the first channel of
3.3V, an output voltage of 2.5V on the second channel, an
input voltage range of 4V to 6V, output current ranges of
0mA to 100mA for the first channel and 0mA to 50mA for
the second channel, with a maximum ambient temperature
of 50°C, what will the maximum junction temperature be?
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor the stress
can be induced by vibrations in the system or thermal
transients. The resulting voltages produced can cause
appreciable amounts of noise, especially when a ceramic
capacitor is used for noise bypassing. A ceramic capaci-
tor produced Figure 5’s trace in response to light tapping
from a pencil. Similar vibration induced behavior can
masquerade as increased output voltage noise.
APPLICATIO S I FOR ATIO
WUUU
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components (for each channel):
1. Output current multiplied by the input/output voltage
differential: (I
OUT
)(V
IN
– V
OUT
), and
2. GND pin current multiplied by the input voltage:
(I
GND
)(V
IN
).
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance
Characteristics section. Power dissipation will be equal to
the sum of the two components listed above. Power
dissipation from both channels must be considered dur-
ing thermal analysis.
The LT3027 regulator has internal thermal limiting de-
signed to protect the device during overload conditions.
100ms/DIV 3027 F05
VOUT
500µV/DIV
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
COUT = 10µF
CBYP = 0.01µF
ILOAD = 100mA
12
LT3027
3027fa
The power dissipated by each channel of the device will be
equal to:
I
OUT(MAX)
(V
IN(MAX)
– V
OUT
) + I
GND
(V
IN(MAX)
)
where (for the first channel):
I
OUT(MAX)
= 100mA
V
IN(MAX)
= 6V
I
GND
at (I
OUT
= 100mA, V
IN
= 6V) = 2mA
so:
P1 = 100mA(6V – 3.3V) + 2mA(6V) = 0.28W
and (for the second channel):
I
OUT(MAX)
= 50mA
V
IN(MAX)
= 6V
I
GND
at (I
OUT
= 50mA, V
IN
= 6V) = 1mA
so:
P2 = 50mA(6V – 2.5V) + 1mA(6V) = 0.18W
The thermal resistance will be in the range of 40°C/W to
60°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
(0.28W + 018W)(60°C/W) = 27.8°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
T
JMAX
= 50°C + 27.8°C = 77.8°C
Protection Features
The LT3027 regulator incorporates several protection fea-
tures which makes it ideal for use in battery-powered cir-
cuits. In addition to the normal protection features asso-
ciated with monolithic regulators, such as current limiting
and thermal limiting, the devices are protected against
reverse input voltages and reverse voltages from output to
input.
Current limit protection and thermal overload protection are
intended to protect the device against current overload
conditions at the output of the device. For normal opera-
tion, the junction temperature should not exceed 125°C.
The input of the device will withstand reverse voltages of
APPLICATIONS INFORMATION
WUUU
20V. Current flow into the device will be limited to less than
1mA (typically less than 100µA) and no negative voltage will
appear at the output. The device will protect both itself and
the load. This provides protection against batteries which
can be plugged in backward.
The output of the LT3027 can be pulled below ground
without damaging the device. If the input is left open circuit
or grounded, the output can be pulled below ground by 20V.
The output will act like an open circuit; no current will flow
out of the pin. If the input is powered by a voltage source,
the output will source the short-circuit current of the de-
vice and will protect itself by thermal limiting. In this case,
grounding the SHDN pins will turn off the device and stop
the output from sourcing the short-circuit current.
The ADJ pins can be pulled above or below ground by as
much as 7V without damaging the device. If the input is left
open circuit or grounded, the ADJ pins will act like an open
circuit when pulled below ground and like a large resistor
(typically 100k) in series with a diode when pulled above
ground.
In situations where the ADJ pins are connected to a resis-
tor divider that would pull the pins above their 7V clamp
voltage if the output is pulled high, the ADJ pin input cur-
rent must be limited to less than 5mA. For example, a re-
sistor divider is used to provide a regulated 1.5V output from
the 1.22V reference when the output is forced to 20V. The
top resistor of the resistor divider must be chosen to limit
the current into the ADJ pin to less than 5mA when the ADJ
pin is at 7V. The 13V difference between output and ADJ
pin divided by the 5mA maximum current into the ADJ pin
yields a minimum top resistor value of 2.6k.
In circuits where a backup battery is required, several dif-
ferent input/output conditions can occur. The output volt-
age may be held up while the input is either pulled to ground,
pulled to some intermediate voltage or is left open circuit.
When the IN pins of the LT3027 are forced below the cor-
responding OUT pins or the OUT pins are pulled above the
IN pins, input current will typically drop to less than 2µA.
This can happen if the input of the device is connected to
a discharged (low voltage) battery and the output is held
up by either a backup battery or a second regulator circuit.
The state of the SHDN pins will have no effect on the reverse
output current when the output is pulled above the input.
13
LT3027
3027fa
TYPICAL APPLICATIO S
U
OUT1
BYP1
ADJ1
OUT2
BYP2
ADJ2
IN1
SHDN1
SHDN2
LT3027
1µF
V
IN1
3.7V TO 20V
IN2
1µF
V
IN2
2.9V TO 20V
OFF ON
0.01µF
0.01µF
422k
261k
249k
249k
10µF
10µF
3027 TA02a
3.3V
AT 100mA
2.5V
AT 100mA
GND
V
SHDN1/SHDN2
1V/DIV
V
OUT1
1V/DIV
V
OUT2
1V/DIV
2ms/DIV 3027 TA02b
C
BYP
(pF)
10
0.1
STARTUP TIME (ms)
1
10
100
100 1000 10000
3027 TA02c
Noise Bypassing Slows Startup, Allows Outputs to Track
Startup Time
Power Supply Controller Provides Coincident Tracking
OUT1
BYP1
OUT2
BYP2
LT3027 10µF
1µF
10µF243k
3027 TA04
2.5V
3.3V
V
IN
3.3V
1.8V
GND
IN1 IN2
115k
SHDN1
ADJ1
ADJ2
SHDN2
115k
93.1k
121k
255k
243k
255k
FB1
STATUS
SDO
FB2
LTC2923
GND
V
OL
GATE RAMP
RAMPBUF
TRACK2
154k
100k
ON
TRACK1
10nF
Q1
14
LT3027
3027fa
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1005
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
15
LT3027
3027fa
MSOP (MSE) 1005
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910
10
1
76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
2.083 ± 0.102
(.082 ± .004)
2.794 ± 0.102
(.110 ± .004)
0.50
(.0197)
BSC
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.83 ± 0.102
(.072 ± .004)
2.06 ± 0.102
(.081 ± .004)
U
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16
LT3027
3027fa
RD/LT 1105 REV A • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2004
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
TYPICAL APPLICATIO S
U
OUT1
BYP1
ADJ1
OUT2
BYP2
ADJ2
LT3027
1µF
V
IN1
3.7V TO 20V
OFF ON
0.01µF
0.01µF
422k
261k
249k
249k
35.7k
28k
10µF
10µF
3027 TA03a
3.3V
AT
100mA
2.5V
AT
100mA
GND
0.47µF
IN1
1µF
V
IN2
2.9V TO 20V IN2
SHDN1
SHDN2
V
SHDN1
1V/DIV
V
OUT1
1V/DIV
V
OUT2
1V/DIV
2ms/DIV
3027 TA03b
VSHDN1
1V/DIV
VOUT1
1V/DIV
VOUT2
1V/DIV
2ms/DIV 3027 TA03c
Startup Sequencing
Turn-On Waveforms Turn-Off Waveforms
PART NUMBER DESCRIPTION COMMENTS
LT1761 100mA, Low Noise Micropower, LDO Low Noise < 20µV
RMS
, Stable with 1µF Ceramic Capacitors,
V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, Dropout Voltage = 0.3V, I
Q
= 20µA,
I
SD
= <1µA, V
OUT
= Adj., 1.5, 1.8, 2, 2.5, 2.8, 3, 3.3, 5, ThinSOT Package
LT1762 150mA, Low Noise Micropower, LDO Low Noise < 20µV
RMS
,
V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, Dropout Voltage = 0.3V, I
Q
= 25µA,
I
SD
= <1µA, V
OUT
= Adj., 2.5, 3, 3.3, 5, MS8 Package
LT1763 500mA, Low Noise Micropower, LDO Low Noise < 20µV
RMS
,
V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, Dropout Voltage = 0.3V, I
Q
= 30µA,
I
SD
= <1µA, V
OUT
= 1.5, 1.8, 2.5, 3, 3.3, 5, S8 Package
LT1764/LT1764A 3A, Low Noise, Fast Transient Response, LDO Low Noise < 40µV
RMS
, "A" Version Stable with Ceramic Capacitors,
V
IN
: 2.7V to 20V, V
OUT(MIN)
= 1.21V, Dropout Voltage = 0.34V, I
Q
= 1mA,
I
SD
= <1µA, V
OUT
= 1.8, 2.5, 3.3, DD, TO220 Packages
LTC1844 150mA, Very Low Drop-Out LDO Low Noise < 30µV
RMS
, Stable with 1µF Ceramic Capacitors,
V
IN
: 1.6V to 6.5V, V
OUT(MIN)
= 1.25V, Dropout Voltage = 0.08V, I
Q
= 40µA,
I
SD
= <1µA, V
OUT
= Adj., 1.5, 1.8, 2.5, 2.8, 3.3, ThinSOT Package
LT1962 300mA, Low Noise Micropower, LDO Low Noise < 20µV
RMS
,
V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22V, Dropout Voltage = 0.27V, I
Q
= 30µA,
I
SD
= <1µA, V
OUT
= 1.5, 1.8, 2.5, 3, 3.3, 5, MS8 Package
LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, LDO Low Noise < 40µV
RMS
, "A" Version Stable with Ceramic Capacitors,
V
IN
: 2.1V to 20V, V
OUT(MIN)
= 1.21V, Dropout Voltage = 0.34V, I
Q
= 1mA,
I
SD
= <1µA, V
OUT
= 1.5, 1.8, 2.5, 3.3, DD, TO220, SOT-223, S8 Packages
LT1964 200mA, Low Noise Micropower, Negative LDO Low Noise < 30µV
RMS
, Stable with Ceramic Capacitors,
V
IN
: –0.9V to –20V, V
OUT(MIN)
= –1.21V, Dropout Voltage = 0.34V, I
Q
= 30µA,
I
SD
= 3µA, V
OUT
= Adj., –5, ThinSOT Package
LT3020 100mA, VLDO in MSOP Low Noise < 245µV
RMS
, Stable with 2.2µF Ceramic Capacitors,
V
IN
: 0.9V to 10V, V
OUT(MIN)
= 0.2 V, Dropout Voltage = 0.155V, I
Q
= 140µA,
I
SD
= <3µA, V
OUT
= Adj., MS8, DFN Packages
LT3023 Dual 100mA, Low Noise Micropower, LDO Dual Low Noise < 20µV
RMS
, Stable with 1µF Ceramic Capacitors,
V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22 V, Dropout Voltage = 0.3V, I
Q
= 40µA,
I
SD
= <1µA, V
OUT
= Adj., MS10, DFN Packages
LT3024 Dual 100mA/500mA, Low Noise Micropower, LDO Dual Low Noise < 20µV
RMS
, Stable with 1µF/3.3µF Ceramic Capacitors,
V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22 V, Dropout Voltage = 0.3V, I
Q
= 60µA,
I
SD
= <1µA, V
OUT
= Adj., TSSOP16, DFN Packages
LT3028 Dual 100mA/500mA, Low Noise Micropower, LDO Dual Low Noise < 20µV
RMS
, Stable with 1µF/3.3µF Ceramic Capacitors,
with Independent Inputs V
IN
: 1.8V to 20V, V
OUT(MIN)
= 1.22 V, Dropout Voltage = 0.3V/0.32V,
I
Q
= 60µA/65µA, I
SD
= <1µA, V
OUT
= Adj., TSSOP16, DFN Packages
RELATED PARTS
