ee July 1998 FAIRCHILD ee SEMICONDUCTOR Im NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM General Description The NM27C512 is one member of a high density EPROM Family which range in densities up to 4 Megabit. The NM27C512 is ahigh performance 512K UV Erasable Electri- cally Programmable Read Only Memory (EPROM). It is manufac- Features tured using Fairchilds proprietary CMOS AMG EPROM tech- nology for an excellent combination of speed and economy while providing excellent reliability. Mf High performance CMOS 90 ns access time Wi Fast turn-off f i tibilit The NM27C512 provides microprocessor-based systems storage Sh MITrol for microprocessor compa y capacity for portions of operating system and application soft- m@ Manufacturers identification code ware. Its 90 ns access time provides no wait-state operation with @ JEDEC standard pin configuration high-performance CPUs. The NM27C512 offers a single chip 28-pin PDIP package solution for the code storage requirements of 100% firmware- 32-pin chip carrier based equipment. Frequently-used software routines are quickly 28-pin CERDIP package executed from EPROM storage, greatly enhancing system utility. The NM27C512 is configured in the standard JEDEC EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs. Block Diagram Data Outputs Og - 07 Vcc OQ> GND VPP OE Output Enable and CE/PGM Chip Enable Logic Output Buffers Y Decoder 524,288-Bit Cell Matrix Ao - A15 Address < Inputs X Decoder DS010834-1 AMG is a trademark of WSI, Inc. WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINN 1998 Fairchild Semiconductor Corporation 1 www .fairchildsemi.comConnection Diagrams 27080 | 27C040 | 27C020 | 27C010 | 270256 DIP 276256 | 27C010 | 27C020 | 27C040 | 27C080 Ria podlpp power power NM27C512 Voc | Yoo | Yeo | Veo 16 16 16 16 XX/PGM|XX/PGM| A18 Aig Ais | Ais | Ais | As VpP | Aisdt \J a8hbVvec Voc | Xx Ai7 Aiz | Aq Ai2 Ai2 Ai2 Ai2 Ai2 Ayo 2 27 BAY4 Ata Ata Ata Ata Ata AZ AZ AZ AZ AZ A743 26 PAY Aig Aig Aig Aig Aig AG AG AG AG AG Ag 4 25 B Ag Ag Ag Ag Ag Ag AS AS AS AS AS A5q5 24 BAg Ag Ag Ag Ag Ag Ag Ag Ag Ag Ag Agd6 23 PAL Aqt Ad Ad Ad Ad A3 A3 A3 A3 A3 A3gqd7 22 b OENV/pp OE OE OE OE JOEVpp Ag Ag Ag Ag Ag Aoq8 C) 21 BAO AO AO AO AO AO A A A A A Aig 20h CE/PGM |ce/Pam| cE | CE |CE/PGM|CE/PGM Ao Ao Ao Ao Ao Ag F 10 1907 o7 | o7 o7 o7 o7 Oo o So o So oo 4 11 18 BP Og Og Og Og Og Og O71 O71 O1 O71 O1 Oy 4 12 17 POs Os Os Os Os Os 2 2 2 2 2 O24 13 16Ho4 O4 o4 o4 o4 o4 qnp_| Gnd _| and | GND _| GND | GND 14 15 HOg 03 03 03 03 03 DS010834-2 Compatible EPROM pin configurations are shown in the blocks adjacement to the NM27C512 pins. Commercial Temp Range (0C to +70C) Pin Names Parameter/Order Number} Access Time (ns) AO-A15 Addresses NM27C512 Q, N, V90 90 CE/PGM Chip Enable/Program NM27C512 Q, N, V 120 120 OE Output Enable NM27C512 Q, N, V 150 150 00-07 Outputs NC Dont Care (During Read) Industrial Temp Range (-40C to +85C) PLCC Parameter/Order Number; Access Time (ns) ~N8yg8x! ttqeracct NM27C512 QE, NE, VE 120 120 NM27C512 QE, NE, VE 150 150 4 3 2 1 32 31 30 Q = Quartz-Windowed Ceramic DIP Package A6 29 - A8 A5 28 | AQ N = Plastic DIP Package A4 o7l_ Alt V = PLCC Package AS 26 - NC A2 25 | OE/VPP * All packages conform to the JEDEC standard. At 24 L_~ A10 + All versions are guaranteed to function for slower speeds. AO 23 } CE/PGM NC 22 | O7 oOo 21 | O08 14 15 16 17 18 19 20 o1 02 GND NC O3 04 O5 DS010834-3 www fairchildsemi.com WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINNAbsolute Maximum Ratings (Note 1) ESD Protection (MIL Std. 883, Method 3015.2) >2000V Storage Temperature -65C to +150C All Output Voltages with All Input Voltages Except AQ with Respect to Ground Veo + 1.0V to GND -0.6V Respect to Ground -0.6V to +7V Vpp and AQ with Respect to Ground -0.7V to +14V Operating Range Voo Supply Voltage with Range Temperature Vec | Tolerance Respect to Ground 0.6V to +7V Commercial 0C to +70C +5V +10% Industrial -40C to +85C +5V +10% Read Operation DC Electrical Characteristics Symbol Parameter Test Conditions Min Max Units Vit Input Low Level -0.5 0.8 Vv Vin Input High Level 2.0 Vec +1 Vv VoL Output Low Voltage Io, = 2.1 mA 0.4 v Vou Output High Voltage loy = -2.5 mA 3.5 v Ispi Veo Standby Current (CMOS) CE = Veg +0.3V 100 pA Ispe Veo Standby Current CE=Viy, 1 mA lect Voc Active Current CE = OE =Vi_ f =5 MHz 40 mA lees Voc Active Current CE = GND, f = 5 MHz CMOS Inputs Inputs = Vee or GND, I/O =O mA 35 mA C, E Temp Ranges Ipp Vpp Supply Current Vpp = Voc 10 LA Vpp Vpp Read Voltage Vec - 0.7 Veco Vv ly Input Load Current Vin = 5.5V or GND -1 1 pA lLo Output Leakage Current Vour = 5.5V or GND -10 10 pA AC Electrical Characteristics Symbol Parameter 90 120 150 Units Min | Max | Min | Max | Min | Max tacc Address to Output Delay 90 120 150 ns tor CE to Output Delay 90 120 150 tor OE to Output Delay 40 50 50 tor Output Disable to 35 25 45 Output Float tox Output Hold from Addresses, CE or OE, 0 0 0 Whichever Occurred First 3 www fairchildsemi.com WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINNCapacitance T, = +25C, f = 1 MHz (Note 2) Symbol Parameter Conditions | Typ | Max | Units Cini Input Capacitance Vin = OV 6 12 pF except OE/Vpp Cour Output Capacitance Vout = OV 9 12 pF Cino OE/Vpp Input Vin = OV 20 25 pF Capacitance AC Test Conditions Output Load 1 TTL Gate and C, = 100 pF (Note 8) Input Rise and Fall Times <5 ns Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level (Note 9) Inputs 0.8V and 2V Outputs 0.8V and 2V AC Waveforms (Notes 6, 7) ADDRESS <%, a Address Valid - x By CE 0.8V am e ~<a tor _ (Note 4, 5) t OE 0.8V 55 t toe =< (Note 3) (Note 4, 5) oureur HZ LOEW eis out Dyes oaV AKG s J a face > > tou (Note 3) DS010834-4 Note 1: Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tacc tog after the falling edge of CE without impacting tacc- Note 4: The tpp and tc compare level is determined as follows: High to TRI-STATE, the measured Vo, (DC) - 0.10V; Low to TRI-STATE, the measured Vo; (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE. Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 uF ceramic capacitor be used on every device between Vcc and GND. Note 7: The outputs must be restricted to Veg + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: Io, = 1.6 MA, Ioy = -400 PA. C,: 100 pF includes fixture capacitance. Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max. 4 www .fairchildsemi.com WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINNProgramming Characteristics (Note 10) and (Note 11) Symbol Parameter Conditions Min Typ Max Units tas Address Setup Time 1 ps toes OE Setup Time 1 ps tos Data Setup Time 1 ps tyes Voc Setup Time 1 ys tay Address Hold Time 0 ps tou Data Hold Time 1 ps tor Chip Enable to Output Float Delay OE = Vi. 0 60 ns tow Program Pulse Width 45 50 105 ys toen OE Hold Time 1 us tov Data Valid from CE OE= Vy 250 ns tear OE Pulse Rise Time 50 ns during Programming tyr Vpp Recovery Time 1 ps Ipp Vpp Supply Current during CE =ViL 30 mA Programming Pulse OE = Vpp loc Veo Supply Current 50 mA Tr Temperature Ambient 20 25 30 C Veco Power Supply Voltage 6.25 6.5 6.75 Vpp Programming Supply Voltage 125 12.75 13 ter Input Rise, Fall Time 5 ns Vit Input Low Voltage 0 0.45 Vv Vin Input High Voltage 2.4 4 Vv tn Input Timing Reference Voltage 0.8 2 v tour Output Timing Reference Voltage 0.8 2 Vv Programming Waveforms Program Addresses Address N tas Data Data in Stable tos toy OE/Vpp toeH || tvR CE/PGM Voc DS010834-5 Note 10: Fairchilds standard product warranty applies to devices programmed to specifications described herein. Note 11: Vo must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a board with voltage applied to Vpp or Veg. Note 12: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 LF capacitor is required across Veg to GND to suppress spurious voltage transients which may damage the device. www fairchildsemi.com WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINNTurbo Programming Algorithm Flow Chart Voc = 6.5V Vpp = 12.75V n=0 ADDRESS = FIRST LOCATION y PROGRAM ONE 50y1s PULSE ~T n DEVICE FAILED CHECK ALL BYTES 1ST: Vog = Vpp = 6.0V 2ND: Vog = Vpp = 4.3V A INCREMENT ADDRESS n=0 INCREMENT PASS PROGRAM ONE 50 ps ADDRESS euSe <<_ Note: The standard National Semiconductor algorithm may also be used but it will take longer programming time. FIGURE 1. DS010834-6 www fairchildsemi.com WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINNFunctional Description DEVICE OPERATION The six modes of operation of the EPROM are listed in Table7. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are Voc and OE/Vpp. The OE/Vpp power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The Vog power supply must be at 6.5V during the three programming modes, and at 5V in the other three modes. Read Mode The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE/V 5) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tacc) is equal to the delay from CE to output (t_). Data is available at the outputs to after the falling edge of OE, assuming that CE has been low and addresses have been stable for atleast tace ~ toe: Standby Mode The EPROM has astandby mode which reduces the active power dissipation by over 99%, from 220 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are ina high impedance state, independent of the OE input. Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI- STATE). Output OR-Typing Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. The 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary device select- ing function, while OE/Vpp be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming CAUTION: Exceeding 14V on pin 22 (OEM pp) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the 1s state. Data is introduced by selectively programming 0s into the desired bit locations. Although only Os will be pro- grammed, both 1s and Os can be presented in the data word. The only way to change a O to a 1 is by ultraviolet light erasure. The EPROM is in the programming mode when the OE/V pp is at 12.75V. It is required that at least a 0.1 WF capacitor be placed across Vcc to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, anactivelow, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algo- rithm shown in Figure 1. Each Address is programmed with a series of 50 1s pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 ps pulse. (The standard National Semiconductor Algorithm may also be used but it will have longer programming time.) The EPROM must not be programmed with a DC signal applied to the CE/PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be con- nected together when they are programmed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM. Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM all like inputs (including OE/Vpp) of the parallel EPROMs may be common. A TTL low level program pulse applied to an EPROMs CE/PGM input with OE/Vppat 12.75V will program that EPROM. ATTLhigh level CE/PGM input inhibits the other EPROMs from being pro- grammed. Program Verify Averify should be performed on the programmed bits to determine whether they were correctly programmed. The verify is accom- plished with OE/Vpp and CE at V,_. Data should be verified Tpy after the falling edge of CE. AFTER PROGRAMMING Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also preventtemporary functional failure due to the generation of photo currents. MANUFACTURERS IDENTIFICATION CODE The EPROM has a manufacturers identification code to aid in programming. When the device is inserted in an EPROM pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturers Identification code, shown in Table 2, specifi- cally identifies the manufacturer and device type. The code for NM27C512 is 8F85, where 8F designates that it is made by Fairchild Semiconductor, and 85 designates a 512K part. The code is accessed by applying 12V +0.5V to address pin AQ. Addresses A1A8, A10-A16, and all control pins www fairchildsemi.com WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINNFunctional Description (Continued) are held at V|,. Address pin AO is held at V, for the manufacturer's code, and held at V),, for the device code. The code is read on the eight data pins, OO -O 7 . Proper code access is only guaranteed at 25C +5C. ERASURE CHARACTERISTICS The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range. The recommended erasure procedure for the EPROM is expo- sure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (i.e., UV intensity x exposure time) for erasure should be minimum of 15W-sec/cm?. The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). Mode Selection Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Program- mers, components, and even system designs have been errone- ously suspected when incomplete erasure was the problem. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, Igg, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated Voc transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 WF ceramic capacitor be used on every device between Voc and GND. This should be a high frequency capacitor of low inherent inductance. In addition, atleast a 4.7 UF bulk electrolytic capacitor should be used between Voc and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. The modes of operation of the NM27C512 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels excepts for Vpp and AQ for device signature. TABLE 1. Mode Selection Pins CE/PGM OE/Vpp Voc Outputs Mode Read Vit Vit 5.0V Dout Output Disable X (Note 13) Vin 5.0V High Z Standby Vin xX 5.0V High Z Programming Vit 12.75V 6.25V Diy Program Verify Vit Vit 6.25V Dour Program Inhibit Vin 12.75V 6.25V High Z Note 13: X can be V, or Vij. TABLE 2. Manufacturers Identification Code Pins AO AQ 07 06 05 04 03 02 01 00 Hex (10) | (24) | (19) | (18) | (17) | (16) | (15) | (13) | (12) | (11) | Data Manufacturer Code] Vj, 12v 1 0 0 0 1 1 1 1 8F Device Code Vin 12v 1 0 0 0 0 1 0 1 85 8 www fairchildsemi.com WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINNPhysical Dimensions inches (millimeters) unless otherwise noted | 1.465 MAX | [37.211] | 28 15 AAAs R 0.02 [0.635] - + . 0.515-0.530 [13.081-13.462] ' \ Ta GT a a tT ata a a a a a 1 14 R 0.030-0.055 [0.762-1.397] 0.290-0.310 TYP [7.366-7.874] U.V. WINDOW 0.050-0.060 Pat] ess ONG) sepa t TYP SEALANT | | : | 4 t 0.225 [5.715] 0.180 [4 572] MAX TYP A ' i 90-1 00 t Typ _0.008-0.012|\- [0.203-0.305] TYP Ty TYP 0.125 [3.175} 40.025 MIN TYP 0018-0021 0.015-0.060 ~ 9.685 5 069 *| 0.060-0.100 015-0. [0.381-1.524] +0.635 11524-2540) | | 7 [ To-s81-0.533) TYP [17.399 soa] TYP 090-0110 _ _.-0.033-0.045 [2.286.2.794] [0.838-1.143] TYP TYP UV Window Cavity Dual-In-Line Cerdip Package (JQ) Order Number NM27C512Q Package Number J28CQ (8175-4191) 0.20 in A 0.125-0.145 (3.175-3.583) 0.080 44 Oppo 0 Wlax (0.762) "| 0.600- 0.620 A 0.082 RAD 1524-1575 0.510 40,005 1.575) t ( ) 0.910 0,005 + (12.95 40.127) 2 A 0.580 *-(0:205-0 381) on 1234567 8 9 1011121314 (14.73) 228-0. 1.393 - 1.420 _ 0.008 (35.38 - 36.07) +0. 0625 Sots 40.635 0.050 ( 5.88 -0.381 ) (1.270) 0.053 - 0.069 Typ 71346 1.753) wl le -0.125-0.165 I 1 (0,508) ~<_ ae 88 0.108 40.010 Typ 0.050 40.015 _ || (2.540 +0.254) (1.270 40.381) 0.018 +0.003 (0.457 +0.076) 28-Lead Plastic One-Time-Programmable Dual-In-Line Order Number NM27C512N Package Number N28B www fairchildsemi.com WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINNPhysical Dimensions inches (millimeters) unless otherwise noted 0.485-0.495 . [12.32-12.57] 0.106-0.112 [HJ Base 0.007[0.18](S) BEES [2.69-2.84] a Plane 0.449-0.453 0.023-0.029 [11.40-11.51] [0.58-0.74] 0015 [0.38] Min Typ os 4 0.00710.18}8)]B |D-E@| . . o 6 0.000-0.010 L_| 0.002I0.05] ()|B sf [0.00-0.25] | l 0.400 0.490-0530 Polished Optional ase (to.16)) [12.45-13.46] 4 oo oo 0.541-0.545 [S]o.ors10.28 8] | D-E, F-G 5 +. 09 [13.74-13-84] ~}]0.01810.38) q Hi 0.549-0.553 q H [13.94-14.05] q H q E i, q D1 0.585-0.595 [14.86-15.11] q E |_0.013-0.021 Typ d L [0.33-0.53] d See detail A | Je ed 0.007[0.18] (M)| | D-E, F-G (8) Lo 0.078-0.095 To oT 0.123-0.140 [1.98-2.41] 14 el 20 0.059) [3.12-3.56] 0.005 0.00710.18 A|EG 0.004[0.10] Max Spoor. A [F-o 0.020 0100 --/0.007[0.18](8) F-G6) [0.51] q [0.254] 0.118-0.129 0.045 yt [3.00-3.28] [1.14] -010/0.25)(L)| BJA|D-E. --aG 0.025 . 0.030-0.040 [S[ponronaaO| APE FSG) 0028, Detail * Roe apex, 0:042-0.048 0028 Typical [1.07-1.22] Od 0.021-0.027 Rotated 90 Mi [0.64] [0 .53-0.69] In 2 Y 0.065-0.071 [1.65-1.80] |__ 0.053-0.059 [1.65-1.80] |__ 0.031-0.037 0.006-0.012 [0.79-0.94] H [0.15-0.30] + 0.027-0.033 > je0.026-0.092 tr. 0.019-0.025 [0.69-0.84] [0.66-0.81] YP [0.48-0.64] Section B-B Typical 32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number NM27C512V Package Number VA32A Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. Acritical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg. Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Frangais Tel: Italiano Tel: +33 (0) 1-6930-3696 +39 (0) 2-249111-1 Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 10 www fairchildsemi.com WOUda SOD aoueUO}ed YBIH (8 X MP9) HA-88277S ZLGOZZINN