BR24A04FJ-WME2 - ROHM Co., Ltd. - Datasheet.Directory

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○Product structure: Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays

1/28 TSZ02201-0R1R0G100140-1-2

6.Nov.2013 Rev .002

TSZ22111･14･001

www.rohm.com

Serial EEPROM Series Automotive EEPROM

105℃ Operation I2C BUS EEPROM (2-Wire)

BR24Axxx-WM

(1K 2K 4K 8K 16K 32K 64K)

●General Description

BR24Axxx-WM is a serial EEPROM of I2C BUS interface method.

●Features

 Completely conforming to the world standard I2C BUS.

All controls available by 2 ports of serial clock

(SCL) and serial data (SDA)

 Wide temperature range -40 ℃ to +105℃

 Other devices than EEPROM can be connected to

the same port, saving microcontroller port

 2.5V to 5.5V single power source operation most

suitable for battery use

 Page write mode useful for initial value write at

factory shipment

 Auto erase and auto end function at data rewrite

 Low current consumption

¾ At write operation (5V) : 1.2mA (Typ.)

*1

¾ At read operation (5V) : 0.2mA (Typ.)

¾ At standby condition (5V) : 0.1μA (Typ.)

 Write mistake prevention function

¾ Write (write protect) function added

¾ Write mistake prevention function at low voltage

 Data rewrite up to 1,000,000 times(Ta≦25℃）

 Data kept for 40 years(Ta≦25℃）

 Noise filter built in SCL / SDA terminal

 Shipment data all address FFh

●Packages W(Typ.) x D(Typ.) x H(Max.)

*1 BR24A32-WM, BR24A64-WM : 1.5mA

 AEC-Q100 Qualified

●Page write

Number of Pages 8Byte 16Byte 32Byte

Product

number BR24A01A-WM

BR24A02-WM

BR24A04-WM

BR24A08-WM

BR24A16-WM

BR24A32-WM

BR24A64-WM

●BR24Axxx-WM

Capacity Bit format Type Power source voltage SOP8 SOP-J8 MSOP8

1Kbit 128×8 BR24A01A-WM 2.5V to 5.5V ● ●

2Kbit 256×8 BR24A02-WM 2.5V to 5.5V ● ● ●

4Kbit 512×8 BR24A04-WM 2.5V to 5.5V ● ●

8Kbit 1K×8 BR24A08-WM 2.5V to 5.5V ● ●

16Kbit 2K×8 BR24A16-WM 2.5V to 5.5V ● ●

32Kbit 4K×8 BR24A32-WM 2.5V to 5.5V ●

64Kbit 8K×8 BR24A64-WM 2.5V to 5.5V ●

SOP8

5.00mm x 6.20mm x 1.71mm

SOP- J8

4.90mm x 6.00mm x 1.65mm

MSOP8

2.90mm x 4.00mm x 0.90mm

Datasheet

2/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Absolute Maximum Ratings (Ta=25℃)

Parameter Symbol Ratings Unit Remarks

Supply Voltage VCC -0.3 to +6.5 V

Power Dissipation Pd 0.45 (SOP8) W

When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.

0.45 (SOP-J8) When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.

0.31 (MSOP8) When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.

Storage Temperature Tstg -65 to +125 ℃

Operating Temperature Topr -40 to +105 ℃

Terminal Voltage ‐ -0.3 to VCC+1.0 V

●Memory cell characteristics (VCC=2.5V to 5.5V)

Parameter Limits Unit Conditions

Min. Typ. Max

Number of data rewrite times *1 1,000,000 - -

Times Ta≦25℃

100,000 - - Ta≦105℃

Data hold years *1 40 - -

Years Ta≦25℃

10 - - Ta≦105℃

○Shipment data all address FFh

*1Not 100% TESTED

●Recommended Operating Ratings

Parameter Symbol Ratings Unit

Power source voltage VCC 2.5 to 5.5 V

Input voltage VIN 0 to VCC

●Electrical characteristics (Unless otherw ise specified, Ta=-40℃ to +105℃, VCC=2.5V to 5.5V)

Parameter Symbol Limits Unit Conditions

Min. Typ. Max.

“HIGH” input voltage VIH 0.7 VCC - - V

“LOW” input voltage VIL - - 0.3 VCC V

“LOW” output voltage 1 VOL - - 0.4 V IOL=3.0mA (SDA)

Input leak current ILI -1 - 1 μA VIN=0V to VCC

Output leak current ILO -1 - 1 μA VOUT=0V to VCC, (SDA)

Current consumption ICC1 - -

2.0 *1 mA VCC =5.5V,fSCL=400kHz, tWR=5ms,

Byte write, Page write

3.0 *2

ICC2 - - 0.5 mA

VCC =5.5V,fSCL=400kHz

Random read, current read, sequential read

Standby current ISB - - 2.0 μA VCC =5.5V, SDA・SCL= VCC

A0, A1, A2=GND, WP=GND

*1 BR24A01A/02/04/08/16-WM, *2 BR24A32/64-WM

Datasheet

3/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Operating timing characte ristics (Unl ess otherwise specified, Ta=-40℃ to +105℃, VCC=2.5V to 5.5V)

Parameter Symbol FAST-MODE

2.5V≦VCC≦5.5V STANDARD-MODE

2.5V≦VCC≦5.5V Unit

Min. Typ. Max. Min. Typ. Max.

SCL frequency fSCL - - 400 - - 100 kHz

Data clock “HIGH“ time tHIGH 0.6 - - 4.0 - - μs

Data clock “LOW“ time tLOW 1.2 - - 4.7 - - μs

SDA, SCL rise time *1 tR - - 0.3 - - 1.0 μs

SDA, SCL fall time *1 tF - - 0.3 - - 0.3 μs

Start condition hold time tHD:STA 0.6 - - 4.0 - - μs

Start condition setup time tSU:STA 0.6 - - 4.7 - - μs

Input data hold time tHD:DAT 0 - - 0 - - ns

Input data setup time tSU:DAT 100 - - 250 - - ns

Output data delay time tPD 0.1 - 0.9 0.2 - 3.5 μs

Output data hold time tDH 0.1 - - 0.2 - - μs

Stop condition setup time tSU:STO 0.6 - - 4.7 - - μs

Bus release time before transfer start tBUF 1.2 - - 4.7 - - μs

Internal write cycle time tWR - - 5 - - 5 ms

Noise removal valid period (SDA, SCL terminal) tI - - 0.1 - - 0.1 μs

WP hold time tHD:WP 0 - - 0 - - ns

WP setup time tSU:WP 0.1 - - 0.1 - - μs

WP valid time tHIGH:WP 1.0 - - 1.0 - - μs

*1 Not 100% tested

●FAST-MODE and STANDARD-MODE

FAST-MODE and STANDARD-MODE are of same operations, and mode is changed. They are distinguished by operating

speeds. 100kHz operation is called STANDARD-MODE, and 400kHz operation is called FAST-MODE. This operating

frequency is the maximum operating frequency, so 100kHz clock may be used in FAST-MODE. At VCC =2.5V to 5.5V,

400kHz, namely, operation is made in FASTMODE. (Operation is made also in STANDARD-MODE.)

●Sync Data Input / Output Timing

○Input read at the rise edge of SCL

○Data ou tput in sync with the fall of SCL

Figure 1-(a) Sync data input / output timing Figure 1-(b) Start-stop bit timing

Figure 1-(c) Write cycle timing Figure 1-(d) WP timing at write execution

○At write execution, in the area from the D0 taken clock rise of the first

DATA(1), to tWR, set WP=“LOW”.

○By setting WP “HIGH” in the area, write can be cancelled.

When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of

address under access is not guaranteed, therefore write it once again.

Figure 1-(e) WP timing at write cancel

SDA

tSU:STA tSU:STOtHD:STA

START BIT STOP BIT

SCL

tHIGH:WP

WP

SDA D1 D0 ACK ACK

DATA(1) DATA(n)

tWR

SCL

SDA

W rite data

(n-th address) Stop condition Start condition

SCL

ｔWR

ACK

D0

SD

A

(入力)

SDA

(出力)

tHD:STA tHD:DAT

tSU:DAT

tBUF tPD tDH

tLOW

tHIGHtR tF

SCL

(input)

(output)

SCL

SDA

WP

ｔHD：WP

ストップコンディション

ｔWR

D1 D0

A

CK

A

CK

DATA(1) DATA(n)

tSU：WP

Stop condition

Datasheet

4/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Block Diagram

●Pin Configuration

●Pin Descriptions

Terminal

name Input /

output

Function

BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM

A0 Input Slave address setting Not connected Slave address setting

A1 Input Slave address setting Not connected Slave address setting

A2 Input Slave address setting Not used Slave address setting

GND - Reference voltage of all input / output, 0V

SDA Input /

output Slave and word address, Serial data input serial data output

SCL Input Serial clock input

WP Input Write protect terminal

Vcc - Connect the power source.

1Kbit to 64Kbit EEPROM array

Control circuit

High voltage

generating circuit Power source

voltage detection

7bit

8bit

9bit

10bit

11bit

12bit

13bit

Address

decoder Slave - word

address register Data

register

8bit

7bit

8bit

9bit

10bit

11bit

12bit

13bit

START STOP

ACK

*1

1

2

3

4

8

7

6

5 SDA

SCL

WP

Vcc

A1

A0

A2

GND

*2

*1 7bit : BR24A01A-WM

8bit : BR24A02-WM

9bit : BR24A04-WM

10bit : BR24A08- WM

11bit : BR24A16-WM

12bit : BR24A32- WM

13bit : BR24A64- WM

*2 A0=N.C. : BR24A04-WM

A0, A1=N.C. : BR24A08-WM

A0, A1= N.C. A2=Don’t Use : BR24A16-WM

2

1

3

4

BR24A01A-WM

BR24A02-WM

BR24A04-WM

BR24A08-WM

BR24A16-WM

BR24A32-WM

BR24A64-WM

A0

A1

A2

GND

Vcc

WP

SCL

SDA

8

7

6

5

(TOP VIEW)

Datasheet

5/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

Figure 4. L output voltage VOL1-IOL1

(VCC =2.5V)

Figure 5. Input leak current ILI (SCL,WP)

Figure 2. H input voltage VIH1,2

(SCL,SDA,WP) Figure 3. L input voltageVIL1,2

(SCL,SDA,WP)

●Typical Performance Cur ves

(The following values are Typ. ones.)

0

1

2

3

4

5

6

0 1 2 3 4 5 6

VIH[V]

Ta=105℃

Ta=-40℃

Ta=25℃

SPEC

Vcc[V]

0

1

2

3

4

5

6

0 1 2 3 4 5 6

VIL[V]

Ta=105℃

Ta=-40℃

Ta=25℃

SPEC

0

0.2

0.4

0.6

0.8

1

0 1 2 3 4 5 6

VOL1[V]

Ta=25℃

Ta=-40℃

Ta=105℃

SPEC

IOL1[mA]

Vcc[V]

0

0.2

0.4

0.6

0.8

1.0

1.2

0 1 2 3 4 5 6

Vcc[V]

ILI[μA]

Ta=105℃

Ta=25℃

Ta=-40℃

SPEC

Datasheet

6/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

Figure 6. Output leak current ILO(SDA)

Figure 7. Current consumption at WRIT E operation

ICC1 (fSCL=400kHz)

Figure 9. Current consumption at READ oper ation

ICC2 (fSCL=400kHz)

Figure 8. Current consumption at W RITE operation

ICC1 (fSCL=400kHz)

●Typical Performance Curves‐Continued

0

0.2

0.4

0.6

0.8

1

1.2

0 1 2 3 4 5 6

Vcc[V]

ILO[μA]

SPEC

Ta=105℃

Ta=25℃

Ta=-40℃

0

0.5

1.0

1.5

2.0

2.5

0 1 2 3 4 5 6

Vcc[V]

ICC1[mA]

fSCL=400kHz

DATA=AAh

Ta=25℃

Ta=105℃

Ta=-40℃

SPEC

[BR24A01A/02/04/08/16-WM]

0

0.1

0.2

0.3

0.4

0.5

0.6

0 1 2 3 4 5 6

Vcc[V]

ICC2[mA]

fSCL=400kHz

DATA=AAh

Ta=25℃

Ta=-40℃

Ta=105℃

SPEC

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 1 2 3 4 5 6

ICC1[mA]

fSCL=400kHz

DATA=AAh

Ta=25℃

Ta=105℃

Ta=-40℃

SPEC

[BR24A32/64-WM]

Vcc[V]

Datasheet

7/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

Figure 10. Current consumption at WRITE operation

ICC1 (fSCL=100kHz)

Figure 11. Current consumption at WRITE operation

ICC1 (fSCL=100kHz)

Figure 12. Current consumption at READ operation

ICC2 (fSCL=100kHz) Figure 13. Standby current ISB

●Typical Performance Curves‐Continued

Vcc[V]

0

0.5

1.0

1.5

2.0

0 1 2 3 4 5 6

Vcc[V]

ICC1[mA]

fSCL=100kHz

DATA=AAh

Ta=25℃

Ta=105℃

Ta=-40℃

SPEC

[BR24A01A/02/04/08/16-WM]

2.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0123 4 56

ICC1[mA]

Ta=25℃

Ta=105℃

Ta=-40℃

[BR24A32/64-WM]

SPEC

fSCL=100kHz

DATA=AAh

0

0.1

0.2

0.3

0.4

0.5

0.6

0 1 2 3 4 5 6

Vcc[V]

ICC2[mA]

SPEC

fSCL=100kHz

DATA=AAh

Ta=-40℃

Ta=105℃

Ta=25℃

0

0.5

1.0

1.5

2.0

2.5

0 1 2 3 4 5 6

ISB[μA]

Ta=-40℃

Ta=105℃ Ta=25℃

SPEC

Datasheet

8/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

Figure 14. SCL frequency fSCL

Figure 15. Data clock "H" time tHIGH

Figure 16. Data clock "L" time tLOW

Figure 17. Start condition hold time tHD:STA

●Typical Performance Curves‐Continued

1

10

100

1000

10000

0 1 2 3 4 5 6

Vcc[V]

fSCL[kHz]

Ta=105℃

Ta=25℃

Ta=-40℃

SPEC2

SPEC1

0

1

2

3

4

5

0123 4 56

Vcc[V]

tHIGH [μs]

SPEC2

Ta=-40℃

Ta=25℃

Ta=105℃SPEC1

0

1

2

3

4

5

0 1 2 3 4 5 6

Vcc[V]

tLOW[μs]

SPEC2

SPEC1

Ta=105℃

Ta=25℃

Ta=-40℃

0

1

2

3

4

5

0123 4 56

tHD:STA[μs]

SPEC2

SPEC1

Ta=105℃

Ta=25℃

Ta=-40℃

Vcc[V]

Datasheet

9/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

Figure 18. Start condition setup time tSU:STA

Figure 19. Input data hold time tHD:DAT(HIGH)

Figure 20. Input data hold time tHD:DAT(LOW)

Figure 21. Input data setup time tSU:DAT(HIGH)

●Typical Performance Curves‐Continued

-200

-150

-100

-50

0

50

0123 4 56

Vcc[V]

tHD:DAT(HIGH)[ns]

SPEC1, 2

Ta=-40℃

Ta=25℃

Ta=105℃

0

1

2

3

4

5

6

0123456

Vcc[V]

tSU:STA[μs]

SPEC2

SPEC1

Ta=-40℃

Ta=25℃

Ta=105℃

-200

-150

-100

-50

0

50

0 1 2 3 4 5 6

tHD:DAT(LOW)[ns]

SPEC1, 2

Ta=-40℃

Ta=105℃

Ta=25℃

Vcc[V]

-200

-100

0

100

200

300

0123 4 56

Vcc[V]

tSU:DAT(HIGH)[ns]

Ta=105℃

Ta=25℃

Ta=-40℃

SPEC1

SPEC2

Datasheet

10/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

Figure 22. Input data setup time tSU:DAT(LOW)

Figure 23. Output data delay time tPD0

Figure 24. Output data delay time tPD1

Figure 25. Bus release time before transfer start tBUF

●Typical Performance Curves‐Continued

-200

-100

0

100

200

300

0 1 2 3 4 5 6

Vcc[V]

tSU:DAT(LOW)[ns]

Ta=-40℃

Ta=105℃

Ta=25℃

SPEC1

SPEC2

0

1

2

3

4

5

0123 4 56

Vcc[V]

tBUF[μs]

SPEC2

SPEC1

Ta=-40℃

Ta=25℃

Ta=105℃

0

1

2

3

4

0123456

Vcc[V

]

tPD0[μs]

Ta=105

℃

Ta=25

℃

Ta=-40

℃

SPEC

2

SPEC

1

SPEC

2

SPEC

1

0

1

2

3

4

0 1 2 3 4 5 6

Vcc[V]

tPD1[μs]

SPEC1

SPEC2

Ta=-40℃

Ta=25℃

Ta=105℃

SPEC1

Datasheet

11/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

Figure 28. Noise removal valid time tI(SCL L)

Figure 29. Noise removal valid time tI(SDA H)

Figure 26. Internal write cycle time tWR

Figure 27. Noise removal valid time tI(SCL H)

●Typical Performance Curves‐Continued

0

0.1

0.2

0.3

0.4

0.5

0.6

0 1 2 3 4 5 6

Vcc

[

V

]

tI(SCL L)[μs]

Ta=-40℃

Ta=25℃ Ta=105℃

SPEC1

0

1

2

3

4

5

6

0 1 2 3 4 5 6

Vcc[V]

tWR[ms]

SPEC1, 2

Ta=25℃

Ta=-40℃

Ta=105℃

0

0.1

0.2

0.3

0.4

0.5

0.6

0123 4 56

Vcc[V]

tI(SCL H)[μs]

SPEC1, 2

Ta=-40℃

Ta=25℃

Ta=105℃

0

0.1

0.2

0.3

0.4

0.5

0.6

0123 4 56

Vcc[V]

tI(SDA H)[μs]

SPEC1, 2

Ta=25℃Ta=-40℃

Ta=105℃

Datasheet

12/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

Figure 30. Noise removal valid time tI(SDA L)

Figure 31. WP setup time tSU:WP

Figure 32. WP valid time tHIGH:WP

●Typical Performance Curves‐Continued

0

0.1

0.2

0.3

0.4

0.5

0.6

0 1 2 3 4 5 6

tI(SDA L)[μs]

SPEC1

Ta=-40℃

Ta=105℃

Ta=25℃

Vcc[V]

-0.6

-0.4

-0.2

0

0123 4 56

Vcc[V]

tSU:WP[μs]

SPEC1, 2

Ta=105℃

Ta=-40℃

Ta=25℃

0

0.2

0.4

0.6

0.8

1

1.2

0 1 2 3 4 5 6

Vcc[V]

tHIGH:WP[μs]

SPEC1, 2

Ta=-40℃

Ta=25℃

Ta=105℃

Datasheet

13/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●I2C BUS Communication

○I2C BUS data communication

I2C BUS data communication starts by start condition input, and ends by stop con ditio n input. Data is always 8bit long, and

acknowledge is al ways requir ed after each byte. I2C BUS carries out data transmission with plural devices connected by

2 communication lines of serial data (SDA) and serial clock (SCL).

Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is

controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during

data communication is called “transmitter”, and the device that receives data is called “receiver”.

○Start condition (Start bit recognition)

・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL

is 'HIGH' is necessary.

・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition

is satisfied, any command is executed.

○Stop condition (stop bit recongnition)

・Each command can be ended b y SDA ris ing from 'LOW ' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'

○Acknowledge (ACK) signal

・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In

master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data

output of readcommand) at the transmitter (sending) side releases the bus after output of 8bit data.

・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read

command) at the receiver (receiving) side s ets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK

signal) showing that it has received the 8bit data.

・This IC, after recognizing start condition a nd slave address (8bit), outputs ackno wledge signal (ACK signal) 'LOW'.

・Each write operation outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write

data).

・Each read operation outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW' .

・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this

IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and

recognizes stop condition (stop bit), and ends read operation. And this IC gets in status.

○Device addressing

・Output slave address after start condition from master.

・The significant 4 bits of slave address are used for recognizing a dev ice type. The device code of this IC is fixed to '1010'.

・Next slave addresses (A2 A1 A0 --- device addr ess) are for selecting devices, and plural ones can be used on a same

bus according to the number of device addresses.

・The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read oper ation, and is

as shown below.

Setting R / W to 0 ------- write (setting 0 to word address setting of random read)

Setting R / W to 1 ------- read

Type Slave address

Maximum number of

connected buses

BR24A01A-WM 1 0 1 0 A2 A1 A0 R/W

― 8

BR24A02-WM 1 0 1 0 A2 A1 A0 R/W

― 8

BR24A04-WM 1 0 1 0 A2 A1 PS R/W

― 4

BR24A08-WM 1 0 1 0 A2 P1 P0 R/W

― 2

BR24A16-WM 1 0 1 0 P2 P1 P0 R/W

― 1

BR24A32-WM 1 0 1 0 A2 A1 A0 R/W

― 8

BR24A64-WM 1 0 1 0 A2 A1 A0 R/W

― 8

PS, P0 to P2 are page select bits.

Note) Up to 4 units BR24A04-WM, up to 2 units of BR24A08-WM, and one unit of BR24A16-WM can be connected.

Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.

Figure 33. Data transfer timing

1

2

1

3

1

4

1

8

1

6

1

5

BR24A01A-WM

BR24A02-WM

BR24A04-WM

BR24A08-WM

BR24A16-WM

BR24A32-WM

BR24A64-WM

A0

1

7

A1

A2

GND

Vcc

WP

SCL

SDA

89 89 89

S P

condition condition

ACK STOPACKDATA DATAADDRES

S

START R/W ACK

1-7

SDA

SCL 1-7 1-7

Datasheet

14/28 TSZ02201-0R1R0G100140-1-2

www.rohm.com

TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Write Command

○Write cycle

・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous

data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is

specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24A32 / A64-WM)

・Data is written to the address designated by word address (n-th address)

・By issuing stop bit after 8bit data input, write to memor y cell ins ide starts.

・When internal write is started, command is not accepted for tWR (5ms at maximum).

・By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24A01A-WM, BR24A02-WM）

: Up to 16bytes (BR24A04-WM, BR24A08-WM,BR24A16-WM）

: Up to 32bytes (BR24A32-WM, BR24A64-WM

And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.

(Refer to "Internal address increment" in Page 15.)

・As for page write cycle of BR24A01A-WM and BR24A02-WM, after the significant 5 bits (4 significant bits in

BR24A01A-WM) of word address are designated arbitra rily, and as for page write command of BR24A04-WM,

BR24A08-WM, and BR24 A1 6-WM, after page select bit (PS) of slave address is designated arbitrarily , by continuing data

input of 2 bytes o r mo re , the ad dress of insign ifican t 4 bits (insignificant 3 bit in BR24A01A-WM, and BR24A02-WM) is

incremented internally, and data up to 16 bytes (up to 8 bytes in BR24A01A-WM and BR24A02-WM) can be written.

・As for page write cycle of BR24A32-WM and BR24A64-WM, after the significant 7 bits (in the case of BR24A32-WM) of

word address, or the significant 8 bits (in the case of BR24A64-WM) of word address are designated arbitrarily, by continuing data

input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

ADDRESS(n) DAT

A

(n)

SDA

LINE

A

C

K

A

C

K

DATA(n+15)

A

C

K

SLAVE

ADDRESS

10 0

1A0 A1 A2 WA

7 D0D7 D0

WA

0

Note) *1

*2

A1 A2 WA

7 D7

1 1 0 0

W

R

I

T

E

S

T

A

R

T

R

/

W

S

T

O

P

WORD

ADDRESS DATA

SLAVE

ADDRESS

A0 WA

0 D0

A

C

K

SDA

LINE

A

C

K

A

C

K

Note) *1

Figure 34. Byte write cycle (BR24A01A/02/04/08/16-WM)

*1 As for WA7, BR24A01A-WM becomes Don’t care.

A1 A2 1 1 0 0

W

R

I

T

E

S

T

A

R

T

R

/

W

S

T

O

P

1st WORD

ADDRESS DATA

SLAVE

ADDRESS

A0 D0

A

C

K

SDA

LINE

A

C

K

A

C

K

Note)

WA

12 WA

11

* WA

0

A

C

K

2nd WORD

ADDRESS

D7

*1

* * *1 As for WA12, BR24A32-WM becomes Don’t care.

Figure 35. Byte write cycle (BR24A32/64-WM)

*1 As for WA7, BR24A01A-WM becomes Don’t care.

*2 As for BR24A01A/02-WM become (n+7).

Figure 36. Page write cycle (BR24A01A/02/04/08/16-WM)

Figure 37. Page write cycle (BR24A32/64-WM)

*1 As for WA12, BR24A32-WM becomes Don’t care.

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

1st WORD

ADDRESS(n)

SDA

LINE

A

C

K

A

C

K

DATA(n+31)

A

C

K

SLAVE

ADDRESS

10 0

1A0 A1 A2 D0

Note) *1

DATA(n)

D0D7

A

C

K

2nd WOR D

ADDRESS(n)

WA

0

WA

12 WA

11

* * *

Note)

10 0

1A0

A1

A2

*1 *2 *3

Figure 38. Difference of slave address of each

*1 In BR24A16-WM, A2 becomes P2.

*2 In BR24A08-WM, BR24A16-WM, A1 become P1.

*3 In BR24A04-WM, A0 becomes PS, and in

BR24A08-WM and

Datasheet

15/28 TSZ02201-0R1R0G100140-1-2

www.rohm.com

TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

○Notes on write cycle continuous input

○Notes on page write cycle

List of numbers of page write

Number of Pages 8Byte 16Byte 32Byte

Product

number BR24A01A-WM

BR24A02-WM

BR24A04-WM

BR24A08-WM

BR24A16-WM

BR24A32-WM

BR24A64-WM

The above numbers are maximum bytes for respective types.

Any bytes below these can be written.

In the case BR24A02-WM, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write.

It does not stand 5ms at maximum × 8byte=40ms(Max.).

○Internal address increment

Page write mode (in the case of BR24A02-WM)

For example, when it is started from address 06h, therefore, increment is made as below,

06h → 07h → 00h → 01h ---, which please note.

*06h･･･06 in hexadecimal, therefore, 00000110 becomes a binary number.

○Write protect (WP) terminal

・Write protect (WP) function

When WP te rminal is set VCC (H level), dat a rew rite of all addresses is prohibited. When it is set GND (L level), data rew rite of

all address is enabled. Be sure to connect this terminal to VCC or GND, or control it to H level or L level. Do not use it open.

At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.

During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

ADDRESS（ｎ） DATA(n)

SDA

LINE

A

C

K

DATA(n+7)

A

C

K

SLAVE

ADDRESS

10 0 1A0 A1 A2 WA

7

D0D7 D0

*1

A

C

K

Note)

WA

0 1 100

Next command

tWR(maximum : 5ms)

Command is not accepted for this period.

At STOP (stop bit),

write starts.

*2

*3

S

T

A

R

T

*1 BR24A01A-WM becomes Don’t care.

*2 BR24A04-WM, BR24A08-W, and BR24A16-WM become (n+15).

*3 BR24A32-WM and BR24A64-WM become (n+31).

10 0

1A0

A1

A2

*1 *2 *3

Figure 40. Difference of each type of slave address

Figure 39. Page write cycle

*1 In BR24A16-WM, A2 becomes P2.

*2 In BR24A08-WM, BR24A16-WM, A1 become P1.

*3 In BR24A04-WM, A0 becomes PS, and in

BR24A08-WM and in BR24A16-WM, A0 becomes P0.

Note)

WA7 ----- WA4 WA3 WA2 WA1 WA0

0 ----- 0 0 0 0 0

0 ----- 0 0 0 0 1

0 ----- 0 0 0 1 0

0 ----- 0 0 1 1 0

0 ----- 0 0 1 1 1

0 ----- 0 0 0 0 0

---------

06h

Significant bit is fixed.

No digit up

Increment

Datasheet

16/28 TSZ02201-0R1R0G100140-1-2

www.rohm.com

TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Read Command

○Read cycle

Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.

Random read cycle is a command to read d ata b y designating address, and is used generally.

Current read cycle is a command to read data of internal address register without designating address, and is used when

to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be

read in succession.

・In random read cycle, data of designated word address can be read.

・When the command just before current read cycle is random read cycle, current read cycle (each including sequential

read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.

・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address

data can be read in succession.

・Read cycle is ended by stop condition where 'H ' is input to ACK si gnal after D0 and SDA signal is started a t SCL signal 'H ' .

・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next d ata is output.

Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop cond ition to

input 'H' to ACK signal after D0, and to start SDA at SCL signal ' H' .

・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitr ary D0 and SDA is started at SCL

signal 'H'.

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

A D D R E S S(n )

SDA

LINE

A

C

K

A

C

K

DATA(n)

A

C

K

SLAVE

ADDRESS

10 0 1 A0 A1 A2 WA

7 A0 D0

SLAVE

ADDRESS

10 0

1A1A2

S

T

A

R

T

D7

R

/

W

R

E

A

D

WA

0

N

ote

)

*1

It is necessary to input 'H' to

the last ACK.

Figure 41. Random read cycle (BR24A01A/02/04/08/16-WM)

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

1st WORD

ADDRESS（ｎ）

SDA

LINE

A

C

K

A

C

K

DATA(n)

A

C

K

SLAVE

ADDRESS

10 0

1A0 A1

A2 D7 D0

*

2nd WORD

ADDRESS（ｎ）

A

C

K

S

T

A

R

T

SLAVE

ADDRESS

100

1A2

A1

R

/

W

R

E

A

D

A0

WA

0

Note) *1

WA

12

WA

11

**

Figure 42. Random read cycle (BR24A32/64 -WM) *1 As for WA12, BR24A32-WM become Don’t care.

*1 As for WA7, BR24A01A-WM become Don’t care.

S

T

A

R

T

S

T

O

P

SDA

LINE

A

C

K

D A T A (n )

A

C

K

SLAVE

ADDRESS

10 0 1 A0 A1 A2 D0 D7

R

/

W

R

E

A

D

Note)

Figure 43. Current read cycle

It is necessary to input 'H' to

the last ACK.

R

E

A

D

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

DATA(n)

SDA

LINE

A

C

K

A

C

K

DATA(n+x)

A

C

K

SLAVE

ADDRESS

10 0

1A0

A1

A2 D0 D7 D0D7

Note）

Figure 44. Sequential read cycle (in the cas e of current read cycle)

*1 In BR24A16-WM, A2 becomes P2.

*2 In BR24A08-WM, BR24A16-WM, A1 become P1.

*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM

and BR24A16-WM, A0 becomes P0.

10 0

1A0

A1

A2

*1 *2 *3

Note)

Figure 45. Difference of slave address of each t ype

Datasheet

17/28 TSZ02201-0R1R0G100140-1-2

www.rohm.com

TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Software reset

Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset

has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Figure 46(a), Figure 46(b), and Figure 46(c).)

In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'

level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading

to instantaneous power failure of system power source or influence upon d evices.

●Acknowledge polling

During internal write e xec ution, all input commands are ignored, therefore ACK is not sent back. During internal automatic

write execution after write cycle input, next command (slav e address) is sent, and if the first ACK signal sends back 'L', then

it means end of write operation, while if it sends back 'H', it means now in writing. By use of ackno wledge poll in g, next

command can be executed without waiting for tWR = 5ms.

When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if

ACK signal sends back 'L', then execute word address input and data output and so forth.

Figure 47. Case to continuously write by acknowledge polling

1 2 13

14

SCL

Dummy clock×14 Start×2

Figure 46-(a) The case of dummy clock +START+START+ command input

タト

※ Start command from START input.

2

1 8 9

Dummy clock×9 Start

Figure 46-(b) The case of START +9 dummy clocks +START+ command input

Start

Normal command

Start×9

SDA

1 2 3 8 9

7

Figure 46-(c) START×9+ command input

Normal command

SCL

SDA

SCL

SDA

S

T

A

R

T

First write command

A

C

K

H

Slave

address

Slave

address

Write command

During internal write,

ACK = HIGH is sent back.

tWR

Second write command

S

T

A

R

T

S

T

A

R

T

S

T

O

P

S

T

O

P

A

C

K

H

A

C

K

H

A

C

K

L

A

C

K

L

Slave

address

Word

address

…

A

C

K

L

Slave

address Data

After completion of internal write,

ACK=LOW is sent back, so input next

word address and data in succession.

tWR

S

T

A

R

T

S

T

A

R

T

S

T

O

P

A

C

K

H

A

C

K

L

Datasheet

18/28 TSZ02201-0R1R0G100140-1-2

www.rohm.com

TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●WP valid timing (write cancel)

WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP

valid timing. During write cycl e execution, in cancel valid area, b y setting WP='H', write cycle can be cancelled. In both byte

write cycle and page write cycle, the area from the first start condition of co mmand to the rise of clock to taken in D0 of

data(in page write cycle, the first byte data) is cancel invalid area.

WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise

of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,

write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Figure 48.)

After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).

●Command cancel by start condition and stop condition

During command input, by continuously inputting start condition and stop condition, command ca n be cancelled.

(Refer to Figure 49.)

However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop

condition cannot be input, so reset is not availab le. Therefore, execute software reset. And when command is cancell ed by

start, stop condition, during random read cycle, sequential r ead cycle, or current read cycle, internal setting address is not

determined, therefore, it is not possible to carry out current read cycle in succession. When to carr y out read c ycle in

succession, carry out random read cycle.

Figure 48. WP valid timing

Figure 49. Case of cancel by start, stop condition during slave address input

SCL

SDA 1 1

0 0

Start condition Stop condition

WP

WP cancels invalid area WP cancels valid area

Write forced end

Data is not written. Data not guaranteed

S

T

A

R

T

A

C

K

L

・Rise of D0 taken clock

SCL

D0 ACK

Enlarged view

SCL

SDA Enlarged view

ACK

D0

・Rise of SDA

SDA D7 D6 D5D4 D3 D2 D1 D0 Data tWR

SDA D1

A

C

K

L

A

C

K

L

A

C

K

L

S

T

O

P

Word

address

Slave

address

Datasheet

19/28 TSZ02201-0R1R0G100140-1-2

www.rohm.com

TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●I/O peripheral circuit

○Pull up resistance of SDA terminal

SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to

this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, operating frequency is

limited. The smaller the RPU, the larger the consumption current at operation.

○Maximum value of RPU

The maximum value of RPU is determined by the following factors.

(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.

And AC timing should be satisfied even when SDA rise time is late.

(2)The bus electric potential○

A to be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA

bus and RPU should sufficientl y secure the i nput 'H' level (VIH) of microcontroller and EEPROM including recommended

noise margin 0.2 VCC.

○Minimum value of RPU

The minimum value of RPU is determined by the following factors.

(1)When IC outputs LOW, it should be satisfied that V OLMAX=0.4V and IOLMAX=3mA.

(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise

margin 0.1 VCC.

VOLMAX ≦ VIL-0.1 VCC

Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3 VCC

from (1)

Therefore, the condition (2) is satisfied.

○Pull up resistance of SCL terminal

When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes

'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ to several ten kΩ is recommended in

consideration of drive perform ance of output port of microcontroller.

●A0, A1, A2, WP process

○Process of device address terminals (A0,A1,A2)

Check whether the set device address coincides with device address input sent from the master side or not, and select

one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or VCC or GND. And,

pins (N, C, PIN) not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.

Types with N.C.PIN BR24A16/F/FJ -WM A0, A1, A2

BR24A08/F/FJ-WM A0, A1

BR24A04/F/FJ -WM A0

○Process of WP terminal

WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only REA D is available and

WRITE of all address is prohibited. In the case of 'L' , both are available. In the case of use it as an ROM, it is

recommended to connect it to pull up or VCC. In the case to use both READ and WRITE, control WP terminal or connect it

to pull down or GND.

RPU ≧ 3－0.4

3×10 -3

≧ 867 [Ω]

And

VOL = 0.4 [V]

VIL = 0.3×3

= 0.9 [V]

∴ R

PU =

Ex. ) When VCC =3V, IL=10μA, VIH=0.7 VCC,

from (2)

0.8×3- 0.7×3

10×10-6

RPU ≦

≦ 300 [kΩ]

0.8Vcc - VIH

IL

Vcc - ILRPU - 0.2Vcc ≧ V

IH

VC-VOL

IOL

VCC-VOL

RPU ≦ I

OL ∴ R

PU ≦

バスライン容量

CBUS

Figure 50. I/O circuit diagram

RPU A

BR24AXX

SDA terminal

IL IL

Microcontroller

Bus line

capacity

CBUS

Datasheet

20/28 TSZ02201-0R1R0G100140-1-2

www.rohm.com

TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Cautions on microcontroller connection

○Rs

In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of

tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.

This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON

simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open

drain input/output, Rs can be used.

○Maximum value of Rs

The maximum value of Rs is determin ed by the following relations.

(1)SDA rise time to be determined by the capacit y (CBUS) of bus line of Rpu and SDA should be tR or below.

And AC timing should be satisfied even when SDA rise time is late.

(2)The bus electric potential ○

A to be determined by Rpu a nd Rs the moment when EEPROM outputs 'L' to SDA bus

should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1 VCC.

Figure 53. I/O circuit diagram

○Minimum value of Rs

The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in po wer source

line, and instantaneous power failure of po wer source may occur. When allo wable over current is defined as I, the follo wing

relation must be satisfied. Determine the allowable current in consideration of impedance of po wer source line in set and so

forth. Set the over current to EEPROM 10mA or below.

Figure 54. I/O circuit diagram

Microcontroller EEPROM

'L' output

R

S

R

PU

'H' output

Over currentⅠ

VCC

RS

VCC

I

≧300［Ω］

∴

Example）When VCC=3V, I=10mA

RS≧3

10×10-3

≦I

RS≧

Example）When VCC=3V,　VIL=0.3VCC,　VOL=0.4V,　RPU=20kΩ,

≦

VIL－VOL－0.1VCC

1.1VCC－VIL

1.1×3－0.3×3

0.3×3－0.4－0.1×3

RS

1.67［kΩ］

RPU+RS

(VCC－VOL)×RS+VOL+0.1VCC≦VIL

RS≦

from(2),

RPU

∴×

≦×20×103

RPU

Microcontroller

RS

EEPROM

Figure 51. I/O circuit diagram

Figure 52. Input / output collision timing

Over current flows to SDA line by 'H'

output of microcontroller and 'L'

output of EEPROM.

A

CK

'L' output of EEPROM

'H' output of microcontroller

SCL

SDA

RPU

Microcontroller

RS

EEPROM

IOL

A

Bus line

capacity CBUS

VOL

VCC

VIL

Datasheet

21/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●I2C BUS input / output circuit

○Input (A0,A2,SCL)

○Input / output (SDA)

○Input (A1, WP)

●Notes on power ON

At power on, in IC internal circuit and set, VCC rises through unstable low voltage area, and IC inside is not completely reset,

and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the operation,

observe the following conditions at power on.

1. Set SDA = 'H' and SCL ='L' or 'H'

2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.

Recommended conditions of tR, tOFF,Vbot

tR tOFF Vbot

10ms or below 10ms or longer 0.3V or below

100ms or below 10ms or longer 0.2V or below

Figure 55. Input pin circuit diagram

Figure 56. Input / output pin circuit diagram

Figure 57. Input pin circuit diagram

tOFF

tR

Vbot

0

VCC

Figure 58. Rise waveform diagram

Datasheet

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

3. Set SDA and SCL so as not to become 'Hi-Z'.

When the above conditions 1 and 2 cannot be observed, take the following countermeasures.

a) In the case when the above condition 1 c annot be observed. When SDA becomes 'L' at power on.

→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.

b) In the case when the above condition 2 cannot be observed.

→After power source becomes stable, execute software reset(Page 17).

c) In the case when the above conditions 1 and 2 cannot be observed.

→Carry out a), and then carry out b).

●Low voltage malfunction prevention function

LVCC circuit prevents data rewrite operation at lo w power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below,

it prevent data rewrite.

●VCC noise countermeasures

○Bypass capacitor

When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is

recommended to attach a by pass capacitor (0 .1μF) betw een IC VCC and GND. At that moment, attach it as close to IC as po ssible.

And, it is also recommended to attach a bypass capacitor bet ween board VCC and GND.

●Note of use

(1) Described numeric values and data are design representative values, and the values a r e not guaranteed.

(2) We believe that application circuit examples are recommend able, however, in actual use, confirm characteristics further

sufficiently. In the case of use b y changin g the fixed number of external parts, make your decision with sufficient margin

in consideration of static characteristics and transition characteristics an d fluctuations of external parts and our LSI.

(3) Absolute maximum ratings

If the absolute maximum ratings such as impressed voltage and operation temperature range and so forth are exceeded,

LSI may be destructed. Do not impress voltage and temperature exceedin g the abso lute maximum ratings. In the case of

fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that

conditions exceeding the absolute maximum ratings should not be impressed to LSI.

(4)GND electric potential

Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is lower than

that of GND terminal.

(5)Terminal design

In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.

(6)Terminal to terminal shortcircuit and wrong packaging

When to package LSI onto a board, pay suff icient attention to LSI direction and displacement. Wrong packaging may

destruct LSI. And in the case of shortcircuit bet ween LSI terminals and terminals and power source, terminal and GND

owing to foreign matter, LSI may be destructed.

(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.

tLOW

tSU:DAT

tDH

A

fter Vcc becomes stable

SCL

VCC

SDA

After Vcc becomes stable tSU:DAT

Figure 59. When SCL= 'H' and SDA= 'L' Figure 60. When SCL='L' and SDA='L'

Datasheet

23/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Ordering Information

Product Code Description

B R 2 4 A x x x x x - WM x x

BUS type

24: I2C

Operating temperature

-40℃ to +105℃

Capacity

01A=1K 08=8K 64=64K

02=2K 16=16K

04=4K 32=32K

Package

F : SOP8

FJ : SOP-J8

FVM : MSOP8

W : Double Cell

M : For Automotive Application

Packaging and formin g sp ecificatio n

E2 : Embossed tape and reel

(SOP8,SOP-J8)

TR : Embossed tape and reel

(MSOP8)

●Lineup

Capacity Package

Type Quantity

1K SOP8 Reel of 2500

SOP-J8 Reel of 2500

2K SOP8 Reel of 2500

SOP-J8 Reel of 2500

MSOP8 Reel of 3000

4K SOP8 Reel of 2500

SOP-J8 Reel of 2500

8K SOP8 Reel of 2500

SOP-J8 Reel of 2500

16K SOP8 Reel of 2500

SOP-J8 Reel of 2500

32K SOP8 Reel of 2500

64K SOP8 Reel of 2500

Datasheet

24/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Physical Dimension Tape and Reel Information

∗

Order quantity needs to be multiple of the minimum quantity.

Embossed carrier tapeTape

Quantity

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

2500pcs

E2

()

Direction of feed

Reel 1pin

(Unit : mm)

SOP8

0.9±0.15

0.3MIN

4

°

+

6

°

−

4

°

0.17 +0.1

-

0.05

0.595

6

43

8

2

5

1

7

5.0±0.2

6.2±0.3

4.4±0.2

(MAX 5.35 include BURR)

1.27

0.11

0.42±0.1

1.5±0.1

S

0.1 S

Datasheet

25/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Physical Dimension Tape and Reel Information‐Continued

∗

Order quantity needs to be multiple of the minimum quantity.

Embossed carrier tapeTape

Quantity

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

2500pcs

E2

()

Direction of feed

Reel 1pin

(Unit : mm)

SOP-J8

4°+6°

−4°

0.2±0.1

0.45MIN

234

5678

1

4.9±0.2

0.545

3.9±0.2

6.0±0.3

(MAX 5.25 include BURR)

0.42±0.1

1.27

0.175

1.375±0.1

0.1 S

S

Datasheet

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Physical Dimension Tape and Reel Information‐Continued

(Unit : mm)

MSOP8

0.08 S

S

4.0±0.2

8

3

2.8±0.1

1

6

2.9±0.1

0.475

4

57

(MAX 3.25 include BURR)

2

1PIN MARK

0.9MAX

0.75±0.05

0.65

0.08±0.05

0.22 +0.05

–0.04

0.6±0.2

0.29±0.15

0.145 +0.05

–0.03

4°

+6°

−4°

Direction of feed

Reel ∗

Order quantity needs to be multiple of the minimum quantity.

Embossed carrier tapeTape

Quantity

Direction

of feed

The direction is the 1pin of product is at the upper right when you hold

reel on the left hand and you pull out the tape on the right hand

3000pcs

TR

()

1pin

Datasheet

27/28 TSZ02201-0R1R0G100140-1-2

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TSZ22111・15・001

BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Marking Diagrams

●Marking Information

Capacity Product

Name

Marking Package Type

1K A01A SOP8

SOP-J8

2K A02 SOP8

SOP-J8

MSOP8

4K A04 SOP8

SOP-J8

8K A08 SOP8

SOP-J8

16K A16 SOP8

SOP-J8

32K A32 SOP8

64K A64 SOP8

SOP8(TOP VIEW)

Part Number Marking

LOT Numbe

r

1PIN MARK

SOP-J8(TOP VIEW)

Part Number Marking

LOT Numbe

r

1PIN MARK

MSOP8(TOP VIEW)

Part Number Marking

LOT Number

1PIN MARK

Datasheet

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BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)

●Revision History

Date Revision Changes

31.Aug.2012 001 New Release

6.Nov.2013 002

P.1 Added AEC-Q100 Qualified

P.2 Changed U nit of Pd

P.23 Updated Product Code Description

Datasheet

Notice – SS Rev.001

Notice

Precaution on using ROHM Products

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred b y you or third parti es arising from the use of any

ROHM’s Products for Specific Applications.

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe d esign against the physical injur y, damage to any property, which

a failure or malfunction of our Products may cause. T he following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expens es or losses arising from the

use of any ROHM’s Products under an y special or extraordinary envir onments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product perform ance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-produci ng comp onents, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flu x (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subj ect to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding nor mal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Po wer Dissipation (P d) depe nding on Ambient temperature (T a). When us ed in sealed area, confirm the actual

ambient temperature.

8. Confirm that o peration temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for fai lure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halog enous (chlori ne, bromin e, etc.) flux is used, the residue of flux ma y negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the

ROHM representative in advance.

For details, please refer to ROHM Mounting specificati on

Datasheet

Notice – SS Rev.001

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own indepe ndent verificati on and judgme nt in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for an y damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please t ake special care under dry con dition (e.g. Grounding of human body / equipment / sol der iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperatur e / humidity control).

Precaution for Storage / Transportati on

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderabil ity of products out of recommended storage time perio d

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommen de d storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Pro ducts within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

QR code printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products pl ease dispose them properly using a n authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,

please consult with ROHM representative in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoi ng information or data will not infringe any int ellectual property rights or any

other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable

for infringement of any intellectual property rights or other damages arising from use of such information or data.:

2. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the information contained in this document.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including b ut not limited to, the development of m ass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated compani es or third parties.

Datasheet

Notice – WE Rev.001

General Precaution

1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.

ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any

ROHM’s Products against warning, caution or note contained in this document.

2. All information contained in this document is current as of the issuing date and subject to change without any prior

notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales

representative.

3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all

information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or

liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or

concerning such information.