ABT Ratings, Specifications and Waveforms Definition of Terms DC Characteristics Currents: Positive current is defined as conventional current flow into a device. Negative current is defined as current flow out of a device. All current limits are specified as absolute values. Voltages: All voltages are referenced to the ground pin. All voltage limits are specified as absolute values. IBVI Input HIGH Current (Breakdown Test). The current flowing into an input when a specified Absolute MAX HIGH voltage is applied to that input. IBVIT I/O Pin HIGH Current (Breakdown Test). The current flowing into a disabled (output is high impedance) I/O pin when a specified Absolute MAX HIGH voltage is applied to that I/O pin. ICEX Output HIGH Leakage Current. The current flowing into a HIGH output due to the application of a specified HIGH voltage to that output. ICCH The current flowing into the VCC supply terminal when the outputs are in the HIGH state. ICCL The current flowing into the VCC supply terminal when the outputs are in the LOW state. ICCT Additional ICC due to TTL HIGH levels forced on CMOS inputs. ICCZ The current flowing into the VCC supply terminal when the outputs are disabled (high impedance). IIL Input LOW Current. The current flowing out of an input when a specified LOW voltage is applied to that input. IIH Input HIGH Current. The current flowing into an input when a specified HIGH voltage is applied to that input. IOH Output HIGH Current. The current flowing out of an output which is in the HIGH state. IOL Output LOW Current. The current flowing into an output which is in the LOW state. IOS Output Short Circuit Current. The current flowing out of an output in the HIGH state when that output is shorted to ground (or other specified potential). IOZL Output OFF current (LOW). The current flowing out of a disabled TRI-STATE (R) output when a specified LOW voltage is applied to that output. IOZH Output OFF current (HIGH). The current flowing into a disabled TRI-STATE output when a specified HIGH voltage is applied to that output. IZZ Bus Drainage. The current flowing into an output or I/O pin when a specified HIGH level is applied to the output or I/O pin of a power-down device. VCC Supply Voltage. The range of power supply voltages over which the device is guaranteed to operate. VCD Input Clamp Diode Voltage. The voltage on an input (-) when a specified current is pulled from that input. VID Input Breakdown Voltage. The voltage on an input of a powered-down device when a specified current is forced into that input. VIH Input HIGH Voltage. The minimum input voltage that is recognized as a DC HIGH-level. VIHD Dynamic Input HIGH Voltage. The minimum input voltage that is recognized as a HIGH-level during a Multiple Output Switching (MOS) operation. VIL Input LOW Voltage. The maximum input voltage that is recognized as a DC LOW-level. VILD Dynamic Input LOW Voltage. The maximum input voltage that is recognized as a LOW-level during Multiple Output Switching (MOS) operation. VOH Output HIGH Voltage. The voltage at an output conditioned HIGH with a specified output load and VCC supply voltage. Minimum (valley) voltage induced on a static HIGH high output during switching of other outputs. VOHV VOL VOLP VOLV Output LOW Voltage. The voltage at an output conditioned LOW with a specified output load and VCC supply voltage. Maximum (peak) voltage induced on a static LOW output during switching of other outputs. Minimum (valley) voltage induced on a static LOW output during switching of other outputs. AC Characteristics ft Maximum Transistor Operating Frequency -- The frequency at which the gain of the transistor has dropped by three decibels. fmax Toggle Frequency/Operating Frequency -- The maximum rate at which clock pulses may be applied to a sequential circuit. Above this frequency the device may cease to function. tPLH Propagation Delay Time -- The time between the specified reference points, normally 1.5V on the input and output voltage waveforms, with the output changing from the defined LOW level to the defined HIGH level. tPHL Propagation Delay Time -- The time between the specified reference points, normally 1.5V on the input and output voltage waveforms, with the output changing from the defined HIGH level to the defined LOW level. tw Pulse Width -- The time between 1.5V amplitude points of the leading and trailing edges of a pulse. th Hold Time -- The interval immediately following the active transition of the timing pulse (usually the clock pulse) or following the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure its continued recogni- TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. SigneticsTM is a trademark of Philips. (c) 1998 National Semiconductor Corporation MS100211 www.national.com ABT Ratings, Specifications and Waveforms August 1998 AC Characteristics Figure 2 describes the input pulse requirements necessary when testing ABT circuits. Figure 3 and Figure 5 show waveforms for all propagation delay and pulse width measurements while Figure 4 shows waveforms for TRI-STATE enable and disable times. The waveforms shown in Figure 6 describe setup, hold and recovery times. These diagrams define all input and output measure points used in testing ABT devices. (Continued) tion. A negative hold time indicates that the correct logic level may be released prior to the active transition of the timing pulse and still be recognized. ts Setup Time -- The interval immediately preceding the active transition of the timing pulse (usually the clock pulse) or preceding the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure its recognition. A negative setup time indicates that the correct logic level may be initiated sometime after the active transition of the timing pulse and still be recognized. AC Loading tPHZ Output Disable Time (of a TRI-STATE Output) from HIGH Level -- The time between the 1.5V level on the input and a voltage 0.3V below the steady state output HIGH level with the TRI-STATE output changing from the defined HIGH level to a high impedance (OFF) state. tPLZ Output Disable Time (of a TRI-STATE Output) from LOW Level -- The time between the 1.5V level on the input and a voltage 0.3V above the steady state output LOW level with the TRI-STATE output changing from the defined LOW level to a high impedance (OFF) state. tPZH Output Enable Time (of a TRI-STATE Output) to a HIGH Level -- The time between the 1.5V levels of the input and output voltage waveforms with the TRI-STATE output changing from a high impedance (OFF) state to a HIGH level. tPZL Output Enable Time (of a TRI-STATE Output) to a LOW Level -- The time between the 1.5V levels of the input and output voltage waveforms with the TRI-STATE output changing from a high impedance (OFF) state to a LOW levels. trec Recovery Time -- The time between the 1.5V level on the trailing edge of an asynchronous input control pulse and the same level on a synchronous input (clock) pulse such that the device will respond to the synchronous input. MS100211-9 *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load AC Loading and Waveforms Figure 1 shows the AC loading circuit used in characterizing and specifying propagation delays of all ABT devices, unless otherwise specified in the data sheet of a specific device. The value of the capacitive load (CL) is variable and is defined in the AC Electrical Characteristics. The 500 resistor to ground in Figure 1 is intended to slightly load the output and limit the quiescent HIGH-state voltage to about +3.5V. Also shown in Figure 1 is a second 500 resistor from the device output to a switch. For most measurements this switch is open; it is closed for measuring a device with open-collector outputs and for measuring one set of the Enable/Disable parameters (LOW-to-OFF and OFF-to-LOW) of a TRI-STATE output. With the switch closed, the pair of 500 resistors and the +7.0V supply establishes a quiescent HIGH level of +3.5V, which correlates with the HIGH level discussed in the preceding paragraph. www.national.com MS100211-10 Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 2. Test Input Signal Levels and Requirements 2 AC Waveforms MS100211-13 FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions MS100211-11 FIGURE 3. Propagation Delay, Pulse Width Waveforms MS100211-14 FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms MS100211-12 FIGURE 4. TRI-STATE Output HIGH and LOW Enable and Disable Times Skew Definitions and Examples Minimizing output skew is a key design criteria in today's high-speed clocking schemes, and National has incorporated skew specifications into the ABT family of devices. This section provides general definitions and examples of skew. CLOCK SKEW Skew is the variation of propagation delay differences between output clock signal(s). See Figure 8. Example: If signal appears at out #1 in 3 ns and in 4 ns at output #5, the skew is 1 ns. Without skew specifications, a designer must approximate timing uncertainties. Skew specifications have been created to help clock designers define output propagation delay differences within a given device, duty cycle and device-to-device delay differences. 3 www.national.com Skew Definitions and Examples (Continued) MS100211-15 FIGURE 7. Simultaneous Switching Test Circuit MS100211-16 FIGURE 8. Clock Output Skew SOURCES OF CLOCK SKEW Total system clock skew includes intrinsic and extrinsic skew. Intrinsic skew is defined as the differences in delays between the outputs of device(s). Extrinsic skew is defined as the differences in trace delays and loading conditions. MS100211-17 FIGURE 9. Sources of Clock Skew Example: 50 MHz Clock signal distribution on a PC Board. 50 MHz signals produces 20 ns clock cycles Total system skew budget = 10% of clock cycle* = 2 ns If extrinsic skew = 1 ns 2 ns - 1 ns Device skew (intrinsic skew) must be less than 1 ns! 1 ns *Clock Design Rule of thumb. CLOCK DUTY CYCLE * Clock Duty Cycle is a measure of the amount of time a signal is High or Low in a given clock cycle. MS100211-18 Duty Cycle = t/T * 100% FIGURE 10. Duty Cycle Calculation www.national.com 4 Skew Definitions and Examples tHIGH and tLOW are each 50% of the clock cycle therefore the clock signal has a Duty Cycle of 50/50%. (Continued) * Clock Signal Clock skew effects the Duty Cycle of a signal. Clock + Skew MS100211-20 FIGURE 12. Clock Skew MS100211-19 FIGURE 11. Clock Cycle Example: 50 MHz clock distribution on a PC board. Skew must be guaranteed less than 1 ns at 50 MHz to achieve 55/45% Duty Cycle requirements of core silicon! Example: TABLE 1. System Skew tHIGH tLOW Duty Cycle Frequency 50 MHz 0 ns 10 ns 10 ns 50/50% 50 MHz 2 ns 12 ns 8 ns 60/40% 50 MHz 1 ns 11 ns 9 ns 55/45% 33 MHz 2 ns 17 ns 15 ns 55/45% Ideal Duty Cycle (50/50%) occurs for zero skew. Note that at lower frequencies, the skew budget is not as tight and skew does not effect the Duty Cycle as severely as seen at higher frequencies. Definition of Parameters tOSLH, tOSHL (Common Edge Skew) tOSHL and tOSLH are parameters which describe the delay from one driver to another on the same chip. This specification is the worst-case number of the delta between the fastest to the slowest path on the same chip. An example of where this parameter is critical is the case of the cache controller and the CPU, where both units use the same transition of the clock. In order for the CPU and the controller to be synchronized, tOSLH/HL needs to be minimized. Definition tOSHL, tOSLH (Output Skew for High-to-Low Transitions): tOSHL = |tPHLMAX - tPHLMIN| Output Skew for Low-to-High Transitions: tOSLH = |tPLHMAX - tPLHMIN| Propagation delays are measured across the outputs of any given device. Example MS100211-21 FIGURE 13. tOSLH, tOSHL 5 www.national.com Definition of Parameters (Continued) tPS (Pin Skew or Transition Skew) tPS, describes opposite edge skews, i.e., the difference between the delay of the low-to-high transition and the high-to-low transition on the same pin. This parameter is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. Ideally this number needs to be 0 ns. Effectively, 0 ns means that there is no degradation of the input signal's Duty Cycle. Many of today's microprocessors require a minimum of a 45:55 percent Duty Cycle. System clock designers typically achieve this in one of two ways. The first method is with an expensive crystal oscillator which meets the 45:55 percent Duty Cycle requirement. An alternative approach is to use a less expensive crystal oscillator and implement a divide by two function. Some microprocessors have addressed this by internally performing the divide by two. Since Duty Cycle is defined as a percentage, the room for error becomes tighter as the system clock frequency increases. For example in a 25 MHz system clock with a 45:55 percent Duty Cycle requirement, tPS cannot exceed a maximum of 4 ns (tPLH of 18 ns and tPLH of 22 ns) and still meet the Duty Cycle requirement. However for a 50 MHz system clock with a 45:55 percent Duty Cycle requirement, tPS cannot exceed a maximum of 2 ns (tPLH of 9 ns and tPHL of 11 ns) and still meet the Duty Cycle requirement. This analysis assumes a perfect 50:50 percent Duty Cycle input signal. Definition tPS (Pin Skew or Transition Skew): tPS = |tPHL-t PLH| Example Both high-to-low and low-to-high propagation delays are measured at each output pin across the given device. MS100211-22 FIGURE 14. tPS Example: A 33 MHz, 50/50% duty cycle input signal would be degraded by 2.6% due to a tPS = 0.8 ns. (See Table and Illustration below.) Note: Output symmetry degradation also depends on input duty cycle. TABLE 2. Duty Cycle Degradation of 33 MHz f (MHz) 33 Input DC Input Device Output tIN TIN tPS tOUT TOUT DC (ns) (ns) (ns) (ns) (ns) Output % DC Input to Output 50%/50% 15.15/15.15 30.3 0.8 14.35/15.95 30.3 47.4%/52.6% 2.6% 45%/55% 13.6/16.6 30.3 1.5 12.1/18.1 30.3 39.9%/60.1% 5.1% MS100211-23 FIGURE 15. Pulse Width Degradation www.national.com 6 Case 1: Single Clock Driver Total Skew = Pin-to-Pin Skew U1 = tOSLH or tOSHL of U1 tOST (Opposite Edge Skew) tOST defines the difference between the fastest and the slowest of both transitions within a given chip. Given a specific system with two components, one being positive-edge triggered and one being negative-edge triggered, tOST helps to calculate the required delay elements if synchronization of the positive- and negative-clock edges is required. MS100211-27 MS100211-24 Definition tPV (Part Variation Skew): tPV = |tPu,v - tPx,y| where is any edge transition (high-to-low or low-to-high) measured from the outputs of any two devices. FIGURE 16. tOST Definition tOST (Opposite Edge Skew): tOST = |tPm-t Pn| where is any edge transition (high-to-low or low-to-high) measured between any two outputs (m or n) within any given device. Example MS100211-28 FIGURE 19. tPV Case 2: Distributed Clock Tree Total Skew (U2, U3) = Pin-to-Pin Skew (U1) Part-to-Part Skew (U2, U3) MS100211-25 FIGURE 17. tOST tPV (Part Variation Skew) tPV illustrates the distribution of propagation delays between the outputs of any two devices. Part-to-part skew, tPV, becomes a critical parameter as the driving scheme becomes more complicated. This usually applies to higher-end systems which go from single clock drivers to distributed clock trees to increase fanout (shown below). In a distributed clock tree, part-to-part skew between U2 and U3 must be minimized to optimize system clock frequency. In the case of the clock tree, the total skew becomes a function of tOSLH/HL of U1 plus tPV of U2 and U3. + Example MS100211-29 FIGURE 20. tPV MS100211-26 FIGURE 18. Clock Distribution 7 www.national.com Absolute Maximum Ratings DC Latchup Source Current (Note 1) Storage Temperature -65C to +150C Ambient Temperature under Bias -55C to +125C -55C to +175C Plastic -55C to +150C Free Air Ambient Temperature Military Ground Pin Input Current (Note 2) -30 mA to +5.0 mA -40C to +85C Supply Voltage -0.5V to +7.0V -0.5V to +7.0V -55C to +125C Commercial VCC Pin Potential to Input Voltage (Note 2) 10V Recommended Operating Conditions Junction Temperature under Bias Ceramic -500 mA Over Voltage Latchup (I/O) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Military +4.5V to +5.5V Commercial +4.5V to +5.5V Minimum Input Edge Rate (V/t) Data Input 50 mV/ns Enable Input Voltage Applied to Any Output 20 mV/ns Clock Input in the Disabled or Power-off State -0.5V to 5.5V in the HIGH State -0.5V to VCC 100 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics (except as noted on device datasheet) Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH VOL Min Typ Max Units 0.8 V -1.2 V Conditions VCC V Recognized HIGH Signal Min Recognized LOW Signal IIN = -18 mA Output HIGH 54ABT/74ABT 2.5 V Min Voltage 54ABT 2.0 V Min 74ABT 2.0 V Min V Min IOH = -3 mA IOH = -12 mA IOH = -32 mA IOL = 48 mA A Max IOL = 64 mA VIN = 2.7V 7 A Max VIN = VCC VIN = 7.0V 100 A Max VIN = 5.5V -5 A Max VIN = 0.5V V 0.0 VIN = 0.0V IID = 1.9 A A 0 - 5.5V 0 - 5.5V Output LOW 54ABT 0.55 Voltage 74ABT 0.55 IIH Input HIGH Current IBVI Input HIGH Current 5 5 Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) IIL Input LOW Current -5 VID Input Leakage Test IIH + IOZH Output Leakage Current IIL + IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX 50 All Other Pins Grounded VOUT = 2.7V; OE = 2.0V (I/O Pins) VOUT = 0.5V; OE = 2.0V (I/O Pins) VOUT = 0.0V -50 A -275 mA Max Output High Leakage Current 50 A Max IZZ Bus Drainage Test 100 A 0.0 VOUT = VCC VOUT = 5.5V; All Others GND ICCH Power Supply Current 50 A Max All Outputs HIGH ICCL Power Supply Current 30 mA Max ICCZ Power Supply Current 50 A Max All Outputs LOW VOUT = HIGH Z www.national.com 8 DC Electrical Characteristics (Continued) (except as noted on device datasheet) Symbol Parameter ICCT Additional ICC/Input Min Typ Max Units Outputs Enabled 2.5 mA Outputs TRI-STATE 2.5 mA Outputs TRI-STATE 50 A VCC Max Conditions VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND OE = VCC; VOUT = HIGH Z Multiple (Simultaneous) Output Switching Propagation Delays These tests are used to ensure compliance to the extended databook specifications and include active propagation delays, disable and enable times at 50 pF and 250 pF output loads. Multiple Output Switching Skew Performance data from the Multiple Output Switching propagation delay testing is analyzed to obtain information regarding output skew of an IC. FMAX (synchronous logic) FMAX determines the minimum frequency at which the device is guaranteed to operate for a clocked IC. This test is package and test environment sensitive. Pulse Width (synchronous logic) Pulse Width testing is used to define the minimum pulse duration that a flip-flop or latch input will accept and still function properly. This test is package and test environment sensitive. F-Toggle (asynchronous logic) F-Toggle is the minimum frequency at which the IC is guaranteed to function under multiple outputs switching condition with outputs operating in phase. This test is package and test environment sensitive. Characterization and Extended Test Specifications Philosophy During the National new product introduction process for logic IC's, a new ABT IC design will undergo a rigorous characterization to baseline its performance. This data is required to correlate with simulation models, determine product specifications, compare performance to other product, provide a feedback mechanism to the fabrication process, and for customer information. National's Logic IC characterizations are designed to get as much information as possible about the product and potential customer application performance. National's logic IC characterization methodology uses past knowledge of design performance, simulation, and process parametrics to determine what electrical parameters to characterize. Characterization samples are selected so that they have key process parametrics (e.g., Drive, Beta, Vtn, Vtp Leff, etc.) which have been shown to significantly affect device electrical parameters. Data is acquired and processed using statistical analysis software. Manufacturing test limits are then set using the knowledge of variations due to fabrication, package, tester, VCC , temperature, and condition. This allows product to be shipped on demand without problems or delays. The following are brief summaries of characterization tests performed. AC Dynamic (Noise) Characteristics VOLP, VOLV -- Ground Bounce (Quiet Output Switching) Measured parameters with 50 pF loading relate the amount that a static conditioned output will change in voltage under multiple outputs switching condition with outputs operating in phase. They are heavily influenced by the magnitude that VCC and Ground move internal to the IC. VILD, VIHD -- Dynamic Threshold Dynamic threshold measures the shift of an IC's input threshold due to noise generated while under multiple outputs switching condition with outputs operating in phase. This test is package and test environment sensitive. Input Edge Rate Test Summaries AC Electrical Characteristics Single Output Switching propagation delays Testing includes measured propagation delays at 50 pF and 250 pF output load capacitances. tPLH Active Propagation Delays tPHL tPZH Enable Propagation Delays This test is performed to determine what minimum edge rate can be applied to an input and have the corresponding output transition with no abnormalities such as glitches or oscillations. tPZL tPLZ Disable Propagation Delays tPHZ Also included are input timing parameters tS Setup Time tH Hold Time 9 www.national.com bands in the final maximum or minimum specifications. The test data for National's ABT product family, taken during product development on each function, provides the ABT family with device specific and guaranteed extended specifications that can be passed directly to the system designers. National offers the extended specifications with the belief that customers can reduce their incoming test requirements and in essence reduce the cost and time for product design-in. Additional guaranteed specifications provided by National include: Single Output Switching (SOS) for 250 pF loads; Multiple Output Switching (MOS) for 50 pF and 250 pF loads; Skew; Quiet Output Switching (QOS) VOLP, VOLV, VOHP, VOHV and Dynamic Threshold (DVTH), VILH, and VIHD. Each of the guaranteed extended specifications involve multiple output switching events, with exception to the SOS specifications. During a multiple output switching event, stray inductance and capacitance inhibit product performance. National has developed standardized hardware that aligns with the industry for ABT product evaluations. Some of the features of the test fixturing include ground planes and low inductive connections, critical in evaluating the product and not the fixture. See Section 2.7 for more information on test fixture hardware. The extended specfication tests have very similiar if not identical test setups. The results of the measurements from each test depend on the application focus. The quantitative analysis from the tests provides insight into product performance. The parameters and typical results from each test type can be easily explained in the sections that follow. Sample plots are generated from National's ABT244 and represent room temperature data at 5.0V VCC. DC Electrical Characteristics Automated Test Equipment (ATE) DC Tests DC test data gathered show the performance of an IC to statically applied voltages and currents. Functional Shmoo The function shmoo shows the function operational window of an IC at a wide range of VCC's and temperatures. Power Up & Power Down Output Shmoo Similar to the function shmoo, the power up and power down output shmoo shows the DC operation of an output during power up and power down conditions. Transfer Characteristic (VIN/VOUT ) Input Traces (VIN/IIN) Output Traces (VOL/IOL, V OH/IOH) Power Power-Up ICC Traces Shows how the supply current reacts to various input conditions during power up. ICC vs VIN Traces Traces of ICC vs VIN show how the supply current changes with input voltage. ICCD (Dynamic ICC) Determines the amount of current an IC will consume at frequency. Capacitance Input/Output Capacitance (CIN/COUT) Reliability Tests TABLE 3. Test Conditions for MOS, Skew, QOS, DVTH Latch-up Testing determines if an IC is susceptible to latch-up from over-current or over-voltage stresses per MIL-STD-883 JEDEC method 17. HBM Electrostatic Discharge, Human Body Model Per MIL-STD-883C method 3015.6. Parameter Input Edge Rate Extended Specifications Input Skew < 300 pS Input Amplitude 0V to 3.0V Input Frequency 1 MHz Output Load 50 pF, 500; 250 pF, 500 With the introduction of the ABT product family, National has taken new steps in aiding the system designer with a better method to predict device performance in his application. National now offers system oriented performance specifications so a designer can feel confident in the way a device will preform over a wider variety of switching conditions. Performance specifications in the form of Extended Specifications are provided with each product datasheet MULTIPLE OUTPUT SWITCHING Multiple output switching simulates a worst case switching environment. With input edges deskewed to < 300 pS, the device has to provide simultaneous switching current for the output. The cumulative effect of environmental inductance and capacitance impacts the output edge rate and ultimately impacts propagation delay and noise immunity performance. The plots of Figure 21 thru Figure 26 demonstrate the ability of the ABT product family to minimize enviromental inductance and capacitance effects as well as propagation delay degradation from increased number of outputs switching. In the past, most extended databook specifications depended on a representative product family function to provide the guaranteed performance data for the rest of the family. The drawback from this method of test and specmanship leaves rather large process, tester and function guard- www.national.com Value 2.5 ns 10 MS100211-30 FIGURE 21. Multiple Outputs Switching, LH, 1, 4, 8 Outputs 74ABT244, VCC = 5.0V, TA = 25C MS100211-31 FIGURE 22. Multiple Output Switching, HL, 1, 4, 8 Outputs 74ABT244, VCC = 5.0V, TA = 25C 11 www.national.com MS100211-32 FIGURE 23. Single Output Switching, LH, 50 pF, 250 pF Capacitive Loading 74ABT244, VCC = 5.0V, TA = 25C MS100211-33 FIGURE 24. Single Output Switching, HL, 50 pF, 250 pF Capacitive Loading 74ABT244, VCC = 5.0V, TA = 25C www.national.com 12 MS100211-34 FIGURE 25. Multiple Outputs Switching (8) LH, 50 pF, 250 pF Capacitive Loading 74ABT244, VCC 5.0V, TA = 25C MS100211-35 FIGURE 26. Multiple Output Switching (8) HL, 50 pF, 250 pF Capacitive Loading 74ABT244, VCC = 5.0V, TA = 25C pins on a part. Across-pin skew can be broken down further into tOSLH, tOSHL and tOST. The (LH) indicates that output skew is measured across all outputs while switching low-to-high. The (HL) indicates output skew measured on the high-to-low transition. The (t) infers that skew is measured across the outputs independent of a low-to-high or high-to-low edge or total output skew. Total output skew is calculated from the MOS propagation delays, tPLH and tPHL, across all pins. Across-Part Skew, tPV SKEW Skew specifications provide a system designer with up front critical timing information to speed design cycle time. Skew measurements are derived from MOS propagation delay data rather than SOS propagation delay data. The advantage of MOS skew from a design engineer's viewpoint, is that MOS is a more realistic condition under which skew becomes critical. Three modes of skew testing are published for each device in the ABT product family. Each skew mode describes a variance either within a pin (i.e. duty cycle), across to pins or across parts (i.e. process) for a given device function. Within-a-Pin Skew, tPS Across-part skew is designated by tPV (part variation), and describes the MOS output edge difference across all output pins on all parts in the population. Across-part skew is calculated from the MOS propagation delays, tPLH and tPHL, across all pins and all parts. Within-a-pin skew is designated by tPS (pin skew), and describes each pin on a part and its ability to maintain 50% duty cycle. Pin skew is a calculation from the MOS propagation delays, tPLH and tPHL on each pin. Across-Pin Skew, tOS Across-pin skew is designated by tOS (output skew), and describes the MOS output edge difference across all output The plots in Figure 27 and Figure 28 describe skew performance in a 50 pF, 500 environment. 13 www.national.com MS100211-36 FIGURE 27. Skew 8 Outputs Switching, LH 74ABT244, VCC = 5.0V, TA = 25C MS100211-37 FIGURE 28. Skew 8 Outputs Switching, HL 74ABT244, VCC = 5.0V, TA = 25C The concern for the system designer evolves from the possiblity that the quiet output voltage shift could impact attached circuitry. VOLP values on some product families peak above threshold high and become recognized as a logic HIGH. The period of time the voltage shift spends in the opposite state is short, in the neighborhood of 10-100 pS, and may not disrupt sequencial circuitry if it is level sensing. If the attached circuitry needs a rising edge, such as a clock input, the sequencial circuitry may take the inadvertent deflection and interpret it. National provides the QOS specification to assist in noise margin planning. QUIET OUTPUT SWITCHING Quiet output switching, (QOS), specifications provide the system designer quantification of ABT's effective control of noise and performance to threshold specifications. The QOS specification is a representation of the resultant shift of an output voltage, either from a static high or low level on a single bit, while the other bits switch simutaneously in phase. The voltage shift from a quiet output is specified through four parameters. * VOLP and VOLV describe the peak or valley of a voltage shift for a quiet output low level. * VOHP and VOHV describe the peak or valley of a voltage shift for a quiet output high level. www.national.com 14 MS100211-38 FIGURE 29. VOHV, VOHP LH Transition 74ABT244, VCC = 5.0V, TA = 25C MS100211-39 FIGURE 30. VOLP, VOLV HL Transition 74ABT244, VCC = 5.0V, TA = 25C * DYNAMIC THRESHOLD Dynamic threshold data, (DVTH), like QOS data, provides the system designer with noise performance criteria. DVTH specifications quantify the magnitude of output voltage deflection that a logic high or low might experience under an MOS switching condition. The voltage deflection is a result of an apparent shift of an input's threshold due to noise generated from MOS switching on the internal die ground and VCC busses. The phenomenon occurs during any logic state transition: LH, HL, ZL, etc. As a practice, National determines the worse case transition for each product and generates the specification based on that transition. VILD - The maximum LOW input level such that normal switching/functional characteristics are observed on the output * VIHD - The minimum HIGH input level such that normal switching/functional characteristics are observed on the output Dynamic threshold failures are bundled into five main failure modes. The most predominant failure is an output deflection in violation of an input threshold level. Others include propagation delay step out in excess of an MOS propagation delay specification, state changes and oscillations. A detailed definition of each failure can be described as follows, Dynamic threshold specifications are denoted by the nomenclature, VILD and VIHD, where the "D" represents "Dynamic". The definitions for each are as follows, 15 www.national.com 1. 2. 3. age level is noted and monitored until a 100 mV amplitute change towards threshold. If no amplitude change occurs, then the next peak or valley on the output is monitored for input threshold violation. Figure 35. On a low output, the LOW level will not rise above an input threshold low level of 0.8V after the transition of the output. Figure 31 and Figure 32. Numbered output curve deflections are a result of 10 mV incremental changes on the low input signal level. 4. On a high output, the HIGH level will not drop below an input threshold high level of 2.0V after the transition of the output. Figure 33 and Figure 34. Numbered output curve deflections are a result of 10 mV incremental changes on the high input signal level. 5. The propagation delay is monitored and is determined a failure when it exceeds the MOS propagation delay for that transition. Gross failures including oscillation and functional state changes. If the natural ringing, other than the initial bounce, of the output violates an input threshold level, the starting volt- MS100211-40 FIGURE 31. VILD 7 Outputs Switching VCC = 5.0V, TA = 25C MS100211-41 FIGURE 32. VILD 8 Outputs Switching VCC = 5.0V, TA = 25C www.national.com 16 MS100211-42 FIGURE 33. VIHD 7 Outputs Switching VCC = 5.0V, TA = 25C MS100211-43 FIGURE 34. VIHD 8 Outputs Switching VCC = 5.0V, TA = 25C 17 www.national.com MS100211-44 FIGURE 35. Characterization Fixture was evaluated and make sure that National's implementation of load configuration, board, and DUT connection is followed as shown below. Unique device pinouts, (20-, 24-, 48-lead, etc.) are used to obtain picosecond accuracy and repeatability. For this reason NSC recommends values of lumped and distributed capacitance used on its AC fixtures to prevent large variations in speed affected by transmission line capacitance. With the introduction of ABT product family with system level specifications that are guaranteed in a high performance AC environment, there is a necessity for a precise and repeatable test environment. Keeping in mind the defacto standards presented by Philips ABT fixture coupled with the understanding that our customers would like to correlate performance of like technologies, National reproduced an electrical equivalent AC fixture to that of the SigneticsTM board documented in their Application Note 602. To maximize correlation to National's product characterization one must match the environment in which the product www.national.com 18 Characterization Fixture (Continued) Bare Board Front Layout Shown MS100211-1 FIGURE 36. 28-Pin SOIC TOP (Viewed from Top) 19 www.national.com Characterization Fixture (Continued) Bare Board Back Layout Shown MS100211-2 FIGURE 37. 28-Pin SOIC BOTTOM (Viewed from Top) The blank AC fixture board can be used to implement the following input and output loads and terminations to provide the most repeatable environment in which to test a device. MS100211-3 r1 = 56 r2 = 450 FIGURE 38. Input www.national.com 20 Characterization Fixture (Continued) MS100211-4 c1 = 27 pF r2 = 450 r3 = 500 FIGURE 39. Output (TRI-STATE/Open Collector) MS100211-5 c1 = 27 pF r2 = 450 r3 = 500 FIGURE 40. Output (2-State) MS100211-6 c2 = 0.1 F FIGURE 41. 21 www.national.com Characterization Fixture (Continued) MS100211-7 FIGURE 42. Component Placement on PC Board For connection of the device to the board, a custom socket firmly presses the device against the board traces without any layers in between that add inductance or change their resitivity over temperature. The socket provides a minimum of contact resistance for the most accurate results. National designed a custom surface mount socket that provides the needed performance without damaging the device under test. Because of its shape and appearance, we call it the ferrari fixture. In the characterization of National's product, we made efforts to correlate performance with other manufacturers. If a customer wishes to verify NSC results and requires an AC fixture, we recommend using Signetics AN-602 to build one. While the board that National uses is probably cost equivalent to the Signetics board, the socket used is expensive. If you wish to build a National fixture, please call the factory at 1-800-341-0392 and ask for applications. We can provide you with the component and manufacturer list for a National board along with a socket. National's AC fixture has the advantage of providing: * low inductance VCC and GND connections * VCC and GND planes to minimize cross talk and enhance power supply by-passing * equal length 50 impedance signal and monitor lines to eliminate skew * * 50 input termination for ease of use 10:1 voltage reduction of the input and output signals to provide ease of use with standard oscilloscope inputs * TRI-STATE load is integrated onto the same AC fixture and is connected via jumper to alleviate shunting effects when it is not required Traces are spaced, and monitor lines are placed, on a different plane than the signal lines to reduce cross talk. Figure 43 shows a cross section of layers used in the manufacture of National's AC test board. Vias in the signal trace are not used to ensure bandwidth. Ground connections are directly underneath the DUT to reduce the distance to the ground plane. Sense resistors are located directly adjacent to the DUT to reduce reflections. www.national.com 22 Characterization Fixture (Continued) MS100211-8 FIGURE 43. Layer Stacking Diagram 23 www.national.com ABT Ratings, Specifications and Waveforms LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.