The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
© 2001
MOS I NTEGRATED CIRCUIT
µ
µµ
µ
PD16705
263/256-OUTPUT TFT-LCD GATE DRIVER
DATA SHEET
Document No. S15818EJ1V0DS00 (1st edition)
Date Published July 2002 NS CP (K)
Printed in Japan
DESCRIPTION
The
µ
PD16705 is a TFT-LCD gate driver equipped with 263/256-output lines. It can output a high-gate scanning
voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit. It can also
drive the XGA/SXGA and SXGA+.
FEATURES
• CMOS level input (3.3 V/2.5 V)
• 263/256 outputs
• High-output voltage (VDD2-VEE: 40 V MAX.)
• Capable of All-on outputting (/AO)
Remark /xxx indic ates active lo w signal.
ORDERING INFORMATION
Part Number Package
µ
PD16705N-xxx TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales
representatives.
Data Sheet S15818EJ1V0DS
2
µ
µµ
µ
PD16705
1. BLOCK DIAGRAM
LS1
Note
LS1
Note
LS1
Note
CLK
STVR STVL
OE
3
O
2
O
3
SR3
SR261 SR262 SR263
SR2SR1
O
262
O
263
263-bit shift register
LS1
Note
O
261
LS1
Note
R,/L
LS1
Note
OE
1
LS1
Note
OE
2
LS1
Note
/AO
V
EE
V
DD1
V
DD2
V
SS
LS2
Note
LS2
Note
LS2
Note
LS2
Note
LS2
Note
LS2
Note
LS1
Note
MODE
O
1
Note LS1: shifts CMOS level and internal level, LS2: shifts interval level and output level (VDD2-VEE).
Data Sheet S15818EJ1V0DS 3
µ
µµ
µ
PD16705
2. PIN CONFIGURATION (
µ
µµ
µ
PD16705N-xxx: Copper foil surface, face-up)
O1
O2
VDD2
VEE
VSS
VDD1
STVR
VSS
R,/L
VDD1
CLK Copper
/AO Foil
OE1Surface
OE2
OE3
STVL
VDD1
MODE
VSS
VEE
VDD2
O261
O262
O263
Remark This figure does not specify the TCP package.
Data Sheet S15818EJ1V0DS
4
µ
µµ
µ
PD16705
3. PIN FUNCTIONS
Pin Symbol Pin Nam e I/O Description
O1 to O263 Driver output O These pins output sc an signals that drive the vert i cal direction (gate lines) of a
TFT-LCD. The output signals changes in synchronization with t he rising edge of
shift clock CLK . The driver output amplitude i s VDD2 to VEE.
R,/L Shift direction select
input
I The shif t di rection c ontrol pin of s hi ft resister.
R,/L = H (right shift): STVR → O1 → O263 → STVL
R,/L = L or Open (lef t shift): STV L → O263 → O1 → STVR
STVR,
STVL
Start pul se
input/output
I/O This is the input of the internal shift regi ster. The s t art pulse is read at the rising
edge of shift clock CLK, and scan si gnal s are output from the dri ver out put pi ns.
The input level i s a VDD1 to VSS (logic level ). When in MODE = H, the start pul se is
output at the falling edge of the 263rd clock of shift clock CLK , and is c l eared at
the falli ng edge of the 264th c l ock. The out put level is VDD1 to VSS (logic level).
CLK Shift clock i nput I This pin i nputs a shift clock to t he i nternal shif t register. The shift operation is
perform ed i n synchronizati on with t he ri sing edge of thi s input.
OE1,
OE2,
OE3
Output enable input I When this pi n goes high level, the driver output is fixed to VEE level. The shift
register i s not cleared. CLK is asynchronous i n the cloc k. Note t hat the output
term i nal , whic h can be controll ed by the enable signal changes, ref ers to 4.
RELATIONS OF ENABLE I NPUT AND OUTPUT TERMIN AL.
/AO All-on c ont rol I When this pin goes low level, all dri ver out put is f i xed to VDD2 level. The shift
register i s not cleared. This pin has pri ori ty over OE1 to OE3. /AO is pull ed up t o
VDD1 inside t he IC. CLK is asynchronous i n the cloc k.
MODE Selection of number of
outputs
IMODE = V
DD1 or open: 263 outputs
MODE = VSS: 256 outputs (driver output pins O129 to O135 are invalid.)
Input level i s VDD1 to VSS (logic l evel ). MODE is pull ed up to VDD1 ins i de t he IC.
VDD1 Logic power supply - 2.3 to 3.6 V
VDD2 Driver positi ve power
supply
- 15 to 25 V. The driver output: hi gh l evel
VSS Logic ground - Connect thi s pin to the ground of the sys t em.
VEE Negative power
supply for i n t e rnal
operation
- –15 to –5 V. The driver output: l ow level
Cautions 1. To prevent latch-up, turn on power to VDD1, VEE, VDD2, and logic input in this order. Turn off
power in the reverse order. These power up/down sequence must be observed also during
transition period.
2. Insert a capacitor of about 0.1
µ
µµ
µ
F between each power line, as shown below, to secure noise
margin such as VIH and VIL.
V
DD2
V
DD1
0.1
F
V
SS
V
EE
µ
0.1
F
µ
0.1
F
µ
Data Sheet S15818EJ1V0DS 5
µ
µµ
µ
PD16705
4. RELATIONS OF ENABLE INPUT AND OUTPUT TERMINAL
Switching is possible for 263/256 with
µ
PD16705 by the MODE pin. And, the output terminal that can be controlled
by the enable signal changes as follows along with this function.
263-output TCP 256-output TCP
263-output mode
(MODE = H)
256-output mode
(MODE = L)
263-output mode
(MODE = H)
256-output mode
(MODE = L)
O1 (OE1)O
1 (OE1)O
1 (OE1)O
1 (OE1)
O2 (OE2)O
2 (OE2)O
2 (OE2)O
2 (OE2)
O3 (OE3)O
3 (OE3)O
3 (OE3)O
3 (OE3)
O4 (OE1)O
4 (OE1)O
4 (OE1)O
4 (OE1)
O5 (OE2)O
5 (OE2)O
5 (OE2)O
5 (OE2)
O6 (OE3)O
6 (OE3)O
6 (OE3)O
6 (OE3)
↓↓↓↓
O127 (OE1)O
127 (OE1)O
127 (OE1)O
127 (OE1)
O128 (OE2)O
128 (OE2)O
128 (OE2)O
128 (OE2)
O129 (OE3)V
X = VEE
O130 (OE1)V
X = VEE
O131 (OE2)V
X = VEE
O132 (OE3)V
X = VEE
O133 (OE1)V
X = VEE
O134 (OE2)V
X = VEE
O135 (OE3)V
X = VEE
O136 (OE1)O
136 (OE3)O
136 (OE1)O
136 (OE3)
O137 (OE2)O
137 (OE1)O
137 (OE2)O
137 (OE1)
↓↓↓↓
O259 (OE1)O
259 (OE3)O
259 (OE1)O
259 (OE3)
O260 (OE2)O
260 (OE1)O
260 (OE2)O
260 (OE1)
O261 (OE3)O
261 (OE2)O
261 (OE3)O
261 (OE2)
O262 (OE1)O
262 (OE3)O
262 (OE1)O
262 (OE3)
O263 (OE2)O
263 (OE1)O
263 (OE2)O
263 (OE1)
Remark VX is power-supply voltage of output pin O1 to O263.
Data Sheet S15818EJ1V0DS
6
µ
µµ
µ
PD16705
5. TIMING CHART (R,/L = H, /A O = H, MODE = H)
CLK
OE3
O1
(O263)
O2
(O262)
O3
(O261)
O262
(O2)
O263
(O1)
O1 of next stage
(O263 of next stage)
O2 of next stage
(O262 of next stage)
31 2 264262 263 266265
OE1
STVL
(STVR)
STVR
(STVL)
OE2
Data Sheet S15818EJ1V0DS 7
µ
µµ
µ
PD16705
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°
°°
°C, VSS = 0 V)
Parameter Symbol Rating Unit
Logic Suppl y Voltage VDD1 −0.5 to +7.0 V
Driver Posi tive Supply V ol tage VDD2 −0.5 to +28 V
Power Supply Voltage VDD2-VEE −0.5 to +42 V
Internal Operat i on Negative Supply Vol tage VEE −16 to +0.5 V
Input Vol tage VI−0.5 to VDD1 +0.5 V
Operating Ambient Temperature TA−20 to +75 °C
Storage Temperature Tstg −55 t o +125 °C
Caution Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = −
−−
−20 to +75°C, VSS = 0 V)
Parameter Symbol MIN. TYP. MAX. Unit
Logic Suppl y Voltage VDD1 2.3 3.3 3.6 V
Driver Posi tive Supply V ol tage VDD2 15 23 25 V
Internal Operat i on Negative Supply Vol tage VEE −15 −10 −5.0 V
Power Supply Voltage VDD2-VEE 20 33 40 V
Clock Frequency fCLK 500 kHz
Data Sheet S15818EJ1V0DS
8
µ
µµ
µ
PD16705
Electrical Characteristics (TA = −
−−
−20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE = −
−−
−10 V, VSS = 0 V)
Parameter Symbol Condition MIN. TYP.Note MAX. Unit
High-level Input Voltage VIH 0.8 VDD1 VDD1 V
Low-level Input Voltage VIL
CLK, STVR (STVL), R,/L,
OE1 to OE3VSS 0.2 VDD1 V
High-level Output Voltage VOH STVR (STVL), IOH = −40
µ
AV
DD1 −0.4 VDD1 V
Low-level Output Voltage VOL STVR (STVL), IOL = +40
µ
AV
SS VSS +0.4 V
LCD Driver Output ON Res i stance RON VOUT = VEE +1.0 V, or
VDD2 −1.0 V
0.33 1.0 kΩ
Pull-up Res i stance RPU VDD1 = 3.3 V, / AO, MODE 10 50 100 kΩ
Input Leak Current IIL VI = 0 V or 3.6 V ,
except for /A O, MODE
±1.0
µ
A
Stati c Current Dis sipation IDD1 VDD1, fCLK = 50 kHz,
OE1 = OE2 = OE3 = L,
fSTV = 60 Hz, no load
390 1000
µ
A
IDD2 VDD2, fCLK = 50 kHz,
OE1 = OE2 = OE3 = L,
fSTV = 60 Hz, no load
10 100
µ
A
IEE VEE, fCLK = 50 kHz,
OE1 = OE2 = OE3 = L,
fSTV = 60 Hz, no load
−1100 −400
µ
A
Remark STV: STVR (STVL).
Switching Characteristics (TA = −
−−
−20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE = −
−−
−10 V, VSS = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Cascade Out put Del ay Ti me tPHL1 CL = 20 pF, 800 ns
tPLH1 CLK → STVL (STVR) 800 ns
Driver Output Delay Ti me tPHL2 CL = 300 pF, CLK → On500 ns
tPLH2 500 ns
tPHL3 CL = 300 pF, OEn → On800 ns
tPLH3 800 ns
Output Ris e Time tTLH CL = 300 pF 800 ns
Output Fall Time tTHL 800 ns
Input Capac i t ance CITA = 25°C 15 pF
Timing Requirements (TA = −
−−
−20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE = −
−−
−10 V, VSS = 0 V,
tr = tf = 20 ns (10 to 90%))
Parameter Symbol Condition MIN. TYP. MAX. Unit
Clock Pulse High Width PWCLK(H) 500 ns
Clock Pulse Low Width PWCLK(L) 500 ns
Enable Pulse Width PWOE 1000 ns
Data Setup Time tSETUP STVR (STVL) ↑ → CLK ↑200 ns
Data Hold Time tHOLD CLK ↑ → STVR (STVL) ↓ 200 ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1.
Data Sheet S15818EJ1V0DS 9
µ
µµ
µ
PD16705
Switching Characteristics Waveform (R,/L= H, MODE = H)
Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1.
t
SETUP
CLK
STVR
t
r
90%
10%
t
HOLD
PW
CLK(H)
t
f
1260 261
23
t
PLH2
O
1
t
PHL2
O
2
O
262
O
263
t
PLH1
STVL
t
PHL1
OE
1
-OE
3
t
PHL3
O
1
-
O
263
t
PLH3
4567262 263
•
•
•
90%
10%
t
TLH
t
THL
PW
OE
PW
CLK(L)
90%
10%
50%
90% 10%
50%
50%
50%
50%
Data Sheet S15818EJ1V0DS
10
µ
µµ
µ
PD16705
7. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the
µ
PD16705.
For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).
Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under
different conditions.
µ
PD16705N-xxx: TCP (TAB Package)
Mounting Condition Mounting Method Condition
Thermoc ompress i on Soldering Heating tool 300 to 350°C, heating for 2 to 3 seconds, pres sure 100g (per
solder)
ACF
(Adhesive
Conductive Fi l m)
Temporary bonding 70 to 100°C, pressure 3 to 8 kg/ cm2, time 3 to 5 sec.
Real bonding 165 to 180°C, pressure 25 to 45 kg/cm2, time 30 to 40 sec.
(When using t he ani sotropy conductive fi l m SUMIZAC1003 of Sum i t omo
Bakeli t e, Ltd).
Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more mounting methods at a time.
Data Sheet S15818EJ1V0DS 11
µ
µµ
µ
PD16705
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
µµ
µ
PD16705
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades On NEC Semiconductor Devices (C11531E)
M8E 00. 4
The information in this document is current as of July, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
•
•
•
•
•
•
