DECEMBER 2002
DSC-5298/03
1
©2002 Integrated Device Technology, Inc.
Pin Description Summary
cycle, and on the next clock cycle the associated data cycle occurs, be it
read or write.
The IDT71V65703/5903 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903
to be suspended as long as necessary. All synchronous inputs are ignored when
CEN is high and the internal device registers will hold their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71V65703/5903 have an on-chip burst counter. In the burst
mode, the IDT71V65703/5903 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V65703/5903 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
Features
◆◆
◆◆
◆256K x 36, 512K x 18 memory configurations
◆◆
◆◆
◆Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized output buffer enable eliminates the
need to control OEOE
OEOE
OE
◆◆
◆◆
◆Single R/WW
WW
W (READ/WRITE) control pin
◆◆
◆◆
◆4-word burst capability (Interleaved or linear)
◆◆
◆◆
◆Individual byte write (BWBW
BWBW
BW1 - BWBW
BWBW
BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆3.3V power supply (±5%)
◆◆
◆◆
◆3.3V (±5%) I/O Supply (VDDQ)
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
A0-A18 Add ress Inputs Inp ut Synchronous
CE1, CE 2, CE2Chip Enab les Inp ut Sync hro nous
OE Output Enable Inp ut Asy nchronous
R/WRead/Write Signal Input Synchronous
CEN Clo c k Enab le Inp ut Sync hro nous
BW1, BW2, BW3, BW4Indiv id ual B yte Wri te Sel e cts Inp ut Sync hro nous
CLK Clock Input N/A
ADV/LD Ad vance B urs t A d dress /Lo ad New Ad dress Inp ut Sync hro nous
LBO Linear/Inte rl eav e d B urst Ord e r Inp ut S tatic
ZZ Slee p Mo de Inp ut Asy nchro nous
I/O0-I/O31, I/OP1-I/OP4 Data Input/Outp ut I/ O Sync hro nous
VDD, V DDQ Co re Powe r, I/ O P owe r Sup ply S tatic
VSS Ground Supply Static
5298 tbl 01
IDT71V65703
IDT71V65903
256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
6.42
2
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
Pin Function
I/O
Active
Description
A0-A18 Address Inputs I N/A Synchro nous Address inputs. The address register is triggered by a combination of the rising edge of
CLK, ADV/LD lo w, CEN lo w, and true chip e nab le s .
ADV/LD Ad vance / Load I N/A ADV/LD is a synchro nous input that is used to load the inte rnal registers with new address and control
when it is sample d low at the rising edge of clock with the chip selected. When ADV/LD is low with
the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the
internal b urs t c ounte r is ad vance d fo r any b urst that was in p rog re ss . The e xte rnal ad d res se s are
ignored when ADV/LD is sampled high.
R/WRe ad / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
Write access to the memory array. The data bus activity for the curre nt cycle takes place one clock
cycle later.
CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including
c loc k are i gnored and outputs rem a i n un changed. The effe ct of CEN sampled high on the device
outputs is as if the low to high clock transition did no t occur. For normal operation, CEN must b e
sampled low at rising edge of clock.
BW1-BW4Individual Byte
Write Enab le s I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load
write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4)
must be valid. The byte write signal mus t also be valid on each cycle of a burst write. Byte Write
signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the
device one cycle later. BW1-BW4 c an all b e tie d lo w if al way s d oing write to the e ntire 36-b it wo rd .
CE
1, CE2Chip Enabl es I LOW S ynchronous active l ow chip enable. CE1 and CE
2 are used with CE2 to e nable the IDT71V65703/ 5903
(CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates
a deselect cycle. The ZBTTM has a o ne cy cle de se le ct, i.e., the d ata bus will tri-s tate one clo ck c ycle
after deselect is initiated.
CE2Chip Enab le I HIGH Sy nchro nous ac tiv e hig h c hip e nab le . CE 2 is us ed with CE1 and CE
2 to e nabl e the c hi p . CE 2 has
inverted polarity but otherwise identical to CE1 and CE2.
CLK Clo ck I N/A This is the clo ck inp ut to the IDT71V65703/5903. Exce pt fo r OE, al l tim ing referenc es for the devi ce are
made with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4 Data Input/Output I/O N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
LBO Line ar B urst
Order I LOW Burst order selection input. When LBO is high the Inte rleaved burst sequence is selected. When LBO
is low the Linear burst sequence is selected. LBO is a s tatic inp ut, and it m ust no t chang e d uring
device operation.
OE Output Enab le I LOW Async hronous output enab le . OE must be lo w to re ad d ata fro m the 71V65703/ 5903. Whe n OE is HIGH
the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and
wri te cycles. In normal operation, OE can be tied low.
ZZ Sleep Mode I HIGH Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V65703/5903 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
VDD Power Supply N/A N/A 3.3V core power supply.
VDDQ Power Supply N/A N/A 3.3V I/O supply.
VSS Ground N/A N/A Ground.
5298 tbl 02
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
3
Functional Block Diagram 256K x 36
Clk
DQ
DQ
DQ
Address A [0:17]
Control Logic
Address
Control
DI DO
Input Register
5298 drw 01
Clock
Data I/O [0:31], I/O P[1:4]
Mux Sel
Gate
OE
CE1,CE
2CE2
R/W
CEN
ADV/LD
BWx
LBO 256K x 36 BIT
MEMORY ARRAY
,
6.42
4
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Block Diagram 512K x 18
Recommended DC Operating
Conditions
NOTE:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD Core Sup ply Vo ltage 3.135 3.3 3.465 V
VDDQ I/O Sup p ly Vo ltage 3.135 3.3 3.465 V
VSS Ground 0 0 0 V
VIH Input High Voltage - Inputs 2.0 ____ VDD + 0.3 V
VIH Input High Voltage - I/O 2.0 ____ VDDQ + 0.3 V
VIL Inp ut Lo w Vo ltag e -0.3(1) ____ 0.8 V
5298 tbl 04
Clk
DQ
DQ
DQ
Address A [0:18]
Control Logic
Address
Control
DI DO
Input Register
5298 drw 01a
Clock
Data I/O [0:15], I/O P[1:2]
Mux Sel
Gate
OE
CE1,CE
2CE2
R/W
CEN
ADV/LD
BWx
LBO 512K x 18 BIT
MEMORY ARRAY
,
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
5
Recommended Operating
Temperature and Supply Voltage
Pin Configuration 256K x 36
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is ≤ VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. Pins 84 is reserved for a future 16M.
4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins TMS, TDI, TDO and TCK. The
current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
Top View
100 TQFP
Grade
Temperature
(1)
V
SS
V
DD
V
DDQ
Co mme rcial 0° C to +70° C 0V 3. 3V±5% 3.3V ± 5%
Ind us tri al -40° C to + 85° C 0V 3.3V±5% 3. 3V±5%
5298 tbl 05
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(3)
A
17
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNU
(4)
DNU
(4)
DNU
(4)
DNU
(4)
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O31
I/O30
VDDQ
VSS
I/O29
I/O28
I/O27
I/O26
VSS
VDDQ
I/O25
I/O24
VSS
VDD
I/O23
I/O22
VDDQ
VSS
I/O21
I/O20
I/O19
I/O18
VSS
VDDQ
I/O17
I/O16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
5298 drw 02
VSS(1)
I/O15
I/OP3
VDD(2)
I/OP4
A
15
A
16
I/OP1
VSS(1)
I/OP2
ZZ
,
NOTES:
1. TA is the “instant on” case temperature.
6.42
6
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
100 TQFP Capacitance(1)
(TA = +25°°
°°
°C, f = 1.0MHz)
Pin Configuration 512K x 18
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the
input voltage is < VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input
voltage is > VIH.
3. Pin 84 is reserved for a future 16M.
4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective
JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows
these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
Top View
100 TQFP
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the “instant on” case temperature.
Symbol
Rating
Commercial &
Industrial
Unit
VTERM(2) Ter mina l V olt a ge w i t h
Re s p e ct to GND -0.5 to +4.6 V
VTERM(3,6) Termina l V olt a ge w it h
Re s p e ct to GND -0.5 to VDD V
VTERM(4,6) Termina l V olt a ge w it h
Re s p e ct to GND -0.5 to VDD +0.5 V
VTERM(5,6) Termina l V olt a ge w it h
Re s p e ct to GND -0.5 to VDDQ +0.5 V
TA(7) Co mm erc ial 0 to + 70 oC
Industrial -40 to +85 oC
TBIAS Temp erature Und er Bias -55 to +125 oC
TSTG Sto rage Te mp erature -55 to +125 oC
PTPo we r Dis s ip atio n 2.0 W
IOUT DC Outp ut Curre nt 50 mA
5 298 t bl 06
Symbol Parameter
(1)
Conditions Max. Unit
CIN Inp ut Cap ac itanc e VIN = 3dV 5 pF
CI/O I/ O Cap ac itanc e VOUT = 3dV 7 pF
5298 tb l 07
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(3)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNU
(4)
DNU
(4)
DNU
(4)
DNU
(4)
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
VDDQ
VSS
NC
I/OP2
I/O15
I/O14
VSS
VDDQ
I/O13
I/O12
VSS
VDD
I/O11
I/O10
VDDQ
VSS
I/O9
I/O8
NC
NC
VSS
VDDQ
NC
NC 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
5298 drw 02a
VSS(1)
NC
NC
VDD(2)
NC
A
16
A
17
NC
VSS(1)
A10
ZZ
A
18
,
Symbol Parameter
(1)
Conditions Max. Unit
CIN Inp ut Cap ac itanc e V IN = 3dV 7 pF
CI/O I/ O Cap ac itan ce V OUT = 3dV 7 pF
5298 tbl 07a
165 fBGA Capacitance(1)
(TA = +25°°
°°
°C, f = 1.0MHz)
119 BGA Capacitance(1)
(TA = +25°°
°°
°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
CIN Inp ut Cap acitanc e VIN = 3dV TBD pF
CI/O I/ O Cap ac itance V OUT = 3dV TBD pF
5298 tbl 07b
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
7
1234567
AV
DDQ
A
6
A
4
A
8
A
16
V
DDQ
BNC CE
2
A
3
ADV/LD A
9
CE
2
NC
CA
7
A
2
V
DD
A
12
A
15
NC
DI/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
EI/O
17
I/O
18
V
SS
V
SS
I/O
13
I/O
14
FV
DDQ
I/O
19
V
SS
OE V
SS
I/O
12
V
DDQ
GI/O
20
I/O
21
BW
3
BW
2
I/O
11
I/O
10
HI/O
22
I/O
23
V
SS
R/WV
SS
I/O
9
I/O
8
JV
DDQ
V
DD
V
DD
V
DD
V
DDQ
KI/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
LI/O
25
I/O
27
BW
4
NC BW
1
I/O
4
I/O
5
MV
DDQ
I/O
28
V
SS
CEN V
SS
I/O
3
V
DDQ
NI/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
PI/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
0
I/O
P1
RNC A
5
LBO V
DD
A
13
TNC NC A
10
A
11
A
14
NC ZZ
UV
DDQ
DNU
(4)
DNU
(4)
DNU
(4)
DNU
(4)
DNU
(4)
V
DDQ
5298 drw 13a
V
SS(1)
NC
NC(3)
CE
1
A
17
V
DD(2)
V
SS(1)
,
NC
1234567
AVDDQ A6A4NC(3) A8A16 VDDQ
BNC CE2 A3ADV/LD A9CE2NC
CA7A2VDD A13 A17 NC
DI/O8NC VSS NC VSS I/O NC
ENC I/O9VSS VSS NC I/O
FVDDQ NC VSS OE VSS I/O VDDQ
GNC I/O10 BW2NC I/O
HI/O11 NC VSS R/WVSS I/O NC
JVDDQ VDD VDD VDD VDDQ
KNC I/O12 VSS CLK VSS NC I/O
LI/O13 NC NC BW1I/O NC
MVDDQ I/O14 VSS CEN VSS NC VDDQ
NI/O15 NC VSS A1VSS I/O NC
PNC I/OP2 VSS A0VSS NC I/O
RNC A5LBO VDD A12
TNC A10 A15 NC A14 A11 ZZ
UVDDQ DNU(4) DNU(4) DNU(4) DNU(4) DNU(4) VDDQ
5298 drw 13b
NC
SS(1)
V
VSS
VSS
CE1
A18
VDD(2) VSS(1)
,
NC
Pin Configuration 256K x 36, 119 BGA
Pin Configuration 512K x 18, 119 BGA
Top View
Top View
NOTES:
1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. J3 does not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
3. A4 is reserved for future 16M.
4. DNU = Do not use; Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST. The current die revision allows
these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
8
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 165 fBGA
Pin Configuration 512K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
(3)
A
7
CE
1
BW
3
BW
2
CE
2
CEN
ADV
/LD
A
17
A
8
NC
B
NC
A
6
CE
2
BW
4
BW
1
CLK
R/
WOE
NC
(3)
A
9
NC
(3)
C
I/O
P3
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
I/O
P2
D
I/O
17
I/O
16
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
15
I/O
14
E
I/O
19
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
F
I/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
11
I/O
10
G
I/O
23
I/O
22
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
9
I/O
8
H
V
SS
(1)
V
DD
(2)
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
ZZ
J
I/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
I/O
6
K
I/O
27
I/O
26
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
I/O
4
L
I/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
M
I/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
N
I/O
P4
NC
V
DDQ
V
SS
DNU
(4)
NC
V
SS
(1)
V
SS
V
DDQ
NC
I/O
P1
P
NC
NC
(3)
A
5
A
2
DNU
(4)
A
1
DNU
(4)
A
10
A
13
A
14
NC
R
LBO
NC
(3)
A
4
A
3
DNU
(4)
A
0
DNU
(4)
A
11
A
12
A
15
A
16
5298 tb l 25a
1234567891011
ANC
(3)
A
7
CE1BW
2
NC CE
2
CEN ADV/LD A
18
A
8
A
10
BNC A
6
CE
2
NC BW
1
CLK R/WOE NC
(3)
A
9
NC
(3)
CNC NCV
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P1
DNC I/O
8
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
7
ENC I/O
9
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
6
FNCI/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
5
GNC I/O
11
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
4
HV
SS
(1) V
DD
(2) NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ
JI/O
12
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
NC
KI/O
13
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
2
NC
LI/O
14
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
NC
MI/O
15
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
0
NC
NI/O
P2
NC V
DDQ
V
SS
DNU(4) NC V
SS
(1) V
SS
V
DDQ
NC NC
PNC NC
(3)
A
5
A
2
DNU(4) A
1
DNU(4) A
11
A
14
A
15
NC
RLBO NC
(3)
A
4
A
3
DNU(4) A
0
DNU(4) A
12
A
13
A
16
A
17
5298 tb l 25b
NOTES:
1. Pins H1 and N7 do not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pin H2 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. Pin B9, B11, A1, R2 and P2 are reserved for a future 18M, 36M, 72M, 144M and 288M respectively.
4. DNU = Do not use. Pins P5, R5, P7, R7 and N5 are reserved for respective JTAG pins: TDI, TMS, TDO, TCK and TRST on future revisions. The current die
revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
9
Interleaved Burst Sequence Table (LBO=VDD)
Partial Truth Table for Writes(1)
Synchronous Truth Table(1)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3 . Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
CEN
R/
WCE
1
,
CE
2
(5)
ADV/
LD
BW
x
ADDRESS
USED
PREVI OUS CYCLE
CURRE NT CYCL E
I/O
(One cycle l ater)
L L L L Valid E xte rnal X LOAD WRITE D(7)
L H L L X External X LOAD READ Q(7)
L X X H Valid Internal LOAD WRITE /
BURST WRITE BURST WRITE
(Ad vance b urst c o unter)(2) D(7)
L X X H X Inte rnal LOAD READ /
BURS T RE AD BURS T RE AD
(Ad vance b urst c o unter)(2) Q(7)
L X H L X X X DESELECT o r STOP(3) HIZ
L X X H X X DESELE CT / NOOP NOOP HIZ
H X X X X X X SUSPEND(4) Pre vious Value
5 298 t bl 08
OPERATION
R/
WBW
1
BW
2
BW
3
(3)
BW
4
(3)
READ HXXXX
WRITE ALL BYTES L L L L L
WRITE BYTE 1 (I/O[0:7], I/OP1)(2) LLHHH
WRITE BYTE 2 (I/O[8:15], I/OP2)(2) LHLHH
WRITE BYTE 3 (I/O[16:23], I/OP3)(2,3) LHHLH
WRITE BYTE 4 (I/O[24:31], I/OP4)(2,3) LHHHL
NO WRITE L HHHH
5 298 t b l 09
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Ad dress 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11100100
5298 tbl 10
6.42
10
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Timing Diagram(1)
Linear Burst Sequence Table (LBO=VSS)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address 000 11011
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11000110
52 98 t bl 11
n+29
A29
C29
D/Q28
ADDRESS
(A0-A
17)
CONTROL
(R/W,ADV/
LD,BWx)
DATA
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q29
n+31
A31
C31
D/Q30
n+32
A32
C32
D/Q31
n+33
A33
C33
D/Q32
n+34
A34
C34
D/Q33
n+35
A35
C35
D/Q34
n+36
A36
C36
D/Q35
n+37
A37
C37
D/Q36
5298 drw 03
(2)
(2)
(2)
,
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
11
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2)
Cycle
Address
R/
W
ADV/
LD CE
1
(1)
CEN BW
x
OE
I/O
Comments
nA
0HL LLXXD
1Lo ad re ad
n+1 X X H XLXLQ
0Burst read
n+2 A1HL LLXLQ
0+1 Load read
n+3 X X L H L X L Q1Deselect or STOP
n+4 X X H X L X X Z NOOP
n+5 A2HL LLXXZLoad read
n+6 X X H XLXLQ
2Burst read
n+7 X X L H L X L Q2+1 Deselect or STOP
n+8 A3L L LLLXZLoad write
n+9 X X H X L L X D3Burst write
n+10 A4L L LLLXD
3+1 Load write
n+11 X X L H L X X D4Deselect or STOP
n+12 X X H X L X X Z NOOP
n+13 A5L L LLLXZLoad write
n+14 A6HL LLXXD
5Lo ad re ad
n+15 A7L L LLLLQ
6Lo ad write
n+16 X X H X L L X D7Burst write
n+17 A8HL LLXXD
7+1 Load read
n+18 X X H X L X L Q8Burst read
n+19 A9L L LLLLQ
8+1 Load write
5 298 t bl 12
6.42
12
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation(1)
Burst Write Operation(1)
Burst Read Operation(1)
Write Operation(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle Address R/WADV/LD CE 1(2) CEN BWxOE I/O Comments
nA
0H L L L X X X Ad dres s and Control me et s etup
n+1 X X X XXXLQ
0Contents of Address A0 Re ad Out
5 298 t bl 13
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
Comments
nA
0H L L L X X X Address and Control meet setup
n+1 X X H XLXLQ
0Address A0 Read Out, Inc. Count
n+2 X X H XLXLQ
0+1 Address A0+1 Read Out, Inc. Count
n+3 X X H XLXLQ
0+2 Address A0+2 Read Out, Inc. Count
n+4 X X H XLXLQ
0+3 Address A0+3 Read Out, Load A1
n+5 A1HL LLXLQ
0Address A0 Read Out, Inc. Count
n+6 X X H XLXLQ
1Address A1 Read Out, Inc. Count
n+7 A2HL LLXLQ
1+1 Address A1+1 Read Out, Load A2
5 298 t bl 14
Cycle Address R/WADV/LD CE 1(2) CEN BWxOE I/O Comments
nA
0L L L L L X X Ad dress and Control mee t se tup
n+1 X X X X L X X D0Write to Address A0
5298 tbl 15
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
Comments
nA
0L L L L L X X Address and Control meet setup
n+1 X X H X L L X D0Address A0 Write, Inc. Count
n+2 X X H X L L X D0+1 Address A0+1 Write, Inc. Count
n+3 X X H X L L X D0+2 Address A0+2 Write, Inc. Count
n+4 X X H X L L X D0+3 Address A0+3 Write , Load A1
n+5 A1L L LLLXD
0Address A0 Write, Inc. Count
n+6 X X H X L L X D1Address A1 Write, Inc. Count
n+7 A2L L LLLXD
1+1 Address A1+1 Wri te , Lo ad A2
5 298 t bl 16
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
13
Read Operation with Clock Enable Used(1)
Write Operation with Clock Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle Address R/WADV/LD CE 1
(2)
CEN BWxOE I/O Comments
nA
0H L L L X X X AddressA0 and Co ntro l me et setup
n+1 X X X X H X X X Clo ck n+1 Igno red
n+2 A1HL LLXLQ
0Address A0 Re ad o ut, Lo ad A1
n+3 X X X X H X L Q0Clock Ignored. Data Q0 is on the bus.
n+4 X X X X H X L Q0Clock Ignored. Data Q0 is on the bus.
n+5 A2HL LLXLQ
1Address A1 Re ad out, Lo ad A 2
n+6 A3HL LLXLQ
2Address A2 Re ad out, Lo ad A 3
n+7 A4HL LLXLQ
3Address A3 Re ad out, Lo ad A 4
5 298 t bl 17
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
Comments
nA
0L L LLLXXAddress A
0 and Co ntro l me et se tup.
n+1 X X X X H X X X Clock n+1 Ignored .
n+2 A1L L LLLXD
0Write d ata D0, Load A1.
n+3 X X X X H X X X Clo c k Igno red .
n+4 X X X X H X X X Clo c k Igno red .
n+5 A2L L LLLXD
1Write Data D1, Load A2
n+6 A3L L LLLXD
2Write Data D2, Load A3
n+7 A4L L LLLXD
3Write Data D3, Load A4
5 298 t bl 18
6.42
14
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
Write Operation with Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X Z Deselected.
n+2 A0H L L L X X Z Address A0 and Co ntro l me et se tup .
n+3 X X L H L X L Q0Address A0 read out, Deselected.
n+4 A1H L L L X X Z Address A1 and Control meet setup.
n+5 X X L H L X L Q1Address A1 read out, Deselected.
n+6 X X L H L X X Z Deselected.
n+7 A2H L L L X X Z Address A2 and Co ntro l me et se tup .
n+8 X X L H L X L Q2Address A2 read out, Deselected.
n+9 X X L H L X X Z Deselected.
5 298 t bl 19
Cycle
Address
R/
W
ADV
/LD CE
(2)
CEN BW
x
OE
I/O
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X Z Deselected.
n+2 A0L L LLLXZAddress A
0 and Co ntro l me et se tup
n+3 X X L H L X X D0Data D0 Write In, Deselected.
n+4 A1L L LLLXZAddress A
1 and Co ntro l me et se tup
n+5 X X L H L X X D1Data D1 Write In, Deselected.
n+6 X X L H L X X Z Deselected.
n+7 A2L L LLLXZAddress A
2 and Co ntro l me et se tup
n+8 X X L H L X X D2Data D2 Write In, Deselected.
n+9 X X L H L X X Z Deselected.
5 298 t bl 20
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V±5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Load AC Test Conditions
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V±5%)
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI| Input Leak age Curre nt VDD = Max., VIN = 0V to VDD ___ 5µA
|ILI|LBO Inp ut Le akag e Current(1) VDD = Max., VIN = 0V to VDD ___ 30 µA
|ILO| Output Leakage Current VOUT = 0V to VCC ___ 5µA
VOL Outp ut L o w Vo l tag e IOL = +8mA, VDD = Min. ___ 0.4 V
VOH Outp ut Hig h Vo ltag e IOH = -8mA, VDD = Min. 2.4 ___ V
5298 tbl 21
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Unit
Com'l
Ind
Com'l
Ind
Com'l
Ind
IDD Operating Power
Supply Current Device Selecte d, Outp uts Open,
ADV/LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX(2) 275 295 250 60 225 60 mA
ISB1 CMOS Standby Po wer
Supply Current Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = 0(2,3) 40 60 40 60 40 60 mA
ISB2 Clock Running Power
Supply Current Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = fMAX(2,3) 105 125 100 120 95 115 mA
ISB3 Id le Po we r
Supply Current Device Selecte d, Outp uts Open,
CEN > VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX(2,3) 40 60 40 60 40 60 mA
IZZ Full Sleep Mode
Supply Current Device Selecte d, Outp uts Open,
CEN < VIL, VDD = Max., ZZ > VHD
VIN > VHD or < VLD, f = fMAX(2,3) 40 60 40 60 40 60 mA
5298 tb l 22
Input Pulse Levels
Inp ut Ri s e / Fa ll Time s
Inp ut Timing Re fere nce Le ve ls
Outp ut Refe re nce Le ve ls
Outp ut Lo ad
0 to 3V
2ns
1.5V
1.5V
Figure 1
5 298 t b l 23
VDDQ/2
50Ω
I/O Z0=50Ω
5298 drw 04 ,
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5298 drw 05
•
••
•
•
,
6.42
16
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
7.5ns
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC Clo ck Cyc le Time 10 ____ 10.5 ____ 11 ____ ns
tCH(1) Clock High Pulse Width 2.5 ____ 2.7 ____ 3.0 ____ ns
tCL(1) Clock Low Pulse Width 2.5 ____ 2.7 ____ 3.0 ____ ns
Output Parameters
tCD Cl o c k Hi g h to Valid Data ____ 7.5 ____ 8____ 8.5 ns
tCDC Cl o ck Hig h to Data Chang e 2 ____ 2____ 2____ ns
tCLZ(2,3,4) Cl oc k Hig h to Outp ut Active 3 ____ 3____ 3____ ns
tCHZ(2,3,4) Cl o ck Hig h to Data Hig h-Z ____ 5____ 5____ 5ns
tOE Outp ut Enab le Ac c ess Time ____ 5____ 5____ 5ns
tOLZ(2,3) Ou tp ut E nable Lo w to Data Ac tiv e 0 ____ 0____ 0____ ns
tOHZ(2,3) Ou tp ut E nab le Hi g h to Data Hig h-Z ____ 5____ 5____ 5ns
Set Up Times
tSE Clock Enable Se tup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
tSA Address Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
tSD Data In Se tup Ti me 2. 0 ____ 2.0 ____ 2.0 ____ ns
tSW Re ad/Write (R/W) Se tup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
tSADV Ad vance/Lo ad (ADV/ LD) S etup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
tSC Chip E nab le /Se l ect Se tup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
tSB Byte Write Enable (BWx) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
Hold Tim es
tHE Clo c k Enab le Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHD Data In Ho l d Time 0. 5 ____ 0.5 ____ 0.5 ____ ns
tHW Re ad/Write (R/W) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHADV Ad vance /Lo ad (ADV/LD) Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHC Chip E nab le /Se le ct Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHB Byte Write Enable (BWx) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
5298 tbl 24
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
17
Timing Waveform of Read Cycle(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don’t care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
(CENhigh, eliminates
current L-H clock edge)
Q(A
2+1
)
t
CD
Read
t
CLZ
t
CHZ
t
CD
t
CDC
Q(A
2+2
)
Q(A
1
)Q(A
2
)Q(A
2+3
)Q(A
2+3
)Q(A
2
)
Burst Read
Read
DATA
OUT
(Burst Wraps around
to initial state)
t
CDC
t
HADV
5298 drw 06
R/W
CLK
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
t
HE
t
SE
A
1
A
2
t
CH
t
CL
t
CYC
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
CEN
,
6.42
18
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base
address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don’t care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
DATA
IN
D(A
1
)D(A
2
)
t
HD
t
SD(CENhigh, eliminates
current L-H clock edge)
D(A
2+1
)D(A
2+2
)D(A
2+3
)D(A
2
)
Burst Write
Write Write
(Burst Wraps around
to initial state)
t
HD
t
SD
t
CH
t
CL
t
CYC
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
t
HB
t
SB
5298 drw 07
B(A
1
)B(A
2
)B(A
2+1
)B(A
2+2
)B(A
2+3
)B(A
2
)
,
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
19
Timing Waveform of Combined Read and Write Cycles(1,2,3)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
DATA
OUT
Q(A
3
)
Q(A
1
)Q(A
6
)Q(A
7
)
t
CD
Read Read
Read Read
t
CHZ
5298 drw 08
Write t
CLZ
D(A
2
)D(A
4
)
t
CDC
D(A
5
)
Write
t
CH
t
CL
t
CYC
t
HW
t
SW
t
HA
t
SA
A
4
A
3
t
HC
t
SC
t
SD
t
HD
t
HADV
t
SADV
A
6
A
7
A
8
A
5
A
9
DATA
IN
t
HB
t
SB
Write
D(A
8
)
Write
B(A2) B(A
4
)B(A
5
)B(A
8
)
OE
,
6.42
20
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur.
All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
DATA
OUT
Q(A
1
)
t
CDC
Q(A
3
)
t
CD
t
CLZ
Q(A
1
)Q(A
4
)
t
CD
t
CDC
t
CHZ
D(A
2
)
t
SD
t
HD
t
CH
t
CL
t
CYC
t
HC
t
SC
A
4
A
5
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
A
3
t
HB
t
SB
DATA
IN
5298 drw 09
B(A
2
)
,
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
21
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the
deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
R/W
A1
CLK
ADV/LD
ADDRESS
CE
1
,CE
2(2)
OE
DATA
OUT
Q(A
1
)Q(A
2
)Q(A
4
)
t
CLZ
Q(A
5
)
t
CD
t
CHZ
t
CDC
D(A
3
)
t
SD
t
HD
t
CH
t
CL
t
CYC
t
HC
t
SC
A
5
A
3
t
SB
DATA
IN
t
HE
t
SE
A
2
t
HA
t
SA
A
4
t
HW
t
SW
t
HB
CEN
t
HADV
t
SADV
5298 drw 10
BW
1
-BW
4
B(A
3
)
,
,
6.42
22
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
23
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
24
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
165 Ball Grid Array (fBGA) Package Diagram Outline
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
25
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATAOUT
tOHZ tOLZ
tOE
Q
5298 drw 11
Q
,
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
S
Power
XX
Speed
XX
Package
PF
BG
BQ
XXXX
75
80
85 Access time (tCD)intenthsofnanoseconds
5298 drw 12
Device
Type
IDT71V65703
IDT71V65903 256Kx36 Flow-Through ZBT SRAM
512Kx18 Flow-Through ZBT SRAM
,
X
Process/
Temperature Range
Blank
ICommercial (0°C to +70°C)
Industrial (-40°C to +85°C)
6.42
26
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
12/31/99 Created new part number and datasheet from 71V657/59 to 71v65703/5903
04/20/00 Pg.5,6 Add JTAG reset pins to TQFP pin configuration; removed footnote
Add clarification note to Recommended Operating Temperature and Absolute Max Ratings tables
Pg. 7 Add note to BGA pin configuration; corrected typo within pinout
Pg. 21 InsertTQFP Package Diagram Outline
05/23/00 Add new package offering: 13mm x 15mm, 165 fine pitch ball grid array
Pg. 23 Correction on 119 Ball Grid Array Package diagram Outline
07/28/00 Pg. 5-8 Remove JTAG pins from TQFP, BG119 and BQ165 pinouts, refer to IDT71V656xx and
IDT71V658xx device errata sheet
Pg. 7,8 Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout
Pg. 23 Update BG119 package diagram dimensions
11/04/00 Pg. 8 Add reference note to pin N5 on the BQ165 pinout, reserved for JTAG TRST
Pg. 15 Add Izz to DC Electrical Characteristics
12/04/02 Pg. 1-25 Changed datasheet fromPreliminary to final release.
Pg. 5,6,15,16,25 Added I temp to datasheet
12/18/02 Pg. 1,2,5,6,7,8 Removed JTAG functionality for current die revision.
Pg. 7 Corrected pin configuration on the x36, 119 BGA. Switched pins I/O0and I/OP1.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Rd 800-345-7015 or 408-284-8200 sramhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775 800-345-7015 or
www.idt.com 408/284-4555
