FSDM0565RWDTU - Fairchild Semiconductor

www.fairchildsemi.com

Rev.1.0.5

Features

• Internal Avalanche Rugged Sense FET

• Advanced Burst-Mode operation consumes under 1 W at

240VAC & 0. 5W load

• Precision Fixed Operating Frequency (66kHz)

• Internal Start-up Circuit

• Pulse by Pulse Current Limiting

• Abnormal Over Current Protection (AOCP)

• Over Voltage Protection (OVP)

• Over Load Protection (OLP)

• Internal Thermal Shutdown Function (TSD)

• Auto- Re st art Mo de

• Under Voltage Lock Out (UVLO) with hysteresis

• Low Operating Current (2.5mA)

•

Built-in Soft Start

Application

• SMPS for LCD monitor and STB

• Adaptor

Description

The FSDM0565R is an integrated Pulse Width Modulator

(PWM) and Sense FET specifically designed for high

performance offline Switch Mode Power Supplies (SMPS)

with minimal external components. This device is an

integrated high voltage power switching regulator which

combine an avalanche rugged Sense FET with a current mode

PW M c ontrol bloc k. The PWM controller includes integrated

fixed frequency oscillator, under voltage lockout, leading edge

blanking (LEB), optimized gate driver, internal soft start,

temperature compensated precise current sources for a loop

compensation and self protection circuitry. Compared with

discrete MOSFET and PWM controller sol u t i on , i t ca n r ed u c e

total cost, component count, size and weight simultaneously

increasing efficiency, productivity, and system reliability. This

device is a basic platform well suited for cost effective

des i gns of flyb a ck converters.

Table 1. Notes: 1. Typical continuous power in a non-ven-

tilat ed enclo se d ada pt er me as ured at 50°C ambient. 2.

Maximum practical continuous power in an op en frame

design at 50°C ambient. 3. 230 VAC or 100/115 VAC with

doubler.

Typical Circuit

Figu re 1. Typic al Flyback Appli catio n

OUTPUT POWER TABLE

PRODUCT 230VAC ±15%(3) 85-265VAC

Adapt-

er(1) Open

Frame(2) Adapt-

er(1) Open

Frame(2)

FSDM0565R 60W 70W 50W 60W

FSDM07652R 70W 80W 60W 70W

Drain

Source

Vstr

Vfb Vcc

PWM

IN DC

OUT

FSDM0565R

Green Mode Fairchild Pow er Switch (FPSTM)

FSDM0565R

Internal Block Diagram

Figure 2. Func tiona l Bloc k Diagr am of FSDM0565R

8V/12V

3 1

Vref Internal

Bias

OSC

Vcc Vref

delay

TSD

Vovp

Vcc

Vocp

2.5R

Vcc good

Vcc Drain

N.C

Vfb

GND

AOCP

Gate

driver

Vstr

start

Vcc good

0.5/0.7V

LEB

PWM

Soft start

Switching disable

FSDM0565R

Pin Definitions

Pin Configuration

Figure 3. Pin Configuration (Top View)

Pin Number Pin Name Pin Function Description

1Drain

This pin is the high voltage power Sense FET drain. It is designed to drive the

transformer directly.

2 GND This pin is the control ground and the Sense FET source.

3Vcc

This pin is the positive supply voltage input. During start up, the power is sup-

plied by an internal high voltage current source that is connected to the Vstr pin.

When Vcc reaches 12V, the internal high volt age current source is disabled and

the power is supplied from the auxiliary transformer winding.

4Vfb

This pin is internally connected to the inverting input of the PWM comparator.

The collector of an opto-coupler is typically tied to this pin. For st able operation,

a capac itor should be placed between this pin and GND. If the voltage of this pin

reaches 6.0V, the over load protection is activated resulting in shutdown of the

FPS

5N.C-

6Vstr

This pin is connected directly to the high voltage DC link. At startup, the internal

high voltage current source supplies internal bias and charges the external ca-

pacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal cur-

rent source is disabled.

6.Vstr

5.N.C.

4.Vfb

3.Vcc

2.GND

1.Drain

TO-220F-6L

FSDM0565R

Absolute Maximum Ratings

(Ta=25°C, unless otherwise specified)

Notes:

1. Repetitive rating: Pulse width limited by maximum junction temperature

2. L=14mH, starting Tj=25°C

3. L=13uH, starting Tj=25 °C

Thermal Impedance

Notes:

1. Free standing with no heat-sink under natural convection.

2. Infinite cooling condition - Refer to the SEMI G30-88.

Parameter Symbol Value Unit

Drain-source voltage V

DSS

650 V

Vstr Max Voltage V

STR

650 V

Pulsed Drain current (Tc=25

°C)

(1)

11 A

Continuous Drain Current(Tc=25

°C)

2.8 A

Continuous Drain Current(Tc=100

°C)

1.7 A

Single pulsed avalanche energy

(2)

190 mJ

Single pulsed avalanche current

(3)

-A

Supply voltage V

20 V

Input voltage range V

-0.3 to V

Total power dissipation(Tc=25

°C)

(Watt H/S) 45 W

Operating junction temperature T

Internally limited °C

Operating ambient temperature T

-25 to +85 °C

Storage temperature range T

STG

-55 to +150 °C

ESD Capability, HBM Model (All pins

excepts for Vstr and Vfb)

2.0

(GND-Vstr/Vfb=1.5kV) kV

ESD Capability, Machine Model (All pins

excepts for Vstr and Vfb)

300

(GND-Vstr/Vfb=225V) V

Parameter Symbol Value Unit

Junction-to-Ambient Thermal

(1)

49.90 °C/W

Junction-to-Case Thermal

(2)

2.78 °C/W

FSDM0565R

Electrical Characteristics

(Ta = 25°C unless otherwise specified)

Parameter Symbol Condition Min. Typ. Max. Unit

Sense FET SECTION

Drain source breakdown voltage BV

DSS

= 0V, I

= 250µA 650 - - V

Zero gate voltage drain curr ent I

DSS

= 650V, V

= 0V - - 50 µA

= 520V

= 0V, T

= 125°C- - 200 µA

Static drain source on resistance

(1)

DS(ON)

= 10V, I

= 2.5A - 1.76 2.2

Ω

Output capacitance C

OSS

= 0V, V

= 25V,

f = 1MHz -78-pF

Turn on delay time T

D(ON)

= 325V, I

= 5A

(MOSFET swit ching

time is essentially

independent of

operating temperature)

-22-

Rise time T

-52-

Turn off delay time T

D(OFF)

-95-

Fall time T

-50-

CONTROL SECTION

Initial frequency F

OSC

= 3V 60 66 72 kHz

Voltage stability F

STABLE

13V ≤ Vcc ≤ 18V 0 1 3 %

Temperature stability

(2)

∆F

OSC

-25°C ≤ Ta ≤ 85°C0±5±10%

Maximum duty cycle D

MAX

-758085%

Minimum duty cycle D

MIN

---0%

Start threshold voltage V

START

=GND 11 12 13 V

Stop threshold voltage V

STOP

=GND 789V

Feedback source current I

=GND 0.7 0.9 1.1 mA

Soft-start time T

Vfb=3 - 10 15 ms

Leading Edge Blanking time T

LEB

- - 250 - ns

BURST MODE SECTION

Burst Mode Voltages

(2)

BURH

Vcc=14V - 0.7 - V

BURL

Vcc=14V - 0.5 - V

PROTECTION SECTION

Peak current limit

(4)

OVER

=5V, V

=14V 2.0 2.25 2.5 A

Over voltage protection V

OVP

-181920V

Abnormal Over current protection

current

(3)

AOCP

- 4.99 5.54 6.09 A

Thermal shutdown temperature

(2)

130 145 160 °C

Shutdown feedback voltage V

≥ 5.5V 5.5 6.0 6.5 V

FSDM0565R

Notes:

1. Pulse test : Pulse width ≤ 300 µS, duty ≤ 2%

2. These parameters, although guaranteed at the design, are not tested in mass production.

3. These parameters, although guaranteed, are tested in EDS(wafer test) process.

4. These parameters indicate the inductor current.

5. This parameter is the current flowing into the control IC.

Shutdown delay current I

DELAY

=5V 2.8 3.5 4.2 µA

TOTAL DEVICE SECT ION

Operating supply current

(5)

=GND, V

=14V

-2.55mAI

OP(MIN)

=GND, V

=10V

OP(MAX)

=GND, V

=18V

FSDM0565R

Comparison Between FS6M07652RTC and FSDM0565R

Function FS6M07652RTC FSDM0565R FSDM0565R Advantages

Soft-Start Adjustable soft-start

time using an

external capacitor

Internal soft-start with

typically 10ms (fixed) • Gradually increasing current limit

during soft-start further reduces peak

current and voltage component

stresses

• Eliminates external components used

for soft-start in most applications

• Reduces or eliminates output

overshoot

Burst Mode Operation • Built into controller

• Output voltage

drops to around

half

• Built into controller

• Output voltage fixed • Improve light load efficiency

• Reduces no-load consumption

FSDM0565R

Typical Performance Characteristics

(These Characteristic Graphs are Normalized at Ta= 25°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

Operating Frequency

(Fosc)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

Start Thershold Voltage

(Vstart)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

Stop Threshold Voltage

(Vstop)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

Maximum Duty Cycle

(Dmax)

Operating Current vs. Temp Start Threshold Voltage vs. Temp

Stop Thre shold Voltage vs. Temp Operating Freqency vs. Temp

Maximum Duty vs. Temp Feedback Sour ce Current vs. Temp

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

Operating Current

(Iop)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

FB Source Current

(Ifb)

FSDM0565R

Typical Performance Characteristics

(Continued)

(These Characteristic Graphs are Normalized at Ta= 25°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

Shutdown Delay Current

(Idelay)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

Over Voltage Protection

(Vovp)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-50 -25 0 25 50 75 100 125

Junction Temperature(℃)

Peak Current Limit(Self protection)

(Iover)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

FB Burst Mode Enable Voltage

(Vfbe)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

FB Burst Mode Disable Voltage

(Vfbd)

ShutDown Feedback Voltage vs. Temp ShutDown Delay Current vs. Temp

Over Voltage Protection vs. Temp Burst Mode Enable Vo ltage vs. Temp

Burst Mode Disable Voltage vs. Temp Current Limit vs. Temp

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 150

Junction Temperature(℃)

Shutdown FB Voltage

(Vsd)

FSDM0565R

Typical Performance Characteristics

(Continued)

(These Characteristic Graphs are Normalized at Ta= 25°C)

Soft Start Time vs. Temp

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-50 -25 0 25 50 75 100 125

Junction Temperature(℃)

Soft Start Time

(Normalized to 25℃)

FSDM0565R

Functional Description

1. 1.

1. Startup : In previous generations of Fairchild Power

Switches (FPS

) the Vcc pin had an external start-up

resistor to the DC input voltage line. In this generation the

startup resistor is replaced by an internal high voltage current

source. At startup, an internal high voltage current source

supplies the internal bias and charges the external capacitor

vcc

) that is connected to the Vcc pin as illustrated in figure

4. When Vcc reaches 12V, the FPS

begins switching and

the internal high voltage current source is disabled. Then, the

FPS

continues its normal switching operation and the

power is supplied from the auxiliary transformer winding

unless Vcc goes below the stop voltage of 8V.

Figure 4. Internal startup circuit

2. Feedback Control : FS DM0565R employ s curre nt mode

control, as shown in figure 5. An opto-coupler (such as the

H11A817A) and shunt regulator (such as the KA431) are

typically used to implement the feedback network.

Comparing the feedback volta ge with the voltage across the

Rsense resistor plus an offset voltage makes it possible to

control the switching duty cycle. When the reference pin

voltage of the KA431 exceeds the internal r eference voltage

of 2.5V, the H11A817A LED current increases, thus pulling

down the feedback voltage and reducing the duty cycle. This

event typically happens when the input voltage is increased

or the output load is decreased.

2.1 Pulse-by-pulse current limit: Because current mode

control is employed, the peak cur ren t thr ough the Sense FET

is limited by the inv erting input of PWM c omparato r (Vfb *)

as shown in figure 5. Assuming that the 0.9mA current

sourc e flows only thro ugh t he inte rnal r esistor (2.5R +R= 2.8

kΩ), the cathode voltage of diode D2 is about 2.5V. Since D1

is blocked when the feedback voltage (Vfb) exceeds 2.5V,

the max i mu m vo l ta ge of th e cat ho de of D2 i s cla m pe d at thi s

voltage, thus clamping Vfb*. Therefore, the peak value of

the current through the Sense FET is limited.

2.2 Leading edge blanking (LEB) : At the instant the

internal Sense FET is turned on, there usually exists a high

curr ent spike thro ugh the Se nse FET, caused by pri ma r y- side

capacitance and secondary-side rectifier reverse recovery.

Excessive voltage across the Rsense resistor would lead to

incorrect feedback operation in the current mode PWM

control. To counter th is effect, the FPS

employs a leading

edge blanking (LEB) circuit. This circuit inhibits the PWM

comparator for a short time (T

LEB

) after the Sense FET is

turned on.

Figure 5. Pulse width modul ation (PWM) circuit

3. Protection Circuit : The FSDM0565R has several self

protective functions such as over load protection (OLP),

abnormal over current protection (AOCP), over voltage

protection (OVP) and thermal shutdown (TSD). Because

these protection circuits are fully integrated into the IC

without external components, the reliability can be improved

without increasing cost. Once the fault condition occurs,

switching is terminated an d the Sense FET rem ains off. This

causes Vcc to fall. When Vcc reaches the UVLO stop

voltage, 8V, the protection is reset and the internal high

voltage current source charges the Vcc capacitor via th e Vstr

pin. When Vcc reaches the UVLO start voltage,12V, the

FPS

resumes its normal operation. In this manner, the

auto-restart can alternately enable and disable the switching

of the power Sense FET until the fault condition is

eliminated (see figure 6).

8V/12V

Vref

Internal

Bias

Vcc 6Vstr

start

Vcc good

Vcc

OSC

Vcc Vref

delay

VSD

2.5R

Gate

driver

OLP

D1 D2

Vfb

KA431

H11A817A

Rsense

SenseFET

FSDM0565R

Figure 6. Auto restart op erati on

3.1 Over Load Protection (OLP) : Overload is defined as

the load current exceeding a pre-set level due to an

unexpected event. In this situation, the protection circuit

should be activated in order to protect the SMPS. However,

even when the SMPS is in the normal operation, the over

load protection circuit can be activated during the load

transition. In order to avoid this undesired operation, the over

load protection circuit is designed to be activated after a

specified time to determine whether it is a transient situation

or an overload situation. Because of the pulse-by-pulse

current limit capability, the maximum peak current through

the Sense FET is limited, and therefore the maximum input

power is restricted with a given input voltage. If the output

consumes beyond this maximum power, the output voltage

(Vo) decreases below the set voltage. This reduces the

current through the opto-coupler LED, which also reduces

the opto-coupler transistor current, thus increasing the

feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked

and the 3.5uA current source starts to charge C

slow ly up t o

Vcc. In this condition, Vfb continues increasing until it

reaches 6V, when the switching operation is terminated as

shown in figure 7. The delay time for shutdown is the time

required to charge C

from 2.5V to 6.0V with 3.5uA. In

general, a 10 ~ 50 ms delay time is typical for most

applications.

Figure 7. Over load protection

3.2 Abnormal Over Current Protection (AOCP) : Even

though the FPS

has OLP (Over Load Protection) and

current mode PWM feedback, these are not enough to protect

the FPS

when a secondary side diode short or a

transformer pin short occurs. The FPS

has an internal

AOCP (Abnormal Over Current Protectio n) circuit as shown

in figure 8. When the gate turn-on signal is applied to the

power Sense FET, the AOCP block is enabled and monitors

the current through the sensing resistor. The voltage across

the resistor is then compared with a preset AOCP level. If the

sensing resistor voltage is greater than the AOCP level for

longer than 300ns, the reset signal is applied to the latch,

resulting in the shutdown of SMPS.

Figure 8. AOCP block

3.3 Over voltage Protection (OVP) : If the secondary side

feedback circuit were to malfunction or a solder defect

caused an open in th e feedback path, the current through the

opto-coupler transistor becomes almost zero. Then, Vfb

climbs up in a similar manner to the over load situation,

forcing the preset maximum current to be supplied to the

SMPS until the over load protection is activated. Because

more energy than required is provided to the output, the

Fault

situation

12V

Vcc

Vds

Fault

occurs Fault

removed

Normal

operation Normal

operation

Power

FBFB

2.5V

2.5V2.5V

2.5V

6.0V

6.0V6.0V

6.0V

Over load protection

Over load protectionOver load protection

Over load protection

1212

= Cfb*(6.0-2.5)/I

= Cfb*(6.0-2.5)/I= Cfb*(6.0-2.5)/I

= Cfb*(6.0-2.5)/I

delay

delaydelay

delay

OSC

2.5R

GND

Gate

driver

LEB

PWM

Vaocp

AOCP

sense

FSDM0565R

output voltag e may exceed the ra ted voltage before the over

load protection is activated, resulting in the breakdown of the

devices in the secondary side. In order to prevent this

situation, an over voltage protection (OVP) circuit is

employed. In general, Vcc is proportional to the output

voltage and the FPS

uses Vcc instead of directly

monitoring the outp ut voltage. If V

exceeds 19V, an OVP

circuit is activated resulting in the termination of the

switching operation. In order to avoid undesired activation of

OVP during normal operation, Vcc should be designed to be

below 19V.

3.4 Thermal Shutdown (TSD) : The Sense FET and the

control IC are built in one package. This makes it easy for

the control IC to detect the heat generation from the Sense

FET. When the temperature exceeds approximately 150°C,

the thermal shutdown is activated.

4. Soft Start : The FPS

has an internal soft start circuit

that increases PWM comparator inverting input voltage

together with th e Sense FET current slo wly afte r it starts up.

The typical soft start time is 10msec, The pulse width to the

power switching device is progressively increased to

establish the correct working conditions for transformers,

inductors, and capacitors. The voltage on the output

capacitors is progressively increased with the intention of

smoothly establishing the required output voltage. It also

helps to p revent transformer saturation and reduce th e stress

on the secondary diode during startup.

5. Burst operatio n : In order to minimize power dissipation

in standby mode, the FPS

enters burst mode operation.

As the load decreases, the feedback voltage decreases. As

shown in figure 9, the device automatically enters burst

mode when the feedback voltage drops below

BURL

(500mV). At this point switching stops and the

output voltages start to drop at a rate dependent on standby

current load. This causes the feedback voltage to rise. Once

it passes V

BURH

(700mV) switching resumes. The feedback

voltage then falls and the process repeats. Burst mode

operation alternately enables and disables switching of the

power Sense FET thereby reducing switching loss in

Standby mode.

Figure 9. Waveforms of burst operation

Vds

0.5V

0.7V

Ids

set

time

Switching

disabled

T1 T2 T3

Switching

disabled

FSDM0565R

Typical application circuit

Features

• High efficiency (>81% at 85Vac input)

• Low zero load power consumption (<300mW at 240Vac input)

• Low standby mode power consumption (<800mW at 240Vac input and 0.3W load)

• Low component count

• Enhanced system reliability through various protection functions

• Intern al soft-start (10ms)

Key Design Notes

• Resistors R102 and R105 are employed to prevent start-up at low input voltage. After startup, there is no power loss in these

resistors since the startup pin is internally disconnected after startup.

• The delay time for over load protection is designed to be about 50ms with C106 of 47nF. If a faster triggering of OLP is

required, C106 can be reduced to 10nF.

• Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zene r diode

fails and remains short, which causes the fuse (F1) blown and prevents explosion of the opto-coupler (IC301). This zener

diode also increases the immunity against line surge.

1. Schematic

Application Output power Input voltage Output voltage (Max current)

LCD Monitor 40W Universal input

(85-265Vac)

5V (2.0A)

12V (2.5A)

C102

220nF

275VAC

LF101

23mH

C101

220nF

275VAC

RT1

5D-9

FUSE

250V

C103

100uF

400V

R102

30kΩ

ΩΩ

Ω

R105

40kΩ

ΩΩ

Ω

R103

56kΩ

ΩΩ

Ω

C104

2.2nF

1kV D101

UF 4007

C106

47nF

50V

C105

22uF

50V

D102

TVR10G R104

5Ω

ΩΩ

Ω

EER3016

BD101

2KBP06M3N257

R101

560kΩ

ΩΩ

Ω

IC1

FSDM0565R

Vstr

Vfb Vcc

Drain

GND

ZD101

22V

D202

MBRF10100

C201

1000uF

25V

C202

1000uF

25V

L201

12V, 2.5A

D201

MBRF1045

C203

1000uF

10V

C204

1000uF

10V

L202

5V, 2A

R201

1kΩ

ΩΩ

Ω

R202

1.2kΩ

ΩΩ

Ω

R204

5.6kΩ

ΩΩ

Ω

R203

12kΩ

ΩΩ

ΩC205

47nF

R205

5.6kΩ

ΩΩ

Ω

C301

4.7nF

IC301

H11A817A IC201

KA431

ZD102

10V

FSDM0565R

2. Transformer Schematic Diagram

3.Winding Specification

4.Electrical Characteristics

5. Core & Bobbin

Core : EER 3016

Bobbin : EER3016

Ae(mm2) : 96

No Pin (s→f) Wire Turns Winding Method

Na 4 → 50.2

× 1 8 Center Winding

Insulation: Polyester Tape t = 0.050mm, 2Layers

Np/2 2 → 10.4

× 1 18 Solenoid Winding

Insulation: Polyester Tape t = 0.050mm, 2Layers

N12v 10 → 80.3

× 3 7 Center Winding

Insulation: Polyester Tape t = 0.050mm, 2Layers

N5v 7 → 60.3

× 3 3 Center Winding

Insulation: Polyester Tape t = 0.050mm, 2Layers

Np/2 3 → 20.4

× 1 18 Solenoid Winding

Outer Insulation: Polyester Tape t = 0.050mm, 2Layers

Pin Specification Remarks

Inductance 1 - 3 520uH ± 10% 100kHz, 1V

Leakage Inductance 1 - 3 10uH Max 2

all short

EER3016

/2 N

12V

FSDM0565R

6.Demo Circuit Part List

Part Value Note Part Value Note

Fuse

C301 4.7nF Polyester Film Cap.

F101 2A/250V

NTC Inductor

RT101 5D-9 L201 5uH Wire 1.2mm

Resistor

L202 5uH Wire 1.2mm

R101 560K 1W

R102 30K 1/4W

R103 56K 2W

R104 5 1/4W

Diode

R105 40K 1/4W D101 UF4007

R201 1K 1/4W D102 TVR10G

R202 1.2K 1/4W D201 MBRF1045

R203 12K 1/4W D202 MBRF10100

R204 5.6K 1/4W ZD101 Zener Diode 22V

R205 5.6K 1/4W ZD102 Zener Diode 10V

Bridge Diode

BD101 2KBP06M 3N257 Bridge Diode

Capacitor

C101 220nF/275VAC Box Capacitor

Line Filter

C102 220nF/275VAC Box Capacitor LF101 23mH Wire 0.4mm

C103 100uF/400V Electrolytic Capacitor

C104 2.2nF/1kV Ceramic Capacitor IC101 FSDM0565R FPS

(5A,650V)

C105 22uF/50V Electrolytic Capacitor IC201 KA431(TL431) Voltage reference

C106 47nF/50V C eramic Capacitor IC301 H11A817A Opto-coupler

C201 1000uF/25V Electrolytic Capacitor

C202 1000uF/25V Electrolytic Capacitor

C203 1000uF/10V Electrolytic Capacitor

C204 1000uF/10V Electrolytic Capacitor

C205 47nF/50V Ceramic Capacitor

FSDM0565R

7. Layout

Figure 10. Layout Considerations for FSDM0565R

Figure 11. Layout Considerations for FSDM0565R

FSDM0565R

Package Dimensions

TO-220F-6L(Forming)

FSDM0565R

Ordering Information

WDTU : Form ing Ty pe

Product Number Package Marking Code BVdss Rds(on)Max.

FSDM0565RWDTU TO-220F-6L(Forming) DM0565R 650V 2.2 Ω

FSDM0565R

1/12/05 0.0m 001

 2005 Fairchild Semiconductor Corporation

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