April 2010 Rev 20 1/59
1
Numonyx® Forté™ Serial Flash Memory
M25P16
16 Mbit, serial Flash memory, 75 MHz SPI bus interface
Features
16 Mbit of Flas h me m or y
Page Program (up to 256 bytes) in 0.64 ms
(typical)
Sector Erase (512 Kbit) in 0.6 s (typical)
Bulk Erase (16 Mbit) in 13 s (typical)
2.7 V to 3.6 V single supply voltage
SPI bus compatible serial interface
75 MHz Clock rate (maximum)
Deep Power-down mode 1 µA (typical)
Electronic signatures
JEDEC standard two- byte signature
(2015h)
Unique ID code (UID) with 16 bytes read-
only, available upon customer request
RES instruction, one-byte, signature (14h ),
for backward compatibility
More than 100,000 Erase/Program cycles per
sector
Hardware Write Protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
More than 20 year data retention
Packages
RoHS compliant
Automotive Certified Parts Available
VDFPN8 (ME)
8 x 6 mm (MLP8)
SO16 (MF)
300 mils width
VFDFPN8 (MP)
6 × 5 mm (MLP8)
SO8N (MN)
150 mils width SO8W (MW)
208 mils width
PDIP8 (BA)
300 mils width
UFDFPN8 (MC)
(MLP8 4 x 3 mm)
www.numonyx.com
Contents M25P16
2/59
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 12
4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 12
4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M25P16 Contents
3/59
6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 26
6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 32
7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12 Ordering Information, Standard Parts . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13 Ordering Information, Automotive Parts . . . . . . . . . . . . . . . . . . . . . . . . 55
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
List of tables M25P16
4/59
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Read Identification (RDID) data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 11. Data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. AC characteristics (110 nm technology). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. AC characteristics (25 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 18. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 20. SO8 wide – 8 lead plastic small outline, 208 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 21. SO16 wide – 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . 49
Table 22. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 23. UFDFPN (MLP8) 8-lead ultra thin fine pitch dual flat package no lead , 4X3 mm package me-
chanical data52
Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
M25P16 List of figures
5/59
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SO8, VFQFPN, VDFPN, and PDIP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20
Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 22
Figure 12. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 25
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. Release from Deep Power-down (RES) instruction sequence. . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 24. Write Protect setup an d ho ld timing du rin g WR SR when SRWD = 1. . . . . . . . . . . . . . . . . 42
Figure 25. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 26. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 27. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat pa ckage no lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 28. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 29. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 47
Figure 30. SO8W – 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . . 48
Figure 31. SO16 wide – 16-lead plastic small outline, 300 mils body width, package outline . . . . . . . 49
Figure 32. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package outline. . . . . . . . . . . 50
Figure 33. UFDFPN (MLP8) 8-lead ultra thin fine pitch dual flat package no lead, 4X3 mm package me-
chanical data51
Description M25P16
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1 Description
The M25P16 is a 16 Mbit (2 Mbit × 8) serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Prog ram
instruction.
The memory is organized as 32 sectors, each containing 256 pages. Each page is 256
bytes wide. Thus, the whole memory can be viewed as consisting of 8192 pages, or 2 097
152 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
Figure 1. Logic diagram
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data input Input
Q Serial Data output Output
SChip Select Input
WWrite Protect Input
HOLD Hold Input
VCC Supply voltage
VSS Ground
AI05762
S
VCC
M25P16
HOLD
VSS
W
Q
C
D
M25P16 Description
7/59
Figure 2. SO8, VFQFPN, VDFPN, and PDIP8 connections
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
Figure 3. SO16 connections
1. DU = Don’t use
2. See Package mechanical section for package dimensions, and how to identify pin-1.
1
AI08517
2
3
4
8
7
6
5DVSS C
HOLDQ
SV
CC
W
M25P16
1
AI08594B
2
3
4
16
15
14
13
DU
DU DU
DU
VCC
HOLD
DUDU
M25P16
5
6
7
8
12
11
10
9WQ VSS
DU
DU
S
D
C
Signal description M25P16
8/59
2 Signal description
2.1 Serial Data output (Q)
This output signal is u sed to transfer dat a serially out of the device . Data is shif ted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into th e device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an intern al Program, Erase or Write Status Register cycle is in pr ogress,
the device will be in the Standby mode (this is not the Deep Power-down mode). Driving
Chip Select (S) Low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the star t of any
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to p ause any serial communica tions with the device without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
2.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against program or erase in structio ns (as specified by the values in the BP2, BP1
and BP0 bits of the Status Register).
M25P16 Signal description
9/59
2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
SPI modes M25P16
10/59
3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The dif ference b etween the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Standby mode and not tran sfe rr ing da ta:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only
one device is sele cted at a time , so o nly one device drives the Serial Dat a outp ut (Q) line at
a time, the other devices are high impedance. Re sistors R (represented in Figure 4) ensure
that the M25P16 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Ma ster may enter a state wher e all inputs/output s are in high impedance at
the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the tSHCH requirement is met). The
typical value of R is 100 k Ω, assuming that the time constant R*Cp (Cp = parasitic
capacit a nce of the bu s line) is sho rter than th e tim e during which th e Bus Master leaves the
SPI bus in high impedance.
AI12836b
SPI Bus Master
SPI memory
device
SDO
SDI
SCK
CQD
S
SPI memory
device
CQD
S
SPI memory
device
CQD
S
CS3 CS2 CS1
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
RR R
VCC
VCC VCC VCC
VSS
VSS VSS VSS
R
M25P16 SPI modes
11/59
Example: Cp = 50 pF, that is R*Cp = 5 µs: the application must ensure that the Bus Master
never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs.
Figure 5. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
Operating features M25P16
12/59
4 Operating features
4.1 Page programming
To program one data byte, two instructions are required: Write Enable (WREN), which is
one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This
is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instru ction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Page Program (PP)).
4.2 Sector Erase and Bulk Erase
The Page Program (PP) instru ction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a tim e, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instr uc tio n. This starts an internal Erase cycle (of
duration tSE or tBE).
The Erase inst ru ctio n mus t be preceded by a Write Enable (WREN) ins tru ct ion .
4.3 Polling during a Write, Program or Erase cycle
A further improvemen t in the time to Write Status Register (WRSR), Pr og ram (PP) or Era se
(SE or BE) can be achieved by not waiting for the worst case d elay (tW, tPP, tSE, or tBE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application progr am
can monitor its value, polling it to est ablish when the previous Write cycle, Program cycle or
Erase cycle is complete.
4.4 Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active
Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Standby Power mode. The device consumption
drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
While in the Deep Power-down mode, the device ignores all Write, Pro gram and Erase
instructions (see Deep Power- down (DP)). This can be used as an e xtra softwar e protection
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.
M25P16 Operating features
13/59
4.5 Status Register
The Status Register contains a number of st atu s and contr ol bi ts that can be read or set (as
appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
4.6 Protection modes
The environme nts where non -vo la tile memo ry de vice s ar e us ed can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P16 features the following data protection mechanisms:
Power on reset and an internal timer (tPUW) can provide protection aga inst inadvertent
changes while the power supply is outside the operating specification
Program, Erase and Write S t atus Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This b it is retur ned to its reset state
by the following events:
–Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Progra m (PP) instr uc tio n co mple tion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Software Protected Mode (SPM): The Block Protect bits (BP2, BP1, BP0) allow part of
the memory to be configured as read-only.
Hardware Protected Mode (HPM): The Write Protect (W) signal allows the Block
Protect bits (BP2, BP1, BP0) and the Status Register Write Disable bit (SRWD) to be
protected.
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all Write, Program and Erase instructions are ignored.
Operating features M25P16
14/59
4.7 Hold condition
The Hold (HOLD) signal is used to p ause any serial communica tions with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 6).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low (this is shown in Figure 6: Hold condition activation).
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the st ate of the internal logic remains unch anged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold con dition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Table 2. Protected area sizes
Status Register
content Memor y content
BP2
bit BP1
bit BP0
bit Protected ar ea Unprotec te d ar e a
0 0 0 none All sectors(1) (32 sectors: 0 to 31)
1. The device is ready to accept a Bulk Erase instruction only if all Block Protect bits (BP2, BP1, BP0) are 0.
0 0 1 Upper 32nd (Sector 31) Lower 31/32nds (31 sectors: 0 to 30)
0 1 0 Upper sixteenth (2 sectors: 30 and 31) Lower 15/16ths (30 sectors: 0 to 29)
0 1 1 Upper eighth (4 sectors: 28 to 31) Lower seven-eighths (28 sectors: 0 to 27)
1 0 0 Upper quarter (8 sectors: 24 to 31) Lower three-quarters (24 sectors: 0 to 23)
1 0 1 Upper half (16 sectors: 16 to 31) Lower half (16 sectors: 0 to 15)
1 1 0 All sectors (32 sectors: 0 to 31) none
1 1 1 All sectors (32 sectors: 0 to 31) none
M25P16 Operating features
15/59
Figure 6. Hold condition activation
AI02029D
HOLD
C
Hold
condition
(standard use)
Hold
condition
(non-standard use)
Memory organization M25P16
16/59
5 Memory organization
The memory is organized as:
2 097 152 bytes (8 bits each)
32 sectors (512 Kbits, 65536 bytes each)
8192 pages (256 bytes each) .
Each pag e can be individually programme d (bits are programme d from 1 to 0). The device is
sector or bulk erasable (bits are erased from 0 to 1) but not page erasable.
Figure 7. Block diagram
AI04987
HOLD
S
WControl Logic High voltage
Generator
I/O Shift Register
Address Register
and Counter 256 byte
Data Buffer
256 bytes (page size)
X Decoder
Y Decoder
Size of the
read-only
memory area
C
D
Q
Status
Register
00000h
1FFFFFh
000FFh
M25P16 Memory organization
17/59
Table 3. Memory organization
Sector Address range
31 1F0000h 1FFFFFh
30 1E0000h 1EFFFFh
29 1D0000h 1DFFFFh
28 1C0000h 1CFFFFh
27 1B0000h 1BFFFFh
26 1A0000h 1AFFFFh
25 190000h 19FFFFh
24 180000h 18FFFFh
23 170000h 17FFFFh
22 160000h 16FFFFh
21 150000h 15FFFFh
20 140000h 14FFFFh
19 130000h 13FFFFh
18 120000h 12FFFFh
17 110000h 11FFFFh
16 100000h 10FFFFh
15 0F0000h 0FFFFFh
14 0E0000h 0EFFFFh
13 0D0000h 0DFFFFh
12 0C0000h 0CFFFFh
11 0B0000h 0BFFFFh
10 0A0000h 0AFFFFh
9 090000h 09FFFFh
8 080000h 08FFFFh
7 070000h 07FFFFh
6 060000h 06FFFFh
5 050000h 05FFFFh
4 040000h 04FFFFh
3 030000h 03FFFFh
2 020000h 02FFFFh
1 010000h 01FFFFh
0 000000h 00FFFFh
Instructions M25P16
18/59
6 Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first. Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip
Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the
device, most significant bit first, on Serial Data input (D), each bit being la tched on the rising
edges of Serial Clock (C). The instruction set is listed in Table 4: Instruct ion set.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(FAST_READ), Read Statu s Register (RDSR), Read Identification (RDID) or Release from
Deep Power-down , and Re ad Electr o nic Sig nature (RES) instruction, the shifted-in
instruction sequence is followed by a dat a-out sequence. Chip Sele ct (S) can be driven High
after any bit of the data-out sequence is being shifted out.
For a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable (WRDI), or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary. Otherwise the
instruction is rejected and not executed. That is, Chip Select (S) must driven High when the
number of clock pulses after Chip Select (S ) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Table 4. Instruction set
Instruction Description One-byte instruction
code Address
bytes Dummy
bytes Data
bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 20
RDSR Read Status Register 0000 0101 05h 0 0 1 to
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RES Release from Deep Power-down,
and Read Electronic Signature 1010 1011 ABh 0 3 1 to
Release from Deep Power-down 0 0 0
M25P16 Instructions
19/59
6.1 Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction i s entered by driving Chip Select (S) Low , sending the
instruction code, and then driving Chip Select (S) High.
Figure 8. Write Enable (WREN) instruction sequence
6.2 Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 9. Write Disable (WRDI) instruction sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
Instructions M25P16
20/59
6.3 Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:
Manufacturer identification (1 byte)
Device identification (2 bytes)
A Unique ID code (UID) (17 bytes, of which 16 available upon customer request).
The manufacture r identification is assigned b y JEDEC, and has the value 20h for Numonyx.
The device identification is assigned by the device man ufacturer, and indicates the memory
type in the first byte (20h), and the memory capacity of the device in the second byte (15h).
The UID contains the length of the following data in the first byte (set to 10h), and 16 bytes
of the optional Customized Factory Data (CFD) content. The CFD bytes are read-only and
can be programmed with customers data upon their request. If the customers do not make
requests , the devices are shipped with all the CFD bytes programmed to zero (00h).
Note: See Section 12: Ordering Information, Standar d Parts on page 53 for CFD programmed
devices.
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on
Serial Data output (Q). Each bit is shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 10: Read Identification (RDID) instruction
sequence and data-out sequence. The Read Identification (RDID) instruction is terminated
by driving Chip Select (S) High at any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the S tan dby Power mode, the device waits to be selected, so that it can receive , decode and
execute instructions.
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence
Table 5. Read Identification (RDID) data-out sequence
Manufacturer
identification
Device identification UID
Memory type Memory capacity CFD length CFD content
20h 20h 15h 10h 16 bytes
C
D
S
213456789101112131415
Instruction
0
AI06809c
Q
Manufacturer identification
High Impedance
MSB
Device identification
MSB
15 14 13 3 2 1 0
16 17 18 28 29 30 31
MSB
UID
M25P16 Instructions
21/59
6.4 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read th e Status Register continuou sly, as shown in Figure 11.
The status and control bits of the Status Register are as follows:
6.4.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to ‘1’, such a cycle is in progress, when reset to
‘0’ no such cycle is in progress.
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to ‘1’ the internal Write Enable Latch is set, when set to ‘0’ the internal Write
Enable Latch is reset and no Write Status Register, Program or Erase instruction is
accepted.
6.4.3 BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. The y defin e the size of the ar ea to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 2) becomes
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardwa re Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
Table 6. Status Register format
b7 b0
SRWD 0 0 BP2 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect bits
Wr ite Enable Latch bit
Write In Progress bit
Instructions M25P16
22/59
6.4.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer accepted for execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
sequence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
M25P16 Instructions
23/59
6.5 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in Figure 12.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bi t of the dat a byte has been latched in.
If not, the Write S tatus Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Wr ite Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Prog re ss (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows
the user to set or reset the St atus Register Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in the Hardware Protected mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware Protected mode
(HPM) is entered.
Figure 12. Write Status Register (WRSR) instruction sequence
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
Instructions M25P16
24/59
The protection features of the de vice are summarized in Table 7.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previo usly been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect ( W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W):
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction
If Write Protect (W) is driven Low, it is not possible to writ e to the Stat us Regis te r eve n
if the Write Ena ble Latch (WEL) bit has prev iously been set by a W rite Enable (WREN)
instruction (attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the me mory area that are
software protected (SPM ) by the Bloc k Pro tec t (BP2, BP1, BP0 ) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Table 7. Protection modes
W
signal SRWD
bit Mode Write Protection of the
Status Register
Memory content
Protected area(1)
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 6.
Unprotected area(1)
10
Software
Protected
mode
(SPM)
Status Register is writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
00
11
01
Hardwar
e
Protected
mode
(HPM)
Status Register is
Hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
M25P16 Instructions
25/59
6.6 Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte addres s (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (Q), each bi t being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter r olls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during dat a output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejecte d without havi ng
any effects on the cycle that is in progress.
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence
1. Address bits A23 to A21 are Don’t care.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-bit address
0
MSB
MSB
2
39
Data Out 2
Instructions M25P16
26/59
6.7 Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory content s, at that address, is shif ted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read wi th a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Dat a Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time d uring dat a output. Any
Read Data Bytes at Highe r Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence
1. Address bits A23 to A21 are Don’t care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24-bit address
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
M25P16 Instructions
27/59
6.8 Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the me mory
(changing bits from 1 to 0). Befo re it can be acce p ted , a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three ad dress bytes and at least one dat a byte on Serial Data input (D).
If the 8 least significant ad dr ess bits (A7-A0) are not all zero, all transm itt ed data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the ad dress whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
If more than 25 6 bytes are sent to the device, previo usly latched dat a are d iscarded and the
last 256 dat a bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instru ction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes.
Chip Select (S) must be driven High after the eighth bit of the last data byte has be en
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Progr am cycle is in progress, the S tatus Register
may be read to check the value of the Write In Progress (WIP) bit. Th e Write In Progre ss
(WIP) bit is 1 during the self -t im e d Pa ge Prog ra m cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
Instructions M25P16
28/59
Figure 15. Page Program (PP) instruction sequence
1. Address bits A23 to A21 are Don’t care.
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Data byte 1
39
51
765432 0
1
Data byte 2
765432 0
1
Data byte 3 Data byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
M25P16 Instructions
29/59
6.9 Sector Erase (SE)
The Sector Erase (SE) instru ction set s to ‘1’ (FFh) all b its in side the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (D). Any address inside the
sector (see Table 3) is a valid address for the Sector Er ase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the last addre ss by te ha s be en
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progr ess (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle , and is 0 when it is completed. At some unspecified
time before the cycle is completed, the W rite Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
Figure 16. Sector Erase (SE) instruction sequence
1. Address bits A23 to A21 are Don’t care.
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
Instructions M25P16
30/59
6.10 Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Da ta input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instructio n is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (W EL) bit is res et .
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits
are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 17. Bulk Erase (BE) instruction sequence
C
D
AI03752D
S
21 345670
Instruction
M25P16 Instructions
31/59
6.11 Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as a soft ware
protection mechanism, while the device is not in active use, as in this mode, the device
ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and put s th e device in the Standby mode
(if there is no internal cycle currently in progress). But this mode is not the De ep Power-
down mode. The Deep Power-down mode can only be entered by executing the Deep
Power-down (DP) instruction, su bsequently redu cing the st andby current (from ICC1 to ICC2,
as specified in Table 14).
To t ake the device out of De ep Power-down mode, th e Release from Deep Power-down and
Read Electronic Signature (RES) instruction must be issued. No other instruction must be
issued while the device is in Deep Power-down mode.
The Release from Deep Power- down and Read Electr on ic Sig nature (RES) in structio n a lso
allows the electronic signature of the device to be output on Serial Data output (Q).
The Deep Power-down mode automatically stops at power-down, and the device always
powers up in the Standby mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 18.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise th e Deep Power-down (DP) instr uction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of tDP before the supp ly curren t is reduced
to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 18. Deep Power-down (DP) instruction sequenc e
C
D
AI03753D
S
21 345670tDP
Deep Power-down mode
Standby mode
Instruction
Instructions M25P16
32/59
6.12 Release from Deep Power-down and Read Electronic
Signature (RES)
To t ake the device out of De ep Power-down mode, th e Release from Deep Power-down and
Read Electronic Signature (RES) instruction must be issued. No other instruction must be
issued while the device is in Deep Power-down mode.
The instruction can also be used to read, on Serial Data output (Q), the old-style 8-bit
electronic signatur e, whose value for the M25P16 is 14h.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit electronic
signature that is read by the Read Identifier (RDID) instruction. The old-style e lec tr on ic
signature is supported for reasons of backward compatibility, only, and should not be used
for new designs. New designs should, instead, make use of the JEDEC 16-bit electronic
signature, and the Read Identifier (RDID) instruction.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release
from Deep Power-down and Read Electronic Signature (RES) instruction always provides
access to the old-style 8-bit electronic signature of the device , and can be applied even if
the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Re ad Electronic Signature (RES) instruction while
an Erase, Program or Wr ite Status Register cycle is in progress, is not deco ded, and has no
effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge
of Serial Clock (C). Then, the old-style 8-bit electronic signature, stored in the memory, is
shifted out on Serial Data output (Q), each bit being shifted out during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 19.
The Release from Deep Power-down and Read Electronic Signature (RES) instruction is
terminated by driving Chip Select (S) High after the electronic signature has been read at
least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is
driven Low, cause the electronic signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the S tandby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S)
must remain High for at least tRES2(max). Once in the Standby Power mode, the device
waits to be selected, so that it can receive, decode and execute instructions.
M25P16 Instructions
33/59
Figure 19. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence
1. The value of the 8-bit electronic signature, for the M25P16, is 14h.
Figure 20. Release from Deep Power-down (RES) instruction sequence
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before
the whole of the 8-bit electronic signa ture has been tr ansmitted for the first time ( as shown in Figure 20),
still ensures that the device is put into Standby Power mode. If the device was not previously in the Deep
Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously
in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES1,
and Chip Select (S) must remain High for at least tRES1(max). Once in the Standby Power mode, the
device waits to be selected, so that it can receive, decode and execute instructions.
C
D
AI04047C
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
765432 0
1
High Impedance Electronic Signature Out
Instruction 3 Dummy bytes
0
MSB
Standby mod
e
Deep Power-down mode
MSB
tRES2
C
D
AI04078B
S
21 345670tRES1
Standby mode
Deep Power-down mode
QHigh Impedance
Instruction
Power-up and power-down M25P16
34/59
7 Power-up and power-down
At power-up and po wer-do wn, the device must not b e selected (that is Chip Sel ect (S ) must
follow the voltage applied on VCC) until VCC reaches the correct value:
VCC(min) at power-up, and then for a further delay of tVSL
VSS at power-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power-On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power-On Reset (POR) threshold voltage, VWI – all operations ar e disa b l ed , an d
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and W rite Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the
correct operation of the de vice is not guaran teed if, by this time , VCC is still below VCC(min).
No Write Status Register, Program or Erase instructions should be sent until the later
occuranc e of:
tPUW after VCC passed the VWI threshold
tVSL after VCC passed the VCC(min) level.
These values are sp ec ified in Table 8.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
At power-up, the device is in the following state:
The device is in the Standby mode (not the Deep Power-down mode)
The Write Enab le Latch (WEL) bit is reset
The Write In Progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC rail decoupled by a suitable cap acitor close to
the package pins. Generally, this capacitor is of the order of 100 nF.
At power-down, when VCC drops from the operating voltage to below the Power-On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. The designer needs to be aware that if a power-down occurs while a
Write, Program or Erase cycle is in prog ress, some data corruption can result.
M25P16 Initial delivery state
35/59
Figure 21. Power-up timing
1. These parameters are characterized only.
8 Initial delivery state
The device is delivered with the memory arr ay erased: all bits are set to ‘1’ (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
Table 8. Power-up timing and VWI threshold
Symbol Parameter Min Max Unit
tVSL(1) VCC(min) to S Low 30 µs
tPUW(1) Time delay to Write instruction 1 10 ms
VWI(1) Write Inhibit voltage 1.0 2.1 V
VCC
AI04009C
VCC(min)
VWI
Reset state
of the
device
Chip selection not allowed
Program, Erase and Write commands are rejected by the device
tVSL
tPUW
tim
e
Read access allowed Device fully
accessible
V
CC(max)
Maximum rating M25P16
36/59
9 Maximum rating
Stressing the device above the rating listed in Table 9: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratin gs only and operation of the
device at these or any ot he r co nd itio ns abo ve tho se ind i ca te d in th e o per at i ng sec tion s of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 9. Absolute maximum ratings
Symbol Parameter Min Max Unit
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during solde rin g see (1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx RoHS
compliant 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS) 2002/95/EU.
°C
VIO Input and output voltage (with respect to ground) –0.6(2)
2. The minimum voltage may reach the value of -2 V for no more than 20 ns during transitions.
VCC +0.6
(3)
3. The maximum voltage may reach the value of VCC+2 V for no more than 20 ns during transitions.
V
VCC Supply voltage –0.6 4.0 V
VESD Electrostatic discharge voltage (Human Body model)(4)
4. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
–2000 2000 V
M25P16 DC and AC parameters
37/59
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Figure 22. AC measurement I/O waveform
Table 10. Operating conditions
Symbol Parameter Min Max Unit
VCC Supply voltage 2.7 3.6 V
TAAmbient operating temperature grade 3 –40 125 °C
grade 6 –40 85 °C
Table 11. Data retention and endurance
Parameter Condition Min Max Unit
Program/Erase Cycles Grade 3, Autograde 6,
Grade 6 100000 Cycles per Sector
Data Retention at 55°C 20 years
Table 12. AC measurement conditions
Symbol Parameter Min Max Unit
CL
Load capacitance 30 pF
Input rise and fall times 5 ns
Input pulse voltages 0.2VCC to 0.8VCC V
Input timing reference voltages 0.3VCC to 0.7VCC V
Output timing reference voltages VCC / 2 V
Table 13. Capacitance(1)
1. Sampled only, not 100% tested, at TA= 25 °C and a frequency of 20 MHz.
Symbol Parameter Test Condition Min Max Unit
COUT Output capacitance (Q) VOUT = 0 V 8 pF
CIN Input capacitance (other pins) VIN = 0 V 6 pF
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and output
timing reference levels
Input levels
0.5VCC
DC and AC parameters M25P16
38/59
Table 14. DC characteristics
Symbol Parameter T est condition (in addition
to those in Table 10)Min Max Unit
ILI Input leakage current ± 2 µA
ILO Output leakage current ± 2 µA
ICC1 Standby current Grade 6 S = VCC, VIN = VSS or VCC —50µA
Grade 3 100 µA
ICC2 Deep Power-down
current Grade 6 S = VCC, VIN = VSS or VCC —10µA
Grade 3 100 µA
ICC3 Operating current (READ)
C=0.1V
CC / 0.9.VCC at
75 MHz, Q = open —8mA
C=0.1V
CC / 0.9.VCC at
33 MHz, Q = open —4mA
ICC4 Operating current (PP) S = VCC —15mA
ICC5 Operating current (WRSR) S = VCC —15mA
ICC6 Operating current (SE) S = VCC —15mA
ICC7 Operating current (BE) S = VCC —15mA
VIL Input low voltage – 0.5 0.3VCC V
VIH Input high voltage 0.7VCC VCC+0.4 V
VOL Output low voltage IOL = 1.6 mA 0 .4 V
VOH Output high voltage IOH = –100 µA VCC–0.2 V
M25P16 DC and AC parameters
39/59
Table 15. AC characteristics (110 nm technology)
Applies only to products made with 110 nm technology
Test conditions sp e ci f ie d in Table 10 an d Table 12
Symbol Alt. Parameter Min Typ(1) Max Unit
fCfC
Clock frequency for the followi ng instructions:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, RDID, RDSR, WRSR DC 75 MHz
fRClock frequency for READ instructio ns DC 33 MHz
tCH(2) tCLH Clock High time 6 ns
tCL(1) tCLL Clock Low time 6 ns
tCLCH(3) Clock Rise time(4) (peak to peak) 0.1 V/ns
tCHCL(3) Clock Fall time (4) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relative to C) 5 ns
tCHSL S Not Active Hold time (relative to C) 5 ns
tDVCH tDSU Data In Setup time 2 ns
tCHDX tDH Data In Hold time 5 ns
tCHSH S Active Hold time (relative to C) 5 ns
tSHCH S Not Active Setup time (rela tive to C) 5 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ(3) tDIS Output Disable time 8 ns
tCLQV tVClock Low to Output Valid under 30 pF/10 p F 8/6 ns
tCLQX tHO Output Hold time 0 ns
tHLCH HOLD Setup time (relative to C) 5 ns
tCHHH HOLD Hold time (relative to C) 5 ns
tHHCH HOLD Setup time (relative to C) 5 ns
tCHHL HOLD Hold time (relative to C) 5 ns
tHHQX(3) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(3) tHZ HOLD to Output High-Z 8 ns
tWHSL(5) Write Protect Setup time 20 ns
tSHWL(5) Write Protect Hold time 100 ns
tDP(3) S High to Deep Power-down mode 3 µs
tRES1(3) S High to Standby mode without Read
Electronic Signature —— 30µs
tRES2(3) S High to Standby mode with Read Electronic
Signature —— 30µs
tWWrite Status Register cycle time 1.3 15 ms
DC and AC parameters M25P16
40/59
tPP (6)
Page Program cycle time (256 bytes) 0.64
5ms
Page Program cycle time (n bytes, where n = 1
to 4) —0.01
Page Program cycle time (n bytes, where n = 5
to 256) int(n/8) × 0.02(7)
tSE Sector Erase cycle time 0.6 3 s
tBE Bulk Erase cycle time 13 40 s
1. Typical values given for TA = 25 °C.
2. tCH + tCL must be greater than or equal to 1/ fC.
3. Value guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set at ‘1’.
6. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes ve rsus several sequences of only a few bytes (1 n
256).
7. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4, int(15.3) =16.
Table 15. AC characteristics (110 nm technology) (continued)
Applies only to products made with 110 nm technology
Test conditions sp e ci f ie d in Table 10 an d Table 12
Symbol Alt. Parameter Min Typ(1) Max Unit
M25P16 DC and AC parameters
41/59
Table 16. AC characteristics (25 MHz operation)
Test conditions specified in Table 10 an d Table 12
Symbol Alt. Parameter Min Typ Max Unit
fCfC
Clock frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, RDSR, WRSR DC 25 MHz
fRClock frequency for READ instructions DC 20 MHz
tCH(1) tCLH Clock High time 18 ns
tCL(1) tCLL Clock Low time 18 ns
tCLCH(2) Clock Rise time(3) (peak to peak) 0.1 V/ns
tCHCL(2) Clock Fall time(3) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relative to C) 10 ns
tCHSL S Not Active Hold time (relative to C) 10 ns
tDVCH tDSU Data In Setup time 5 ns
tCHDX tDH Data In Hold time 5 ns
tCHSH S Active Hold time (relative to C) 10 ns
tSHCH S Not Active Setup time (rel ative to C) 10 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ(2) tDIS Output Disable time 15 ns
tCLQV tVClock Low to Output Valid 15 ns
tCLQX tHO Output Hold time 0 ns
tHLCH HOLD Setup time (relative to C) 10 ns
tCHHH HOLD Hold time (relative to C) 10 ns
tHHCH HOLD Setup time (relative to C) 10 ns
tCHHL HOLD Hold time (relative to C) 10 ns
tHHQX(2) tLZ HOLD to Output Low-Z 15 ns
tHLQZ(2) tHZ HOLD to Output High-Z 20 ns
tWHSL(4) Write Protect Setup time 20 ns
tSHWL(4) Write Protect Hold time 100 ns
tDP(2) S High to Deep Power-down mode 3 µs
tRES1(2) S High to Standby mode without Electroni c
Signature Read —— 3 µs
tRES2(2) S High to Standby mode with Electronic
Signature Read —— 1.8 µs
tW(5) Wr ite Status Register cycle time 1.5 15 ms
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at ‘1’.
DC and AC parameters M25P16
42/59
Figure 23. Serial input timing
Figure 24. Write Protect setup and hold timing during WRSR when SRWD = 1
5. Typical values given for TA = 85 °C.
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI0743
9
M25P16 DC and AC parameters
43/59
Figure 25. Hold timing
Figure 26. Output timing
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
C
Q
AI01449e
S
LSB OUT
DADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
Package mechanical M25P16
44/59
11 Package mechanical
In order to meet envi ronmental re quirements, Numonyx offers these devices in RoHS
compliant package s, which have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
Figure 27. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
6 × 5 mm, package outline
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
D
E
70-M
E
A2
AA3
A1
E1
D1
eE2
D2
L
b
θ
R1
ddd
bbb
C
CAB
aaa CAA
B
aaa CB
M
0.10 CA
0.10 CB
2x
M25P16 Package mechanical
45/59
Table 17. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
6 × 5 mm, package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.85 0.80 1.00 0.033 0.031 0.039
A1 0.00 0.05 0.000 0.002
A2 0.65 0.026
A3 0.20 0.008
b 0.40 0.35 0.48 0.016 0.014 0.019
D6.00 0.236
D1 5.75 0.226
D2 3.40 3.20 3.60 0.134 0.126 0.142
E5.00 0.197
E1 4.75 0.187
E2 4.00 3.80 4.30 0.157 0.150 0.169
e1.27 0.050
R1 0.10 0.00 0.004 0.000
L 0.60 0.50 0.75 0.024 0.020 0.029
Θ 12° 12°
aaa 0.15 0.006
bbb 0.10 0.004
ddd 0.05 0.002
Package mechanical M25P16
46/59
Figure 28. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm,
package outline
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 18. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm,
package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.85 1.00 0.033 0.039
A1 0.00 0.05 0.000 0.002
b 0.40 0.35 0.48 0.016 0.014 0.019
D8.00 0.315
D2 5.16 (1)
1. D2 Max should not exceed (D – K – 2 × L).
0.203
ddd 0.05 0.002
E6.00 0.236
E2 4.80 0.189
e1.27 0.050
K 0.82 0.032
L 0.50 0.45 0.60 0.020 0.018 0.024
L1 0.15 0.006
N8 8
D
E
VDFPN-02
A
e
E2
D2
L
b
L1
A1 ddd
K
M25P16 Package mechanical
47/59
Figure 29. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 19. SO8N – 8 lead plastic small outline , 150 mils body width, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A—1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e1.27 0.050
h 0.25 0.50 0.010 0.020
k—0°8°0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
be
A
D
c
1E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
Package mechanical M25P16
48/59
Figure 30. SO8W – 8 lead plastic small outline, 208 mils bod y width, p ack age outline
1. Drawing is not to scale.
Table 20. SO8 wide – 8 lead plastic small outline, 208 mils body width,
package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A—2.500.098
A1 0.00 0.25 0.000 0.010
A2 1.51 2.00 0.059 0.079
b 0.40 0.35 0.51 0.016 0.014 0.020
c 0.20 0.10 0.35 0.008 0.004 0.014
CP 0.10 0.004
D—6.050.238
E 5.02 6.22 0.198 0.245
E1 7.62 8.89 0.300 0.350
e1.27 0.050
k 10° 10°
L 0.50 0.80 0.020 0.031
N8 8
6L_ME
E
N
CP
be
A2
D
c
LA1 k
E1
A
1
M25P16 Package mechanical
49/59
Figure 31. SO16 wide – 16-lead plastic small outline, 300 mils body width, package
outline
1. Drawing is not to scale.
Table 21. SO16 wide – 16-lead plastic small outline, 300 mils body width,
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 10.10 10.50 0.398 0.413
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
θ
ddd 0.10 0.004
E
16
D
C
H
18
9
SO-H
LA1
A
ddd
A2
θ
Be
h x 45˚
Package mechanical M25P16
50/59
Figure 32. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package
outline
1. Package is not to scale.
Table 22. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A—4.800.188
A1 0.50 0.019
A2 3.10 3.30 3.50 0.122 0.129 0.137
b 0.38 0.55 0.014 0.021
b2 1.47 1.52 1.57 0.057 0.059 0.061
c 0.21 0.35 0.008 0.013
D 9.10 9.20 9.30 0.358 0.362 0.366
E 7.62 7.87 8.25 0.300 0.309 0.324
E1 6.25 6.35 6.45 0.246 0.250 0.253
e 2.54 0.100
eA 7.62 0.300
eB 7.62 8.80 10.90 0.300 0.346 0.429
L 2.92 3.30 3.81 0.114 0.122 0.150
PDIP-B
A2
A1
A
L
be
D
E1
8
1
c
eA
b2
eB
E
M25P16 Package mechanical
51/59
Figure 33. UFDFPN (MLP8) 8-lead ultra t hin f ine p itch dua l flat package no lead, 4X3
mm package mechanical data
1. Drawing is not to scale.
Package mechanical M25P16
52/59
Table 23. UFDFPN (MLP8) 8-lead ultra thin f i ne pit ch dua l flat package no lead, 4X3
mm package mechanical data(1)
1. Maximum package warpage is 0.05 mm; maximum allowable burrs is 0.076 mm in all directions; and
bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals.N is the total
number of terminals.
Symbol Databook (mm) Drawing (mm)
Typ Min Max Typ Min Max
A 0.55 0.45 0.60 0.55 0.45 0.60
A1 0.02 0.00 0.05 0.02 0.00 0.05
A3 0.127 0.15 0.127 0.15
θ 12° 12°
D2 0.80 0.70 0.90 0.80 0.70 0.90
E2 0.20 0.10 0.30 0.20 0.10 0.30
e 0.80 0.80
N(2)
2. N is the total number of terminals.
88
ND(3)
3. ND refers to the number of terminals on D side.
44
b(4)
4. Dimension b applies to metallized terminal and is measured between 0.15 and 0.30mm From terminal tip.
if the terminal has the optional radius on the other end of the terminal, The dimension b should not be
measured in that radius area.
0.30 0.25 0.35 0.30 0.25 0.35
L 0.60 0.55 0.65 0.60 0.55 0.65
D 4.00 3.90 4.10 4.00 3.90 4.10
E 3.00 2.90 3.10 3.00 2.90 3.10
M25P16 Ordering Information, Standard Parts
53/59
12 Ordering Information, Standard Parts
Table 24. Ordering information scheme
Example: M25P16 V MN 6 T P B A
Device type
M25P = Serial Flash memory for code storage
Device fun cti on
16 = 16 Mbit (2 Mbit × 8)
Security features(1)
– = no extra security
S = CFD programmed with UID
Operating voltage
V = VCC = 2.7 V to 3.6 V
Package
MP = VFDFPN8 6 × 5 mm (MLP 8)
ME = VDFPN8 8 × 6 mm (MLP8)(2)
MN = SO8N (150 mils width)
MW = SO8W (208 mils width)
MF = SO16 (300 mils width)
BA = PDIP8 (300 mils width)
MC = UFDFPN8 (MLP8), 4 x 3 mm
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3(3) = Automotive temperature range, –40 to 125 °C.
Device tested with high reliability certified flow.(4)
Option
blank = Standard packing
T = Tape and reel packing
Plating Technology
P or G = RoHS compliant
Lithography
blank = 110nm, Catania Diffusion Plant
B = 110nm, Fab.2 Diffusion Plant
Automotive Grade
A(4) = Automotive –40 °C to 125 °C Part
Device tested with high reliability certified flow(3).
blank = standard –40 to 85 °C device
1. Secure options are available upon customer request.
2. Not for new design, please use MP package version of the device.
3. Device grade 3 available in an SO8 RoHS compliant package.
Ordering Information, Standard Parts M25P16
54/59
Note: For a list of available option s (speed, p ackage, etc.), for further information on any aspect of
this device or when ordering parts operating at 75 MHz (0.11 µm, process digit ‘4’), please
contact your nearest Numonyx Sales Office.
4. Numonyx strongly recommends the use of the Automotive Grade devices (AutoGrade 6 and Grade 3) for use in an
automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801.
M25P16 Ordering Information, Automotive Parts
55/59
13 Ordering Information, Automotive Parts
Note: Numonyx strongly recommends the use of the Automotive Grade devices (Auto Grade 6
and 3) in an automotive envirnoment. The high reliability certified flow (HRCF) is described
in the quality note QNEE9801. Please ask your Numonyx sales office for a copy.
Table 25. Ordering information scheme
Example: M25P16 V MN 6 T P B A
Device type
M25P = Serial Flash memory for code storage
Device fun cti on
16 = 16 Mbit (2 Mbit × 8)
Security features
– = no extra security
Operating voltage
V = VCC = 2.3 to 3.6 V
Package
MN = SO8N (150 mils width)
MF = SO16 (300 mils width)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with high reliability certified flow
3 = Automotive temperature range, –40 to 125 °C.
Device tested with high reliability certified flow.
Option
blank = Standard packing
T = Tape and reel packing
Plating Technology
P or G = RoHS compliant
Lithography
/4 = 110nm, Catania Diffusion Plant (no t suggested for
new design)
B = 110nm, Fab.2 Diffusion Plant
Automotive Grade
blank = Automotive –40 to 125 °C part
A = Automotive –40 °C to 85 °C part (used ONLY in
conjunction with Device Grade 6 to distinguish the Auto
Tested Parts from the non Auto Tested parts).
Revision history M25P16
56/59
14 Revision history
Table 26. Document revision history
Date Revision Changes
16-Jan-2002 0 .1 Target Specificatio n Document written
23-Apr-2002 0.4
Clarification of descriptions of entering Stan dby Power mode from Deep
Power-down mode, and of terminating an instruction sequence or data-
out sequence.
ICC2(max) value changed to 10µA
13-Dec-2002 0.5
Typical Page Program time improved. Write Protect setup and hold times
specified, for applications that switch Write Protect to exit the Hardware
Protection mode immediately before a WRSR, and to enter the Hardware
Protection mode again immediately after
15-May-
2003 0.6 MLP8 package added
0.7 50MHz operation, and RDID instruction added. Published internally, only
20-Jun-2003 0.8 8x6 MLP8 and SO16 (300 mil) packages added
24-Sep-2003 1.0 tPP, tSE and tBE revised. SO16 package code changed. Output Timing
Reference Voltage changed. Docu ment promoted to Preliminary Data.
24-Nov-2003 2.0
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added.
Value of tVSL(min) and tBE(typ) changed. Change of naming for VDFPN8
packages. Document promoted to full Datasheet.
17-May-
2004 3.0 MLP8(5x6) package removed. Soldering temperature information
clarified for RoHS complian t devices. Device Grade clarified
01-Apr-2005 4.0
Notes 1 and 2 removed from Table 24: Ordering information scheme.
Small text changes.
Read Identification (RDID) , Deep Power-down (DP) and Release from
Deep Power-down and Read Electronic Signature (RES) instructions,
and Active Power, Standby Power and Deep Power-down modes
paragraph clarified.
01-Aug-2005 5.0 Updated Page Program (PP) instructions in Page programming, Page
Program (PP) and Table 15: AC characteri stics (Grade 6).
20-Oct-2005 6.0
VFQFPN8 package added (see Figure 27: VFQFPN8 (MLP8) 8-lead very
thin fine pitch quad flat package no lead, 6 × 5 mm, package outline and
Table 17: VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package
no lead, 6 × 5 mm, package mechanical data).
All packages are RoHS compliant. “Blank” option removed under Plating
Technology.
27-Feb-2006 7
SO8 Narrow and SO8 Wide packages added (see Section 11: Package
mechanical). VDFPN8 package updated (see Table 18: VDFPN8 (MLP8)
8-lead very thin dual flat package no lead, 8 × 6 mm, package
mechanical data). Note 2 add ed to Table 24: Ordering info rmation
scheme.
04-Jul-2006 8 F igure 4: Bus master an d memory devices on the SPI bus updated and
Note 2 added. SO8N package specifications updated (see Figure 29 and
Table 19). Small text changes.
M25P16 Revision history
57/59
10-Oct-2006 9
Page Program, Sector Erase and Bulk Erase updated in Features.
VIO max modified in Table 9: Absolute maximum ratings.
Table 15: AC chara cteristics (110 nm technology) added.
VFQFPN8 package specifications updated (see Table 17). Note 1 added
to Table 18. Note: on page 54 modified.
09-Jan-2007 10
Small text changes. Hardware Write protection added to Features.
VCC supply voltage and VSS ground signal descriptions added. Figure 4:
Bus master and memory devices on the SPI bus modified, note 2
removed and replaced by an explanatory paragraph. Write In Progress bit
behavior specified at Power-up (see Section 7: Power-up and power-
down). TLEAD added to Table 9: Absolute maximum ratings. Grade 3
temperature range added.
Table 11: Data retention and endurance and Table 16: AC characteristics
(25 MHz operation) add ed.
SO8W and VFQFPN8 package specifications updated (see Section 11:
Package mechanical).
15-Jun-2007 11
Eliminated the reference to the Deep Power-down mode and updated the
Read Identification instruction in Section 6.3: Read Identification (RDID).
Inserted UID and CFI content columns in Table 5: Read Identificati on
(RDID) data-out sequence.
Modified Data bytes for RDID instruction in Table 4: Instruction set.
Modified Q signal in Figure 10: Read Identification (RDID) instruction
sequence and data-out sequence .
Modified Test condition and maximum va lues for ICC3 in Table 14: DC
characteristics.
Eliminated Table 15: AC characteristics (Grade 6).
Modified the maximum value for fC in Table 15: AC characteristics (110
nm technology).
31-Oct-2007 12
Removed ‘low voltage’ from the title. Changed the typical time for Bulk
Erase on page 1.
Section 6.3: Rea d Identifi cation (RDID) updated.
Added note 2 and 3 to Table 9: Absolute maximum ratings.
Modified maximum value for tCLQV in Table 15: AC characteristics (110
nm technology).
10-Dec-2007 13 Applied Numonyx branding.
20-Jun 2008 14
Added a reference to customer’s ability to request dedicated part number
in Section 6.3: Read Identification (RDID) on page 20.
Moved specifications in “max” column to “min” column and changed the
“min” for grade 3 to 10,000 in Table 11: Data retention and endurance on
page 37.
Deleted “grade 6” reference in Table 15: AC characteristics (110 nm
technology) on page 39 .
Deleted “grade 3” reference and “preliminary note” in Tab le 16: AC
characteristics (25 MHz operatio n) on page 41.
Revised Section 12: Ordering Information, Standard Parts on page 53.
5-Dec-2008 15 Added th e PDIP8 (BA), 300 mils width package information.
Table 26. Document revision history (continued)
Date Revision Changes
Revision history M25P16
58/59
6-March
2008 16 Added “Automotiv e Certified Parts” information to cover page, data
retention table, AC Characteristics table, and ordering information.
3-August-
2009 17
Made changes to the following tables:
Table 8.: Power-up timing and VWI threshold
vWI changed min and max from 1.5 / 2.5 to 1.0 / 2.1 V respectively.
Table 14.: DC characteristics
ICC3 (Read) changed from 12 mA to 8 mA.
Table 16.: AC characteristics (25 MHz operation)
Removed tPP, tSE, and tBE, and the associated notes.
14-Oct-2009 18 Created separate order information for standard parts and automotive
parts.
23-Feb-2010 19 Added the fo llowing package information:
Figure 33.: UFDFPN (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead, 4X3 mm package mechanical data.
14-April-
2010 20 Corrected package nomenclature.
Table 26. Document revision history (continued)
Date Revision Changes
M25P16
59/59
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