ASAHI KASE I [AK4114 ]
MS0098-E-04 2004/03
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GENERAL DESCRIPTION
The AK4114 is a digital audio transceiver supporting 192kHz, 24bits. The channel status decoder
supports both consumer and professional m odes. The AK4114 can automatically detect a Non-PCM bit
stream. When combined with the multi channel codec (AK4527B or AK4529), the two chips provide a
system solution for AC-3 applications. The dedicated pins or a serial µP I/F can contr ol the mode setting.
The sma ll packag e, 48pin LQF P saves t he system spa ce.
*AC-3 is a trademark of Dolby Laboratories.
FEA TURES
AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
Low jitter Analog PLL
PLL Lock Ra nge : 32 kHz to 192kHz
Clock Source: PLL or X'tal
8-channel Receiver input
2-channel Transm iss ion output (Through output or DIT)
A uxiliary digital input
De-emphas i s for 3 2kHz , 4 4.1kHz, 48kHz and 96kHz
Detection Functions
• No n-P CM Bit Str eam Detection
• DTS-CD Bi t S tream Detec tion
• Sampling Frequency Detection
(32kHz , 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
• Unlock & Parity Error Detection
• Validity Flag Detection
Up to 24bit Audio Data Format
Audio I/ F: Ma ster o r Sl ave Mo de
40-bit Channel Status Buffer
Burs t Preamb l e bit Pc an d P d Buffer for Non -PCM bi t str eam
Q- su bco d e Bu ffer for CD b i t str eam
S e r ial µP I/F
Two M aster Clock Outputs : 64fs/128fs/256fs/512fs
Operating Voltag e: 2.7 to 3. 6V with 5V toleranc e
Small Pack age: 48pin LQFP
T a: -10 to 70°C
AK4114
High Feature 192 kHz 24bi t Digital Audio Interface Tran sceive
r
ASAHI KASE I [AK4114 ]
MS0098-E-04 2004/03
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In
p
ut
Selector
Clock
Recovery Clock
Generato
r
DAIF
Decoder
A
C-3/MPEG
Detect
DEM
µP I/F
A
udio
I/F
X'tal
Oscillator
PDN
INT0 P/S=”L”
LRCK
BICK
SDTO
DAUX
MCKO2
XTOXTI
RAVDDAVSS
CDTI
CDTO
CCLK
CSN
DVDD
DVSS
TVDD
MCKO1
IIC
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
DIT
TX0
Error &
Detect
STATUS
INT1
Q-subcode
buffe
r
TX1
B,C,U,VOUT
8 to 3
VIN
Serial Control Mode
In
p
ut
Selector
Clock
Recovery Clock
Generato
r
DAIF
Decoder
A
C-3/MPEG
Detect
DEM
A
udio
I/F
X'tal
Oscillator
PDN
INT0 P/S=”H”
LRCK
BICK
SDTO
DAUX
XTOXTI
RAVDDAVSS
CM1
CM0
OCKS1
OCKS0
DVDD
DVSS
TVDD
IPS1
RX0
RX1
RX2
RX3
IPS0
DIF0
DIF1
DIF2
DIT
TX0
Error &
Detect
STATUS
INT1
TX1
B,C,U,VOUT
4 to 2
VIN
MCKO2
MCKO1
Parallel Control Mode
ASAHI KASE I [AK4114 ]
MS0098-E-04 2004/03
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Ordering Guide
AK4114VQ -10 ~ +70 °C 48pin LQFP (0.5mm pitch)
Pi n Layout
IPS0/RX4
RX3
1
A
VSS
48
2
DIF0/RX5 3
TEST2 4
DIF1/RX6 5
A
VSS 6
DIF2/RX7 7
IPS1/IIC 8
P/SN 9
XTL0 10
XTL1
A
VSS
47
RX2
46
45
44
A
VSS
43
RX0
42
A
VSS
41
VCOM
40
R
39
AVDD
38
TVDD 13
NC 14
TX0 15
TX1 16
BOU
T
17
18
UOU
T
19
VOU
T
20
DVDD 21
DVSS 22
MCKO1 23
36
35
34
33
32
31
30
29
28
27
26
INT0
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
PDN
XTI
XTO
DAUX
MCKO2
BICK
AK4114VQ
Top View
COU
T
TEST1
RX1
INT1
37
LRC
K
24
11
VIN 12 25 SDTO
ASAHI KASE I [AK4114 ]
MS0098-E-04 2004/03
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PIN/FUNCTION
No. Pin Name I/O Function
IPS0 I Input Channel Select 0 Pin in Parallel Mode
1 RX4 I R eceiver Channel 4 Pin in Serial Mode (Internal biased pi n)
2 NC(AVSS) I No Connect
No internal bonding. This pin should be connected to AVSS.
DIF0 I A udio Data Interface Format 0 Pin in Parallel Mode
3 RX5 I R eceiver Channel 5 Pin in Serial Mode (Internal biased pi n)
4 TEST2 I TEST 2 pin
This pi n should be connect to AVSS.
DIF1 I A udio Data Interface Format 1 Pin in Parallel Mode
5 RX6 I R eceiver Channel 6 Pin in Serial Mode (Internal biased pi n)
6 NC(AVSS) I No Connect
No internal bonding. This pin should be connected to AVSS.
DIF2 I A udio Data Interface Format 2 Pin in Parallel Mode
7 RX7 I R eceiver Channel 7 Pin in Serial Mode (Internal biased pi n)
IPS1 I Input C hannel Select 1 Pin in Parallel Mode
8 IIC I
I IC Select Pin i n Seri al Mode.
“L”: 4-w ire S erial, “H”: IIC
9 P/SN I Parallel/Serial Select Pin
“L”: Serial Mode, “ H”: Parallel Mode
10 X TL0 I X’ta l Fr eq u enc y Sele ct 0 Pi n
11 XTL1 I X’tal Frequency Select 1 Pin
12 VIN I V-bit In put Pin for Tran smitter Output
13 TVDD I Input Buffer P ower Supply Pin, 3.3V or 5V
14 NC I No Connect
No intern al bonding. This pin should be open or connected to DVSS .
15 TX0 O Tran s mit Ch an nel (Thr ou gh D ata ) Ou t put 0 Pin
16 TX1 O When TX bit = “0” , Tr ans mit Channel (Through Data) Output 1 Pin.
When TX bit = “1”, Transmit Channel (DAUX Data) Output Pin (Defaul t).
17 BOUT O Bl oc k- Star t Out put Pin for Receiver Input
“H” during first 40 flames.
18 COUT O C-bit Output Pin for Receiver In put
19 UO UT O U-bit Output Pin for Receiver Input
20 VO U T O V-bit Ou tput Pin for Recei ver Inpu t
21 DVDD I Digit al Power Sup pl y Pin , 3. 3V
22 DV SS I Di git al Grou nd Pin
23 MC KO1 O Mas t er C loc k Ou tpu t 1 Pin
24 LRCK I/O Channel Clock Pin
25 SDTO O Audio Seri al Data Output Pin
26 BICK I/O Audio S eri al Data Clock Pin
27 MC KO2 O Mas t er C loc k Ou tpu t 2 Pin
28 DA U X I Auxilia ry Audio Data Input Pi n
29 XTO O X'tal Ou tput Pin
30 XTI I X'tal Input Pin
ASAHI KASE I [AK4114 ]
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PIN/FUNCTION (Continued)
No. Pin Name I/O Function
31 PDN I Power-Down Mode Pin
When “L”, the AK4114 is powered-down and reset.
CM0 I Master Clock Operation Mode 0 Pin in Parallel Mode
CDTO O Control Data Out put Pin in Serial Mode, IIC= “L”.
32 CAD1 I Chip Address 1 Pin in Serial Mode, IIC= “H”.
CM1 I Master Clock Operation Mode 1 Pin in Parallel Mode
CDTI I Control Data Input Pin in Serial Mode, IIC= “L”.
33 SDA I/O Control Data Pin in Serial Mode, IIC= “H”.
OCKS1 I Output Clock Select 1 Pin in Parallel Mode
CCLK I Control D ata Clock P in in Serial Mode, IIC= “L”
34 SCL I Control Data Clock Pin in Serial M ode, IIC= “ H”
OCKS0 I Output Clock Select 0 Pin in Parallel Mode
CSN I Chip Select Pin in Serial Mo de, IIC=”L” .
35 CAD0 I Chip Address 0 Pin in Serial Mode, IIC= “H”.
36 INT0 O Interrupt 0 Pin
37 INT1 O Interrupt 1 Pin
38 AVDD I Analog Power Supply Pi n, 3.3V
39 R - External Resistor Pin
18kΩ +/-1% resistor should be connected t o AVSS externally.
40 VCOM - Common Voltage Output Pin
0.47µF c apacitor should be connect ed to AVSS e xternally.
41 AVSS I Analog Ground Pin
42 RX0 I Receiver Channel 0 P in (Internal biased pin)
This channel is default in serial mode.
43 NC(AVSS) I No Connect
No internal bonding. This pin should be connected to AVSS.
44 RX1 I Receiver Channel 1 Pin (Internal biased pin)
45 TEST1 I TEST 1 pin.
This pin should be connected to AVSS .
46 RX2 I Receiver Channel 2 Pin (Internal biased pin)
47 NC(AVSS) I No Connect
No internal bonding. This pin should be connected to AVSS.
48 RX3 I Receiver Channel 3 Pin (Internal biased pin)
Note 1. All input pins except internal biased pins should not be left floating.
ASAHI KASE I [AK4114 ]
MS0098-E-04 2004/03
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ABSO LU TE MAXI MUM RATING S
(AVSS, DVSS=0V; Note 2)
Parameter Symbol min max Units
Power Supplies: Analog
Digital
Input Buffer
|AVSS-DVSS| (Note 3)
AVDD
DVDD
TVDD
∆GND
-0.3
-0.3
-0.3
4.6
4.6
6.0
0.3
V
V
V
V
Inpu t Cu rr en t (A ny pins ex cept su ppl i es ) II N - ±10 mA
Inpu t Vol tage (E xce pt XTI pin )
Inpu t Vol tage (XT I pi n) VIN
VINX -0.3
-0.3 TVDD+0.3
DVDD+0.3 V
V
Ambient Temperature ( Pow er applied) Ta -10 70 °C
Storage Temperat ure Tstg -65 150 °C
Note 2. All voltages with respect to ground.
Note 3. AVSS and DVSS must be connected to the same ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Nor mal operation is not guaranteed at these extremes.
RECOMMENDED OPERA TING CONDITIONS
(AVSS, DVSS=0V; Note 2)
Parameter Symbol min typ max Units
Power Supplies: Analog
Digital
Input Buffer
AVDD
DVDD
TVDD
2.7
2.7
DVDD
3.3
3.3
3.3
3.6
AVDD
5.5
V
V
V
Note 2. All voltages with respect to ground.
S/PDIF RECEIVER CHA RACTERISTICS
(Ta=25°C; AVDD, DVDD= 2.7~3.6V;TVDD=2.7~5.5V)
Parameter Symbol min typ max Units
Input Resistance Zin 10 kΩ
Input Voltage VTH 200 mVpp
Input Hyst eresis VHY 50 mV
Input Sample Frequency fs 32 - 192 kHz
DC CHARACTERI STICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7 ~5.5V; unless otherwis e specified )
Parameter Symbol min typ max Units
Power Suppl y Current
Normal operation: PDN = “H” (Note 4)
Power down: PDN = “L” (Note 5)
28
10
56
100
mA
µA
High -Level Input Voltage
Low- Le vel In put Voltage VIH
VIL 70%DVDD
DVSS-0.3 -
- TVDD
30%DVDD V
V
High-Level Output Voltage (Iout=-400µA)
Low-Level Output Voltage
(Except SDA pin: Iout=4 00µA)
( SDA pin: Iout= 3mA)
VOH
VOL
VOL
DVDD-0.4
-
-
-
-
-
-
0.4
0.4
V
V
V
In pu t Le a k a ge C u r r e n t Ii n - - ± 10 µA
Note 4 . AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=192kHz, X'tal=24.576MHz, Clock Operation Mode 2,
OCKS1=1, OCKS0 =1. AVDD=11mA (t yp), DVDD=17mA (t yp), TVDD=10µA (typ).
DVDD=28mA (typ) when the circuit of Fi gure 22 is attached to both TX0 and TX1 pins.
Note 5. RX inputs are open and a ll digital input pins are held DVD D or DVS S.
ASAHI KASE I [AK4114 ]
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SWI TCHING CHARA CTERI STICS
(Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz
External Clock Frequency
Duty fECLK
dECLK 11.2896
40
50 24.576
60 MHz
%
MC KO1 Ou t put Fr eq uen c y
Duty fMCK1
dMCK1 4.096
40
50 24.576
60 MHz
%
MC KO2 Ou t put Fr eq uen c y
Duty fMCK2
dMCK2 2.048
40
50 24.576
60 MHz
%
PLL Clock Recover Frequency (RX0-7) fpll 32 - 192 kHz
LRCK Frequen cy
Duty Cycle fs
dLCK 32
45 192
55 kHz
%
Audio I nterface Timing
Slave Mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (Note 6)
BICK “↑” to LRCK Edge (Note 6)
LRCK to SDTO (MSB)
BICK “↓” to SDTO
DAU X Hold Time
DAUX Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRM
tBSD
tDXH
tDXS
80
30
30
20
20
20
20
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
Master Mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
DAU X Hold Time
DAUX Setup Time
fBCK
dBCK
tMBLR
tBSD
tDXH
tDXS
-20
20
20
64fs
50
20
10
Hz
%
ns
ns
ns
ns
Control Interface Timing (4-wire se rial mode)
CC LK Peri od
CC LK Pul se Wi dth Low
Pulse Width High
CDTI Se t up Ti me
CDTI Hold Ti me
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CS N “↑”
CDTO Delay
CSN “↑” to CDTO Hi -Z
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
150
50
50
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6. BICK r ising edge must not occur at the same time as LRCK edge.
ASAHI KASE I [AK4114 ]
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SWITCHING CHARACTE RI S TI CS (Continued )
(Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5 V; CL=2 0pF)
Parameter Symbol min typ max Units
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Ti me Between Trans missi ons
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock H igh Time
Setup Time for Repeated Start Condi tion
SDA Hol d Time fro m SC L F al l i ng (Note 7)
SDA Setu p Ti me from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Cap aci t ive load on bus
fSCL
tBUF
tHD:STA
tLO W
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
-
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.0
-
100
-
-
-
-
-
-
-
1000
300
-
400
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
Reset Timing
PDN P uls e W idth
tPW
150
ns
Note 7 . Data mu st be hel d for sufficient time to brid ge the 300 ns transition time of SC L.
Note 8 . I2C is a regi stered tr ademark of Phil i ps Se micondu ct ors.
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips
I2C patent to use the components in the I2C system, provided the syste m conform to the I2C
specifications defined by Philips.
ASAHI KASE I [AK4114 ]
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Timing Diagram 1/fECLK
tECLKL
VIH
tECLKH
XTI VIL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
1/fMCK1
50%DVDDMCKO1
tMCKL1tMCKH1 dMCK1 = tMCKH1 x fMCK1 x 100
= tMCKL1 x fMCK1 x 100
1/fMCK2
50%DVDDMCKO2
tMCKL2tMCKH2 dMCK2 = tMCKH2 x fMCK2 x 100
= tMCKL2 x fMCK2 x 100
1/fs
LRCK VIH
VIL
tLRLtLRH dLCK = tLRH x fs x 100
= tLRL x fs x 100
Figu re 1. Clock Timing
tLRB
LRCK
BICK
SDTO
tBSD
tBLR tBCKL tBCKH
tLRM
50%DVDD
DAUX
tDXS tDXH
VIH
VIL
VIH
VIL
VIH
VIL
tBCK
Figure 2. Serial Interface Timing (Slave Mode)
ASAHI KASE I [AK4114 ]
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LRCK
BICK
SDTO
tBSD
tMBLR
50%DVDD
50%DVDD
50%DVDD
DAUX
tDXHtDXS
VIH
VIL
Figure 3. Serial Interface Timing (Master Mode)
tCCKL
CSN
CCLK
tCDS
CDTI
tCDH
tCSS
C0
A
4
tCCKH
CDTO Hi-Z
R/W
C1
VIH
VIL
VIH
VIL
VIH
VIL
tCCK
Figure 4. WRITE/READ Command Input Timing in 4-wire serial mode
ASAHI KASE I [AK4114 ]
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tCSW
CSN
CCLK
CDTI D2 D0
tCSH
CDTO Hi-Z
D1D3
VIH
VIL
VIH
VIL
VIH
VIL
Fi gur e 5 . WRITE Da ta In pu t Timin g in 4-wi r e seri al mode
CSN
CCLK
tDCD
CDTO D7 D6
CDTI A1 A0
D5
Hi-Z 50%DVDD
VIH
VIL
VIH
VIL
VIH
VIL
Figure 6. READ Data Output Timing 1 in 4-wire serial mode
CSN
CCLK
tCCZ
CDTO D2 D1
CDTI
D0
D3
tCSW
tCSH
50%DVDD
VIH
VIL
VIH
VIL
VIH
VIL
Figu re 7. READ Da ta Input Timing 2 in 4-wir e serial mode
ASAHI KASE I [AK4114 ]
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tHIGH
SCL
SDA VIH
tLOW
tBUF
tHD:STA
tR tF
tHD:DAT tSU:DAT tSU:STA
Sto
Start Start Sto
tSU:STO
VIL
VIH
VIL
tSP
Figure 8. I2C Bus mode Timing
tPW
PDN VIL
Fi gure 9. Power Down & Reset Timin g
ASAHI KASE I [AK4114 ]
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OPERATION OVERV IEW
Non -P CM (AC-3, MPE G, etc.) and DTS-CD Bitstream Detection
Th e AK4 114 has a Non-PC M steam auto-detection function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Dat a Stream in IEC60958 Interface” is detected, the AUTO bi t goes “1”. The 96bit sync code consists of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO “1”. Once the AUTO is set
“1”, it will remain “1” until 4096 frames pass through the chip without additional sync pattern being detected. When
those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers. The
AK4114 also has the DTS-CD bitstream auto-detection functi on. When AK4114 detects DTS-CD bitstreams , DTSCD bit
goes to “1”. When the next sync code does not come within 4096 flames, DTSCD bit goes to “0” until when AK4114
detects the stream ag ain.
192k Hz Cl oc k Recovery
On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4114
has t he sampl ing frequen c y d etect fun ction. B y eith er t he clock co mpari son ag ains t X’tal oscil lat or or u sing t he chan nel
status, AK4114 detects the sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz). Th e
PLL loses lock when t he received sync interval i s incorrect.
Master Clock
Th e AK4114 has t wo clo ck out put s, MCKO1 and M CKO2. These cl ocks ar e deri ved fr om eit her the r ecove red cloc k or
from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 and MCKO2) are set by OCKS0 and
OCKS1 as shown in Table 1. Th e 512fs clock will not output when 96kHz and 192kHz. The 256fs clock will not output
when 192kHz.
No. OCKS1 OCKS0 MCKO1 MCKO2 X’tal fs (max)
0 0 0 256fs 256fs 256fs 96 kHz
1 0 1 256fs 128fs 256fs 96 kHz
2 1 0 512fs 256fs 512fs 48 kHz
3 1 1 128fs 64fs 128fs 192 kHz
Default
Ta ble 1. Master Clock Frequency Select (Stereo mode)
Clock O peratio n Mo de
The CM0/CM1 pins (or bits) select the clock source and the data source of SDTO. In Mode 2, the clock source is
switched from PLL to X'tal when PLL goes unlock state. In Mode3, the clock source is fixed to X'tal, but PLL is also
operating and the recovered data such as C bits can be monitored. For Mode2 and 3, it is recommended that the
frequency of X’t al is different from the recovered frequency from PLL.
Mode CM1 CM0 UNLOCK PLL X'tal Clock source SDTO
0 0 0 - ON ON(Note) PLL RX
1 0 1 - OFF ON X'tal DAUX
0 ON ON PLL RX
2 1 0 1 ON ON X'tal DAUX
3 1 1 - ON ON X'tal DAUX
Default
ON: Osci l l a tion (Powe r -u p), OFF : STOP (Pow er-d ow n)
Note : When t he X’tal is not us ed as cloc k comparison for fs detect ion (i . e. XTL1 , 0= “1 , 1”) , the X’tal i s off.
Table 2. Clock Oper ation Mode select
ASAHI KASE I [AK4114 ]
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Cloc k S ource
The followi ng circuits are availabl e to feed the clock to XTI pin of AK4114 .
1 ) X’tal
XTI
XTO AK4114
Fi gu re 10 . X’ta l mod e
Note: E xternal capacitance depends on the crystal oscillat or (Typ. 10-40pF )
2) External clock
XTI
XTO AK4114
External Clock
Figure 11. External clock mode
Note : In put cloc k mus t not exc e ed DVDD .
3) Fixed to the Clock Operation Mode 0
XTI
XTO AK4114
Figure 12. off mode
ASAHI KASE I [AK4114 ]
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S ampli ng Frequency and Pre-em p hasis Dete ction
The AK4114 has two methods for detecting the sampling frequenc y as follows.
1. Clock compar ison between recovered clock and X’tal oscillator
2. Sampling frequency information on channel status
Those could be selected by XTL1, 0 bits. And the detected frequency is reported on FS3-0 bits.
XTL1 XTL0 X’tal Frequency
0 0 11.2896MHz
0 1 12.288MHz
1 0 24.576MHz
1 1 (Use channel status)
Default
Table 3. Reference X’tal frequency
Except XTL1, 0= “ 1,1” XTL1,0= “1,1”
Register output fs Consumer
mode
(Not e 2) Pr ofessi onal mode
FS3 FS2 FS1 FS0
C loc k comparison
(Note 1) Byte3
Bit3,2,1,0 Byte0
Bit7,6 Byte4
Bit6,5,4,3
0 0 0 0 44.1kHz 44.1kHz 0 0 0 0 0 1 0 0 0 0
0 0 0 1 Reserved Reserved 0 0 0 1 (Others)
0 0 1 0 48kHz 48kHz 0 0 1 0 1 0 0 0 0 0
0 0 1 1 32kHz 32kHz 0 0 1 1 1 1 0 0 0 0
1 0 0 0 88.2kHz 88.2kHz ( 1 0 0 0 ) 0 0 1 0 1 0
1 0 1 0 96kHz 96kHz ( 1 0 1 0 ) 0 0 0 0 1 0
1 1 0 0 176.4kHz 176.4kHz ( 1 1 0 0 ) 0 0 1 0 1 1
1 1 1 0 192kHz 192kHz ( 1 1 1 0 ) 0 0 0 0 1 1
Note1: At least ±3% range is identified as the value in the Table 4. In case of intermediate frequency of those two,
FS3-0 bits indicate near er value. When the frequ ency is much bigger than 192kHz or much smaller than 32kHz,
FS3- 0 bit s may in dic ate “0 00 1” .
Note2: When consumer mod e, Byte3 Bit3-0 are copi ed to F S3-0.
Tabl e 4. fs Information
The pre-emphasis information is detected and reported on PEM bit. These information are extracted from channel 1 at
default. It can be switched to channel 2 by CS12 bit in control register.
PEM Pre-emphasis Byte 0
Bits 3- 5
0 OFF
≠ 0X10 0
1 ON 0X100
Table 5. PEM in Consumer Mode
PEM Pre-emphasis Byte 0
Bits 2- 4
0 OFF
≠110
1 ON 110
Table 6. PEM in Profes sional Mode
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De -empha si s F ilte r Control
The AK4114 inclu des the digital de-emphasis filter (tc=50/15µs) by IIR filter cor responding to four sampling frequenc ies
(32kHz, 44. 1kHz, 48kHz and 96 kHz). When DEAU bi t =“1”, t he de-em phasi s filt er is enabl ed au to mat i cally by sa mplin g
frequency and pre-emphasis information in the channel status. The AK4114 goes this mode at default. Therefore, in
Parallel Mode, th e AK411 4 is always placed in th is mode and th e status bits in channel 1 control the de-emphasis filter.
In Seri al Mode, DEM 0/1 and DFS bits can cont rol th e de-e mphasi s fi lter w hen DE AU is “ 0”. The in tern al de-e mphasi s
filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis Mode is
OFF.
PEM FS3 FS2 FS1 FS0 Mode
1 0 0 0 0 44.1kHz
1 0 0 1 0 48kHz
1 0 0 1 1 32kHz
1 1 0 1 0 96kHz
1 (Others) OFF
0 x x x x OFF
Ta ble 7. De-emphasis Auto Control at DEAU = “1” (Default)
PEM DFS DEM1 DEM0 Mode
1 0 0 0 44.1kHz
1 0 0 1 OFF Default
1 0 1 0 48kHz
1 0 1 1 32kHz
1 1 0 0 OFF
1 1 0 1 OFF
1 1 1 0 96kHz
1 1 1 1 OFF
0 x x x OFF
Table 8. De-emphasi s Manual Control at DEAU = “0”
S ystem Re set and Power-Down
Th e AK4114 has a power-down mode f or all ci rcuits by PDN pi n can be partially powerd-down by PWN bi t. The RSTN
bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled. The
AK4114 should be reset once by bringing PD N pin = “L” u pon power-up.
PDN Pi n:
All analog and digital circuit are placed in the power-down and reset mode by bringing PDN= “L”. All the
registers are initialized, and clocks are stopped . Reading/Witting to the register are disabled.
RSTN Bit (Address 00H; D0):
All the registers except PWN and RS TN are initialized by b ringing RSTN bi t = “0”. The int ernal timings are
also initialized. Witting to the register is not available except PWN and RSTN. Reading to the register is
disabled.
PWN Bit (Address 00H; D1):
The clock reco very part is initialized by bringing PWN bit = “0”. In this case, clocks ar e st op ped. The registers
are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled.
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Biphase Input and Thr ough Output
Eight receiver inputs (RX0-7) are available in Serial Control Mode. Each input includes amplifier corresponding to
unbalan c e mode and can a cc e pt t he si gnal of 2 00 mV or mor e. IPS2-0 s elect s t he recei ver chan n el. When BC U bi t = “ 1”,
the Block start signal, C bit and U bit can output from each pins.
IPS2 IPS1 IPS0 INPUT Data
0 0 0 RX0 Default
0 0 1 RX1
0 1 0 RX2
0 1 1 RX3
1 0 0 RX4
1 0 1 RX5
1 1 0 RX6
1 1 1 RX7
Table 9. Recovery Data Select
B
COUT (or U,V)
LRCK
(except I2S)
C(L0) C(R0) C(L1) C(R31)C(L31) C(L32)
C(R191)
1/4fs
SDTO L191 R191 L30 L31
R30
L0
R190
LRCK
(except I2S)
SDTO
(except I2S)
L30
R190
(Mo no mode)
(Normal mode)
L191 R191 L0 R30 L31
LRCK
(I2S)
LRCK
(I2S)
Figure 13. B, C, U, V output/input timings
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Biphase Ou tput
The AK4114 can output either the through output(from DIR) or transmitter output(DIT; the data from DAUX is
transformed to IEC60958 format.) from TX1/0 pins. Those could be selected by DIT bit. The source of the through
output from TX0 could be selected among RX0-8 by OPS00,01 and 02 bits, for TX1, by OPS10,11 and 12 bits
respect i vel y. When out put DAUX data, V bit could be con trol l ed by V IN pin and first 5 bytes o f C bit coul d be control led
by CT39-CT0 bits in control registers. When bit0= “0”(consumer mode), bit20-23(Audio channel) could not be
controlled directly but be controlled by CT20 bit. When the CT20 bit is “ 1”, AK4114 out puts “1000” as C20-23 for left
channel and output “0100” at C20-23 for right channel automatically. When CT20 bit is “0”, AK4114 outputs “0000” set
as “1000” for sub frame 1, and “0100” for sub frame 2. U bits are fixed to “0”.as C20-23 for both channel. U bit could be
cont roll ed by U DI T bi t as f ol lows; When UDIT bi t i s “0”, U bit is al ways “L”. When UD IT bi t i s “ 1”, the r ecovered U
bits are used for DIT( DIR-DIT loop mode of U bit). This mode is only available when PLL is locked and the master
mode.
OPS02 OPS01 OPS00 Output Data
0 0 0 RX0 Default
0 0 1 RX1
0 1 0 RX2
0 1 1 RX3
1 0 0 RX4
1 0 1 RX5
1 1 0 RX6
1 1 1 RX7
Table 10. Output Data Sele ct for TX0
DIT OPS12 OPS11 OPS10 Output Data
0 0 0 0 RX0
0 0 0 1 RX1
0 0 1 0 RX2
0 0 1 1 RX3
0 1 0 0 RX4
0 1 0 1 RX5
0 1 1 0 RX6
0 1 1 1 RX7
1 x x x DAUX Default
Table 11. Output Data Select for TX1
LRCK
(
I2S
)
VIN
L0 R0 L1
DAUX
L0 R0 L1
R191
R1
(Mo no mode)(Normal mode)
LRCK
(excep t I2S)
L0 R0 L1
L0/R0 L1/R1
L191/R191
R1
Fi gure 1 4. DAUX and VIN input timings
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Double sampling frequency mode
When MONO bit = “1”, the AK4114 outputs data with double speed according to “Single channel double sampling
frequency mode” of AES3. For example, when 192kHz mono data is transmitted or received, L/R channels of 96kHz
biphase data are used. In this case, 1 frame is 96kHz and LRCK freq uency is 192kHz.
1) RX
When M ONO bit = “1”, AK4114 outputs mono data from SD TO as foll ows.
Biphase (Image)
A
1
A
0
1 fra me
A
0
A
0
A
1
A
1
LRCK
(except IIS)
SDTO
1 LRCK
RX
MONO = 1
LRCK
(IIS)
Fi gure 15 . MONO mode (R X)
AK4114Lch
AK4114Rch
DAC
(AK4394/5)
SW
MCLK
BICK
LRCK
SDTI
(Master)
(Slave)
RX SDTO
MCKO
RX SDTO
Figure 16. MONO mode Connection Example (RX)
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2) TX
When MONO bi t = “1” and TLR bit = “0”, the AK4114 out puts Lch data through TX1 as biphase sign al. Wh en MONO
bit = “1” and TLR bit = “1”, then Rch data.
A
0B0
A
1B1
Serial Data
LRCK
(except IIS)
DAUX
1 LRCK
MONO = 1, TLR= 0
Biphase (Image)
A
1
A
0
1 frame
TX
MONO = 1, TLR= 1
Biphase (Image) B1B0
TX
LRCK
(IIS)
Fi gur e 17. MONO mode ( TX)
AK4114Lch
AK4114Rch
ADC
(AK5394)
MCLK
BICK
LRCK
SDATA
(Master)
(Slave)
TX DAUX
MCKO
TX DAUX
XTI
XTI XTO
Figure 18. MONO mode Connection Example (TX)
Note: When the connection example (Figure 18) or multiple AK4114s are used, LRCK and BICK should be input after
reset so that the phase of TX outputs is aligned. The AK4114s should be set by following sequence (Figure 19).
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Upon power on
Mode
PDN pin
LR CK, BICK
Stereo mode Mono mode
D ur i n g operat i on
Mode
RSTN bit
LR CK, BICK
Stereo mode Mono mode
(1) Reset all the AK4114s by PDN pin = “L” → “H” or RSTN bit = “0” → “1”.
(2) Set all th e AK4114s t o MONO mode while they are still in slave mode.
(3) Set one of the AK4114s to master mode so that LRCK is input to all other AK4114s at the same time, or LRCK
should be input to all the AK4114s at the same time.
Figure 19. MONO mode setup sequence (TX )
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Biphase sign al input/o ut put circuit
RX
AK4114
0.1uF
75Ω
Coax 75
Ω
Fi gur e 2 0. Con sumer In put Ci r cu it ( Coaxi al Input )
Note: In case of coaxial input, if a coupling level to this input from the next RX input line
patter n exce eds 50mV, t here i s a possibil it y t o occur an inco rrect op erati on. In th is case, it is
possi ble to lower the coupli ng level by addi ng this decoupling ca pacitor.
RX
AK4114
470
O/E
Optical Receiv er
Optical
Fiber
Figure 21. Consumer Input C ircuit (Optical Input)
In case of coaxial input, as the input level of RX line is small, in Serial Mod e, be careful not to crosstalk among RX input
lines. For example, by inserting the shield pattern among them. In Parallel Mode, four channel inputs (RX0,1,2,3) are
available and RX4-7 change to other pins for audio format control. Those pins must be fi xed to “H” or “ L”.
Th e AK4 114 i nclu des th e TX out put bu ffer. The out put l evel meets co mbinat ion 0. 5V+/-20 % usin g the ext ernal resi stor
net w or k. The T1 i n Fi gur e 22 i s a tr an sf or mer of 1: 1 .
TX
DVSS
R2
T1
75
Ω
cable
R1
Vdd R1 R2
3.3V 240Ω 150Ω
3.0V 220Ω 150Ω
Figure 22. TX Extern al Resistor Ne twor k
Note: When the AK4114 is in the power-d own mode (PDN= “L”), power suppl y current can be suppr essed by using AC
couple capacitor as followin g figure since TX1 pin output bec omes uncertain at power-down mode .
TX1
DVSS
R2
T1
75
Ω
cabl e
R1
Vdd R1 R2
3.3V 240Ω 150Ω
3.0V 220Ω 150Ω
0.1uF
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Q-subcode bu ffers
The AK4114 has Q-subcode buffer for CD application. The AK4114 takes Q-subcode into registers by following
conditions.
1. The sync word (S0,S1) is constr ucted at least 16 “0”s.
2. The start bit is “1”.
3. Those 7bits Q-W follows to the start bit.
4. The distance between two start bits are 8-16 bits .
The QIN T bit in the control register g oes “1” when the new Q-subcode differs from ol d one, and goes “0” when QINT bit
is r ead.
1 2 3 4 5 6 7 8 *
S0 0 0 0 0 0 0 0 0 0…
S1 0 0 0 0 0 0 0 0 0…
S2 1 Q2 R2 S2 T2 U2 V2 W2 0…
S3 1 Q3 R3 S3 T3 U3 V3 W3 0…
: : : : : : : : : :
S97 1 Q97 R97 S97 T97 U97 V97 W97 0…
S0 0 0 0 0 0 0 0 0 0…
S1 0 0 0 0 0 0 0 0 0…
S2 1 Q2 R2 S2 T2 U2 V2 W2 0…
S3 1 Q3 R3 S3 T3 U3 V3 W3 0…
: : : : : : : : : :
(*) number of "0" : min=0; max=8.
Figure 23. Configur ation of U-bit(CD)
Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
CTRL ADRS TRACK NUMBER INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE SECOND FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO ABSOLUTE MINUTE ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME CRC
G(x)=x^16+x^12+x^5+1
Figu re 24. Q-subc ode
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
Q-subcod e Address / Control Q9 Q8 · · · · · · · · · · · · Q3 Q2
Q-subcode Track Q17 Q16 · · · · · · · · · · · · Q11 Q10
Q-subco d e Index · · · · · · · · · · · · · · · · · · · · · · · ·
Q-subco d e Minute · · · · · · · · · · · · · · · · · · · · · · · ·
Q-subco d e Second · · · · · · · · · · · · · · · · · · · · · · · ·
Q-subco d e Frame · · · · · · · · · · · · · · · · · · · · · · · ·
Q-subcode Zero · · · · · · · · · · · · · · · · · · · · · · · ·
Q-subco d e ABS Minute · · · · · · · · · · · · · · · · · · · · · · · ·
Q-subco d e ABS Second · · · · · · · · · · · · · · · · · · · · · · · ·
Q-subcod e ABS Frame Q81 Q80 · · · · · · · · · · · · Q75 Q74
Figure 25. Q-subcode registe r
↑
Q
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Error Handling
There are the foll owing eight events who make INT0/1 pi n “H”. INT0/ 1 pin shows the status of following conditions.
1. UNLOCK : “1” when the PLL los es lock.
AK4114 loses lock when the distance between two preambles is not correct or when those
pre ambles are not correct.
2. PAR : “1” when parity error or biphase coding error is detected, and keeps “1” un til this r egister is read.
Updated every sub-frame cycle. Reading this register resets itself.
3. AUTO : “1” wh en Non-PCM bitstrea m is detected.
Updated e very 4096 frames cycle.
4. DTSCD : “1” when DTS-CD bitstream is detected.
Updated e very D TS -CD sync cycl e.
5. AUDION : “1” when the “AUDIO” bit in r ecovered channel status indicates “1 ”.
U p d a te d eve ry block c y c l e .
6. PEM : “1” wh en “PEM” in recovered channel status indicates “1”.
U p d a te d eve ry block c y c l e .
7. QINT : “ 1” w hen Q-subcode differ from old one, a nd keeps “1” until this register is read.
Updated ever y sync code cycle for Q-subc ode. Reading this register resets itself.
8. CINT : “1” when received C bits differ from old one, and keeps “1” until this register is read.
Updated every block cycle. Reading this register resets itself.
Both INT0 /1 are f ixed to “L” when the PLL is off (CM1,0= “01”). Once the INT0 pi n goes to “H”, this pin holds “H” for
102 4/ fs cycles(t his value c an be chan ged by EF H0 /1 bit s) aft er those e vents are re mo ved. IN T1 goes t o “L” at the same
ti me w hen th ose event s are removed. Each INT0/1 pins can mask th ose ei ght event s ind ivid uall y. Once PAR, QINT an d
C INT bit goes t o “1”, those register s are hel d t o “1” unti l t hose r egi sters ar e read. Whil e the AK4114 loses l ock, r egist er s
regarding C-bit or U-bits are not initialized and keep previous value.
1. Parallel mode
In Parallel Mode, INT0 pin outputs the ORed signal between UNLOCK and PAR, INT1 pin outputs the ORed signal
among AUTO, DTSCD and AUDION. Once INT0 pin goes ”H”, it maintains “H” for 1024/fs cycles after the all error
events are removed. Table 12 shows the st ate of each output pins when the INT0/1 pin is “H”.
Event (State of Internal Register) Pin
UNLOCK PAR AUTO DTSCD AUDION INT0 INT1 SDTO V TX
1 x x x x “L” “L”
0 1 x x x “H” P re vi ous D at a O utput
0 0 x x x “L”
- Output Output
x x 1 x x
x x x 1 x
x x x x 1 “H”
x x 0 0 0
-
“L”
- -
Output
Ta ble 12. E rror Handling (Parallel Mode) x: Don’t care
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2. Serial mode
In Serial Mode, INT0/1 pin output the ORed signal among those eight events. However, each events can be masked by
each mask bits. When each bit masks those events, the event does not affect INT0/1 pin operation (those mask do not
affect those resisters (UNLOCK, PAR, etc.) themselves. Once INT0 pin goes “H”, it maintains “H” for 1024/fs cycles
(this value can be chan ged by EFH0-1 bit s) after the all events are removed. Once those PAR, QINT or CINT bit goes
“1”, it holds “1 ” un til read in g th ose regist ers . Whi le the AK4114 loses l ock, th e chan nel st atu s an Q -subcod e bi ts are n ot
updated and holds the previous data. At initial state, INT0 outputs the ORed signal between UNLOCK and PAR, INT 1
outpu t s t h e ORed si gnal among A U TO, DTSCD an d A UDION .
Register Pin
UNLOCK PAR AUTO DTSCD AUDION PEM QINT CINT SDTO V TX
1 x x x x x x x “L” “L” Output
0 1 x x x x x x Previous Data Output Output
0 0 1 x x x x x Output Output Output
0 0 x 1 x x x x Output Output Output
0 0 x x 1 x x x Output Output Output
0 0 x x x 1 x x Output Output Output
0 0 x x x x 1 x Output Output Output
0 0 x x x x x 1 Output Output Output
Ta ble 13. Error Handling (Serial Mode)
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Error
(UNLOCK, PAR,..)
INT1 pin
SDTO
(UNLOCK)
MCKO,BICK,LRCK
(UNLOCK)
Previous Data
Register
(PAR,CINT,QINT) Hold ”1”
Command READ 06H
MCKO,BICK,LRCK
(except UNLOCK)
(fs: around 20kHz)
SDTO
(PAR error)
Hold Time = 0
Reset
(Error)
SDTO
(others)
Normal Operation
INT0 pin Hold Time (max: 4096/fs)
Register
(others)
Free Run
Vpin
(UNLOCK)
Vpin
(except UNLOCK)
Figure 26. INT0/1 pin timing
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INT0/1 pin ="H"
No
Yes
Yes
Initialize
PD pin ="L" to "H"
Read 06H
Mute DAC out put
Read 06H
No
(Ea ch Er ror Ha ndlin g)
Read 06H
(Resets registers)
INT0/1 pin ="H"
Release
Muting
Figure 27. Error Handling Sequence Exa mpl e 1
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INT1 pin ="H"
No
Yes
Initialize
PD pin ="L" to "H"
Read 06H
Read 06H
and
Detect QSUB= “1”
No
(Read Q-buffer)
New data
is valid
INT1 pin ="L"
QCRC = “0”
Yes
Yes
New data
is invalid
No
Figure 28. Error Handling Sequence Example (for Q/CINT)
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Audio Serial Interface Format
Th e DIF0, DIF1 and DIF2 pins can select ei ght ser ial dat a format s as shown in Table 14 . In all for mats the ser ial dat a is
MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on
the rising edge of B ICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to
128 fs at fs=48 kHz. In th e format equ al or l ess t han 20bi t (Mode0- 2), LSBs i n sub-frame are t runcat ed. In Mode 3-7, the
last 4LSBs are auxiliary data (see Figure 29) .
When the Parity Error, Biphase Error or Frame Length Error oc curs in a sub-frame, AK4114 continues to output the last
normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4114 output
“0” f rom SDTO. In c ase of using DAUX pin, the data is transformed and output fro m SDTO. DAUX pin is u s ed in Clock
Operation Mode 1, 3 and unlock state of Mode 2.
Th e input data format to DAUX sh ould be left justified except in Mode5 and 7( Ta ble 14). In M ode5 or 7, bot h the input
data format of DAUX and outpu t dat a for mat of SDTO are I2S. Mode6 and 7 are Sl ave Mod e t hat is correspond i ng t o th e
Master Mode of Mode4 and 5. In salve Mode, LRCK and BICK should be fed with synchronizing to MCKO1/2.
034 781112 27 28 29 30 31
preamble Aux.
LSB MSB
VUCP
sub-frame of IEC958
023
AK4112 Audio Data (MSB First)
LSBMSB
Figure 29. Bit configurat ion
LRCK BICK
Mode DIF2 DIF1 DIF0 DAUX SDTO I/O I/O
0 0 0 0 24bit, Left justified 16bit, Right justified H/L O 64fs O
1 0 0 1 24bit, Left justified 18bit, Right justified H/L O 64fs O
2 0 1 0 24bit, Left justified 20bit, Right justified H/L O 64fs O
3 0 1 1 24bit, Left justified 24bit, Right justified H/L O 64fs O
4 1 0 0 24bit, Left justified 24bit, Left justified H/L O 64fs O
5 1 0 1 24bit, I2S 24bit, I2S L/H O 64fs O
6 1 1 0 24bit, Left justified 24bit, Left justified H/L I 64-128fs I Default
7 1 1 1 24bit, I2S 24bit, I2S L/H I 64-128fs I
Table 14. Audio data format
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LRCK(0)
BIC
K
(
0:64fs
)
SDTO
(
0
)
012 31 0 1
15:MSB, 0:LSB
Lch Data Rch Data
15 1716 1531 0 1 2 1716
010115 141415
Figure 30. Mode 0 Timing
LRCK
(
0
)
BICK
(
0:64fs
)
SDTO
(
0
)
012 31 0 1
23:MSB, 0:LSB
Lch Data Rch Data
91110 931 0 1 2 1110
0101
12
21 202021
12
2223 2223
Figure 31. Mode 3 Timing
LRCK
BICK
(
64fs
)
SDTO
(
0
)
012 31 0 1
23:MSB, 0:LSB
Lch Data Rch Data
21 2322 2131 0 1 2 2322
23 222
24
1 001
24
212223 32 23 22
Figure 32. Mode 4, 6 Timing Mode4 : LRCK, BICK : Output
Mode6 : LRCK, BICK : Input
LRCK
BICK
(
64fs
)
SDTO
(
0
)
012 31 0 1
23:MSB, 0:LSB
Lch Data Rch Data
2322 2131 0 1 2 2322
23 22
24
1 0
24
32 23
25
2 01212223
25
Figure 33. Mode 5, 7 Timing Mode5 : LRCK, BICK : Output
Mode7 : LRCK, BICK : Input
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Ser ial Control Interface
(1). 4-wire seri al control mode (IIC= “ L”)
The internal registers may be either writt en or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on t his interf ace consis ts of Chip ad dress (2 bit s, C1-0 ar e fixed t o “0 0”), Read/ Wri te (1bi t), Regist er addr es s (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
hi gh-t o- l ow tr an si ti on of CS N. F or re ad operations, t h e C DTO output goes h i gh impedance a fter a l ow -to -hi gh t r ans i t i on
of CSN. Th e maxi mu m sp eed of C C LK is 5M Hz. PDN= “ L” reset s the regi sters to thei r default values. When th e stat e o f
P/S pin is changed, the AK4114 should be reset by PDN= “L”.
CDTI
CCLK
CSN
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7
A
1
A
2
A3
A
4R/WC0
A
0D0D1D2D3
CDTO Hi-Z
WRITE
CDTI C1 D4D5D6D7
A
1
A
2
A3
A
4R/WC0
A
0D0D1D2D3
CDTO Hi-Z
READ
D4D5D6D7 D0D1D2D3 Hi-Z
C1-C0: Chip Address (Fixed to “00”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 34. 4-wire Serial Control I/F Timing
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(2). I2C bus control mode (IIC= “H”)
AK4114 supports the standard-mode I2C-bus (max : 100kHz). Then AK4114 can not be incorporated in a fast-mode
I2C-bus system (max : 40 0kHz).
(2)-1. Data transfer
All commands are preceded by a START condition. Aft er the START con dition, a slave address is sent. After the AK4 114
recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the
SDA line. If the transmitted slave add ress matches an addres s for one of the de vices, the desi gnated slave device pulls the
SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the
master device.
(2)-1-1. Data validity
Th e dat a on t he S DA li ne must be st abl e du ri ng t he HIGH pe ri od of th e clock. The H IGH or LOW st ate of th e dat a l ine
can only change when the clock signal on the SCL line is LOW except for th e START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 35. Data transfer
(2)-1-2. START and STOP condition
A HIGH to LOW tr ansi tion on the SD A l ine while SCL i s HIGH ind icates a S TART condi tion. All seq uences st art fro m
the START cond iti on.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
SCL
SDA
STO P CONDIT IO NSTART CONDITION
Fi gure 36 . START and STOP condi ti ons
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(2)-1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will
release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the
acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4114 will
generates an acknowledge after each byte h as been received.
In the read mode, the slave, AK4114 will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an ackn owledge is detected and no STOP condition is generated by the ma ster, the slave will cont inue to
tran smi t dat a. If an ackn owled ge i s not d etected, the slave wi ll t erminate fur ther d ata t ransmissi ons an d await the STO P
condition.
SCL FROM
MASTER
acknowledge
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
1 98
START
CONDITION
Clock pulse
for acknowledge
not ack nowl edge
Figure 37. Acknowledge on the I2C-bus
(2)-1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condit ion. If the
tran smi tt ed sla ve address matches an addres s for on e of t he de vi ce, t he recei ver who h as been addres sed pul ls down the
SDA line.
Th e most si gnif icant five bit s of the sl ave add ress are fix ed as “00100 ”. The ne xt t wo bits are CAD1 and CAD0 ( devi ce
address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0
pi n) set them. The eighth bit (LSB) of the first byte (R /W bit) defi nes whether a write or read condition is requested by
the master. A “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed.
0 0 1 0 0 CAD1 CAD0 R/W
(Those CAD1/0 should match with CAD1/0 pins.)
Figure 38. The First Byte
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(2)-2. WRITE Operatio ns
Set R/W bit = “0” for the WRITE operation of AK4114.
After receipt the start condition and the first byte, the AK4114 generates an acknowledge, and awaits the second byte
(regist er addr ess) . The sec ond byte con sists o f th e add ress for con trol r egi sters of AK4114. Th e f or mat is MSB first, and
those most significant 3-bits are “Don’t care”.
* * * A4 A3 A2 A1 A0
(*: Don’t car e)
Figure 39. The Second Byte
After receipt the second byte, the AK4114 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7 D6 D5 D4 D3 D2 D1 D0
Figure 40. Byte structu re after the second byte
The AK4114 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4114 generates an acknowledge, and awaits the next data again. The master can
transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the
recei pt of each data, the internal 5bits address counter is incremented by one, and th e next data is taken into next address
automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “roll over” to
00H and t he previous data will be overwritten.
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
Address
A
C
K
Register
Address(n) Data(n)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
Figure 41. WRITE Operation
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(2)-3. READ Operations
Set R/W bit = “1” for t he READ operation of AK4 114.
After transmission of a data, the master can read next address’s data by generating the acknowledge instead of
terminating the write cycle after the receipt the first data word. After t he receipt of each data, the internal 5bits address
coun ter i s incr ement ed b y one, an d th e next dat a is taken i n to next ad dr ess aut omatically. If th e add ress exceed 1FH pri or
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
Th e AK4114 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
(2)-3-1. CURRENT ADD RESS READ
The AK4114 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1.
After receipt of the slave address with R/W bit set to “1”, the AK4114 generates an acknowledge, tr ansmits 1byt e data
whi ch add ress i s set by the i nter nal ad dr ess coun ter and incre ments t he i ntern al add ress count er by 1. If t he mast er does
not generate an acknowledge to the data but generate the stop c ondition, the AK411 4 discontinues transmission
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
Address
A
C
K
Data(n) Data(n+1)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+2)
Figure 4 2. CURRENT ADDRES S READ
(2)-3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues the start condition, slave address(R/W=“0”) and then the register address to read. After the register
add ress’s acknowl edge, the mast er immed iat ely reissu es the st art condi tion and t he slave address wi th th e R/W bit set t o
“1”. Then the AK4114 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the
master does not generate an acknowledge to the data but generate the stop condition, the AK4114 discontinues
transm ission.
SDA
S
T
A
R
T
A
C
K
A
C
K
SS
S
T
A
R
T
Slave
Address Word
Address(n) Slave
Address
A
C
K
Data(n)
A
C
K
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
Fi gure 43. R ANDOM READ
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Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H CLK & Power Down Control CS12 BCU C M1 CM0 OCKS1 OCKS0 PWN RSTN
01H Format & De-em Control MONO DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS
02H Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00
03H Input/ Output Control 1 EFH1 EFH0 UDIT TLR DIT IPS2 IPS1 IPS0
04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MDTS0 MPE0 MAUD0 MPAR0
05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MDTS1 MPE1 MAUD1 MPAR1
06H Receiver status 0 QINT AUTO CINT UNLCK DTSCD PEM AUDION PAR
07H Receiver status 1 FS3 FS2 FS1 FS0 0 V QCRC CCRC
08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8
0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16
0BH RX Channel Status Byte 3 CR31 C R30 CR29 CR28 CR27 CR26 CR25 CR24
0CH RX Channel Status Byte 4 CR39 C R38 CR37 CR36 CR35 CR34 CR33 CR32
0DH TX Channel Status Byte 0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0
0EH TX Channel Status Byte 1 CT15 CT14 CT13 CT12 CT11 CT10 CT9 CT8
0FH TX Channel Status Byte 2 CT23 CT22 CT21 CT20 CT19 CT18 CT17 CT16
10H TX Channel Status Byte 3 CT31 CT30 CT29 CT28 CT27 CT26 CT25 CT24
11H TX Channel Status Byte 4 CT39 CT39 CT39 CT39 CT39 CT39 CT39 CT32
12H Burst Preamble Pc Byt e 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
13H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
14H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
15H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8
16H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2
17H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10
18H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18
19H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26
1AH Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34
1BH Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42
1CH Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50
1DH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58
1EH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66
1FH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timi ng is reset and the registers are ini tialized to their default values.
All data can be written to th e register even i f PWN bit is “0”.
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Register Definitions
Reset & In it ia liz e
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H CLK & Power Down Contr ol CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 1 0 0 0 0 1 1
RSTN: Timing Reset & Register Initialize
0: Reset & Initi alize
1: Normal Operat ion
PWN: Power Down
0: Power Down
1: Normal Operat ion
OCKS1-0: Master Clock Frequency Select
CM1 -0: Master Clock Operation Mode Select
BCU: Bl ock sta rt & C/U Output Mode
When BCU=1, t he three Output Pins(BOUT, COUT, UOUT) become to be enabled.
The block signal goes high at the start of fr ame 0 and remains high until the end of frame 31.
CS12: Channel Status Select
0: Channel 1
1: Channel 2
Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0,
Pc and Pd. The de-e mphasis f ilter is controlled by channel 1 in the Parallel Mode.
Format & De-emphasis Control
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H For mat & De-em Control MONO DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 1 1 0 1 0 1 0
DFS: 96kHz De-emphasis Control
DEM1-0: 32, 44.1, 48kHz De-emphasis Control (see Table 8.)
DEAU: De-emphasis Auto Detect Enable
0: Disable
1: Enable
DIF2-0: Audi o Data Format Control (see Table 14.)
MONO: Double sampling frequency mode enable
0: St ereo mode
1: Mono mode
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Input/Output Control
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Input/ Output Control 0 TX 1E OP S12 OPS11 OPS10 TX0E OPS02 OPS 01 OPS00
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 0 0 0 1 0 0 0
OPS02-00: Output Through Data Select for TX0 pin
OPS12-10: Output Through Data Select for TX1 pin
TX0E: TX0 Outpu t Enable
0: Disable. TX0 output s “L”.
1: Enable
TX1E: TX1 Outpu t Enable
0: Disable. TX1 output s “L”.
1: Enable
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Input/ Output Control 1 EFH1 EFH0 UDIT TLR DIT IP S2 IPS1 IPS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 1 0 0 1 0 0 0
IPS2 -0: Input Recovery Data Select
DIT: Through data/Tra nsmit data select for TX1 pin
0: Through data (RX data).
1: Transmit data (DAUX data).
TLR: Double sampling freq uency m ode channel select for DIT(stereo)
0: L channel 1: R channel
UDIT: U bit control for DIT
0: U bit is fixed to “0” 1: Recovered U bit is us e d for DIT (loop mode for U bi t)
EFH1-0: Interrupt 0 Pin Hold Count Select
00: 512 LRCK 01: 1024 LRCK
10: 2048 LRCK 11: 4096 LRCK
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M as k Control for IN T0
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H INT0 MASK MQI0 MAT0 MCI0 MUL0 MDTS0 MPE0 MAN0 MPR0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 0 1 1 1 0
MPR0: Mask Enable for PAR bit
MAN0: Mas k Enable for AUDN bit
MPE0: Mask Enable for PEM bit
MDTS0: Mask Enable for DTSCD bit
MUL0: Mask Enabl e for UN LOCK bit
MCI0: Mask Enable for C INT bit
MAT0: Mask Enable for AUTO bit
MQI0: Mask Enable for QINT bit
0: Mask disable
1: Mask enable
M as k Control for IN T1
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
05H INT1 MASK MQI1 MAT1 MCI1 MUL1 MDTS1 MPE1 MAN1 MPR1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 0 1 1 0 1 0 1
MPR1: Mask Enable for PAR bit
MAN1: Mas k Enable for AUDN bit
MPE1: Mask Enable for PEM bit
MDTS1: Mask Enable for DTSCD bit
MUL1: Mask Enable for UNLOCK0 bit
MCI1: Mask Enable for C INT bit
MAT1: Mask Enable for AUTO bit
MQI1: Mask Enable for QINT bit
0: Mask disable
1: Mask enable
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Receiver Status 0
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
06H Receiver status 0 QINT AUTO CINT UNLCK DTSCD PEM AUDION PAR
R/W RD RD RD RD RD RD RD RD
Default 0 0 0 0 0 0 0 0
PAR: Parity Error or Biphase Error Status
0:No Error 1:Error
It is “1” if Parity Error or Biphase Error is detected in the sub-frame.
AUDION: Audio Bit Out put
0: Audio 1: Non Audio
This bi t is made by encoding channel s tatus bits.
PEM: Pre-emphasi s Detect .
0: OFF 1: ON
This bi t is made by encoding channel s tatus bits.
DTSC D: DTS-CD Auto Detect
0: No detect 1: Detect
UNLCK: PLL Lock Status
0: Locked 1: Out of Lock
CINT: Channel Status Buffer Interrupt
0: No change 1: Changed
AUTO: Non-PC M Au to Det ect
0: No detect 1: Detect
QINT: Q-subcode Buffer Interrupt
0: No change 1: Changed
QINT, CINT and PAR bits are initialized when 06H is read.
Receiver Status 1
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
07H Receiver status 1 FS3 FS2 FS1 FS0 0 V QCRC CCRC
R/W RD RD RD RD RD RD RD RD
Default 0 0 0 1 0 0 0 0
CCRC: Cyclic Redundancy Check for Channel Status
0:No Error 1:Error
QCR C : Cycl ic Red un d anc y Chec k for Q-su bc od e
0:No Error 1:Error
V: Validity of channel status
0:Valid 1:Invalid
FS3-0: Sampling Frequency detection (see Ta ble 4.)
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Re ceiv er Channel Status
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
09H RX Channel Stat us Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 C R9 CR8
0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16
0BH RX Channel Status Byte 3 CR31 CR30 C R29 CR28 CR27 CR26 CR25 CR24
0CH RX Channel Status Byte 4 CR39 CR38 C R37 CR36 CR35 CR34 CR33 CR32
R/W RD
Default Not initialized
CR 39-0: Receiver Channel Status Byte 4-0
Transmitter Channel Status
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0DH TX Channel Status Byte 0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0
0EH TX Channel Status Byte 1 CT15 CT14 CT13 CT12 CT11 CT10 CT9 CT8
0FH TX Channel Status Byte 2 CT23 CT22 CT21 CT20 CT19 CT18 CT17 CT16
10H TX Channel Status Byte 3 CT31 CT30 CT29 CT28 CT27 CT26 CT25 CT24
11H TX Channel Status Byte 3 CT39 CT38 CT37 CT36 CT35 CT34 CT335 CT32
R/W R/W
Default 0
CT39-0: Transmi tter Channel Status Byte 4-0
Burst Prea m ble Pc/Pd in non-PCM encoded Audio Bitstreams
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
12H Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
13H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
14H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
15H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8
R/W RD
Default Not initialized
PC15-0: Burst Preamble Pc Byte 0 and 1
PD15-0: Burst Preamble Pd Byte 0 and 1
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Q -subcode Bu ffer
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
16H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2
17H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10
18H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18
19H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26
1AH Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34
1BH Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42
1CH Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50
1DH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58
1EH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66
1FH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74
R/W RD
Default Not initialized
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Burst P reambles in non-PCM Bitstreams
0
16 bits o f bitstream
34 781112 27 28 29 30 31
preamble Aux. LSB MSB V U C P
sub-frame of IEC958
015
Pa Pb Pc Pd Burst_payload stuffing
re petition time of the burst
Figure 44. Data structure in IEC60958
Preamble word Length of fi el d Contents Value
Pa 16 bits sync word 1 0xF872
Pb 16 bits sync wor d 2 0x4E1F
Pc 16 bits Burst info See Table 16
Pd 16 bits Length code Numbers of bits
Table 15. Burst pr eambl e words
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Bits of Pc Value Contents Repetition time of burst
in IEC60958 frames
0-4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
data type
NUL L data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Laye r2 or 3 data or MPEG-2 w it hout e xtension
MPEG-2 data with extension
MPEG- 2 AAC ADT S
MPEG-2, Layer1 Low s ample rate
MPEG-2, Layer 2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
≤4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
5, 6 0 reserved, shall be set to “0”
7 0
1 e rror-flag i ndic ating a valid burst_payload
error-flag indicating that the burst_payl oad may contain
errors
8-12 data type dependent info
13-15 0 bit stream nu mber, shall be set to “0”
Ta bl e 16 . Fi e lds of bur st in fo Pc
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Non-PCM Bitstream timing
1) When Non-PCM pr eamble is not coming with in 4096 frames,
Pa Pc1Pd1
Pb Pa Pc2Pd2
Pb Pa Pc3Pd3
Pb
“0” Pc1Pc2
“0” Pd1Pd2Pd3
Pc3
PDN pin
Bit stream
AUTO bit
Pc Register
Pd Register
Re
p
etition tim e >4096 frames
Figu re 45. Timing example 1
2) When Non-PCM bitstream stops (when MULK0=0),
Pa Pc1Pd1
Pb Stop Pa PcnPdn
Pb
Pc0Pc1
Pd0Pd1Pdn
Pcn
INT0 pin
Bit stream
AUTO bit
Pc Register
Pd Register
INT0 hold time
2~3 Syncs (B,M or W)
<20mS (Lock time)
<Repetition time
Figu re 46. Timing example 2
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SYSTEM DESIG N
Figure 47 shows the example of syste m connection diagram for Serial Mode.
R
Microcontroller
RX3
RX4 1
2
3
4
5
6
7
8
9
11
10
A
VSS
A
VSS
RX6
A
VSS
RX7
IIC
P/SN
XTL0
(
*
)
XTL1
(
*
)
CSN
AVSS
RX2
AVSS
RX0
AV
SS
VCOM
AVDD
TVDD
INT0
13
14
1
5
16
17
18
19
20
21
22
23
TX1
NC
TX
0
B
U
V
DVDD
DVSS
M
C
K
O
1
CCLK
CDTI
CDTO
PDN
XTI
XTO
DAU
X
MCKO2
BICK
AK4114
C
AVSS
RX1
RX5
36
35
34
33
32
31
30
29
28
26
27
48
47
4
6
45
44
43
42
41
40
39
38
12 VIN
24 LRCK
SDTO 25
INT1 37
(SPDIF Sources)
(SPDIF Sources)
+3.3V Analog
Supply 10µF
0.1µF
+3.3V Digital
Supply
CODEC
(AK4626)
DSP
+3.3V to +5V
Digital Supply
10µF 0.1µF
(SPDIF out)
(Shield)
SDTO
MCLK
BICK
LRCK
SDTI1
(Micro
controller)
(Microcontroller)
0.1µF
10µF
SDTI2
SDTI3
X’tal=11.2896MHz
R
C
C
Analog Ground Digital Ground
+
+
+
Figure 47. Typical Connecti on Diagram (Serial Mode)
Notes:
- For setting of XTL0 and XTL1, refer the Table 3.
- “C” depends on t he crystal.
- AV SS and DVSS must be c onnected th e same ground plane.
- Digital signal s, es peciall y cl ocks, should be kept away from the R pi n in order to a voi d an effect to the clock
jitter performance.
ASAHI KASE I [AK4114 ]
MS0098-E-04 2004/03
- 47 -
PACKAGE
1
12
48 13
7.0
9.0 ± 0.2
7.0
9.0 ± 0.2
0.22 ± 0.08
48
p
in LQFP
(
Unit:mm
)
0.10
37 24
2536
0.16 ± 0.07
1.40
±
0.05
0.13
±
0.13
1.70Max
0° ∼ 10°
0.10
0.5 ± 0.2
0.5 M
M aterial & Lead finish
Package molding compound: Epoxy
Lead fra me material : Cu
Lead fra me surf ace treatment: Solder ( Pb fr ee) plat e
ASAHI KASE I [AK4114 ]
MS0098-E-04 2004/03
- 48 -
MARKING
A
K4114VQ
XXXXXXX
1
XXXXXXXX: Date code identi fier
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