LT110 3/LT110 5
1
Rev. E
For more information www.analog.comDocument Feedback
TYPICAL APPLICATION
FEATURES DESCRIPTION
Offline Switching Regulator
The LT
®
1105 Offline Switching Regulator is designed
for high input voltage applications using an external FET
switch. The LT1105 is available and its totem pole out-
put drives the gate of an external FET. Unique design of
the LT1105 eliminates the need for an optocoupler while
still providing ±1% load and line regulation in a magnetic
flux-sensed converter. This significantly simplifies the
design of offline power supplies and reduces the number
of components which must cross the isolation barrier to
one, the transformer.
The LT1105 current mode switching techniques are well
suited to transformer isolated flyback and forward topolo-
gies while providing ease of frequency compensation with
a minimum of external components.
Fully Isolated Flyback 100kHz 50W Converter with Load Regulation Compensation
Danger!! Lethal Voltages Present – See Text
Load Regulation
APPLICATIONS
n ±1% Line and Load Regulation with No Optocoupler
n Switch Frequency Up to 200kHz
n Internal 2A Switch and Current Sense (LT1103)
n Internal 1A Totem-Pole Driver (LT1105)
n Start-Up Mode Draws Only 200µA
n Fully Protected Against Overloads
n Overvoltage Lockout of Main Supply
n Protected Against Underdrive or Overdrive to FET
n Operates in Continuous or Discontinuous Mode
n Ideal for Flyback and Forward Topologies
n Isolated Flyback Mode Has Fully Floating Outputs
n Up to 250W Isolated Mains Converter
n Up to 50W Isolated Telecom Converter
n Fully Isolated Multiple Outputs
n Distributed Power Conversion Networks
All registered trademarks and trademarks are the property of their respective owners.
220k
1W
499Ω
39µF
35V
1000pF 100Ω
1N4148
13k
1%
4.75k
1%
BUK426-800A
MBR2045 10µH 5V
10A
50V
470µF
*50V
3600µF
WINDINGS FOR
OPTIONAL
±12VDC OUTPUTS
10Ω
1µF
25V
220µF
385V
BAV21
BAV21
390pF
1.5KE300A
5W
MUR150
BRIDGE
RECTIFIER
+
LINE
FILTER
85VAC TO 270VAC
+
–
TRANSFORMER DATA:
COILTRONICS CTX110228-3
L(PRI) = 1.6mH
NPRI:NSEC = 1:0.05
NBIAS:NSEC = 1:0.27
18.7k
0.047µF
1N4148
330Ω
0.1µF
LT1103 TA13
*OUTPUT CAPACITOR IS THREE 1200µF,
50V CAPACITORS IN PARALLEL TO
ACHIEVE REQUIRED RIPPLE CURRENT
RATING AND LOW ESR.
OPTIONAL OUTPUT FILTER
0.047µF
VC
VSW
GND OSC
15V
LT1103
VIN
FB
DANGER!!
HIGH VOLTAGE!!
+
+
+
++
IOUT (A)
0
V
OUT
(V)
5.05
5.15
5.25
8
LT1103 TA02
4.95
4.85
4.75 246
10
4.80
4.90
5.00
5.10
5.20
135 7 9
220VAC
270VAC
85VAC
110VAC
THE LT1103 IS OBSOLETE:
FOR INFORMATION PURPOSES ONLY
Contact Analog Devices for Potential Replacement
THE LT1105 IS AVAILABLE, BUT NOT
RECOMMENDED FOR NEW DESIGNS
LT110 3/LT110 5
2
Rev. E
For more information www.analog.com
Maximum Operating Ambient Temperature Range
LT1103C (OBSOLETE) .............................. 0°C to 70°C
LT1105C ................................................... 0°C to 70°C
Maximum Operating Temperature Range
LT1103C (OBSOLETE) ............................ 0°C to 100°C
LT1105C ................................................. 0°C to 100°C
LT1105I .............................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
DESCRIPTION WARNING
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN ............................................................................30V
VSW Output Voltage (LT1103)....................................50V
VSW Output Current (200ns)(LT1105) .................... ±1.5A
VC, FB, OSC, SS ..........................................................6V
ILIM (LT1105) ...............................................................3V
OVLO Input Current ..................................................1mA
Lead Temperature (Soldering, 10 sec.) ..................300°C
200kHz maximum switching frequency to achieve high
power density. Performance at switching frequencies
above 100kHz may be degraded due to internal timing
constraints associated with fully isolated flyback mode.
Included are the oscillator, control, and protection cir-
cuitry such as current limit and overvoltage lockout.
Switch frequency and maximum duty cycle are adjustable.
Bootstrap circuitry draws 200µA for start-up of isolated
topologies. A 5V reference as well as a 15V gate bias
are available to power external primary-side circuitry. No
external current sense resistor is necessary with LT1103
because it is integrated with the high current switch. The
LT1105 brings out the input to the current limit amplifier
and requires the use of an external sense resistor.
The LT1103/LT1105 have unique features not found on
other offline switching regulators. Adaptive antisat switch
drive allows wide ranging load currents while maintain-
ing high efficiency. The external FET is protected from
insufficient or excessive gate drive voltage with a drive
detection circuit. An externally activated shutdown mode
reduces total supply current to less than 200µA, typical
for standby operation. Fully isolated and regulated outputs
can be generated in the optional isolated flyback mode
without the need for optocouplers or other isolated feed-
back paths.
DANGEROUS AND LETHAL POTENTIALS ARE
PRESENT IN OFFLINE CIRCUITS!
BEFORE PROCEEDING ANY FURTHER, THE
READER IS WARNED THAT CAUTION MUST
BE USED IN THE CONSTRUCTION, TESTING
AND USE OF OFFLINE CIRCUITS. HIGH
VOLTAGE, AC LINE-CONNECTED POTENTIALS
ARE PRESENT IN THESE CIRCUITS. EXTREME
CAUTION MUST BE USED IN WORKING WITH
AND MAKING CONNECTIONS TO THESE
CIRCUITS. REPEAT: OFFLINE CIRCUITS
CONTAIN DANGEROUS, AC LINE-CONNECTED
HIGH VOLTAGE POTENTIALS. USE CAUTION.
ALL TESTING PERFORMED ON AN OFFLINE
CIRCUIT MUST BE DONE WITH AN ISOLATION
TRANSFORMER CONNECTED BETWEEN THE
OFFLINE CIRCUIT’S INPUT AND THE AC LINE.
USERS AND CONSTRUCTORS OF OFFLINE
CIRCUITS MUST OBSERVE THIS PRECAUTION
WHEN CONNECTING TEST EQUIPMENT TO
THE CIRCUIT TO AVOID ELECTRIC SHOCK.
REPEAT: AN ISOLATION TRANSFORMER MUST
BE CONNECTED BETWEEN THE CIRCUIT INPUT
AND THE AC LINE IF ANY TEST EQUIPMENT IS
TO BE CONNECTED.
LT110 3/LT110 5
3
Rev. E
For more information www.analog.com
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IQSupply Current 8V < VIN < 30V, After Device Has Started l10 20 30 mA
ISTART Start-Up Current VIN < VIN Start Threshold
Industrial Grade
l
l
200 400
450
µA
µA
VIN Start Threshold l14.5 16.0 17.5 V
VIN Shutdown Threshold Note: Switching Stops When VSW < 10V (LT1103)
Note: Switching Stops When VGATE < 10V (LT1105)
l5.0 7.0 8.0 V
VREF 5V Reference Voltage l4.80 4.95 5.20 V
VREF Line Regulation 10V < VIN < 30V l0.025 0.1 %V
VREF Load Regulation 0mA < IL < 20mA l0.025 0.05 %mA
VREF Short-Circuit Current Commercial Grade
Industrial Grade
l
l
25
20
60 110
120
mA
mA
15V Short-Circuit Current Commercial Grade
Industrial Grade
l
l
30
25
130
140
mA
mA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VC = 0.85V, OVLO = 0V, VSW Open, unless otherwise noted.
LT1105 LT1105 LT1103
1
2
3
4
5
6
7
TOP VIEW
N PACKAGE
14-LEAD PDIP
PINS 1 AND 7 MUST BE TIED TOGETHER
TJMAX = 100°C, JA = 100°C/W
14
13
12
11
10
9
8
PWRGND
OVLO
FB
VC
5V
SS
GND
VSW
NC
NC
15V
VIN
OSC
ILIM
1
2
3
4 5
6
7
8
TOP VIEW
GND
15V
V
SW
ILIM
VIN
OSC
FB
VC
N8 PACKAGE
8-LEAD PDIP
T
JMAX
= 100°C,
JA
= 130°C/W
15V
VIN
OSC
GND
VC
FB
VSW
T7 PACKAGE
7-LEAD TO-220
CASE IS CONNECTED TO GROUND. LEADS ARE FORMED
T
JMAX
= 100°C,
JA
= 50°C/W
FRONT VIEW
7
6
5
4
3
2
1
OBSOLETE PACKAGE
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1105CN#PBF LT1105CN#TRPBF LT1105CN 14-Lead PDIP 0°C to 100°C
LT1105IN#PBF LT1105IN#TRPBF LT1105IN 14-Lead PDIP –40°C to 125°C
LT1105CN8#PBF LT1105CN8#TRPBF LT1105CN8 8-Lead PDIP 0°C to 100°C
LT1105IN8#PBF LT1105IN8#TRPBF LT1105IN8 8-Lead PDIP –40°C to 125°C
OBSOLETE PACKAGE
LT1103CT7#PBF LT1103CT7#TRPBF LT1103CT7 7-Lead TO-220 0°C to 100°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
PIN CONFIGURATION
LT110 3/LT110 5
4
Rev. E
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VGATE 15V Gate Bias Reference 17 < VIN < 30V, 0mA < IL < 30mA l13.8 15.0 16.2 V
15V Dropout Voltage VIN = 15V, IL = 30mA l2.0 2.5 V
15V Short-Circuit Current l30 70 130 mA
SF Oscillator Scaling Factor FB = 4V, VC = Open, Measured at VSW, ISW = 25mA,
OVLO = 5V, fOSC = SF/COSC, 40kHz < fOSC < 200kHz
l
36
32
40
40
44
48
Hz • µF
Hz • µF
Oscillator Valley Voltage 2.0 V
Oscillator Peak Voltage 4.5 V
DC Preset Max Switch Duty Cycle
(LT1103)
FB = 4V, VC = Open, fOSC = 40kHz, ISW = 25mA,
Note: Maximum Duty Cycle Can Be Altered at OSC Pin
l58 65 72 %
Preset Max Switch Duty Cycle
(LT1105)
FB = 4V, VC = Open, fOSC = 40kHz, ISW = 25mA,
Note: Maximum Duty Cycle Can Be Altered at OSC Pin
Industrial Grade
l
l
56
55
63 70
75
%
%
OVLO Threshold Overvoltage Lockout Threshold at Which Switching is Inhibited
Industrial Grade
l
l
2.3
2.2
2.5 2.7
2.8
V
V
OVLO Input Bias Current OVLO = 2V, Measured Out of Pin (Note 2) l1.0 3.0 µA
VFB FB Threshold Voltage I(VC) = 0mA
l
4.425
4.400
4.50
4.50
4.575
4.600
V
V
FB Input Bias Current FB = VFB (Note 3)
Industrial Grade
l
l
5
4
10 20
22
µA
µA
Change in FB Input
Bias Current with Change in VC
FB = VFB, VC = 1V to 4V (Note 3)
Industrial Grade
l
l
8
7
6
11
11
13
14
15
µA/V
µA/V
µA/V
FB Threshold Line Regulation 10V < VIN < 30V l0.025 0.10 %/V
gmError Amp Transconductance ∆I(VC) = ±50µA
l
l
9000
6000
5000
12000
12000
17500
20000
24000
µmho
µmho
µmho
AVError Amp Voltage Gain 1V < VC < 3V
Industrial Grade
l
l
500
450
1250 V/V
V/V
VC Switching Threshold Switch Duty Cycle = 0% l0.85 1.25 1.4 mA
Shutdown Threshold Voltage
Industrial Grade
l
l
50
50
150 250
300
mV
mV
Error Amp Source Current l150 275 µA
Error Amp Sink Current
Industrial Grade
l
l
1.5
0.7
3 4.5
4.5
mA
mA
Error Amp Clamp Voltage FB = 4.75V
FB = 4.0V
l
l
0.3
4.2
0.7
4.4
0.9
4.6
V
V
Soft-Start Charging Current SS = 0V
Industrial Grade
l
l
25
20
40 60
75
µA
µA
Soft-Start Reset Current VIN = 6V, SS = 0.3V l1 2 mA
Output Switch Leakage
(LT1103)
VSW = 45V
VSW = 15V
l
l
500
200
µA
µA
BV Switch Breakdown Voltage
(LT1103)
ISW = 5mA l50 70 V
VSW Current Limit (LT1103) Duty Cycle = 25% (Note 4) l2.0 2.5 3.0 A
Output Switch On Resistance
(LT1103)
l0.4 0.75 Ω
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VC = 0.85V, OVLO = 0V, VSW Open, unless otherwise noted.
LT110 3/LT110 5
5
Rev. E
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The OVLO pin is clamped with a 5.5V Zener and can sink a
maximum input current of 1mA.
Note 3: FB input bias current changes as a function of the VC pin voltage.
Rate of change of FB input bias current is 11µA/V of change on VC. By
including a resistor in series with the FB pin, load regulation can be set to
zero.
Note 4: Current limit on VSW is constant for DC < 35% and decreases for
DC > 35% due to internal slope compensation circuity. The LT1103 switch
current limit is given by ILIM = 1.76 (1.536 – DC) above 35% duty cycle.
Note 5: The current limit threshold voltage is constant for DC < 35% and
decreases for DC > 35% due to internal slope compensation circuitry. The
LT1105 switch current limit threshold voltage is given by VLIM = 0.225
(1.7 – DC) above 35% duty cycle.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆IIN
∆ISW
IQ Increase During Switch On Time
(LT1103)
ISW = 0.5A to 1.5A l30 50 mA/A
Switch Output High Level
(LT1105)
Switch Output High Level
Industrial Grade
ISW = 200mA, VGATE = 15V
ISW = 750mA, VGATE = 15V
ISW = 200mA, VGATE = 15V
ISW = 750mA, VGATE = 15V
l
l
l
l
13.00
12.50
12.75
12.25
13.5
13.2
V
V
V
V
Switch Output Low Level
(LT1105)
ISW = 200mA
ISW = 750mA
l
l
0.25
0.75
0.50
1.50
V
V
Rise Time (LT1105) CL = 1000pF 50 ns
Fall Time (LT1105) CL = 1000pF 20 ns
ILIM Threshold Voltage (LT1105) Duty Cycle = 25% (Note 5) l300 375 450 mV
Low Switch Drive Lockout
Threshold
Measured at VSW (LT1103)
Measured at 15V Gate Bias Reference (LT1105)
l9.0 9.5 10.5 V
High Switch Drive Lockout
Threshold
Measured at VSW (LT1103)
Measured at 15V Gate Bias Reference (LT1105)
l17.0 18.5 20.0 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VC = 0.85V, OVLO = 0V, VSW Open, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Input Voltage
Start-Up Supply Current vs
Input Voltage
Quiescent Supply Current vs
Input Voltage
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (mA)
5
10
15
20
25
510 15 20
LT1103 G01
25 30
ISTART
ISHUT
25°C
INPUT VOLTAGE (V)
0
START-UP SUPPLY CURRENT (µA)
300
400
500
12
LT1103 G02
200
50
036915
100
150
250
350
450
125°C 25°C
–55°C
INPUT VOLTAGE (V)
0
12
QUIESCENT SUPPLY CURRENT (mA)
13
15
16
17
22
19
10 20 25
LT1103 G03
14
20
21
18
5 15 30 35 40
125°C
25°C
–55°C
LT110 3/LT110 5
6
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Supply Current vs
Temperature
Shutdown Supply Current vs Input
Voltage
Shutdown Supply Current vs
VC Voltage
VIN Start-Up Threshold vs
Temperature
VIN Shutdown Threshold vs
Temperature
Output Switch Frequency vs
Temperature
Preset Switch Maximum Duty
Cycle vs Temperature
Switch Oscillator Frequency vs
Capacitance
Overvoltage Lockout Threshold vs
Temperature
TEMPERATURE (°C)
–75
QUIESCENT SUPPLY CURRENT (mA)
18
20
22
125
LT1103 G04
16
14
12 –50 –25 0
175
25 50 75 100 150
21
19
17
15
13
30V
8V
INPUT VOLTAGE (V)
0
0
SHUTDOWN SUPPLY CURRENT (µA)
50
150
200
250
500
350
10 20 25
LT1103 G05
100
400
450
300
515 30 35
VC = 75mV
VC = 0
VC (mV)
0
SHUTDOWN CURRENT (µA)
300
400
500
160
LT1103 G06
200
100
040 80 120
200
50
150
250
350
450
20 60 100 140 180
25°C 125°C
–55°C
TEMPERATURE (°C)
–75
14.5
V
IN
START-UP THRESHOLD (V)
15.0
15.5
16.0
16.5
17.0
17.5
–25 25 75 125
LT1103 G07
175
–50 0 50 100 150
TEMPERATURE (°C)
–75
IN
7.4
7.7
125
7.1
6.8
6.5 –25 25 75
–50 0 50 100 150
TEMPERATURE (°C)
–75
35
OUTPUT SWITCH FREQUENCY (kHz)
37
41
43
45
–25 25 50 150
LT1103 G09
39
–50 0 75 100 125
COSC = 1000pF
TEMPERATURE (°C)
–75
PRESET SWITCH DUTY CYCLE (%)
69
72
75
125
LT1103 G10
66
63
60 –25 25 75
175
150
10050
0–50
COSC = 1000pF
CAPACITANCE (pF)
100
10
SWITCH FREQUENCY (kHz)
100
1000
1000
10000
LT1103 G11
TEMPERATURE (°C)
–75
OVERVOLTAGE LOCKOUT THRESHOLD (V)
2.6
2.8
3.0
125
LT1103 G12
2.4
2.2
2.0 –25 25 75
175
150
10050
0–50
LT110 3/LT110 5
7
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
OVLO Input Bias Current vs
Temperature
Soft-Start Charging Current vs
Temperature
Soft-Start Reset Current vs
Temperature
5V Reference Voltage vs
Temperature
5V Load Regulation vs
Temperature
5V Line Regulation vs
Temperature
5V Reference Short-Circuit
Current vs Temperature
15V Gate Bias Reference vs
Temperature
15V Gate Bias Dropout Voltage vs
Temperature
TEMPERATURE (°C)
–75
–3.0
OVLO INPUT BIAS CURRENT (µA)
–2.5
–2.0
–1.5
–1.0
–0.5
0
–25 25 75 125
LT1103 G13
175
–50 0 50 100 150
OVLO = 2V
TEMPERATURE (°C)
–75
0
SOFT-START CHARGING CURRENT (µA)
10
20
30
40
50
60
–25 25 75 125
LT1103 G14
175
–50 0 50 100 150
TEMPERATURE (°C)
–75
SOFT-START RESET CURRENT (mA)
3
4
5
125
LT1103 G15
2
1
0–25 25 75
175
150
10050
0–50
TEMPERATURE (°C)
–75
5V REFERENCE VOLTAGE (V)
5.10
5.20
125
LT1103 G16
5.00
4.90
4.80 –25 25 75
175
–50 050 100 150
5.15
5.05
4.95
4.85
TEMPERATURE (°C)
–75
5V LOAD REGULATION (%/mA)
0.015
0.020
0.025
125
LT1103 G17
0.010
0.005
0–25 25 75
175
150
10050
0–50
TEMPERATURE (°C)
–75
5V LINE REGULATION (%/V)
0.03
0.04
0.05
125
LT1103 G18
0.02
0.01
0–25 25 75
175
150
10050
0–50
TEMPERATURE (C)
–75
5V REFERENCE SHORT-CIRCUIT CURRENT (mA)
90
110
125
LT1103 G19
70
50
30 –25 25 75
175
–50 050 100 150
100
80
60
40
TEMPERATURE (°C)
–75
13.8
15V GATE BIAS REFERENCE (V)
14.2
14.6
15.0
15.4
15.8
16.2
–25 25 75 125
LT1103 G20
175
–50 0 50 100 150
TEMPERATURE (°C)
–75
15V GATE BIAS DROPOUT VOLTAGE (V)
1.5
2.0
2.5
125
LT1103 G21
1.0
0.5
0–25 25 75
175
150
10050
0–50
LT110 3/LT110 5
8
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
15V Gate Bias Short-Circuit
Current vs Temperature
Low Switch Drive Lockout
Threshold vs Temperature
High Switch Drive Lockout
Threshold vs Temperature
Feedback Threshold vs
Temperature
FB Input Bias Current vs
Temperature (VC = 1V)
Change in FB Input Bias Current
with Change in VC vs Temperature
(VC = 1V to 4V)
Error Amplifier Transconductance
vs Temperature
Error Amplifier Transconductance
and Phase vs Frequency
Error Amplifier Voltage Gain vs
Temperature
TEMPERATURE (°C)
–75
15V GATE BIAS SHORT-CIRCUIT CURRENT (mA)
90
110
130
125
LT1103 G22
70
50
30 –25 25 75
175
150
10050
0–50
TEMPERATURE (°C)
–75
LOW SWITCH DRIVE LOCKOUT THRESHOLD (V)
9.9
10.2
10.5
125
LT1103 G23
9.6
9.3
9.0 –25 25 75
175
150
10050
0–50
TEMPERATURE (°C)
–75
17.0
HIGH SWITCH DRIVE LOCKOUT THRESHOLD (V)
17.5
18.0
18.5
19.0
19.5
20.0
–25 25 75 125
LT1103 G24
175
–50 0 50 100 150
TEMPERATURE (°C)
–75
FEEDBACK THRESHOLD (V)
4.52
4.56
4.60
125
LT1103 G25
4.48
4.44
4.40 –25 25 75
175
150
10050
0–50
TEMPERATURE (°C)
–75
FB INPUT BIAS CURRENT (µA)
12
16
20
125
LT1103 G26
8
4
0–25 25 75
175
150
10050
0–50
TEMPERATURE (°C)
–75
7
CHANGE IN FB INPUT BIAS CURRENT
WITH CHANGE IN VC (µA/V)
8
10
11
12
14
–50 50 100
LT1103 G27
9
13
25 150 175
–25 075 125
TEMPERATURE (°C)
–75
ERROR AMPLIFIER TRANSCONDUCTANCE (µmho)
25000
125
LT1103 G28
15000
10000
5000 –25 25 75
175
–50 0 50 100 150
20000
FREQUENCY (kHz)
0.004
ERROR AMPLIFIER TRANSCONDUCTANCE (mho)
0.008
0.012
0.016
0.020
0.1 10 100 1000
LT1103 G29
01
0.018
0.014
0.010
0.006
0.002
40
80
120
160
200
0
180
140
100
60
20
PHASE (DEGREES)
PHASE
PHASE
gm
gm
TEMPERATURE (°C)
–75
ERROR AMPLIFIER VOLTAGE GAIN (V/V)
2500
125
LT1103 G30
1500
1000
500 –25 25 75
175
–50 050 100 150
2000
LT110 3/LT110 5
9
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Error Amplifier Source Current vs
Temperature
Error Amplifier Sink Current vs
Temperature
Error Amplifier High Clamp
Voltage vs Temperature (FB = 4V)
Error Amplifier Low Clamp
Voltage vs Temperature
(FB = 4.75V)
VC Switching Threshold Voltage
vs Temperature
LT1103 Output Switch Leakage
Current vs Temperature
LT1103 Switch Saturation Voltage
vs Temperature
LT1103 VSW Current Limit vs
Duty Cycle
LT1103 VSW Current Limit vs
Temperature
TEMPERATURE (°C)
–75
ERROR AMPLIFIER SOURCE CURRENT (µA)
350
125
LT1103 G31
250
200
150 –25 25 75
175
–50 0 50 100 150
300
325
275
225
175
TEMPERATURE (°C)
–75
1.5
ERROR AMPLIFIER SINK CURRENT (mA)
2.0
2.5
3.0
3.5
4.0
4.5
–25 25 75 125
LT1103 G32
175
–50 0 50 100 150
TEMPERATURE (°C)
–75
ERROR AMPLIFIER HIGH CLAMP VOLTAGE (V)
4.3
4.4
4.5
125
LT1103 G33
4.2
4.1
4.0 –25 25 75
175
150
10050
0–50
TEMPERATURE (°C)
–75
0.3
ERROR AMPLIFIER LOW CLAMP VOLTAGE (V)
0.4
0.5
0.6
0.7
0.8
0.9
–25 25 75 125
LT1103 G34
175
–50 0 50 100 150
TEMPERATURE (°C)
–75
V
C
SWITCHING THRESHOLD (V)
1.1
1.3
1.5
125
LT1103 G35
0.9
0.7
0.5 –25 25 75
175
150
10050
0–50
TEMPERATURE (°C)
–75
LT1103 OUTPUT SWITCH LEAKAGE CURRENT (µA)
120
160
200
125
LT1103 G36
80
40
0–25 25 75
175
150
10050
0–50
VSW = 45V
VSW = 15V
TEMPERATURE (°C)
–75
0
LT1103 SWITCH SATURATION VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
–25 25 75 125
LT1103 G38
175
–50 0 50 100 150
ISW = 1.5A
ISW = 0.5A
DUTY CYCLE (%)
0
0
LT1103 V
SW
CURRENT LIMIT (A)
0.5
1.0
1.5
2.0
20 40 60 80
LT1103 G39
2.5
3.0
10 30 50 70
25°C
125°C
–55°C
TEMPERATURE (°C)
–75
LT1103 V
SW
CURRENT LIMIT (A)
2.6
2.8
3.0
125
LT1103 G40
2.4
2.2
2.0 –25 25 75
175
2.1
2.3
2.5
2.7
2.9
–50 050 100 150
DC = 25%
LT110 3/LT110 5
10
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
LT1103 Driver Current vs
Temperature
LT1105 VSW Low Saturation
Voltage vs Temperature
LT1105 VSW High Saturation
Voltage vs Temperature
LT1105 Current Limit Threshold
Voltage vs Temperature
LT1105 VSW Rise Time vs
Temperature
LT1105 VSW Fall Time vs
Temperature
TEMPERATURE (°C)
–75
LT1103 DRIVER CURRENT (mA/A)
30
40
50
125
LT1103 G41
20
10
0–25 25 75
175
150
10050
0–50
TEMPERATURE (°C)
–75
0
LT1105 V
SW
LOW SATURATION VOLTAGE (V)
0.5
1.0
1.5
2.0
2.5
3.0
–25 25 75 125
LT1103 G42
175
–50 0 50 100 150
ISW = 750mA
ISW = 200mA
TEMPERATURE (°C)
–75
0
LT1105 V
SW
HIGH SATURATION VOLTAGE (V)
0.5
1.0
1.5
2.0
2.5
3.0
–25 25 75 125
LT1103 G43
175
–50 0 50 100 150
ISW = 750mA
ISW = 200mA
TEMPERATURE (°C)
–75
LT1105 V
SW
RISE TIME (ns)
60
80
100
125
LT1103 G44
40
20
0–25 25 75
175
150
10050
0–50
CLOAD = 4700pF
CLOAD = 1000pF
TEMPERATURE (°C)
–75
LT1105 V
SW
FALL TIME (ns)
60
80
100
125
LT1103 G45
40
20
0–25 25 75
175
150
10050
0–50
CLOAD = 4700pF
CLOAD = 1000pF
TEMPERATURE (°C)
–75
300
LT1105 CURRENT LIMIT THRESHOLD VOLTAGE (mV)
325
350
375
400
425
450
–25 25 75 125
LT1103 G46
175
–50 0 50 100 150
DC = 25°C
LT110 3/LT110 5
11
Rev. E
For more information www.analog.com
PIN FUNCTIONS
LT1103
FB: The Feedback pin is the inverting input to the sampling
error amplifier. The noninverting input is tied to a 4.5V
reference. The FB pin is used for output voltage sensing.
The input bias current is a function of the control pin VC
voltage and can be used for load regulation compensa-
tion by including a resistor in series with the FB pin. The
sampling error amplifier has a typical gm of 0.012 mhos
and the output of the sampling error amplifier has asym-
metrical slew rate to reduce overshoot during start-up
conditions or following the release of an output overload.
VC: The VC control pin is used for frequency compensa-
tion, current limiting and shutdown. It is the high imped-
ance output of the sampling error amplifier and the input
of the current limit comparator.
GND: The Ground pin acts as both the negative sense
point for the internal sampling error amplifier feedback
signal and as the high current path for the 2A switch. Also,
the case of the 7-lead TO-220 is connected to ground.
Proper connections to ground for signal paths and high
current paths must be made in order to insure good load
regulation.
OSC: The Oscillator pin sets the operating frequency
of the regulator with one external capacitor to ground.
Maximum duty cycle can also be adjusted by using an
external resistor to alter the charge/discharge ratio.
V
IN
: The Input Supply pin is designed to operate with volt-
ages of 12V to 30V. The supply current is typically 200µA
up to the start-up threshold of 16V. Normal operating
supply current is fairly flat at 18mA down to the shutdown
threshold of 7V. Switching is inhibited for VIN less than
12V due to the gate drive detection circuit.
15V: A 15V reference is used to bias the gate of an exter-
nal power FET. The voltage temperature coefficient is typi-
cally 3mV/°C and the output can source 30mA. Typical
dropout voltage is 1.5V for VIN less than 17V and 30mA
of load current.
V
SW
: The Switch Output pin is the collector of the internal
NPN power switch. This pin has a typical ON resistance of
0.4Ω and a minimum breakdown voltage of 50V. This pin
also ties to the FET gate drive detection circuit.
LT1105
All functions on the LT1105 are equivalent to the LT1103
with the exception of the VSW pin and the ILIM pin and the
availability of the OVLO, 5V, and SS functions.
OVLO: The Overvoltage Lockout pin inhibits switching
when the pin is pulled above its threshold voltage of 2.5V.
OVLO is implemented with a resistor divider network from
the rectified DC line and is used to protect the external
FET from an overvoltage condition in the off state. This
function is only available on the 14-lead PDIP.
5V: A 5V reference is available to power primary-side cir-
cuitry. The temperature coefficient is typically 50ppm/°C
and the output can source 25mA. This function is only
available on the 14-lead PDIP.
SS: The Soft-Start pin is used to either program start-up
time with a capacitor to ground or to set external current
limit with a resistor divider. The SS pin has a 40µA pull-up
current and is reset to 0V by a 1mA pull-down current dur-
ing start-up and shutdown. This function is only avail-able
on the 14-lead PDIP.
V
SW
: The Switch Output pin is the output of a 1A NPN
totem-pole stage. The VSW pin turns the external FET
on by pulling its gate high. Break-Before-Make action of
200ns on each switch edge is built in to eliminate cross
conduction currents.
ILIM: The ILIM pin is the input to the current limit amplifier
and requires the use of a noninductive, power sense resis-
tor from ILIM to ground to set current limit. The typical
current limit threshold voltage is 350mV. The typical input
bias current is 100µA out of the pin.
LT110 3/LT110 5
12
Rev. E
For more information www.analog.com
BLOCK DIAGRAM
LT1103
LT1105
–
+
AV = 10
GATE
BIAS
DETECT
15V
GATE
BIAS
SAMPLING
ERROR AMP
gm = 0.012
OVERVOLTAGE
LOCKOUT 0.15V
2.5V
40µA
CURRENT
LIMIT
AMP
0.15Ω
6V
VSW
OSC
START-UP OSCILLATOR
15V
VIN
5V
FB
0VLO
16V
7V
4.5V
VCSS
5V
VREF
SPIKE
BLANK
COMP
LOGIC DRIVER
ANTISAT
–
+
GND
LT1103 BD
SHUT
DOWN
RESET
–
+
AV = 10
GATE
BIAS
DETECT
15V
GATE
BIAS
SAMPLING
ERROR AMP
gm = 0.012
OVERVOLTAGE
LOCKOUT 0.15V
2.5V
RESET
40µA
CURRENT
LIMIT
AMP
6V
V
SW
OSC
START-UP OSCILLATOR
15V
VIN
5V
FB
0VLO
16V
7V
4.5V
V
C
SS
5V
VREF
SHUT
DOWN
SPIKE
BLANK
COMP
LOGIC
–
+
GND
LT1105 BD
DRIVER
DRIVER
ANTISAT
ILIM
LT110 3/LT110 5
13
Rev. E
For more information www.analog.com
OPERATION
LT1103
The LT1103 is a current mode switcher. Switch duty cycle
is controlled by switch current rather than directly by the
output voltage. Referring to the block diagram, the switch
is turned on at the start of each oscillator cycle. It is turned
off when switch current reaches a predetermined level.
Control of output voltage is obtained by using the output
of a voltage sensing error amplifier to set current trip
level. This technique has several advantages. First, it has
immediate response to input voltage variations, unlike
ordinary switchers which have notoriously poor line tran-
sient response. Second, it reduces the 90°phase shift at
mid frequencies in the transformer. This greatly simpli-
fies closed-loop frequency compensation under widely
varying input voltage or output load conditions. Finally, it
allows simple pulse-by-pulse current limiting to provide
maximum switch protection under output overload or
short-circuit conditions.
A start-up loop with hysteresis allows the IC supply volt-
age to be bootstrapped from an extra primary side wind-
ing on the power transformer. From 0V to 16V on VIN, the
LT1103 is in a prestart mode and total input current is typ-
ically 200µA. Above 16V, up to 30V, the 6V regulator that
biases the internal circuitry and the externally available
15V regulator is turned on. The internal circuitry remains
biased on until VIN drops below 7V and the part returns to
the prestart mode. Output switching stops when the VSW
drive is less than 10V corresponding to VIN of about 12V.
The oscillator provides the basic clock for all internal tim-
ing. Frequency is adjustable to 200kHz with one external
capacitor from OSC to ground. The oscillator turns on the
output switch via the logic and driver circuitry. Adaptive
antisat circuitry detects the onset of saturation in the
power switch and adjusts driver current instantaneously
to limit switch saturation. This minimizes driver dissipa-
tion and provides very rapid turn-off of the switch.
The LT1103 is designed to drive the source of an exter-
nal power FET in common gate configuration. The 15V
regulator biases the gate to guarantee the FET is on when
the switch is on. Special drive detection circuitry senses
the gate bias voltage and prevents the output switch from
turning on if the gate voltage is less than 10V or greater than
20V, the industry standards for power MOSFET operation.
The switch current is sensed internally and amplified to
trip the comparator and turn off the switch according to
the VC pin control voltage. A blanking circuit suppresses
the output of the current limit comparator for 500ns at
the beginning of each switch cycle. This prevents false
tripping of the comparator due to current spikes caused
by external parasitic capacitance and diode stored charge.
The 4.5V Zener-based reference biases the positive input
of the sampling error amplifier. The negative input (FB)
is used for output voltage sensing. The sampling error
amplifier allows the LT1103 to operate in fully isolated
flyback mode by regulating from the flyback voltage of
the bootstrap winding. The leakage inductance spike at
the leading edge of the flyback waveform is ignored with
a blanking circuit. The flyback waveform is directly pro-
portional to the output voltage in a transformer-coupled
flyback topology. Output voltages are fully floating up
to the breakdown voltage of the transformer windings.
Multiple floating outputs are easily obtained with addi-
tional windings.
The error signal developed at the comparator input is
brought out externally. This V
C
pin has three functions
including frequency compensation, current limit adjust-
ment and total regulator shutdown. During normal opera-
tion, this pin sits at a voltage between 1.2V (low output
current) and 4.4V (high output current). The error ampli-
fier is a current output (gm) type, so this voltage can be
externally clamped for adjusting current limit. Switch duty
cycle goes to zero if the VC pin is pulled to ground through
a diode, placing the LT1103 in an idle mode. Pulling the
VC pin below 0.15V causes total regulator shutdown and
places the LT1103 in a prestart mode.
LT1105
The LT1105 is a current mode switcher. Switch duty cycle
is controlled by switch current rather than directly by out-
put voltage. Referring to the block diagram, the switch is
turned on at the start of each oscillator cycle. It is turned
off when switch current reaches a predetermined level.
LT110 3/LT110 5
14
Rev. E
For more information www.analog.com
Control of output voltage is obtained by using the output
of a voltage sensing error amplifier to set current trip
level. This technique has several advantages. First, it has
immediate response to input voltage variations, unlike
ordinary switchers which have notoriously poor line tran-
sient response. Second, it reduces the 90°phase shift at
midfrequencies in the transformer. This greatly simpli-
fies closed-loop frequency compensation under widely
varying input voltage or output load conditions. Finally, it
allows simple pulse-by-pulse current limiting to provide
maximum switch protection under output overload or
short-circuit conditions.
A start-up loop with hysteresis allows the IC supply volt-
age to be bootstrapped from an extra primary side wind-
ing on the power transformer. From 0V to 16V on VIN,
the LT1105 is in prestart mode and total input current is
typically 200µA. Above 16V, up to 30V, the 6V regulator
that biases the internal circuitry and the externally avail-
able 5V and 15V regulators are turned on. The internal
circuitry remains biased on until VIN drops below 7V and
the part returns to prestart mode. Output switching stops
when the 15V gate bias reference is less than 10V cor-
responding to VIN of about 12V.
The oscillator provides the basic clock for all internal tim-
ing. Frequency is adjustable to 200kHz with one external
capacitor from OSC to ground. The oscillator turns on the
output switch via the logic and driver circuitry.
The LT1105 is designed to drive the gate of an external
power FET in common source configuration. The drivers
and the 1A maximum totem-pole output stage are biased
from the 15V gate bias reference. Special drive detec-
tion circuity senses the gate bias reference voltage and
prevents the output switch from turning on if this voltage
is less than 10V or greater than 20V. Break-Before-Make
action of 200ns is built into each switch edge to eliminate
cross conduction currents.
Switch current is sensed externally through a precision,
power resistor. This allows for greater flexibility in switch
current and output power than allowed by the LT1103.
The voltage across the sense resistor is fed into the ILIM
pin and amplified to trip the comparator and turn off the
switch according to the V
C
pin control voltage. A blanking
circuit suppresses the output of the current limit com-
parator for 500ns at the beginning of each switch cycle.
This prevents false tripping of the comparator due to cur-
rent spikes caused by external parasitic capacitance and
diode stored charge.
A 4.5V Zener-based reference biases the positive input
of the sampling error amplifier. The negative input (FB)
is used for output voltage sensing. The sampling error
amplifier allows the LT1105 to operate in fully isolated
flyback mode by regulating the flyback voltage of the
bootstrap winding. The leakage inductance spike at the
leading edge of the flyback waveform is ignored with a
blanking circuit. The flyback waveform is directly propor-
tional to the output voltage in the transformer coupled
flyback topology. Output voltages are fully floating up
to the breakdown voltage of the transformer windings.
Multiple floating outputs are easily obtained with addi-
tional windings.
The error signal developed at the comparator input is
brought out externally. The V
C
pin has three functions
including frequency compensation, current limit adjust-
ment and total regulator shutdown. During normal opera-
tion, this pin sits at a voltage between 1.2V (low output
current) and 4.4V (high output current). The error ampli-
fier is a current output (gm) type, so this voltage can be
externally clamped for adjusting current limit. Switch duty
cycle goes to zero if the VC pin is pulled to ground through
a diode, placing the LT1105 in an idle mode. Pulling the
VC pin below 0.15V causes total regulator shutdown and
places the LT1105 in prestart mode.
The SS pin implements soft-start with one external capac-
itor to ground. The internal pull-up current and clamp
transistor limit the voltage at VC to one diode drop above
the voltage at the SS pin, thereby controlling the rate of
rise of switch current in the regulator. The SS pin is reset
to 0V when the LT1105 is in prestart mode.
A final protection feature includes overvoltage lockout
monitoring of the main supply voltage on the OVLO pin.
If the OVLO pin is greater than 2.5V, the output switch is
prevented from turning on. This function can be disabled
by grounding the OVLO pin.
LT110 3/LT110 5
15
Rev. E
For more information www.analog.com
Bootstrap Start
It is inefficient as well as impractical to power a switching
regulator control IC from the rectified DC input as this
voltage is several hundred volts. Self-biased switching
regulator topologies take advantage of a lower voltage
auxiliary winding on the power transformer or inductor to
power the regulator, but require a start-up cycle to begin
regulation.
Start-up circuitry with hysteresis built into the LT1103/
LT1105 allows the input voltage to increase from 0V to
16V before the regulator tries to start. During this time
the start-up current of the switching regulator is typi-
cally 200µA and all internal voltage regulators are off.
The low quiescent current allows the input voltage to be
trickled up with only 500µA of current from the rectified
DC line voltage, thereby minimizing power dissipation in
the start-up resistor. At 16V, the internal voltage regula-
tors are turned on and switching begins. If enough power
feeds back through the auxiliary winding to keep the input
voltage to the switching regulator above 12V, then switch-
ing continues and a bootstrap start is accomplished. If
the input voltage drops below 12V, then the FET drive
detection circuit locks out switching. The input voltage
continues to fall as the VIN bypass capacitor is discharged
by the normal quiescent current of the LT1103/LT1105.
Once the input voltage falls below 7V, the internal volt-
age regulators are turned off and the switching regulator
returns to the low start-up current state. A continuous
“burp start” mode indicates a fault condition or an incom-
plete power loop.
The trickle current required to bootstrap the regulator
input voltage is typically generated with a resistor from
the rectified DC input voltage. When combined with the
regulator input bypass capacitor, the start-up resistor cre-
ates a ramp whose slope governs the turn-on time of the
regulator as well as the period of the “burp start” mode.
The design trade-offs are power dissipated in the trickle
resistor, the turn-on time of the regulator, and the hold-up
time of the regulator input bypass capacitor. The value
of the start-up resistor is set by the minimum rectified
DC input voltage to guarantee sufficient start-up current.
The recommended minimum trickle current is 500µA.
The power rating of the start-up resistor is set by the
APPLICATIONS INFORMATION
maximum rectified DC input voltage. A final consideration
for the start-up resistor is to insure that the maximum
voltage rating of the resistor is not exceeded. Typical car-
bon film resistors have a voltage rating of 250V. The most
reliable and economical solution for the start-up resistor
is generally provided by placing several 0.25W resistors
in series.
The LT1103/LT1105 is designed to operate with supply
pin voltages up to 30V. However, the auxiliary bias wind-
ing should be designed for a typical output voltage of
17V to minimize IC power dissipation and efficiency loss.
Allowances must also be made for cross regulation of
the bias voltage due to variations in the rectified DC line
voltage and output load current.
Soft-Start
Soft-start refers to the controlled increase of switch cur-
rent from a start-up or shutdown state. This allows the
power supply to come up to voltage in a controlled man-
ner and charge the output capacitor without activating
current limit. In general, soft-start is not required on the
LT1105 due to the design of the sampling error amplifier
gm stage which generates asymmetrical slew capability
on the VC pin.
This feature exhibits itself as a typical 3mA sink current
capability on the VC pin whereas source current is only
275µA. The low g
m
of the error amplifier allows small-
valued compensation capacitors to be used on VC. This
allows the sink current to slew the compensation capaci-
tor quickly. Therefore, overshoot of the output voltage on
start-up sequences and recovery from overload or short-
circuit conditions is prevented. However, if a longer start-
up period is required, the soft-start function can be used.
Soft-start is implemented with an internal 40µA pull-up
and a transistor clamp on the VC pin so that a single exter-
nal capacitor from SS ground can define the linear ramp
function. The voltage at VC is limited to one VBE above the
soft-start pin (SS). The time to maximum switch current is
defined as the capacitance on SS multiplied by the active
range in volts of the VC pin divided by the pull-up current:
T=
C •(3.2V )
40µA
LT110 3/LT110 5
16
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
SS is reset to 0V whenever VIN is less than 7V (prestart
mode) or when shutdown is activated by pulling V
C
below
0.15V. The SS pin has a guaranteed reset sink current of
1mA when either the regulator supply voltage V
IN
falls
below 7V or the regulator is placed in shutdown.
Shutdown
The LT1103/LT1105 can be put in a low quiescent cur-
rent shutdown mode by pulling VC below 150mV. In the
shutdown mode the internal voltage regulators are turned
off, SS is reset to 0V and the part draws less than 200µA.
To initiate shutdown, about 400µA must be pulled out
of VC until the internal voltage regulators turn off. Then,
less than 50µA pull-down current is required to maintain
shutdown. The shutdown function has about 60mV of
hysteresis on the VC pin before the part returns to normal
operation. Soft-start, if used, controls the recovery from
shutdown.
5V Reference
A 5V reference output is available for the user’s conve-
nience to power primary-side circuitry or to generate a
clamp voltage for switch current limiting. The output will
source 25mA and the voltage temperature coefficient is
typically 50ppm/°C. If bypassing of the 5V reference is
required, a 0.1µF is recommended. Values of capacitance
greater than 1µF may be susceptible to ringing due to
decreased phase margin. In such cases, the capacitive
load can be isolated from the reference output with a
small series resistor at the expense of load regulation
performance.
Overvoltage Lockout
The switching supply and primarily the external power
MOSFET can be protected from an extreme surge of the
input line voltage with the overvoltage lockout feature
implemented on the OVLO pin. If the voltage on OVLO
rises above its typical threshold voltage of 2.5V, output
switching is inhibited. This feature can be implemented
with a resistive divider off of the rectified DC input voltage.
This feature is only available on the LT1105 in the 14-lead
PDIP and must be tied to ground if left unused.
Ground (LT1103)
The ground pin of the LT1103 is important because it acts
as the negative sense point for the internal error amplifier
feedback signal, the negative sense point for the current
limit amplifier, and as the high current path for the 2A
switch. The tab of the 7-lead TO-220 is internally con-
nected to GND (Pin 4).
To avoid degradation of load regulation, the feedback
resistor divider string and the reference side of the bias
winding should be directly connected to the ground pin
on the package. These ground connections should not
be mixed with high current carrying ground return paths.
The length of the switch current ground path should be
as short as possible to the input supply bypass capacitor
and low resistance for best performance. The case of the
LT1103 package is desirable to use as the high current
ground return path as this is a lower resistive and induc-
tive path than that of the actual package pin and will help
minimize voltage spikes associated with the high dI/dt
switch current.
Avoiding long wire runs to the ground pin minimizes
load regulation effects and inductive voltages created by
the high dI/dt switch current. Ground plane techniques
should also be used and will help keep EMI to a mini-
mum. Grounding techniques are illustrated in the Typical
Applications section.
Ground (LT1105)
The ground pin of the LT1105 is important because it acts
as the negative sense point for the internal error amplifier
feedback signal and as the negative sense point for the
current limit amplifier. The LT1105 8-pin PDIP has Pin
1 as its ground. The LT1105 14-pin PDIP has Pin 1 and
Pin 7 as grounds and must be tied together for proper
operation.
To avoid degradation of load regulation, the feedback
resistor divider should be directly connected to the pack-
age ground pin. These ground connections should not
be mixed with high current carrying ground return paths.
The length of the switch current ground path should be
as short as possible to the input supply bypass capacitor
and low resistance for best performance. This will help
LT110 3/LT110 5
17
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
minimize voltage spikes associated with the high dI/dt
switch current.
Avoiding long wire runs to the ground pin minimizes
load regulation effects and inductive voltages created by
the high dI/dt switch current. Ground plane techniques
should also be used and will help keep EMI to a mini-
mum. Grounding techniques are illustrated in the Typical
Applications section.
Oscillator
The oscillator of the LT1103/LT1105 is a linear ramp type
powered from the internal 6V bias line. The charging cur-
rents and voltage thresholds are generated internally so
that only one external capacitor is required to set the fre-
quency. The 150µA pull-up current, which is on all the
time, sets the preset maximum on-time of the switch and
the 450µA pull-down current which is turned on and off,
sets the dead time. The threshold voltages are typically 2V
and 4.5V, so for a 400pF capacitor the ramp-up time of the
voltage on the OSC pin is 6.67µs and the ramp-down time
is 3.3µs, resulting in an operating frequency of 100kHz.
Although the oscillator, as well as the rest of the switching
regulator, will function at higher frequencies, 200kHz is
the practical upper limit that will allow control range for
line and load regulation. The lowest operating frequency
is limited by the sampling error amplifier to about 10kHz.
The frequency temperature coefficient is typically
–80ppm/°C with a good low T.C. capacitor. This means
that with a low temperature coefficient capacitor, the tem-
perature coefficient of the currents and the temperature
coefficient of the thresholds sum to –80ppm/°C over the
commercial temperature range. Bowing in the tempera-
ture coefficient of the currents affects the frequency about
±3% at the extremes of the military temperature range.
The capacitor type chosen will have a direct effect on the
frequency tempco.
Maximum duty cycle is set internally by the pull-up and
pull-down currents, independent of frequency. It can be
adjusted externally by modifying the fixed pull-up current
with an additional resistor. In practice, one resistor from
the OSC pin to the 5V reference or to ground does the job.
Note that the capacitor value must change to maintain the
same frequency. For example, a 24k resistor from 5V to
OSC and a 440pF capacitor from OSC to ground will yield
100kHz with 50% maximum duty cycle. A 56k resistor and
a 280pF capacitor from OSC to ground will yield 100kHz
with 80% maximum duty cycle.
The oscillator can be synchronized to an external clock by
coupling a sync pulse into the OSC pin. The width of this
pulse should be a minimum of 500ns. The oscillator can
only be synchronized up in frequency and the synchroniz-
ing frequency must be greater than the maximum pos-
sible unsynchronized frequency (for the chosen oscillator
capacitor value). The amplitude of the sync pulse must be
chosen so that the sum of the oscillator voltage amplitude
plus the sync pulse amplitude does not exceed the 6V
bias reference. Otherwise, the oscillator pull-up current
source will saturate and erroneous operation will result.
If the LT1103/LT1105 is positioned on the primary side
of the transformer and the external clock on the isolated
secondary output side, the sync signal must be coupled
into the OSC pin using a pulse transformer. The pulse
transformer must meet all safety/isolation requirements
as it also crosses the isolation boundary. An example of
externally synchronizing the oscillator is shown in the
Typical Applications section.
Gate Biasing (LT1103)
The LT1103 is designed to drive an external power
MOSFET in the common gate or cascode connection with
the VSW pin. The advantage is that the switch current
can be sensed internally, eliminating a low value, power
sense resistor. The gate needs to be biased at a voltage
high enough to guarantee that the FET is saturated when
the open-collector source drive is on. This means 10V as
specified in FET data sheets, plus 1V for the typical switch
saturation voltage, plus a couple of volts for temperature
variations and processing tolerances. This leads to 15V
for a practical gate bias voltage.
Power MOSFETs are well suited to switching power sup-
plies because their high speed switching characteris-
tics promote high switching efficiency. To achieve high
switching speed, a special circuit in the LT1103 senses
LT110 3/LT110 5
18
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
the voltage at VSW prior to turning on the switch. VSW is
tied to the source of the FET and should represent the
bias voltage on the gate when the switch is off. When
the switch first turns off, the drain flies back until it is
clamped by a snubber network. The source also flies
high due to parasitic capacitive coupling on the FET and
parasitic inductance of the leads. An extra diode from the
source to the gate or VIN will provide insurance against
fault conditions that might otherwise damage the FET.
The diode clamps the source to one diode drop above
the gate or VIN, thereby limiting the gate source reverse
bias. Once the energy in the leakage inductance spike
is dissipated and the primary is being regulated to its
flyback voltage, the diode shuts off. The source is then
floating and its voltage will be close to the gate voltage.
If the sensed voltage on VSW is less than 10V or greater
than 20V, the circuit prevents the switch from turning on.
This protects the FET from dissipating high power in a
nonsaturated state or from excessive gate-source voltage.
The oscillator continues to run and the net effect is to skip
switching cycles until the gate bias voltage is corrected.
One consequence of the gate bias detection circuit is that
the start-up window is 6V if the gate is biased from VIN
and to 4V if the gate is biased from the 15V output. This
influences the size of the bypass capacitor on VIN.
VSW Output (LT1103)
The VSW pin of the LT1103 is the collector of an internal
NPN power switch. This NPN has a typical on resistance
of 0.4Ω and a typical breakdown voltage (BVCBO) of 75V.
Fast switching times and high efficiency are obtained by
using a special driver loop which automatically adapts
base drive current to the minimum required to keep the
switch in a quasisaturated state. The key element in the
loop is an extra emitter on the output power transistor as
seen in the block diagram. This emitter carries no current
when the NPN output transistor collector is high (unsatu-
rated). In this condition, the driver circuit can deliver very
high base drive to the switch for fast turn-on. When the
switch saturates, the extra emitter acts as a collector of
an NPN operating in inverted mode and pulls base current
away from the driver. This linear feedback loop serves
itself to keep the switch just at the edge of saturation. Very
low switch current results in nearly zero driver current
and high switch currents automatically increase driver
current as necessary. The ratio of switch current to driver
current is approximately 30:1. This ratio is determined by
the sizing of the extra emitter and the value of the current
source feeding the driver circuitry. The quasisaturation
state of the switch permits rapid turn-off without the need
for reverse base emitter voltage drive.
Gate Biasing (LT1105)
The LT1105 is designed to drive an external power
MOSFET in the common source configuration with the
totem-pole output VSW pin. The advantage is added
switch current flexibility (limited only by the choice of
external power FET) and higher output power applications
than allowed by LT1103. An external, noninductive, power
sense resistor must be used in series with the source of
the FET to detect switch current and must be tied to the
input of the current limit amplifier. The gate needs to be
biased at a voltage high enough to guarantee that the
FET is saturated when the totem-pole gate drive is on.
This means 10V as specified in FET data sheets, plus
the totem-pole high side saturation voltage plus a couple
of volts for temperature variations and processing toler-
ances. This leads to 15V for a practical gate bias voltage.
Power MOSFETs are well suited to switching power sup-
plies because their high speed switching characteris-
tics promote high switching efficiency. To achieve high
switching speed, the gate capacitance must be charged
and discharged quickly with high peak currents. In par-
ticular, the turn-off current can be as high as the peak
switch current. The switching speed is controlled by
the impedance seen by the gate capacitance. Practically
speaking, zero impedance is not desirable because of the
high frequency noise spikes introduced to the system.
The gate bias supply which drives the totem-pole output
stage should be bypassed with a 1µF low ESR capacitor
to ground. This capacitor supplies the energy to charge
the gate capacitance during gate drive turn-on. The power
MOSFET should have a 5Ω resistor or larger in series with
its gate from the VSW pin to define the source impedance.
LT110 3/LT110 5
19
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
The LT1105 provides a 15V regulated output intended
for driving the totem-pole output stage. It will source
30mA into a capacitive load with no stability problems.
The output voltage temperature coefficient is 3mV/°C. If
VIN drops below 17V, the 15V output follows about 2.0V
below VIN until the part shuts down. If the 15V output is
pulled above 17.5V, it will sink 5mA.
A special circuit in the LT1105 senses the voltage at the
15V regulated output prior to turning on the switch. The
15V regulator drives the totem-pole output stage and the
V
SW
pin will pull the gate of the FET very close to the
value of the 15V output when VSW turns on. Therefore,
the 15V output represents what the gate bias voltage on
the FET will be when the FET is turned on. If the sensed
voltage on the 15V output is less than 10V or greater
than 20V, the circuit prevents the switch from turning
on. This protects the FET from dissipating high power
in a nonsaturated state or from excessive gate-source
voltage. The oscillator continues to run and the net effect
is to skip switching cycles until the gate bias voltage is
corrected. One consequence of the gate bias detection
circuit is that the start-up window is 4V. This influences
the size of the bypass capacitor on VIN.
VSW Output (LT1105)
The VSW pin of the LT1105 is the output of a 1A totem-
pole driver stage. This output stage turns an external
power MOSFET on by pulling its gate high. Break-Before-
Make action of 200ns is built into each switch edge to
eliminate cross-conduction currents. Fast switching times
and high efficiency are obtained by using a low loss output
stage and a special driver loop which automatically adapts
base drive current to the totem-pole low side drive. The
key element in the loop is an extra emitter on the output
pull-down transistor as seen in the block diagram. This
emitter carries no current when the low side transistor
collector is high (unsaturated). In this condition, the driver
can deliver very high base drive to the output transistor
for fast turn-off. When the low side transistor saturates,
the extra emitter acts as a collector of an NPN operating
in inverted mode and pulls base current away from the
driver. This linear feedback loop serves itself to keep the
switch just at the edge of saturation. This results in nearly
zero driver current. The quasisaturation state of the low
side switch permits rapid turn-on of the external FET when
VSW pulls high.
Fully Isolated Flyback Mode
A unique sampling error amplifier included in the control
loop of the LT1103/LT1105 eliminates the need for an
optoisolator while providing ±1% line and load regulation
in a magnetic flux-sensed flyback converter. In this mode,
the flyback voltage on the primary during “switch off” time
is sensed and regulated. It is difficult to derive a feedback
signal directly from the primary flyback voltage as this
voltage is typically several hundred volts. A dedicated
winding is not required because the bias winding for the
regulator lends itself to flux-sensing. Flux-sensing made
practical simplifies the design of off line power supplies
by minimizing the total number of external components
and reduces the components which must cross the isola-
tion barrier to one, the transformer. This inherently implies
greater safety and reliability. The transformer must be
optimized for coupling between the bias winding and
the secondary output winding(s) while maintaining the
required isolation and minimizing the parasitic leakage
inductances.
Although magnetic flux-sensing has been used in the
past, the technique has exhibited poor output voltage
regulation due to the parasitics present in a transformer
coupled design. Transformers which provide the safety
and isolation as required by various international safety/
regulatory agencies also provide the poorest output volt-
age regulation. Solutions to these parasitic elements have
been achieved with the novel sampling error amplifier of
the LT1103/LT1105. A brief review of flyback converter
operation and the problems which create a poorly regu-
lated output will provide insight on how the sampling error
amplifier of the LT1103/LT1105 addresses the regulation
issue of magnetic flux sensed converters.
The following figure shows a simplified diagram of a fly-
back converter using magnetic flux sensing. The major
parasitic elements present in the transformer coupled
design are indicated. The relationships between the
LT110 3/LT110 5
20
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
primary voltage, the secondary voltage, the bias voltage
and the winding currents are indicated in the figures found
on the following page for both continuous and discontinu-
ous modes of operation.
to zero or changing polarity. Therefore, the voltage on
the bias winding is only valid as a representation of the
output voltage while the secondary is delivering current.
Although the bias winding flyback voltage is a representa-
tion of the output voltage, its voltage is not constant. For
a brief period following the leakage inductance spike, the
bias winding flyback voltage decreases due to nonlineari-
ties and parasitics present in the transformer. Following
this nonlinear behavior is a period where the bias winding
flyback voltage decreases linearly. This behavior is easily
explained. Current flow in the secondary decreases lin-
early at a rate determined by the voltage across the sec-
ondary and the inductance of the secondary. The parasitic
secondary leakage inductance appears as an impedance
in series with the secondary winding. In addition, parasitic
resistances exist in the secondary winding, the output
diode and the output capacitor. These impedances can
be combined to form a lumped sum equivalent and which
cause a voltage drop as secondary current flows. This
voltage drop is coupled from the secondary to the bias
winding flyback voltage and becomes more significant
as the output is loaded more heavily. This voltage drop is
largest at the beginning of “switch off” time and smallest
just prior to either all transformer energy being depleted
or the switch turning on again.
The best representation of the output voltage is just prior
to either all transformer energy being used up and the
bias winding voltage collapsing to zero or just prior to
the switch turning on again and the bias winding going
negative. This point in time also represents the small-
est forward voltage for the output diode. It is possible to
redefine the relationship between the secondary winding
voltage and the bias winding voltage as:
VBIAS =VOUT +Vf +I• RP
( )
N1
where Vf is the forward voltage of the output diode, I is
the current flowing in the secondary, R
P
is the lumped
sum equivalent secondary parasitic impedance and N1 is
the transformer turns ratio from the secondary to the bias
winding. It is apparent that even though the above point
Simplified Flyback Converter
When the switch “turns on,” the primary winding sees the
input voltage and the secondary and bias windings go to
negative voltages as a function of the turns ratio. Current
builds in the primary winding as the transformer stores
energy. When the switch “turns off,” the voltage across
the switch flies back to a clamp level as defined by a snub-
ber network until the energy in the leakage inductance of
the primary dissipates. Leakage inductance is one of the
main parasitic elements in a flux-sensed converter and
is modeled as an inductor in series with the primary and
secondary of the transformer. These parasitic inductances
contribute to changes in the bias winding voltage and thus
the output voltage with increasing load current.
The energy stored in the transformer transfers through
the secondary and bias windings during “switch off” time.
Ideally, the voltage across the bias winding is set by the DC
output voltage, the forward voltage of the output diode,
and the turns ratio of the transformer after the energy in
the leakage inductance spike of the primary is dissipated.
This relationship holds until the energy in the transformer
drops to zero (discontinuous mode) or the switch turns on
again (continuous mode). Either case results in the volt-
age across the secondary and bias windings decreasing
D1
1:N
LT1103 AI01
V
BIAS
S1
R
L(lkSEC)
VOUT
C1
COMMON
L(IkPRI)
V
IN
1:N1
N = TURNS RATIO FROM SECONDARY TO PRIMARY.
N1 = TURNS RATIO FROM SECONDARY TO BIAS.
N2 = N/N1
L(lkPRI) = PRIMARY LEAKAGE INDUCTANCE.
L(lkSEC) = SECONDARY LEAKAGE INDUCTANCE.
R = PARASITIC WINDING, DIODE AND OUTPUT
CAPACITOR RESISTANCE.
LT110 3/LT110 5
21
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
VZENER
AREA “a” = AREA “b” TO MAINTAIN
ZERO VOLTS ACROSS PRIMARY
[VOUT + Vf + (ISEC • RP)]/N
VIN
0V
PRIMARY SWITCH VOLTAGE
AREA “c” = AREA “d” TO MAINTAIN
ZERO VOLTS ACROSS SECONDARY
[VOUT + Vf + (ISEC • RP)]
0V
N • VIN
SECONDARY WINDING VOLTAGE
[VOUT + Vf + (ISEC • RP)]/N1
0V
BIAS WINDING VOLTAGE
AREA “e” = AREA “f” TO MAINTAIN
ZERO VOLTS ACROSS BIAS WINDING
N2 • VIN
a
b
c
d
e
f
∆I
IPRI
PRIMARY CURRENT
0A
ISEC = IPRI/N
SECONDARY CURRENT
0A
IPRI
∆I
0A
SWITCH CURRENT
IPRI
SNUBBER DIODE CURRENT
0A
∆t = (IPRI)[L(lkPRI)]/VSNUB
a
b
V
ZENER
AREA “a” = AREA “b” TO MAINTAIN
ZERO VOLTS ACROSS PRIMARY
[VOUT + Vf + (ISEC • RP)]/N
VIN
0V
PRIMARY SWITCH VOLTAGE
AREA “c” = AREA “d” TO MAINTAIN
ZERO VOLTS ACROSS SECONDARY
[VOUT + Vf + (ISEC • RP)]
0V
N • VIN
SECONDARY WINDING VOLTAGE
[VOUT + Vf + (ISEC • RP)]/N1
0V
BIAS WINDING VOLTAGE
AREA “e” = AREA “f” TO MAINTAIN
ZERO VOLTS ACROSS BIAS WINDING
N2 • VIN
e
f
∆I
∆I
IPRI
SNUBBER DIODE CURRENT
0A
IPRI
PRIMARY CURRENT
0A
ISEC = IPRI/N
SECONDARY CURRENT
0A
IPRI
0A
SWITCH CURRENT
LT1103 WF01
∆t = (IPRI)[L(lkPRI)]/VSNUB
c
d
Flyback Waveform for Continuous Mode Operation Flyback Waveform for Discontinuous Mode Operation
LT110 3/LT110 5
22
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
in time is the most accurate representation of the output
voltage, the answer given by the bias winding voltage is
still off from the “true” answer by the amount I • RP/N1.
The sampling error amplifier of the LT1103/LT1105 pro-
vides solutions to the errors associated with the bias
winding flyback voltage. The error amplifier is comprised
of a leakage inductance spike blanking circuit, a slew rate
limited tracking amplifier, a level detector, a sample-and-
hold, an output gm stage and load regulation compensa-
tion circuitry. This all seems complicated at first glance,
but its operation is straightforward and transparent to
the user of the IC. When viewed from a system or block
level, the sampling error amplifier behaves like a simple
transconductance amplifier. Here’s how it works.
The sampling error amplifier takes advantage of the fact
that the voltage across the bias winding during at least a
portion of switch off time is proportional to the DC output
voltage of the secondary winding. The feedback network
used to sense the bias winding voltage is no longer com-
prised of a traditional peak detector in conjunction with a
resistor divider network. The feedback network consists
of a diode in series with the bias winding feeding the resis-
tor divider network directly. The resultant error signal is
then fed into the input of the error amplifier. The purpose
of the diode in series with the bias winding is now not to
peak detect, but to prevent the FB pin (input of the error
amplifier) from being pulled negative and forward biasing
the substrate of the IC when the bias winding changes
polarity with “switch turn-on.”
The primary winding leakage inductance spike effects
are first eliminated with an internal blanking circuit in the
LT1103/LT1105 which suppresses the input of the FB
pin for 1.5µs at the start of “switch off” time. This pre-
vents the primary leakage inductance spike from being
propagated through the error amplifier and affecting the
regulated output voltage.
With the effects of the leakage inductance spike eliminated,
the effects of decreasing bias winding flyback voltage can
be addressed. With the traditional diode/capacitor peak
detector circuitry eliminated from the feedback network,
the tracking amplifier of the LT1103/LT1105 follows the
flyback waveform as it changes with time and amplifies
the difference between the flyback signal and the internal
4.5V reference. Tracking is maintained until the point in
time where the bias winding voltage collapses as a result
of all transformer energy being depleted (discontinuous
mode) or the switch turning on again (continuous mode).
The level detector circuit senses the fact that the bias
winding flyback voltage is no longer a representation of
the output voltage and activates an internal peak detector.
This effectively saves the most accurate representation of
the output voltage which is then buffered to the second
stage of the error amplifier.
The second stage of the error amplifier consists of a
sample-and-hold. When the switch turns on, the sample-
and-hold samples the buffered error voltage for 1µs and
then holds for the remainder of the switch cycle. This
held voltage is then processed by the output gm stage and
converted into a control signal at the output of the error
amplifier, the VC pin.
The final adjustment in regulation is provided by the load
regulation compensation circuitry. As stated earlier, output
regulation degrades with increasing load current (output
power). The effect is traced to secondary leakage induc-
tance and parasitic secondary winding, diode and output
capacitor resistances. Even though the tracking ampli-
fier has obtained the most accurate representation of the
output voltage, its answer is still flawed by the amount of
the voltage drop across the secondary parasitic lumped
sum equivalent impedance which is coupled to the bias
winding voltage. This error increases with increasing load
current. Therefore, a technique for sensing load current
conditions has been added to the LT1103/LT1105. The
switch current is proportional to the load current by the
turns ratio of the transformer. A small current proportional
to switch current is generated in the LT1103/LT1105 and
fed back to the FB pin. This allows the input bias current
of the sampling error amplifier to be a function of load
current. A resistor in series with the FB pin generates
a linear increase in the effective reference voltage with
increasing load current. This translates to a linear increase
in output voltage with increasing load current. By adjust-
ing the value of the series resistor, the slope of the load
LT110 3/LT110 5
23
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
compensation can be set to cancel the effects of these
parasitic voltage drops. The feature can be ignored by
eliminating the series resistor and lowering the equivalent
divider impedance to swamp out the effects of the input
bias current.
Frequency Compensation
In order to prevent a regulator loop using the LT1103/
LT1105 from oscillating, frequency compensation is
required. Although the architecture of the LT1103/LT1105
is simple enough to lend itself to a mathematical approach
to frequency compensation, the added complication of
input/or output filters, unknown capacitor ESR, and gross
operating point changes with input voltage and load cur-
rent variations all suggest a more practical empirical
approach. Many hours spent on breadboards have shown
that the simplest way to optimize the frequency compen-
sation of the LT1103/LT1105 is to use transient response
techniques and an “RC” box to quickly iterate toward the
final compensation network. Additional information on
this technique of frequency compensation can be found
in Linear Technology’s Application Note 19.
In general, frequency compensation is accomplished with
an RC series network on the VC pin. The error amplifier
has a gm (voltage “in” to current “out”) of ≈ 12000 µmhos.
Voltage gain is determined by multiplying gm times the
total equivalent error amplifier output loading, consisting
of the error amplifier output impedance in parallel with the
series RC external frequency compensation network. At
DC, the external RC can be ignored. The output imped-
ance of the error amplifier is typically 100kΩ resulting in
a voltage gain of ≈ 1200V/V. At frequencies just above DC,
the voltage gain is determined by the external compensa-
tion, RC and CC. The gain at mid frequencies is given by:
AV=
g
m
2π• f • C
C
The gain at high frequencies is given by:
AV = gm • RC
Phase shift from the FB pin to the VC pin is 90° at mid
frequencies where the external CC is controlling gain, then
drops back to 0° (actually 180° since FB is an inverting
input) when the reactance of C
C
is small compared to
RC. Thus, this RC series network forms a pole-zero pair.
The pole is set by the high impedance output of the error
amplifier and the value of CC on the VC pin. The zero is
formed by the value of CC and the value of RC in series
with CC on the VC pin. The RC series network will have
capacitor values in the range of 0.1µF to 1.0µF and series
resistor values in the range of 100Ω to 1000Ω .
It is noted that the RC network on the VC pin forms
the main compensation network for the regulator loop.
However, if the load regulation compensation feature is
used as explained in the section on fully-isolated flyback
mode, additional frequency compensation components
are required. The load regulation compensation feature
involves the use of local positive feedback from the V
C
pin to the FB pin. Thus, it is possible to add enough load
regulation compensation to make the loop oscillate. In
order to prevent oscillation, it is necessary to roll off
this local positive feedback at high frequencies. This is
accomplished by placing a capacitor in parallel with the
compensation resistor which is in series with the FB pin.
A value for this capacitor in the range of 0.01µF to 0.1µF is
recommended. The time constant associated with this RC
combination will be longer than that associated with the
loop bandwidth. Thus, transient response will be affected
in that settling time will be increased. However, this is typi
-
cally not as important as controlling the absolute under
or overshoot amplitude of the system in response to load
current changes which could cause deleterious system
operation.
Switching Regulator Topologies
Two basic switching regulator topologies are pertinent to
the LT1103/LT1105, the flyback and forward converter.
The flyback converter employs a transformer to convert
one voltage to either a higher or lower output voltage.
VOUT in continuous mode is defined as:
VOUT =VIN •N •
DC
(1– DC)
LT110 3/LT110 5
24
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
where N is the transformer turns ratio of secondary to
primary and DC is the duty cycle. This formula can be
rewritten in terms of duty cycle as:
DC =
V
OUT
VOUT +N • VIN
( )
It is important to define the full range of input voltage,
the range of output loading conditions and the regulation
requirements for a design. Duty cycle should be calcu-
lated for both minimum and maximum input voltage.
In many applications, N can vary over a wide range with-
out degrading performance. If maximum output power is
desired, N can be optimized:
NOPT
( )
=
V
OUT +
Vf
VM– VIN MAX
( )
– VSNUB
( )
where
Vf = Forward voltage of the output diode
VM = Maximum switch voltage
VSNUB = Snubber clamp level – primary flyback voltage.
In the isolated flyback mode, the LT1103/LT1105 sense
and regulate the transformer primary voltage VPRI during
“switch off” time. The secondary output voltage will be
regulated if VPRI is regulated. VPRI is related to VOUT by:
VPRI =VOUT +Vf
( )
N
This allows duty cycle for an isolated flyback converter
to be rewritten as:
DC =Duty Cycle =
V
PRI
V
PRI
+V
IN
( )
An important transformer parameter to be determined is
the primary inductance LPRI. The value of this inductance
is a trade-off between core size, regulation requirements,
leakage inductance effects and magnetizing current ∆I.
Magnetizing current is the difference between the primary
current at the start of “switch on” time and the current at
the end of “switch on” time. If maximum output power is
needed, a reasonable starting value is found by assigning
∆I a value of 20% of the peak switch current (2A for the
LT1103 and set by the external FET rating used with the
LT1105). With this design approach, LPRI is defined as:
LPRI =
V
IN
(ΔI)(f) 1+VIN
VPRI
⎛
⎝
⎜⎞
⎠
⎟
If maximum output power is not required, then ∆I can
be increased which results in lower primary inductance
and smaller magnetics. Maximum output power with an
isolated flyback converter is defined by the primary fly-
back voltage and the peak allowed switch current and is
limited to:
POUT(MAX) =VPRI
( )
V
PRI
+V
IN
( )
VIN IP±ΔI
2
⎛
⎝
⎜⎞
⎠
⎟± Ip
( )
2R
⎡
⎣
⎢⎤
⎦
⎥E
where
R = Total “switch” on resistance
IP = Maximum switch current
E = Overall efficiency ≈ 75%
Peak primary current is used to determine core size for
the transformer and is found from:
IPRI =VOUT
( )
IOUT
( )
VPRI +VIN
( )
E V
PRI
( )
V
IN
( )
+ΔI
2
A second consideration on primary inductance is the
transition point from continuous mode to discontinuous
mode. At light loads, the flyback pulse across the primary
will drop to zero before the end of “switch off” time. The
load current at which this starts to occur can be calculated
from:
IOUT(TRANSITION) =VPRI • VIN
( )
2
VPRI +VIN
( )
22VOUT
( )
f
( )
LPRI
( )
The forward converter as shown below is another trans-
former-based topology that converts one voltage to either
a higher or a lower voltage.
LT110 3/LT110 5
25
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
TYPICAL APPLICATIONS
VOUT in continuous mode is defined as:
VOUT = VIN • N • DC
The secondary voltage charges up L1 through D1 when
S1 is on. When S1 is off, energy in L1 is transferred
through free-wheeling diode D2 to C1. The extra trans-
former winding and diode D3 are needed in a single
switch forward converter to define the switch voltage
when S1 is off. This “reset” winding limits the maximum
duty cycle allowed for the switch. This topology trades
off reduced transformer size for increased complexity and
parts count. A separate isolated feedback path is required
for full isolation from input to output because voltages on
the primary are no longer related to the DC output voltage
during switch off time.
The isolated feedback path can take several forms. A
second transformer in a modulator/demodulator scheme
provides the isolation, but with significant complexity. An
optoisolator can be substituted for the transformer with a
savings in volume to be traded off with component varia-
tions and possible aging problems with the optoisolator
transfer function. Finally, an extra winding closely coupled
to the output inductor L1 can sense the flux in this ele-
ment and give a representation of the output voltage when
S1 is off.
D1
VOUT
C1
1:N
LT1103 AI02
V
IN
S1
D2
D3
L1
COMMON
Simplified Forward Converter
LT1103 FET Connection
LT1105 FET Connection
15V
VSW
LT1103
LT1103 TA03
15V
VSWLT1105
LT1103 TA04
ILIM
LT110 3/LT110 5
26
Rev. E
For more information www.analog.com
TYPICAL APPLICATIONS
Setting Oscillator Frequency
Decreasing Oscillator
Maximum Duty Cycle
Setting Overvoltage Lockout
Synchronizing Oscillator Frequency
to an External Clock
Increasing Oscillator
Maximum Duty Cycle
OSC
COSC
LT1103/LT1105
LT1103 TA05
CHOOSE 20kHz ≤ f
OSC ≤ 200kHz
C
OSC = = =
SF
fOSC
I
DC 0.66 66%
2.5V fOSC
100µA
( )(
)
∆V fOSC
( )( )
OSC
COSC
LT1103/LT1105
LT1103 TA06
RI1
CHOOSE 0.66 ≤ DC ≤ 1.0
SOLVE FOR X
X =
0 ≤ X ≤ 1.5
I1 = X • I = X • 100µA
R =
C
OSC = • 1 –
(9DC – 6)
2
3.25V
I1
2.5V fOSC
100µA
( )( )
3X + 2X2
( )
9
OSC
COSC
LT1105
LT1103 TA07
RI1
5V
CHOOSE 0 ≤ DC ≤ 0.66
SOLVE FOR X
X =
0 ≤ X ≤ 3
I1 = X • I = X • 100µA
R =
C
OSC = • 1 +
(6 – 9DC)
2
1.75V
I1
2.5V fOSC
100µA
( )( )
3X – 2X2
( )
9
OSC
COSC
LT1103/LT1105
LT1103 TA08
1µF
500ns
ISOLATION
BOUNDARY
5V
0V
1:0.5
OVLO
R2 LT1105
LT1103 TA09
R1
OVLO
TH
( )
CHOOSE OVLOTH
LET R1 = 5k
R2 = –1 R1
OVLOTH
2.5V
LT110 3/LT110 5
27
Rev. E
For more information www.analog.com
TYPICAL APPLICATIONS
LT1103 Ground Connections
LT1105 Ground Connections
SWITCH CURRENT PATH
KEEP RESISTANCE LOW
TO BIAS
WINDING OUTPUT GND
LT1103 TA11a
VSW
FB
VC
GND
VIN
15V
OSC
TO BIAS
WINDING OUTPUT GND
SEPARATE
GROUND PATH
SWITCH CURRENT PATH
KEEP RESISTANCE LOW
LT1103 TA11b
VSW
FB
VC
GND
VIN
15V
OSC
TO BIAS
WINDING
OUTPUT
HIGH CURRENT
GROUND PATH
LT1103 TA12a
GND VSW
ILIM
VIN
FB
VC
LT110 3/LT110 5
28
Rev. E
For more information www.analog.com
PACKAGE DESCRIPTION
N8 REV I 0711
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ±.005
(3.302 ±0.127)
.020
(0.508)
MIN
.018 ±.003
(0.457 ±0.076)
.120
(3.048)
MIN
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
( )
1 2 34
87 65
.255 ±.015*
(6.477 ±0.381)
.400*
(10.160)
MAX
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
LT110 3/LT110 5
29
Rev. E
For more information www.analog.com
PACKAGE DESCRIPTION
N14 REV I 0711
.020
(0.508)
MIN
.120
(3.048)
MIN
.130 ±.005
(3.302 ±0.127)
.045 – .065
(1.143 – 1.651)
.065
(1.651)
TYP
.018 ±.003
(0.457 ±0.076)
.005
(0.127)
MIN
.255 ±.015*
(6.477 ±0.381)
.770*
(19.558)
MAX
31 24567
8910
11
1213
14
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
( )
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
LT110 3/LT110 5
30
Rev. E
For more information www.analog.com
PACKAGE DESCRIPTION
OBSOLETE PACKAGE
.050
(1.27)
.026 – .036
(0.660 – 0.914)
T7 (TO-220) 0801
.135 – .165
(3.429 – 4.191)
.700 – .728
(17.780 – 18.491)
.045 – .055
(1.143 – 1.397)
.165 – .180
(4.191 – 4.572)
.095 – .115
(2.413 – 2.921)
.013 – .023
(0.330 – 0.584)
.620
(15.75)
TYP
.155 – .195*
(3.937 – 4.953)
.152 – .202
(3.860 – 5.130)
.260 – .320
(6.604 – 8.128)
.147 – .155
(3.734 – 3.937)
DIA
.390 – .415
(9.906 – 10.541)
.330 – .370
(8.382 – 9.398)
.460 – .500
(11.684 – 12.700)
.570 – .620
(14.478 – 15.748)
.230 – .270
(5.842 – 6.858)
BSC
SEATING PLANE
*MEASURED AT THE SEATING PLANE
T7 Package
7-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1422)
LT110 3/LT110 5
31
Rev. E
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
E 11/18 Reflects LT1103 being obsolete and the LT1105 being available. All
(Revision history begins at Rev B)
LT110 3/LT110 5
32
Rev. E
ANALOG DEVICES, INC. 2018
11/18
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1241 High Speed Current Mode Pulse Width Modulators Up to 500kHz Operation
LT1246 Off-Line Current Mode PWM 1MHz Operation
LT1248 Power Factor Controller Programmable Frequency, 16-Pin SO
LT1249 Power Factor Controller 100kHz, SO-8
LT1508 Power Factor and PWM Controller Voltage Mode
LT1509 Power Factor and PWM Controller Current Mode
Minimum Parts Count Fully-Isolated Flyback 100kHz 50W Converter
Load Regulation
220k
1W
330Ω
0.1µF
499Ω
39µF
25V
1000pF
100Ω
1N4148
16.2k
1%
5.36k
1%
BUK426-800A
MBR2045 10µH 5V
10A
50V
470µF
35V
3600µF
WINDINGS FOR
OPTIONAL
±12VDC OUTPUTS
10Ω
1µF
25V
220µF
385V
BAV21
BAV21
390pF
1.5KE300A
5W
MUR150
BRIDGE
RECTIFIER
+
LINE
FILTER
85VAC TO 270VAC
+
–
TRANSFORMER DATA:
COILTRONICS - CTX110228-3
L(PRI) = 1.6mH
NPRI:NSEC = 1:0.05
NBIAS:NSEC = 1:0.27
0.047µF
LT1103 TA01
*OUTPUT CAPACITOR IS THREE 1200µF,
50V CAPACITORS IN PARALLEL TO
ACHIEVE REQUIRED RIPPLE CURRENT
RATING AND LOW ESR.
OPTIONAL OUTPUT FILTER
VIN VSW
VC
FB
GND OSC
15V
LT1103
DANGER!!
HIGH VOLTAGE!!
+
+
+
++
Danger!! Lethal Voltages Present – See Text
IOUT (A)
0
V
OUT
(V)
5.05
5.15
5.25
8
LT1103 TA14
4.95
4.85
4.75 246
10
4.80
4.90
5.00
5.10
5.20
135 7 9
270VAC
85VAC
110VAC
220VAC