Application Notes SH 100 G
Semiconductor Group 1 Vers.: 1.3
GCDR3300A
The GCDR3300A is a macro to be used within the SH100G Gate Array-environment. This macro is
designed for 2.5 - 3.3 GHz applications. It contains a 1:2 demultiplexer and a phase detector (PD) [1]
with bit error detection and VCO (fig. 1).
The block named ’UP’ and ’DOWN’ represents a mixer circuit for the UP and DOWN signals of the PD
and the FD. The VCO has its own GND (I9) and negativ e sup ply N2V5 (I10), and is controlled by pin I7
(VF0). With a frequency window det ector (FD), an operational amplif ier and a voltage refe rence diode, a
complete PLL can be built. The extern al configuration is shown in f igur e 3.
fig. 1: Block diagram GCDR3300A
Table 1 sho ws t he si gnal cl ass and t he funct ion o f the i nput and t he output pins. The correct pin pad c om-
bination is gi ven in table2.
DON
UPN
VCO
O9, O10
O11, O12
I3, I4
I5, I6
O3, O4
O1, O2
O5,O6 O7,O8
I7
clock
I9
I10
CDR3300 Stand: 10.12.96
DEMUX
DOWN
FD
PD
UP
FD
PD
Data
I1, I2
Test
Alex
tclk
control I11, I12
I13, I14
I15, I16
I17, I18
O13
O14
I8
Reset
Data
Clock
D1
D2
CLK/4
Application Notes SH 100 G
Semiconductor Group 2 Vers.: 1.3
Table 1: Pin list
Pinname Signal class Notes
I1,I2
data Analog Differential data, 10 mV- 500 mVpp. 50
Ohm on chip resistors
I3,I4
tclk CML2 Differential clock used for testing.
I5,I6
test ECL2 Select test mode. High = Test mode on
I7
control Analog Input integral path from PD, FD
I8 CML Reset toggle ff’s demux
I9, I19 Analog GND for inte rn al VCO
I10 Analog N2V5 for internal VCO nom. -2.5V
I11, I12 CML2 Down signal frequency detector
I13, I14 CML2 Down signal phase detector
I15, I16 CML2 Up signal frequency detector
I17, I18 CML2 Up signal phase detector
O1,O2
down CML2 Down signal phase detector
O3,O4
up CML2 Up signal phase detector
O5,O6
ber CML2 Bit error detection
O7,O8
c/4 ECL2 Clock/4
O9,O10
d1 CML2 Data 1
O11,O12
d2 CML2 Data 2
O13
DON Analog DON signal phase detector + 1/10
frequency detector
O14
UPN Analog UPN signal phase detector + 1/10
frequency detector
Application Notes SH 100 G
Semiconductor Group 3 Vers.: 1.3
Description Block Diagram
In figure 1, the inter nal st ruct ure of th e macro i s shown. The bl ock ALEX represents the combin ed phas e
detector and deci sion circuit [1] . In this block, the dat a signal is recover ed and the UP and DOWN signals
are generated. Also a Bit error detecti on signal (BER) is available. Thi s BER signal can be used to bui ld
a ’Loss Of Signal’ detection (LOS). The VCO is a ring oscillator structure with a K vco of about 2 GHz/V
(fig. 3). The 1:2 demultipl exer circuit gets the data and clock signal from the ALEX.
fig. 2: VCO frequency as functi on of the voltage at I7
.
Table 2: Pad macros
Pin name Pad macro
I1, I2 PA50I
I7 PIWIRE2A
I9 PASUP1
I10 PASUP1
O13 PAWIRE
O14 PAWIRE
CDR3300 VCOsim u l ati on V EE= 2. 5V
2,00
2,20
2,40
2,60
2,80
3,00
3,20
3,40
3,60
3,80
4,00
1,40 1,50 1,60 1,70 1,80 1,90 2,00 2,10 2,20 2,30 2,40
FD/V
F/GHz
F-10
F25
F80
F125
Application Notes SH 100 G
Semiconductor Group 4 Vers.: 1.3
fig. 3: External Parts of the PLL circuit
a) negative VCO Supply from external reference (LM385-2.5).
b) negative VCO Supply from external reference(TL431(SO8)).
c) Integrator (part of Loop filter) e.g. TS3V912.
Remark:
The values given in this application note result in a supply range from 4 to 5.5V and a lower fre-
quency limit of 2.4GHz.
1k
UPN
+
-
1k
VF0
844
844 100p 100p
VCC VCC
VCC
6mA
100
100n
100 5
100n
DON
100n
100
N2V5
15mA
5
10uF T
TL431(D)
80
-4.5V
20mA
VCC VCC
b)
c)
+
N2V5
15mA
5
10uF T
LM386-2.5
80
-4.5V
20mA
VCC VCC
+
a) 4
8
1
2,3,6,7
OPAMP requirements
I(-1V): 0 mA
I(-2.8V): 4.8 mA
Uos: < 5 mV
Application Notes SH 100 G
Semiconductor Group 5 Vers.: 1.3
Pinout
Table 3 shows the pad numbers for the G1 and G2 master with the two possible placements of the
macro. Table 4 shows the placement of the connections from the core side.
Table 3: Pad list of pad numbers
Pin G1 Top G1 Bottom G2 Top G2 Bottom
I1 PP317 PP124 PP309 PP118
I2 PP318 PP123 PP311 PP116
I7 PP321 PP119 PP315 PP112
I9 PP316 PP125 PP310 PP117
I10 PP315 PP126 PP306 PP121
I19 PP319 PP122 PP312 PP115
O13 PP321 PP117 PP317 PP110
O14 PP320 PP118 PP316 PP111
Table 4: Core ports
Pin G1 Top G1 Bottom G2 Top G2 Bottom
I3, I4 C1625 C0152 C1007 C0137
I5, I6 C1627 C0150 C1009 C0135
I8 C1643 C0132 C1028 C0116
I11, I12 C1651 C0126 C1038 C0107
I13, I14 C1642 C0134 C1027 C0117
I15, I16 C1649 C0128 C1036 C0109
I17, I18 C1641 C0135 C1026 C0118
O1, O2 C1628 C0149 C1010 C0134
O3, O4 C1629 C0148 C1011 C0133
O5,O6 C1626 C0151 C1008 C0136
O7, O8 C1647 C0130 C1033 C0111
O9, O10 C1650 C0127 C1037 C0108
O11, O12 C1648 C0129 C1034 C0110
Application Notes SH 100 G
Semiconductor Group 6 Vers.: 1.3
Test Description
A static test can be done by switching into the test mode (I5 = High, I6 = Low). Then the macro can be
tested with an external clock (pin I3, I4) and data (pin I1, I2 ). At the beginning of a test sequence a reset
(pin8) is done. The internal VCO can be stopped by leaving the pins N2V5 and VF0 open.
Hints for Simulation
In the simulation model, the VCO is inoperable. For si mulations, the testmode is switched on. When the
test mode is off, all outputs of the macro show the X-state. To simulate the demulti plexer part of the
macro, a reset (pin8) has to be done.
Data recovery Circuit in the SH100G Environment
To build a complet e PLL with LOS and demultiplexer, some additional circuits in the perip hery and in the
core area are needed.
PLL
The PLL consist s of a phase detector(PD) , a fr equency detector (FD), and a l oopfilte r. The PD is realiz ed
in the macro GCDR3300A.The outputs O1-O4 of this macro are the UP and DOWN signals of the PD.
These UP and DOWN signals are mixed with the UP and DOWN signals of the FD. This can be done
with the input s I11-I18 of t he GCDR3300A. The signal s of the PD are weight ed 9 times str onger than t he
signals of the FD. So it is impor tant to use the righ t input for each signal (see figure 1 and table 1)! Pin
O13 and O14 of the GCDR3300A are fed to the loop filter. The external circuits can be implemented as
shown in figure 3. The FD compares the divided VCO signal with a reference clock. The value of a
counter, after a certain time, gives the information wether the VCO is too fast or too slow. When the FD
gives the value ’too slow’ or ’too fast’ the PD signals have to be tur ned off at pin I13, I14 and I17, I18.
This can be done by a multiplexer
(fig. 4).
Application Notes SH 100 G
Semiconductor Group 7 Vers.: 1.3
fig. 4: Internal PLL circuit
Frequency Detector
For the frequency window detector (FWD) a reference clock (REF) is needed. This reference clock is
divided by n, a nd this di vided clock is the main p arameter fo r designi ng the other p art s of the FWD. A cer-
tain frequency window (FW) is given when the FWD is turned off.
The counter is clocked by the VCO signal divided by x. After a certain time, given by REF, the value of
the counter is compared with a reference value window. This comparison gives an UP or DOWN or OK
(UP=DOWN= LOW) signal that is passed on a pulse former and then to the loop fil ter. For the design of
the PLL, there are two constrains tha t have to be considered : the size of the l oop filter and the si ze of the
counter. A large counter range will determine the accuracy of the frequency but the FD will give less
information in a cer tai n time. Therefore a l arge loop fi lter is needed.Thi s invokes a long transient time for
the PLL.
O1,O2
O3,O4
O5,O6
O7,O8
O9,O10
O11,O12
O13
O14
I1,I2
I3,I4
I5,I6
I7
I8
I9
I10
I11,I12
I13,I14
I15,I16
I17,I18
GCDR3300A
FD
Up
DOWN
1
MUX
0
1
0
1
LOW
LOS
DON
UPN
VST
VST
BER
LOS LOS
Application Notes SH 100 G
Semiconductor Group 8 Vers.: 1.3
fig. 5: Frequency window detector block diagram
fig. 6: Waveform frequency detector
1/N
1/X
REF
VCO
Compare
Counter
START
UP
DOWN
EARLY
LATE
VST
1ERR
out
VST
EARLY
VST
OUT VCO
Counter
OK UP
DOWN
LATE
Application Notes SH 100 G
Semiconductor Group 9 Vers.: 1.3
LOS
A LOS can be generated with the help of the BER signal, pin O5 O6 of the GCDR3300A. This can be
done with a counter tha t is res et after a certain time gene rat ed by t he refe rence cl ock. When this count er
reaches a specified value a LOS will be set immediately. The LOS will be reset when the value of the
counter drops below another specified value that is below the first value.
This time is specified by VST and SHIFT (fig. 8).
fig. 7: LOS detection
Example:
The LOS has to be HIGH when the pulse rate of BER is higher the n 10E-3.
f
LOS is LOW if less then 128 BER pulses are generated in a certain time.
Counter
Bit 1 2 3 4 5 6 7 8 9 ....
RESET
R
S
R
S
BER
LOS
OK
SHIFT
NOLOS
LOS
REFCL
VST
VST Fbit()216
⁄=
2()
16 65536Bit. 10E-3 65Bit==
Application Notes SH 100 G
Semiconductor Group 10 Vers.: 1.3
fig. 8: SHIFT
The Flip-flops in SHIFT are positive edge triggered
D
R
D
R
D
R
&NOLOS
OK
LOS
REFCL
Application Notes SH 100 G
Semiconductor Group 11 Vers.: 1.3
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
Bit Error Ratio
-28 -27 -26 -25 -24
Optical Power / dBm
-3dB
-6dB
-9dB
Application Notes SH 100 G
Semiconductor Group 12 Vers.: 1.3
References
[1] J. J. D. H. Alexander: "Clock Recovery from Random Binary Signals",
Electronics Letters 11, pp. 541-542, Oct. 1975.
DOWN
UP
40% 40% 20%
UP DOWN 0
Jitter distribution
UP UP UP
DOWN UP UP
DOWN DOWN UP
DOWN DOWN DOWN
